A high common-mode input voltage switching circuit

Abstract

The application provides a high common-mode input voltage switching circuit, and belongs to the technical field of common-mode input voltage switching. The input common-mode voltage and the power supply voltage are compared through a comparison module and a shaping comparison module in the voltage switching circuit. When the power supply voltage is higher than the common-mode voltage, the power supply voltage is output through a switch tube circuit to supply power to a high-voltage circuit. When the common-mode voltage is higher than the power supply voltage, the common-mode voltage is output through a switch tube circuit to supply power to a high-voltage module circuit through a conversion circuit. The problem of generating a deviation in common-mode input voltage by using a large number of resistors for voltage division is avoided.

Description

Technical Field

[0001] This application belongs to the field of common-mode input voltage switching technology, and specifically relates to a high common-mode input voltage switching circuit. Background Technology

[0002] An integrated operational amplifier is a circuit unit with very high amplification. In practical circuits, it is usually combined with a feedback network to form a functional module. Operational amplifiers require a power supply circuit to regulate the switching of the common-mode voltage during operation. High common-mode operational amplifiers, in particular, require a power supply structure that separates the power supply from the input common-mode voltage to provide a high input common-mode voltage.

[0003] Currently, typical high input common-mode voltage operational amplifiers use resistor dividers to reduce the high input common-mode voltage to a suitable voltage range for the internal op-amp. This approach requires a large number of resistors for voltage division, which is prone to mismatch and offset, and also limits the bandwidth of the overall current sense amplifier. Summary of the Invention

[0004] In view of the above problems, this application proposes a high common-mode input voltage switching circuit. When the common-mode voltage is higher than the power supply voltage, the common-mode voltage is used to power the high-voltage module circuit through the conversion circuit, avoiding the problem of offset that is easily caused by using a large number of resistors to divide the voltage to increase the common-mode input voltage.

[0005] This application provides a high common-mode input voltage switching circuit, including:

[0006] Sampling and comparison circuit and switching transistor circuit;

[0007] The input terminal of the sampling and comparison circuit is connected to the common-mode input voltage and the power supply voltage, and the output terminal of the sampling and comparison circuit is connected to the input terminal of the switching transistor circuit.

[0008] The output terminal of the switching transistor circuit is the output terminal of the switching circuit, used to output the supply voltage to the subsequent circuit.

[0009] The sampling comparison circuit includes: a feedback module, a comparison module, and a shaping comparison module;

[0010] The input terminal of the feedback module is connected to the power supply voltage VCC, and the output terminal of the feedback module is connected to the first input terminal of the comparison module.

[0011] The second input terminal of the comparator module is connected to the common-mode input voltage, the output terminal of the comparator module is connected to the input terminal of the shaping comparator module, and the output terminal of the shaping comparator module is connected to the input terminal of the switching transistor circuit as the output terminal of the sampling comparator circuit.

[0012] Preferably, the feedback module includes:

[0013] The fourth current source I4, the first NMOS transistor N1, the second NMOS transistor N2, and the first resistor R1;

[0014] The first terminal of the fourth current source I4 is connected to the power supply voltage VCC, the second terminal of the fourth current source I4 is connected to the drain of the first NMOS transistor N1, and a terminal is led out between the second terminal of the fourth current source I4 and the drain of the first NMOS transistor N1 and connected to the gate of the second NMOS transistor N2.

[0015] The gate of the first NMOS transistor N1 is connected to the feedback terminal of the shaping and comparating module as the input terminal of the feedback circuit. The source of the first NMOS transistor N1 is connected to the first terminal of the first resistor R1, and the second terminal of the first resistor R1 is grounded.

[0016] Preferably, the feedback module further includes:

[0017] The first PMOS transistor P1, the third resistor R3, and the first current source I1;

[0018] The drain of the first PMOS transistor P1 is connected to the power supply voltage VCC, and a third resistor R3 is connected between the gate and the source of the first PMOS transistor P1.

[0019] A terminal is led out between the gate of the first PMOS transistor P1 and the first end of the third resistor R3 to connect to the source of the second NMOS transistor N2 and to the first end of the first current source I1, and the second end of the first current source I1 is grounded.

[0020] A terminal is led out between the source of the first PMOS transistor P1 and the second end of the third resistor R3 to connect to the drain of the second NMOS transistor N2.

[0021] Furthermore, a terminal is led out between the source of the first PMOS transistor P1 and the second end of the third resistor R3 as the output terminal of the feedback circuit and connected to the input terminal of the comparator module.

[0022] Preferably, the comparison module includes:

[0023] First resistor R1, second PMOS transistor P2, third PMOS transistor P3, and second current source I2;

[0024] The first end of the first resistor R1 is connected to the common-mode input voltage Vinn, and the second end of the second resistor R2 is connected to the drain of the second PMOS transistor P2.

[0025] The gate and source of the second PMOS transistor P2 are connected, and the gate and source of the second PMOS transistor P2 are connected to the first terminal of the second current source I2, and the second terminal of the second current source I2 is grounded.

[0026] The gate and source of the second PMOS transistor P2 are also connected to the gate of the third PMOS transistor P3.

[0027] Preferably, the comparison module further includes:

[0028] The second resistor R2, the fourth PMOS transistor P4, and the third NMOS transistor N3;

[0029] The first end of the second resistor R2 is connected to the common-mode input voltage Vinp, the second end of the second resistor R2 is connected to the first end of the first resistor R1, and is also connected to the drain of the third PMOS transistor P3.

[0030] The source of the third PMOS transistor P3 is connected to the drain of the fourth PMOS transistor P4. The gate of the fourth PMOS transistor P4 serves as the input terminal of the comparator module and is connected to the source of the first PMOS transistor P1 in the feedback module and the second terminal of the third resistor R3.

[0031] The source of the fourth PMOS transistor P4 is connected to the drain of the third NMOS transistor N3. The drain of the third NMOS transistor N3 is connected to its gate and also to the gate of the fourth NMOS transistor N4.

[0032] The source of the third NMOS transistor N3 is grounded.

[0033] Preferably, the comparison module further includes:

[0034] The third current source I3 and the fourth NMOS transistor N4;

[0035] The first terminal of the third current source I3 is connected to the voltage level V1, and the second terminal of the third current source I3 is connected to the drain of the fourth NMOS transistor N4.

[0036] A terminal is led out between the second terminal of the third current source I3 and the drain of the fourth NMOS transistor N4 as the output terminal of the comparator module and connected to the input terminal of the shaping comparator module.

[0037] The source of the fourth NMOS transistor N4 is grounded.

[0038] Preferably, the shaping comparison module includes:

[0039] The first inverter NOT_1, the second inverter NOT_2, and the comparator COMP;

[0040] The input terminal of the first inverter NOT_1 is connected to the second terminal of the third current source I3 in the comparison module as the input terminal of the shaping comparison module;

[0041] The output of the first inverter NOT_1 is connected to the first input of the comparator COMP, and the output of the first inverter NOT_1 is connected to the input of the second inverter NOT_2.

[0042] The output of the second inverter NOT_2 is connected to the gate of the first NMOS transistor N1 in the feedback module as the feedback terminal of the shaping and comparison module.

[0043] The second input of comparator COMP is connected to a fixed level V2, and the first and second outputs of comparator COMP are connected to the third and fourth inputs of the switching transistor circuit.

[0044] Preferably, the switching transistor circuit includes:

[0045] The fourth resistor R4 and the fifth resistor R5;

[0046] The first terminal of the fourth resistor R4 is connected to the common-mode input voltage Vinp, and the first terminal of the fifth resistor R5 is connected to the common-mode input voltage Vinn.

[0047] The second terminal of the fourth resistor R4 is connected to the second terminal of the fifth resistor R5.

[0048] Preferably, the switching transistor circuit further includes:

[0049] The drain of the sixth PMOS transistor P6 is connected to the junction of the second terminal of the fourth resistor R4 and the second terminal of the fifth resistor R5.

[0050] The gate of the sixth PMOS transistor P6 is connected to the first output of the comparator COMP as the third input terminal of the switching transistor circuit.

[0051] The source of the sixth PMOS transistor P6 is connected to the output terminal of the switching transistor circuit.

[0052] Preferably, the switching transistor circuit further includes:

[0053] The eighth PMOS transistor P8 and the seventh resistor R7;

[0054] The drain of the eighth PMOS transistor P8 is connected to the power supply VCC.

[0055] The gate of the eighth PMOS transistor P8 is connected to the second output of the comparator COMP as the fourth input terminal of the switching transistor circuit.

[0056] The source of the eighth PMOS transistor P8 is connected to the first terminal of the seventh resistor R7, and the second terminal of the seventh resistor R7 is connected to the output terminal of the switching transistor circuit.

[0057] The beneficial effects of this application are as follows: Based on the above technical solution, the input common-mode voltage is compared with the power supply voltage through the comparison module and the shaping comparison module in the voltage switching circuit. When the power supply voltage is higher than the common-mode voltage, the power supply voltage is output through the switching transistor circuit to power the high-voltage circuit; when the common-mode voltage is higher than the power supply voltage, the switching circuit switches the voltage and then outputs the common-mode voltage through the switching transistor circuit to power the high-voltage module circuit. This avoids the problem of offset caused by using a large number of resistors to divide the voltage to increase the common-mode input voltage.

[0058] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures pointed out in the description and the accompanying drawings. Attached Figure Description

[0059] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0060] Figure 1 This paper shows a high common-mode input voltage switching circuit structure according to an embodiment of the present application;

[0061] Figure 2 A high common-mode input voltage switching circuit topology diagram according to an embodiment of this application is shown. Detailed Implementation

[0062] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0063] It should be noted that the terms "first," "second," etc., used in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," "longitudinal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings.

[0064] This application provides a high common-mode input voltage switching circuit. See also: Figure 1 ,include:

[0065] Sampling and comparison circuit 1 and switching transistor circuit 2;

[0066] The input terminal of the sampling and comparison circuit 1 is connected to the common-mode input voltage and the power supply voltage, and the output terminal of the sampling and comparison circuit 1 is connected to the input terminal of the switching transistor circuit 2.

[0067] The output terminal of the switching transistor circuit 2 is the output terminal of the switching circuit, used to output the power supply voltage to the subsequent circuit.

[0068] The sampling comparison circuit 1 includes: a feedback module 101, a comparison module 102, and a shaping comparison module 103;

[0069] The input terminal of the feedback module 101 is connected to the power supply voltage VCC, and the output terminal of the feedback module 101 is connected to the first input terminal of the comparison module 102.

[0070] The second input terminal of the comparison module 102 is connected to the common-mode input voltage, the output terminal of the comparison module 102 is connected to the input terminal of the shaping comparison module 103, and the output terminal of the shaping comparison module 103 is connected to the input terminal of the switching transistor circuit 2 as the output terminal of the sampling comparison circuit 1.

[0071] Specifically, in current / voltage sense amplifiers, the high-side voltage sensing circuit needs to handle high common-mode input voltage signals, whose common-mode voltage is much higher than the chip's own supply voltage. Existing current / voltage sense amplifiers use resistor dividers in the input stage, which requires a large number of resistors, is prone to mismatch and offset, and also limits the overall bandwidth of the current sense amplifier.

[0072] This application compares the input common-mode voltage with the power supply voltage using a comparison module and a shaping comparison module in the voltage switching circuit. When the power supply voltage is higher than the common-mode voltage, the power supply voltage is output through the switching transistor circuit to power the high-voltage circuit. When the common-mode voltage is higher than the power supply voltage, a switching circuit is used to switch the output of the common-mode voltage to power the high-voltage module circuit. This avoids the offset problem caused by using a large number of resistors to divide the voltage and increase the common-mode input voltage.

[0073] Specifically, see Figure 2 High common-mode input switching circuit, such as Figure 2The circuit shown consists of a sampling comparator circuit 1 and a switching transistor circuit 2. The common-mode input voltage VCM is defined as (Vinn + Vinp) / 2. The sampling comparator circuit 1 compares the input common-mode voltage VCM with the power supply voltage VCC. When VCM ≤ VCC, the output Z of the sampling comparator circuit 1 is high and ZN is low. The switching transistor circuit 2 controls the output Vout to be approximately equal to the power supply voltage VCC based on the input signals Z and ZN. When VCM > VCC, the output Z of the sampling comparator circuit 1 is low and ZN is high. The switching transistor circuit 2 controls the output voltage Vout to be approximately equal to the common-mode voltage VCM based on the input signals Z and ZN. The output voltage Vout is used to supply power to subsequent circuits or high-voltage circuits to ensure that these circuits have a suitable supply voltage.

[0074] The high common-mode input voltage switching circuit of this application will be described in detail below with reference to specific embodiments and accompanying drawings.

[0075] See Figure 1 The voltage switching circuit includes a sampling and comparison circuit 1 and a switching transistor circuit 2. The sampling and comparison circuit 1 includes a feedback module 101, a comparison module 102, and a shaping and comparison module 103.

[0076] In some specific embodiments, see Figure 2 The feedback module 101 includes:

[0077] The fourth current source I4, the first NMOS transistor N1, the second NMOS transistor N2, and the first resistor R1;

[0078] The first terminal of the fourth current source I4 is connected to the power supply voltage VCC, the second terminal of the fourth current source I4 is connected to the drain of the first NMOS transistor N1, and a terminal is led out between the second terminal of the fourth current source I4 and the drain of the first NMOS transistor N1 and connected to the gate of the second NMOS transistor N2.

[0079] The gate of the first NMOS transistor N1 is connected to the feedback terminal of the shaping and comparison module 103 as the input terminal of the feedback circuit. The source of the first NMOS transistor N1 is connected to the first terminal of the first resistor R1, and the second terminal of the first resistor R1 is grounded.

[0080] Specifically, the feedback module 101 further includes:

[0081] The first PMOS transistor P1, the third resistor R3, and the first current source I1;

[0082] The drain of the first PMOS transistor P1 is connected to the power supply voltage VCC, and a third resistor R3 is connected between the gate and the source of the first PMOS transistor P1.

[0083] A terminal is led out between the gate of the first PMOS transistor P1 and the first end of the third resistor R3 to connect to the source of the second NMOS transistor N2 and to the first end of the first current source I1, and the second end of the first current source I1 is grounded.

[0084] A terminal is led out between the source of the first PMOS transistor P1 and the second end of the third resistor R3 to connect to the drain of the second NMOS transistor N2.

[0085] Furthermore, a terminal is led out between the source of the first PMOS transistor P1 and the second end of the third resistor R3 as the output terminal of the feedback circuit and connected to the input terminal of the comparator module 102.

[0086] Specifically, see Figure 2 In the feedback module 101, when the gate voltage of the first NMOS transistor N1 is low, the first NMOS transistor N1 is turned off, the gate voltage of the second NMOS transistor N2 is pulled to a high level, the second NMOS transistor N2 is turned on, and the second NMOS transistor N2 pulls down the gate voltage of the fourth PMOS transistor P4, ensuring that the fourth PMOS transistor P4 is fully turned on, thus forming positive feedback.

[0087] In some specific embodiments, see Figure 2 The comparison module 102 includes:

[0088] First resistor R1, second PMOS transistor P2, third PMOS transistor P3, and second current source I2;

[0089] The first end of the first resistor R1 is connected to the common-mode input voltage Vinn, and the second end of the second resistor R2 is connected to the drain of the second PMOS transistor P2.

[0090] The gate and source of the second PMOS transistor P2 are connected, and the gate and source of the second PMOS transistor P2 are connected to the first terminal of the second current source I2, and the second terminal of the second current source I2 is grounded.

[0091] The gate and source of the second PMOS transistor P2 are also connected to the gate of the third PMOS transistor P3.

[0092] Specifically, the comparison module 102 further includes:

[0093] The second resistor R2, the fourth PMOS transistor P4, and the third NMOS transistor N3;

[0094] The first end of the second resistor R2 is connected to the common-mode input voltage Vinp, the second end of the second resistor R2 is connected to the first end of the first resistor R1, and is also connected to the drain of the third PMOS transistor P3.

[0095] The source of the third PMOS transistor P3 is connected to the drain of the fourth PMOS transistor P4, and the gate of the fourth PMOS transistor P4 serves as the input terminal of the comparator module 102, which is connected to the source of the first PMOS transistor P1 in the feedback module 101 and the second terminal of the third resistor R3.

[0096] The source of the fourth PMOS transistor P4 is connected to the drain of the third NMOS transistor N3. The drain of the third NMOS transistor N3 is connected to its gate and also to the gate of the fourth NMOS transistor N4.

[0097] The source of the third NMOS transistor N3 is grounded.

[0098] Specifically, the comparison module 102 further includes:

[0099] The third current source I3 and the fourth NMOS transistor N4;

[0100] The first terminal of the third current source I3 is connected to the voltage level V1, and the second terminal of the third current source I3 is connected to the drain of the fourth NMOS transistor N4.

[0101] A terminal is led out between the second end of the third current source I3 and the drain of the fourth NMOS transistor N4 as the output terminal of the comparator module 102 and connected to the input terminal of the shaping comparator module 103.

[0102] The source of the fourth NMOS transistor N4 is grounded.

[0103] Specifically, see Figure 2 In the comparison module 102, when the common-mode voltage VCM > the power supply voltage VCC, VGSP4 = (VCM - VR2) - (VCC - VGSP1) > VGSP1 (ignore VR2), then P4 is turned on, the third NMOS transistor N3 and the fourth NMOS transistor N4 are turned on, and the drain of the fourth NMOS transistor N4 is pulled to a low potential.

[0104] Wherein, VGSP4 is the gate and source voltage of the fourth PMOS transistor P4, VR2 is the voltage of the second resistor R2, and VGSP1 is the gate and source voltage of the first PMOS transistor P1.

[0105] Set R1=R2, R4=R5. In comparator module 102, the source voltage VSP4 of the fourth PMOS transistor P4 = VCM-VR2, where VCM is the common-mode voltage, VR2 is the voltage across the second resistor, and the gate voltage VGP4 of the fourth PMOS transistor P4 < VCC-VGSP1. Here, VCC is the power supply voltage, and VGSP1 is the voltage between the gate and source of the first PMOS transistor P1. When VCM≤VCC, the source voltage VGSP4 of the fourth PMOS transistor P4 = (VCM-VR2)-(VCC-VGSP1)<VGSP1 (ignoring VR2), then the fourth PMOS transistor P4 is turned off, no current flows through NMOS transistors N3 and N4, and the drain of N4 is pulled high by the third current source I3.

[0106] In some specific embodiments, see Figure 2 The shaping comparison module 103 includes:

[0107] The first inverter NOT_1, the second inverter NOT_2, and the comparator COMP;

[0108] The input terminal of the first inverter NOT_1 is connected to the second terminal of the third current source I3 in the comparison module 102 as the input terminal of the shaping comparison module 103.

[0109] The output of the first inverter NOT_1 is connected to the first input of the comparator COMP, and the output of the first inverter NOT_1 is connected to the input of the second inverter NOT_2.

[0110] The output of the second inverter NOT_2 is connected to the gate of the first NMOS transistor N1 in the feedback module 101 as the feedback terminal of the shaping comparison module 103.

[0111] The second input of comparator COMP is connected to a fixed level V2, and the first and second outputs of comparator COMP are connected to the third and fourth inputs of the switching transistor circuit 2.

[0112] Specifically, see Figure 2 In the shaping and comparison module 103, the first inverter NOT_1 and the second inverter NOT_2 are inverters, and COMP is a comparator. When the input of the first inverter NOT_1 is pulled low, the output of the first inverter NOT_1 is high. When the input of the second inverter NOT_2 is high, the output is low. The positive input V2 of the comparator COMP is fixed, so VIN+ < VIN-. The output Z of the comparator COMP is low, and ZN is high. Therefore, P6 is turned on, P8 is turned off, and Vout = VCM - VDSP6 - VR4.

[0113] Wherein, VIN- is the input voltage of the first terminal (negative terminal) of the comparator, VIN+ is the input voltage of the second terminal (positive terminal) of the comparator, VDSP6 is the voltage between the drain and source of the sixth PMOS transistor P6, and VR4 is the voltage of the fourth resistor R4.

[0114] When the input of the first inverter NOT_1 is pulled high by the third current source I3, the output of the first inverter NOT_1 is low. When the input of the second inverter NOT_2 is low, its output is high. Since the positive input V2 of comparator COMP is fixed, VIN+ > VIN-. Therefore, the output Z of comparator COMP is high and ZN is low. Consequently, the sixth PMOS transistor P6 is turned off, and the eighth PMOS transistor P8 is turned on. The output voltage Vout = VCC - VDSP8 - VR7.

[0115] Where VDSP8 is the voltage between the drain and source of the eighth PMOS transistor P8, and VR7 is the voltage of the seventh resistor R7.

[0116] In some specific embodiments, see Figure 2 The switching transistor circuit 2 includes:

[0117] The fourth resistor R4 and the fifth resistor R5;

[0118] The first terminal of the fourth resistor R4 is connected to the common-mode input voltage Vinp, and the first terminal of the fifth resistor R5 is connected to the common-mode input voltage Vinn.

[0119] The second terminal of the fourth resistor R4 is connected to the second terminal of the fifth resistor R5.

[0120] Specifically, the switching transistor circuit 2 further includes:

[0121] The drain of the sixth PMOS transistor P6 is connected to the junction of the second terminal of the fourth resistor R4 and the second terminal of the fifth resistor R5.

[0122] The gate of the sixth PMOS transistor P6 is connected to the first output of the comparator COMP as the third input terminal of the switching transistor circuit 2.

[0123] The source of the sixth PMOS transistor P6 is connected to the output terminal of the switching transistor circuit 2.

[0124] Specifically, the switching transistor circuit 2 further includes:

[0125] The eighth PMOS transistor P8 and the seventh resistor R7;

[0126] The drain of the eighth PMOS transistor P8 is connected to the power supply VCC.

[0127] The gate of the eighth PMOS transistor P8 is connected to the second output terminal of the comparator COMP as the fourth input terminal of the switching transistor circuit 2.

[0128] The source of the eighth PMOS transistor P8 is connected to the first terminal of the seventh resistor R7, and the second terminal of the seventh resistor R7 is connected to the output terminal of the switching transistor circuit 2.

[0129] This application compares the input common-mode voltage with the power supply voltage using a comparison module and a shaping comparison module in the voltage switching circuit. When the power supply voltage is higher than the common-mode voltage, the power supply voltage is output through the switching transistor circuit to power the high-voltage circuit. When the common-mode voltage is higher than the power supply voltage, a switching circuit is used to switch the output of the common-mode voltage to power the high-voltage module circuit. This avoids the offset problem caused by using a large number of resistors to divide the voltage and increase the common-mode input voltage.

[0130] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A high common-mode input voltage switching circuit, characterized in that, include: Sampling and comparison circuit (1) and switching transistor circuit (2); The input terminal of the sampling comparison circuit (1) is connected to the common-mode input voltage and the power supply voltage, and the output terminal of the sampling comparison circuit (1) is connected to the input terminal of the switching transistor circuit (2). The output terminal of the switching transistor circuit (2) is the output terminal of the switching circuit, which is used to output the power supply voltage to the subsequent circuit. The sampling comparison circuit (1) includes: a feedback module (101), a comparison module (102), and a shaping comparison module (103). The input terminal of the feedback module (101) is connected to the power supply voltage VCC, and the output terminal of the feedback module (101) is connected to the first input terminal of the comparison module (102). The second input terminal of the comparison module (102) is connected to the common-mode input voltage. The output terminal of the comparison module (102) is connected to the input terminal of the shaping comparison module (103). The output terminal of the shaping comparison module (103) is connected to the input terminal of the switching transistor circuit (2) as the output terminal of the sampling comparison circuit (1).

2. The circuit according to claim 1, characterized in that, The feedback module (101) includes: The fourth current source I4, the first NMOS transistor N1, the second NMOS transistor N2, and the first resistor R1; The first terminal of the fourth current source I4 is connected to the power supply voltage VCC, the second terminal of the fourth current source I4 is connected to the drain of the first NMOS transistor N1, and a terminal is led out between the second terminal of the fourth current source I4 and the drain of the first NMOS transistor N1 and connected to the gate of the second NMOS transistor N2. The gate of the first NMOS transistor N1 is connected to the feedback terminal of the shaping and comparison module (103) as the input terminal of the feedback circuit. The source of the first NMOS transistor N1 is connected to the first terminal of the first resistor R1, and the second terminal of the first resistor R1 is grounded.

3. The circuit according to claim 1 or 2, characterized in that, The feedback module (101) further includes: The first PMOS transistor P1, the third resistor R3, and the first current source I1; The drain of the first PMOS transistor P1 is connected to the power supply voltage VCC, and a third resistor R3 is connected between the gate and the source of the first PMOS transistor P1. A terminal is led out between the gate of the first PMOS transistor P1 and the first end of the third resistor R3 to connect to the source of the second NMOS transistor N2 and to the first end of the first current source I1, and the second end of the first current source I1 is grounded. A terminal is led out between the source of the first PMOS transistor P1 and the second end of the third resistor R3 to connect to the drain of the second NMOS transistor N2. Furthermore, a terminal is led out between the source of the first PMOS transistor P1 and the second end of the third resistor R3 as the output terminal of the feedback circuit and connected to the input terminal of the comparator module (102).

4. The circuit according to claim 3, characterized in that, The comparison module (102) includes: First resistor R1, second PMOS transistor P2, third PMOS transistor P3, and second current source I2; The first end of the first resistor R1 is connected to the common-mode input voltage Vinn, and the second end of the second resistor R2 is connected to the drain of the second PMOS transistor P2. The gate and source of the second PMOS transistor P2 are connected, and the gate and source of the second PMOS transistor P2 are connected to the first terminal of the second current source I2, and the second terminal of the second current source I2 is grounded. The gate and source of the second PMOS transistor P2 are also connected to the gate of the third PMOS transistor P3.

5. The circuit according to claim 4, characterized in that, The comparison module (102) further includes: The second resistor R2, the fourth PMOS transistor P4, and the third NMOS transistor N3; The first end of the second resistor R2 is connected to the common-mode input voltage Vinp, the second end of the second resistor R2 is connected to the first end of the first resistor R1, and is also connected to the drain of the third PMOS transistor P3. The source of the third PMOS transistor P3 is connected to the drain of the fourth PMOS transistor P4. The gate of the fourth PMOS transistor P4 serves as the input terminal of the comparator module (102) and is connected to the source of the first PMOS transistor P1 in the feedback module (101) and the second terminal of the third resistor R3. The source of the fourth PMOS transistor P4 is connected to the drain of the third NMOS transistor N3. The drain of the third NMOS transistor N3 is connected to its gate and also to the gate of the fourth NMOS transistor N4. The source of the third NMOS transistor N3 is grounded.

6. The circuit according to claim 5, characterized in that, The comparison module (102) further includes: The third current source I3 and the fourth NMOS transistor N4; The first terminal of the third current source I3 is connected to the voltage level V1, and the second terminal of the third current source I3 is connected to the drain of the fourth NMOS transistor N4. A terminal is led out between the second end of the third current source I3 and the drain of the fourth NMOS transistor N4 as the output terminal of the comparator module (102) and connected to the input terminal of the shaping comparator module (103); The source of the fourth NMOS transistor N4 is grounded.

7. The circuit according to claim 6, characterized in that, The plastic surgery comparison module (103) includes: The first inverter NOT_1, the second inverter NOT_2, and the comparator COMP; The input terminal of the first inverter NOT_1 is connected to the second terminal of the third current source I3 in the comparison module (102) as the input terminal of the shaping comparison module (103); The output of the first inverter NOT_1 is connected to the first input of the comparator COMP, and the output of the first inverter NOT_1 is connected to the input of the second inverter NOT_2. The output of the second inverter NOT_2 is connected to the gate of the first NMOS transistor N1 in the feedback module (101) as the feedback terminal of the shaping comparison module (103). The second input terminal of comparator COMP is connected to a fixed level V2, and the first and second output terminals of comparator COMP are connected to the third and fourth input terminals of the switching transistor circuit (2).

8. The circuit according to claim 7, characterized in that, The switching transistor circuit (2) includes: The fourth resistor R4 and the fifth resistor R5; The first terminal of the fourth resistor R4 is connected to the common-mode input voltage Vinp, and the first terminal of the fifth resistor R5 is connected to the common-mode input voltage Vinn. The second terminal of the fourth resistor R4 is connected to the second terminal of the fifth resistor R5.

9. The circuit according to claim 8, characterized in that, The switching transistor circuit (2) also includes: The drain of the sixth PMOS transistor P6 is connected to the junction of the second terminal of the fourth resistor R4 and the second terminal of the fifth resistor R5. The gate of the sixth PMOS transistor P6 is connected to the first output terminal of the comparator COMP as the third input terminal of the switching transistor circuit (2); The source of the sixth PMOS transistor P6 is connected to the output terminal of the switching transistor circuit (2).

10. The circuit according to claim 9, characterized in that, The switching circuit (2) further includes: an eighth PMOS transistor P8 and a seventh resistor R7; the drain of the eighth PMOS transistor P8 is connected to the power supply VCC; the gate of the eighth PMOS transistor P8 serves as the fourth input terminal of the switching circuit (2) and is connected to the second output terminal of the comparator COMP; the source of the eighth PMOS transistor P8 is connected to the first terminal of the seventh resistor R7, and the second terminal of the seventh resistor R7 is connected to the output terminal of the switching circuit (2).

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