An adjustable adaptive biasing circuit for a power amplifier

Abstract

The application relates to an adjustable adaptive bias circuit for a power amplifier, which comprises a bias voltage generating circuit and a positive feedback voltage dividing circuit; the bias voltage generating circuit generates a bias voltage input to the positive feedback voltage dividing circuit, and the bias voltage input to the positive feedback voltage dividing circuit is adjusted through an adjustable current source in the bias voltage generating circuit; the positive feedback voltage dividing circuit forms a positive feedback mechanism through voltage division on a gate bias voltage Vcs input to the power amplifier, which automatically increases with the increase of input power, so that the power amplifier maintains high transconductance and gain at large power output, thereby inhibiting the gain compression phenomenon and realizing adaptive bias control. The circuit structure is simple, can realize real-time sensing of output power change and adaptive adjustment of the size of the bias voltage, dynamically enhances the bias voltage with the increase of the output power, thereby effectively offsets the gain compression effect, and maintains high and stable gain output in a wide power range.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, and more particularly to an adjustable adaptive bias circuit for a power amplifier. Background Technology

[0002] In radio frequency power amplifier (PA) design, the setting of the quiescent operating point of the bias circuit directly affects the amplifier's linearity, power, and large-signal output characteristics. Traditional solutions commonly use diode-connected MOS transistors to construct a fixed-voltage bias network. While this structure offers advantages such as circuit simplicity and good temperature stability, its output bias voltage remains essentially constant and cannot dynamically change with the PA's operating state. In practical applications, when the input signal power increases, leading to an increase in output power, factors such as power transistor current saturation, self-heating effects, or channel modulation cause a gradual decrease in transconductance, resulting in significant gain compression—that is, the output power growth rate is lower than the input power growth rate. This leads to a continuous decay of the system's effective gain, severely limiting signal fidelity and transmission efficiency in high-power scenarios.

[0003] The fundamental limitation of the aforementioned fixed bias mechanism lies in the disconnect between the static operating point and dynamic load conditions: under large-signal drive, constant bias struggles to compensate for performance degradation caused by transistor nonlinearity, instead exacerbating gain drops and harmonic distortion. Especially in applications like 5G communication and radar, which demand stringent output power flatness and linear dynamic range, traditional solutions cannot maintain gain stability in the high-power range, leading to insufficient system link budget redundancy or the need for additional post-amplification stages, increasing design complexity and power consumption. Therefore, there is an urgent need to develop a circuit architecture capable of real-time sensing of output power changes and adaptively adjusting the bias, allowing the bias level to dynamically increase with output power, effectively counteracting gain compression and maintaining high and stable gain output over a wide power range, providing crucial support for the design of high-performance power amplifiers. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide an adjustable adaptive bias circuit for power amplifiers, thus solving the deficiencies of the prior art.

[0005] The objective of this invention is achieved through the following technical solution: an adjustable adaptive bias circuit for a power amplifier, comprising a bias voltage generating circuit and a positive feedback voltage divider circuit, wherein the bias voltage generating circuit is connected to the positive feedback voltage divider circuit, and the positive feedback voltage divider circuit is connected to the power amplifier. The bias voltage generating circuit generates a bias voltage input to the positive feedback voltage divider circuit, and adjusts the bias voltage input to the positive feedback voltage divider circuit through an adjustable current source in the bias voltage generating circuit. The positive feedback voltage divider circuit forms a positive feedback mechanism on the gate bias voltage Vcs input to the power amplifier through voltage division. It automatically increases with the increase of input power, so that the power amplifier maintains high transconductance and gain when outputting high power, thereby suppressing gain compression and realizing adaptive bias control.

[0006] The bias voltage generation circuit includes: an adjustable current source Ibias, and NMOS transistors MN0 and MN2; The source of NMOS transistor MN2 is connected to the drain of MN0, and the gates of MN0 and MN2 are connected to their respective sources. The adjustable current source Ibias is connected to the drain of NMOS transistor MN2, and the gates of MN0 and MN2 are also connected to a positive feedback voltage divider circuit. The adjustable current source Ibias provides current bias to NMOS transistors MN0 and MN2 and generates bias voltages vbn1 and vbn2. By adjusting the current of the adjustable current source Ibias, the magnitude of the bias voltages vbn1 and vbn2 can be adjusted.

[0007] The positive feedback voltage divider circuit includes: NMOS transistors MN1 and MN3, and resistors R1 and R2; The resistors R1 and R2 are connected in series between the source of NMOS transistor MN3 and the drain of MN1. The gate of MN3 is connected to a bias voltage vbn2, and the gate of MN1 is connected to a bias voltage vbn1. The two bias voltages are only affected by the adjustment of the adjustable current source Ibias, and are not affected by the RF input power RFin. When the bias voltage is kept constant, the change of RF input power RFin causes the gate-source voltage of MN3 to change. A positive feedback mechanism is formed through resistors R1 and R2 to realize the dynamic adjustment of the gate bias voltage Vcs of the power amplifier.

[0008] The circuit's operation includes: As the RF input power RFI gradually increases, the NMOS transistor MN1 detects the RF input signal. As the RF input power RFI increases, the drain-source voltage Vds, i.e. Vcs, of MN1 increases due to the increase in the envelope of the RF input signal. The increase in Vcs is transmitted to the source of MN3 through the voltage divider of resistors R1 and R2, causing the gate voltage Vs2 of MN3 to increase. Since vbn2 is provided by a constant bias and remains unchanged, the gate-source voltage Vgs = vbn2 - Vs2 of MN3 will decrease, resulting in a decrease in the bias current flowing through MN3, that is, a decrease in the current flowing through resistors R1 and R2, which in turn leads to a decrease in the voltage drop across resistors R1 and R2, thus accelerating the increase in Vcs voltage and forming a positive feedback mechanism to achieve dynamic adjustment of Vcs. Ultimately, Vcs serves as the gate bias voltage of the power amplifier, which automatically increases with the increase of RF input power, enabling the power amplifier to maintain high transconductance and gain at high power output, thereby suppressing gain compression and achieving adaptive bias control.

[0009] The present invention has the following advantages: an adjustable adaptive bias circuit for a power amplifier has a simple circuit structure, can sense changes in output power in real time and adaptively adjust the magnitude of the bias voltage, so that the bias voltage dynamically increases with the increase of output power, thereby effectively offsetting the gain compression effect and maintaining a high and stable gain output over a wide power range. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of the circuit structure of the present invention. Detailed Implementation

[0011] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the detailed description of the embodiments of this application provided below with reference to the accompanying drawings is not intended to limit the scope of protection of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application. The present invention will be further described below with reference to the accompanying drawings.

[0012] Specifically, this invention relates to an adjustable adaptive bias circuit for a power amplifier. The output voltage of this bias circuit can increase with the increase of the PA input power, and the magnitude of the Ibias current can be adjusted to manually configure the value of the voltage, thereby improving the PA output power and gain.

[0013] like Figure 1 As shown, this invention consists of NMOS transistors MN0, MN1, MN2, and MN3, an adjustable current source Ibias, and resistors R1 and R2. The current source Ibias provides current bias to MN2 and MN0 and generates bias voltages vbn1 and vbn2. The voltage magnitudes of vbn1 and vbn2 can be adjusted by regulating the current in the current source. Resistors R1 and R2 are connected in series in the current path between MN1 and MN3 to form positive feedback and generate a voltage divider Vcg. MN1 mainly functions as a power detector. o is the output impedance of transistor MN1.

[0014] In this circuit, MN0 and MN2 are diodes connected. The voltage values ​​of vbn1 and vbn2 are adjusted by regulating the ibias current. Vbn1 and vbn2 remain constant and are unaffected by the input power RFin. The circuit operation is as follows: 1. As the RF input power RFin gradually increases, NMOS transistor MN1 detects the RF input signal. With the increase in input power, the drain-source voltage Vds of MN1 (i.e., node Vcs) will increase slightly due to the increase in the envelope of the input signal; 2. Since resistors R1 and R2 are connected in series on the source path of MN3, the rise of Vcs will be transmitted to the source of MN3 through the voltage divider network of R1 and R2, causing its source voltage Vs2 to rise accordingly. 3. Since vbn2 is provided by a constant bias and remains basically unchanged, the gate-source voltage Vgs = vbn2-Vs2 of MN3 will decrease accordingly, resulting in a decrease in the bias current Io flowing through MN3. 4. As the current Io flowing through R1 and R2 decreases, the voltage drop across R1 and R2 decreases, further accelerating the rise of Vcs voltage, forming a positive feedback mechanism, and realizing dynamic adjustment of Vcs. 5. Finally, Vcs serves as the gate bias voltage of the PA, which automatically increases with the increase of input power, enabling the PA to maintain high transconductance and gain when outputting high power, effectively suppressing gain compression and achieving adaptive bias control.

[0015] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and improvements, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. An adjustable adaptive bias circuit for a power amplifier, characterized in that: It includes a bias voltage generating circuit and a positive feedback voltage divider circuit, wherein the bias voltage generating circuit is connected to the positive feedback voltage divider circuit, and the positive feedback voltage divider circuit is connected to the power amplifier. The bias voltage generating circuit generates a bias voltage input to the positive feedback voltage divider circuit, and adjusts the bias voltage input to the positive feedback voltage divider circuit through an adjustable current source in the bias voltage generating circuit. The positive feedback voltage divider circuit forms a positive feedback mechanism on the gate bias voltage Vcs input to the power amplifier through voltage division. It automatically increases with the increase of input power, so that the power amplifier maintains high transconductance and gain when outputting high power, thereby suppressing gain compression and realizing adaptive bias control.

2. The adjustable adaptive bias circuit for a power amplifier according to claim 1, characterized in that: The bias voltage generation circuit includes: an adjustable current source Ibias, and NMOS transistors MN0 and MN2; The source of NMOS transistor MN2 is connected to the drain of MN0, and the gates of MN0 and MN2 are connected to their respective sources. The adjustable current source Ibias is connected to the drain of NMOS transistor MN2, and the gates of MN0 and MN2 are also connected to a positive feedback voltage divider circuit. The adjustable current source Ibias provides current bias to NMOS transistors MN0 and MN2 and generates bias voltages vbn1 and vbn2. By adjusting the current of the adjustable current source Ibias, the magnitude of the bias voltages vbn1 and vbn2 can be adjusted.

3. The adjustable adaptive bias circuit for a power amplifier according to claim 2, characterized in that: The positive feedback voltage divider circuit includes: NMOS transistors MN1 and MN3, and resistors R1 and R2; The resistors R1 and R2 are connected in series between the source of NMOS transistor MN3 and the drain of MN1. The gate of MN3 is connected to a bias voltage vbn2, and the gate of MN1 is connected to a bias voltage vbn1. The two bias voltages are only affected by the adjustment of the adjustable current source Ibias, and are not affected by the RF input power RFin. When the bias voltage is kept constant, the change of RF input power RFin causes the gate-source voltage of MN3 to change. A positive feedback mechanism is formed through resistors R1 and R2 to realize the dynamic adjustment of the gate bias voltage Vcs of the power amplifier.

4. The adjustable adaptive bias circuit for a power amplifier according to claim 3, characterized in that: The circuit's operation includes: As the RF input power RFI gradually increases, the NMOS transistor MN1 detects the RF input signal. As the RF input power RFI increases, the drain-source voltage Vds, i.e. Vcs, of MN1 increases due to the increase in the envelope of the RF input signal. The increase in Vcs is transmitted to the source of MN3 through the voltage divider of resistors R1 and R2, causing the gate voltage Vs2 of MN3 to increase. Since vbn2 is provided by a constant bias and remains unchanged, the gate-source voltage Vgs = vbn2 - Vs2 of MN3 will decrease, resulting in a decrease in the bias current flowing through MN3, that is, a decrease in the current flowing through resistors R1 and R2, which in turn leads to a decrease in the voltage drop across resistors R1 and R2, thus accelerating the increase in Vcs voltage and forming a positive feedback mechanism to achieve dynamic adjustment of Vcs. Ultimately, Vcs serves as the gate bias voltage of the power amplifier, which automatically increases with the increase of RF input power, enabling the power amplifier to maintain high transconductance and gain at high power output, thereby suppressing gain compression and achieving adaptive bias control.

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