Power amplifier assembly and multi-stage amplifier system

Abstract

Power amplifier assemblies and multi-stage amplifier systems include a first semiconductor die and a second semiconductor die, each semiconductor die including an integrated transistor. The second semiconductor die is physically and electrically coupled to a die mount interface at a mounting surface of the first semiconductor die in a "flip-chip" orientation. This arrangement provides a multi-stage amplifier including the integrated transistor of the first semiconductor die coupled in a cascaded arrangement with the integrated transistor of the second semiconductor die. The first semiconductor die and the second semiconductor die can be formed of different semiconductor materials.

Description

Technical Field

[0001] This invention generally relates to multi-stage amplifier systems. More specifically, this invention relates to amplifier systems having multiple power amplifiers implemented using transistors in multiple semiconductor dies. Background Technology

[0002] Multistage power amplifiers typically include an amplifier substrate (e.g., a printed circuit board (PCB)) and a plurality of semiconductor dies carrying transistors coupled to a mounting surface of the amplifier substrate (e.g., one die for each of multiple amplification stages). When two amplification stages are coupled in a cascaded arrangement, the output (e.g., the drain terminal) of a first transistor in a first semiconductor die is electrically coupled through the amplifier substrate to the input (e.g., the gate terminal) of a second transistor in a second semiconductor die. In some cases, the amplifier substrate may also support impedance matching circuitry between the output of the first transistor and the input of the second transistor. To dissipate heat from the semiconductor die during operation, the die may be connected to a thermally conductive "coin" or thermal via in the amplifier substrate.

[0003] The overall size (e.g., footprint) of a multistage amplifier includes the PCB area occupied by multiple semiconductor dies and impedance matching circuitry (if included), as well as the area occupied by any additional circuitry associated with the amplifier (e.g., biasing circuitry, input / output connectors, etc.). With the ongoing trend towards miniaturization, amplifier designers are striving to develop multistage amplifiers and thermal systems that occupy less space without sacrificing performance. Summary of the Invention

[0004] According to a first aspect of the present invention, a power amplifier assembly is provided, comprising: a first semiconductor die formed of a first semiconductor material, the first semiconductor die including a mounting surface, a first die input terminal, a first die output terminal, a first transistor, and a die mounting interface, wherein the die mounting interface is located at the mounting surface, and the die mounting interface includes at least one first contact pad, at least one second contact pad, and at least one third contact pad, and the first transistor is integrally formed within the first semiconductor die, and the first transistor includes a first transistor gate terminal electrically coupled to the first die input terminal and a first transistor drain terminal electrically coupled to the at least one first contact pad of the die mounting interface; and a second semiconductor die formed of a second semiconductor material, wherein the second semiconductor die is physically and electrically coupled at the mounting surface of the first semiconductor die. The semiconductor die is connected to the die mounting interface, and the second semiconductor die includes a second die interface surface and a second transistor, wherein the second transistor is integrally formed within the second semiconductor die, and the second transistor includes a second transistor gate terminal coupled to at least one second transistor gate pad located on the second die interface surface, a second transistor source region coupled to at least one second transistor source pad located on the second die interface surface, and a second transistor drain terminal coupled to at least one second transistor drain pad located on the second die interface surface. The at least one second transistor gate pad is physically and electrically coupled to the at least one first contact pad, the at least one second transistor source pad is physically and electrically coupled to the at least one second contact pad, and the at least one second transistor drain pad is physically and electrically coupled to the at least one third contact pad.

[0005] In one or more embodiments, the first semiconductor material of the first semiconductor die is selected from the group consisting of silicon and silicon carbide; and the second semiconductor material of the second semiconductor die is selected from the group consisting of gallium nitride, gallium arsenide, gallium phosphide, indium phosphide and indium antimonide.

[0006] In one or more embodiments, the power amplifier assembly further includes a die-to-die interconnect system that physically and electrically couples the first semiconductor die and the second semiconductor die together, wherein the die-to-die interconnect system includes a plurality of direct solder connections between the at least one first contact pad, the at least one second contact pad, and the at least one third contact pad and the at least one second transistor gate pad, the at least one second transistor source pad, and the at least one second transistor drain pad.

[0007] In one or more embodiments, the power amplifier assembly further includes: a die-to-die interconnect system that physically and electrically couples the first semiconductor die and the second semiconductor die together, wherein the die-to-die interconnect system includes at least one first conductive post connected between the at least one first contact pad and the at least one second transistor gate pad, at least one second conductive post connected between the at least one second contact pad and the at least one second transistor source pad, and at least one third conductive post connected between the at least one third contact pad and the at least one second transistor drain pad.

[0008] In one or more embodiments, the first semiconductor die further includes: a bottom surface opposite to the mounting surface; a ground reference node at the bottom surface; and a conductive through-substrate via electrically coupling the at least one second contact pad to the ground reference node.

[0009] In one or more embodiments, the ground reference node includes a conductive layer at the bottom surface of the first semiconductor die; the first die input terminal is located at the mounting surface of the first semiconductor die and includes a first bonding pad configured to connect to one or more input lead bonding pads; and the first die output terminal is located at the mounting surface of the first semiconductor die and includes a second bonding pad configured to connect to one or more output lead bonding pads.

[0010] In one or more embodiments, the second bonding pad and the at least one third contact pad form a portion of a single conductive feature.

[0011] In one or more embodiments, the first semiconductor die further includes: a first conductive feature formed by a first portion of a patterned conductive layer at the bottom surface of the first semiconductor die, wherein the first conductive feature corresponds to an input terminal of the first die; a second conductive feature formed by a second portion of the patterned conductive layer, wherein the first conductive feature and the second conductive feature are separated by a first non-conductor region at the bottom surface, and wherein the second conductive feature corresponds to the ground reference node; a third conductive feature formed by a third portion of the patterned conductive layer, wherein the second conductive feature and the third conductive feature are separated by a second non-conductor region at the bottom surface, and wherein the third conductive feature corresponds to an output terminal of the first die; a first conductive through-substrate via electrically coupling the gate terminal of the first transistor to the first conductive feature; a second conductive through-substrate via electrically coupling the at least one second contact pad to the second conductive feature; and a third conductive through-substrate via electrically coupling the at least one third contact pad to the third conductive feature.

[0012] In one or more embodiments, the first conductive through-hole in the substrate is lined with a dielectric material; and

[0013] The dielectric material is lining the third conductive through-hole in the substrate.

[0014] In one or more embodiments, the first semiconductor die further includes an impedance matching circuit electrically connected between the drain terminal of the first transistor and the at least one first contact pad of the die mounting interface.

[0015] According to a second aspect of the present invention, a multi-stage amplifier system is provided, comprising: a system substrate, the system substrate including a top surface of the substrate, an amplifier input terminal, and an amplifier output terminal; a power amplifier assembly coupled to the top surface of the substrate, wherein the power amplifier assembly includes a first semiconductor die and a second semiconductor die, wherein the first semiconductor die is formed of a first semiconductor material, and the first semiconductor die includes a mounting surface, a bottom surface, a first die input terminal electrically coupled to the amplifier input terminal, a first die output terminal electrically coupled to the amplifier output terminal, a first transistor, and a die mounting interface, wherein the die mounting interface is located at the mounting surface, and the die mounting interface includes at least one first contact pad, at least one second contact pad, and at least one third contact pad, and the first transistor is integrally formed within the first semiconductor die, and the first transistor includes a first transistor gate terminal electrically coupled to the first die input terminal and a first transistor drain terminal electrically coupled to the at least one first contact pad of the die mounting interface; The second semiconductor die is formed of a second semiconductor material, wherein the second semiconductor die is physically and electrically coupled to the die mounting interface at the mounting surface of the first semiconductor die, and the second semiconductor die includes a second die interface surface, a second surface opposite to the second die interface surface, and a second transistor, wherein the second transistor is integrally formed within the second semiconductor die, and the second transistor includes a second transistor gate terminal coupled to at least one second transistor gate pad located at the second die interface surface, a second transistor source region coupled to at least one second transistor source pad located at the second die interface surface, and a second transistor drain terminal coupled to at least one second transistor drain pad located at the second die interface, the at least one second transistor gate pad being physically and electrically coupled to the at least one first contact pad, the at least one second transistor source pad being physically and electrically coupled to the at least one second contact pad, and the at least one second transistor drain pad being physically and electrically coupled to the at least one third contact pad.

[0016] In one or more embodiments, the first semiconductor material of the first semiconductor die is selected from the group consisting of silicon and silicon carbide; and the second semiconductor material of the second semiconductor die is selected from the group consisting of gallium nitride, gallium arsenide, gallium phosphide, indium phosphide and indium antimonide.

[0017] In one or more embodiments, the power amplifier assembly is coupled to the top surface of the substrate such that the bottom surface of the first semiconductor die faces the top surface of the substrate.

[0018] In one or more embodiments, the power amplifier assembly further includes: a packaging material above the mounting surface of the first semiconductor die and surrounding the sidewalls of the second semiconductor die, wherein the second surface of the second semiconductor die is exposed at the top surface of the packaging material; and a heat dissipation structure coupled to the top surface of the packaging material and the second surface of the second semiconductor die.

[0019] In one or more embodiments, the system substrate further includes a ground reference pad located on the top surface of the substrate between the amplifier input pad and the amplifier output pad; and the first semiconductor die further includes a first conductive feature formed by a first portion of a patterned conductive layer on the bottom surface of the first semiconductor die, wherein the first conductive feature corresponds to the first die input terminal; a second conductive feature formed by a second portion of the patterned conductive layer; wherein the first conductive feature and the second conductive feature are separated by a first non-conductor region on the bottom surface; wherein the second conductive feature corresponds to the ground reference node; and wherein the second conductive feature is coupled to the ground reference node. The system substrate has a ground reference pad, a third conductive feature formed by a third portion of the patterned conductive layer, wherein the second conductive feature and the third conductive feature are separated by a second non-conductor region on the bottom surface, and wherein the third conductive feature corresponds to the first die output terminal, a first conductive through-substrate via electrically couples the first transistor gate terminal to the first conductive feature, a second conductive through-substrate via electrically couples at least one second contact pad to the second conductive feature, and a third conductive through-substrate via electrically couples at least one third contact pad to the third conductive feature.

[0020] In one or more embodiments, the power amplifier assembly is coupled to the top surface of the substrate such that the second surface of the second semiconductor die faces the top surface of the substrate; the system substrate further includes a heat dissipation structure embedded in the system substrate and exposed at the top surface of the substrate; and the power amplifier assembly further includes an encapsulation material above the mounting surface of the first semiconductor die and surrounding the sidewalls of the second semiconductor die, wherein the second surface of the second semiconductor die is exposed at the top surface of the encapsulation material, and the second surface of the second semiconductor die is thermally coupled to the heat dissipation structure.

[0021] In one or more embodiments, the power amplifier assembly further includes a die-to-die interconnect system that physically and electrically couples the first semiconductor die and the second semiconductor die together, wherein the die-to-die interconnect system includes a plurality of direct solder connections between the at least one first contact pad, the at least one second contact pad, and the at least one third contact pad and the at least one second transistor gate pad, the at least one second transistor source pad, and the at least one second transistor drain pad.

[0022] In one or more embodiments, the power amplifier assembly further includes: a die-to-die interconnect system that physically and electrically couples the first semiconductor die and the second semiconductor die together, wherein the die-to-die interconnect system includes at least one first conductive post connected between the at least one first contact pad and the at least one second transistor gate pad, at least one second conductive post connected between the at least one second contact pad and the at least one second transistor source pad, and at least one third conductive post connected between the at least one third contact pad and the at least one second transistor drain pad.

[0023] In one or more embodiments, the first semiconductor die further includes an impedance matching circuit electrically connected between the drain terminal of the first transistor and the at least one first contact pad of the die mounting interface.

[0024] In one or more embodiments, the multistage amplifier system further includes a final amplifier stage physically coupled to the system substrate, wherein the final amplifier stage includes a final stage input electrically coupled to the output of the first die and a final stage output electrically coupled to the output of the amplifier. Attached Figure Description

[0025] The same reference numerals in the accompanying drawings refer to the same or similarly functional elements throughout the individual views. The drawings are not necessarily drawn to scale and are incorporated into and form part of the specification together with the following detailed description. The drawings are used to further illustrate various embodiments and explain various principles and advantages, all of which are consistent with the present invention.

[0026] Figure 1 A top view of a power amplifier assembly according to an embodiment is shown;

[0027] Figure 2A Illustrations according to embodiments Figure 1 A side cross-sectional view of the power amplifier assembly along line 2-2;

[0028] Figure 2B An illustration according to another embodiment Figure 1 A side cross-sectional view of the power amplifier assembly along line 2-2;

[0029] Figure 2C An illustration is shown according to yet another embodiment. Figure 1 A side cross-sectional view of the power amplifier assembly along line 2-2;

[0030] Figure 3 A top view of a power amplifier assembly according to another embodiment is shown;

[0031] Figure 4A Illustrations according to embodiments Figure 3 A side cross-sectional view of the power amplifier assembly along line 4-4;

[0032] Figure 4B An illustration according to another embodiment Figure 3 A side cross-sectional view of the power amplifier assembly along line 4-4;

[0033] Figure 4C An illustration is shown according to yet another embodiment. Figure 3 A side cross-sectional view of the power amplifier assembly along line 4-4;

[0034] Figure 5A Illustrations according to embodiments Figure 1 A top view of the first semiconductor die of a power amplifier assembly of type 3;

[0035] Figure 5B An illustration according to another embodiment Figure 1 A top view of the first semiconductor die of a power amplifier assembly of type 3;

[0036] Figure 6A Illustrations according to embodiments Figure 1 A top view of the second semiconductor die of the power amplifier assembly of type 3;

[0037] Figure 6B An illustration according to another embodiment Figure 1 A top view of the second semiconductor die of the power amplifier assembly of type 3;

[0038] Figure 7A Illustrations according to embodiments Figure 6A A side cross-sectional view of the second semiconductor die along line 7A-7A;

[0039] Figure 7B Illustrations according to embodiments Figure 6B A side cross-sectional view of the second semiconductor die along line 7B-7B;

[0040] Figure 8 A top view of a multi-stage amplifier system according to an embodiment is shown;

[0041] Figure 9 A top view of a multistage amplifier system according to another embodiment is shown;

[0042] Figure 10 This is a top view of a Dougherty power amplifier module according to an embodiment, the Dougherty power amplifier module including a first power amplifier component for a carrier amplifier and a second power amplifier component for a peak amplifier;

[0043] Figure 11 This is a top view of a Dougherty power amplifier including dual-input, dual-output drive power amplifier components according to an embodiment;

[0044] Figure 12 A side cross-sectional view of a multi-stage amplifier system with a top-side cooling arrangement according to an embodiment is shown;

[0045] Figure 13 A side cross-sectional view of a multi-stage amplifier system with a top-side cooling arrangement according to another embodiment is shown; and

[0046] Figure 14 A side cross-sectional view of a multistage amplifier system with a bottom-side cooling arrangement according to another embodiment is shown. Detailed Implementation

[0047] In general, the embodiments disclosed herein include power amplifier assemblies and multi-stage amplifier systems comprising a first semiconductor die and a second semiconductor die, each semiconductor die including an integrated transistor. The second semiconductor die is physically and electrically coupled in a "flip-chip" orientation to a die-mount interface at a mounting surface of the first semiconductor die. This arrangement provides a compact multi-stage amplifier including integrated transistors of the first semiconductor die coupled in a cascaded arrangement to the integrated transistors of the second semiconductor die. In some embodiments, the first and second semiconductor dies may be formed of different semiconductor materials, but in other embodiments they may be formed of the same semiconductor material.

[0048] The power amplifier assemblies of the various embodiments described herein may offer certain technical advantages over conventional multistage power amplifiers. For example, the power amplifier assemblies of the various embodiments may include multiple amplification stages that consume a significantly smaller area on the system substrate than those required by conventional multistage power amplifiers (i.e., have a much smaller footprint). Furthermore, as will be described in detail later, the power amplifier assemblies of the various embodiments are suitable for attachment to top-side and bottom-side cooling structures, which may be ideal because a given type of cooling structure can enable a reduction in overall system size.

[0049] Figure 1 A top view of a power amplifier assembly 100, 100', or 100" according to one or more embodiments is shown. For enhanced understanding, Figure 1 Should be with Figure 2A , 2B View simultaneously with 2C. Figure 2A , 2B And 2C shows Figure 1 Three side cross-sectional views of several embodiments of the power amplifier assemblies 100, 100', 100" along line 2-2. The power amplifier assemblies 100, 100', 100" include a first semiconductor die 110 and a second semiconductor die 150 physically and electrically coupled together. As will be discussed in more detail below, the first semiconductor die 110 includes a first transistor 130 (corresponding to a first amplification stage), and the second semiconductor die 150 includes a second transistor 170 (corresponding to a second amplification stage). The first transistor 130 and the second transistor 170 are electrically coupled in a cascaded arrangement to provide a two-stage power amplifier implemented in the power amplifier assemblies 100, 100', 100"

[0050] Furthermore, as will be described in detail below, the first semiconductor die 110 includes a die mounting interface 142 to which the second semiconductor die 150 is "flip-chip" mounted. This configuration produces power amplifier assemblies 100, 100', 100" in which the first transistor 130 and the second transistor 170 of the first semiconductor die 110 and the second semiconductor die 150 are electrically coupled in a manner that does not require an intervention circuit system on a separate PCB, as is done in conventional multistage power amplifiers. As stated above, the flip-chip connection between the first semiconductor die 110 and the second semiconductor die 150 produces a multistage amplifier that consumes a significantly smaller area than a conventional multistage power amplifier (i.e., occupies a significantly smaller footprint).

[0051] The first semiconductor die 110 includes a mounting surface 111, an opposite bottom surface 112, a first die input terminal 125, a first die output terminal 127, a first transistor 130, and a die mounting interface 142. According to one or more embodiments, the first semiconductor die 110 may further include an interstage matching circuit 141 electrically coupled between the first transistor 130 and the die mounting interface 142.

[0052] The first semiconductor die 110 includes a substrate semiconductor substrate 116 and a multilayer structure 118 formed on the substrate semiconductor substrate 116. The material of the substrate semiconductor substrate 116 classifies the first transistor 130. For example, the first transistor 130 may be a silicon-based field-effect transistor (FET) (e.g., a laterally diffused metal-oxide-semiconductor (LDMOS) FET) or another type of FET. Therefore, according to one or more embodiments, the substrate semiconductor substrate 116 may include one or more layers of a first semiconductor material (e.g., a material selected from silicon, silicon carbide (SiC), or other materials).

[0053] The conductive layer 124 on the bottom surface of the substrate semiconductor substrate 116 can be used as a ground reference node for power amplifier assemblies 100, 100', 100" . Finally, as will be discussed later Figure 8 As described, when the power amplifier components 100, 100', 100" are incorporated into a larger electronic system, the conductive layer 124 can be coupled to a system ground structure, which in turn is coupled to a system ground reference voltage or another DC voltage.

[0054] The multilayer structure 118 includes multiple patterned conductive layers 119 and 120 interleaved with multiple dielectric material layers 121 and 122. Portions of the different patterned conductive layers 119 and 120 are electrically coupled to conductive vias. Although Figure 2A-2C Only two patterned conductive layers 119, 120 and two dielectric material layers 121, 122 are shown, but more or fewer of one or two types of layers can be used to provide the necessary wiring and connections for the first transistor 130, the interstage matching circuit 141 and the die mounting interface 142.

[0055] The first die input terminal 125, the first die output terminal 127, and the die mounting interface 142 are exposed at the mounting surface 111 of the first semiconductor die 110. For example, the first die input terminal 125, the first die output terminal 127, and the conductive pads 143, 144, and 145 of the die mounting interface 142 can be formed from a portion of the uppermost patterned conductive layer 120 in the multilayer structure 118. Furthermore, as described below, the first die input terminal 125, the first die output terminal 127, and the conductive pads 143, 144, and 145 of the die mounting interface 142 can be exposed through openings in the uppermost dielectric material layer 122, which can be used as a solder mask.

[0056] According to an embodiment, a first die input terminal 125 is located near a first side of a first semiconductor die 110, and a first die output terminal 127 is located near a second, opposite side of the semiconductor die 110. Both the first die input terminal 125 and the first die output terminal 127 are configured to connect to a first wire bond 106 and a second wire bond 107 (also referred to as input wire bond 106 and output wire bond 107), respectively. Figure 8 In more detail, the first wire bond 106 may have a connection to the system substrate (e.g., system substrate 801). Figure 8 The first end of the input signal trace () Figure 1 (or not shown in 2A-C), and the second end connected to the first die input terminal 125, as shown. Figure 1 and 2A As shown in -C. Similarly, the second wire bond 107 may have a first end connected to the first die output 127, as shown in Figure 107. Figure 1 and 2A -C is shown, and connected to the system substrate (e.g., system substrate 801, Figure 8 The second end of the output signal trace () Figure 1 and 2A -C (not shown). During operation, an input signal (e.g., a radio frequency (RF) input signal) can be received via the first lead bond 106, and an output signal (e.g., an amplified version of the RF input signal) can be provided via the second lead bond 107.

[0057] The first transistor 130 is integrally formed within the first semiconductor die 110. More specifically, the first transistor 130 includes a first transistor gate terminal 131 and a first transistor drain terminal 134 (e.g., formed by a portion of a patterned conductive layer 119) formed in a multilayer structure 118, and a plurality of doped and unintentionally doped regions in the substrate semiconductor substrate 116, corresponding to a drain region (not shown), a source region (not shown), and a channel region (not shown) disposed between the drain and source regions. Additionally, the first transistor 130 includes a plurality of gates (not shown) in the multilayer structure 118, wherein the gates are overlaid on the channel regions.

[0058] The gate terminal 131 of the first transistor is located near the first side of the first semiconductor die 110. The gate terminal 131 of the first transistor is electrically coupled to the input terminal 125 of the first die through a conductive path 140 in the multilayer structure 118. The conductive path 140 includes conductive portions of patterned conductive layers 119 and 120 and conductive vias between the conductive portions.

[0059] The drain terminal 134 of the first transistor is located between the first transistor 130 and the die mounting interface 142. A drain region, a source region, and a channel region are disposed in the active region of the die 110 between the gate terminal 131 and the drain terminal 134. The proximal end of the gate is electrically coupled to the gate terminal 131 of the first transistor, and the proximal end of the drain region is electrically coupled to the drain terminal 134 of the first transistor. The source region is electrically coupled to a ground reference node (e.g., to a conductive layer 124 on the bottom surface of the substrate semiconductor substrate 116) through one or more through-substrate vias (TSVs) or sink regions 137. During operation, a time-varying signal applied to the gate terminal 131 of the first transistor (and thus to the gate) alters the conductivity of the underlying channel region, causing a time-varying current to flow between the source and drain regions (and thus between the ground reference and the drain terminal 134).

[0060] As described above, the interstage impedance matching circuit 141 can be electrically coupled between the first die drain terminal 134 and the die mounting interface 142. More specifically, the impedance matching circuit 141 can be electrically coupled between the first die drain terminal 134 and at least one first contact pad 143 of the die mounting interface 142. The interstage impedance matching circuit 141 is configured to provide impedance matching between the first transistor 130 and the second transistor 170. Various impedance matching circuits can be implemented for the network 141. For example, the interstage impedance matching circuit 141 can simply include an inductor (e.g., an integrated spiral inductor or a discrete inductor coupled to the mounting surface 111 of the first semiconductor die 110). Alternatively, the interstage impedance matching circuit 141 can include a T-matching network (e.g., two series inductors, with a shunt capacitor coupled between the two series inductors) or another type of impedance matching circuit. In some embodiments, the interstage impedance matching circuit 141 can be excluded, and the first die drain terminal 134 can be directly coupled to the die mounting interface 142.

[0061] The die mounting interface 142 is located at the mounting surface 111. The die mounting interface 142 includes at least one first contact pad 143, at least one second contact pad 144, and at least one third contact pad 145. The first contact pad 143, the second contact pad 144, and the third contact pad 145 are all arranged within a perimeter (in Figure 5A and 5B (Represented by the dashed box labeled 142). The perimeter defines the area where the second semiconductor die 150 is flip-chip mounted to the first semiconductor die 110.

[0062] As described above, at least one first contact pad 143 is electrically coupled to the first die drain terminal 134 via a conductive path (unlabeled) in the multilayer structure 118 (possibly via interstage impedance matching circuit 141). As will be explained below, at least one first contact pad 143 is configured to be coupled to at least one gate bonding pad 173 of the signal and ground interface 164 of the second semiconductor die 150 via die-to-die interconnect system 186, 186', or 186"

[0063] At least one second contact pad 144 is electrically coupled to a conductive layer 124 at the bottom of the first semiconductor die 110 (e.g., to a ground reference node) via a conductive path (including one or more TSVs 146). As will be explained below, at least one second contact pad 144 is configured to be coupled to at least one source bonding pad 179 of the signal and ground interface 164 of the second semiconductor die 150 via a die-to-die interconnect system 186, 186', or 186"

[0064] At least one third contact pad 145 is electrically coupled to the first die output terminal 127. In some embodiments, the at least one third contact pad 145 and the first die output terminal 127 form a portion of a single conductive feature. In other embodiments, the at least one third contact pad 145 and the first die output terminal 127 can be electrically coupled via conductive paths in the multilayer structure 118. As will be explained below, the at least one third contact pad 145 is configured to be coupled via die-to-die interconnect system 186, 186', or 186" to at least one drain bonding pad 176 of the signal and ground interface 164 of the second semiconductor die 150.

[0065] The second semiconductor die 150 includes a second die interface surface 151, a second surface 152 opposite to the second die interface surface 151, a signal and ground interface 164, and a second transistor 170. (Brief Reference) Figure 7A , Figure 7A This is a side cross-sectional view of an embodiment of the second semiconductor die 150, which includes a substrate semiconductor substrate 156 and a multilayer structure 158 formed on the substrate semiconductor substrate 156.

[0066] The material of the substrate semiconductor substrate 156 categorizes the second transistor 170. For example, the second transistor 170 may be a III-V FET (e.g., gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), or indium antimonide (InSb) FET) or another type of FET. Therefore, according to one or more embodiments, the substrate semiconductor substrate 156 may include one or more layers of a second semiconductor material (e.g., a material selected from GaN, GaAs, GaP, InP, InSb). According to one or more embodiments, the second semiconductor material of the second semiconductor die 150 is different from the first semiconductor material of the first semiconductor die 110. According to other embodiments, the first semiconductor material and the second semiconductor material may be the same (e.g., the first semiconductor material and the second semiconductor material may include silicon, SiC, GaN, GaAs, GaP, InP, InSb, or other suitable materials).

[0067] The multilayer structure 158 includes multiple patterned conductive layers 159 and 160 interlaced with multiple dielectric material layers 161 and 162. Portions of the different patterned conductive layers 159 and 160 are electrically coupled to conductive vias. Although Figure 2A-2C Only two patterned conductive layers 159, 160 and two dielectric material layers 161, 162 are shown, but more or fewer of one or two types of layers can be used to provide the necessary wiring and connections for the second transistor 170.

[0068] Also refer to Figure 1 ,2A 2B and 2C, the second transistor 170 is integrally formed within the second semiconductor die 150. More specifically, the second transistor 170 includes a second transistor gate terminal 171 and a second transistor drain terminal 174 (e.g., formed by a portion of a patterned conductive layer 159) formed in a multilayer structure 158, and a plurality of doped and unintentionally doped regions in the substrate semiconductor substrate 156, these regions corresponding to drain regions (e.g., drain region 175, ...). Figure 6A ), source pole region (e.g., source pole region 178, Figure 6A The second transistor 170 includes a channel region (not labeled) disposed between the drain region and the source region in the multilayer structure 158. Additionally, the second transistor 170 includes multiple gates (e.g., gate 172, ...) in the multilayer structure 158. Figure 6A ), wherein the gate is overlaid on the channel region.

[0069] The gate terminal 171 of the second transistor is located near the first side of the second semiconductor die 150, and the drain terminal 174 of the second transistor is located near the opposite second side of the second semiconductor die 150. A drain region, a source region, and a channel region are disposed in the active region of the die 150 between the gate terminal 171 and the drain terminal 174. The proximal end of the gate is electrically coupled to the gate terminal 171 of the second transistor, and the proximal end of the drain region is electrically coupled to the drain terminal 174 of the second transistor. According to one or more embodiments, the source region is electrically coupled to a ground reference node (e.g., conductive layer 124) via a signal and ground interface 164, a die-to-die interconnect system 186, 186', or 186" and a first semiconductor die 110 (specifically, the second contact pad 144 of the die mounting interface 142 and one or more TSVs 146 of the first semiconductor die 110). During operation, a time-varying signal applied to the gate terminal 171 of the second transistor (and thus to the gate) alters the conductivity of the underlying channel region, causing a time-varying current to flow between the source and drain regions (and thus between the ground reference and the drain terminal 174).

[0070] According to one or more embodiments, input, output, and source-to-ground connections of the second transistor 170 are provided via a signal and ground interface 164. The signal and ground interface 164 includes a plurality of conductive pads 173, 176, and 179 exposed at a second die interface surface 151 of the second semiconductor die 150. The plurality of conductive pads includes at least one second transistor gate pad 173, at least one second transistor drain pad 176, and at least one second transistor source pad 179.

[0071] For example, at least one second transistor gate pad 173, at least one second transistor drain pad 176, and at least one second transistor source pad 179 of the signal and ground interface 164 can be formed by a multilayer structure 158. Figure 7AThe topmost patterned conductive layer in ) (e.g., layer 160, Figure 7A The signal and ground interface 164 is partially formed. Furthermore, at least one second transistor gate pad 173, at least one second transistor drain pad 176, and at least one second transistor source pad 179 of the signal and ground interface 164 can be formed through the uppermost dielectric material layer (e.g., layer 162). Figure 7A The openings in the layer are exposed, and the layer can be used as a solder mask, as described below.

[0072] To provide electrical connections between the gate, drain, and source regions and the conductive pads at the second die interface surface 151, the gate terminal 171 of the second transistor is coupled to the gate pad 173, the drain terminal 174 of the second transistor is coupled to the drain pad 176, and the source region of the second transistor (e.g., source region 178) is coupled to the conductive pads at the interface surface 151. Figure 7A It is coupled to the source pad 179 of the second transistor.

[0073] As discussed above, the second semiconductor die 150 and the first semiconductor die 110 are connected via a die-to-die interconnect system (e.g., one of systems 186, 186', 186"). Figure 2A , 2B (2C) Physically and electrically coupled together. Specifically, the signal and ground interface 164 of the second semiconductor die 150 is physically and electrically coupled to the die mounting interface 142 of the first semiconductor die 110.

[0074] More specifically, as will be discussed in more detail below, through die-to-die interconnect systems 186, 186', 186", at least one second transistor gate pad 173 of the second semiconductor die 150 is physically and electrically coupled to at least one first contact pad 143 of the first semiconductor die 110, at least one second transistor source pad 179 of the second semiconductor die 150 is physically and electrically coupled to at least one second contact pad 144 of the first semiconductor die 110, and at least one second transistor drain pad 176 of the second semiconductor die 150 is physically and electrically coupled to at least one third contact pad 145 of the first semiconductor die 110.

[0075] Figure 2A , 2B The cross-sectional views of 2C show three different embodiments of die-to-die interconnect systems 186, 186', and 186" respectively. First refer to... Figure 2AThe image shows a cross-sectional side view of a power amplifier assembly 100, which includes one or more first embodiments of a die-to-die interconnect system 186. The die-to-die interconnect system 186 includes a plurality of direct solder connections 187, including a first direct solder connection between at least one second transistor gate pad 173 and at least one first contact pad 143, a second direct solder connection between at least one second transistor source pad 179 and at least one second contact pad 144, and a third direct solder connection between at least one second transistor drain pad 176 and at least one third contact pad 145. As described above, by utilizing the uppermost dielectric layers 122, 162 as solder masks, solder associated with the first, second, and third solder connections is controlled to avoid bridging between pads during reflow operation.

[0076] Next reference Figure 2B A cross-sectional side view of power amplifier assembly 100' is shown, which differs from power amplifier assembly 100' except for the die-to-die interconnect systems 186, 186'. Figure 2A The same. More specifically, Figure 2B The power amplifier assembly 100' includes one or more second embodiments of a die-to-die interconnect system 186'. The die-to-die interconnect system 186' includes a plurality of rigid conductive posts 188 (e.g., copper posts), the proximal ends of which are rigidly connected (e.g., sintered or brazed) to a first contact pad 143, a second contact pad 144, and a third contact pad 145 of a die mounting interface 142. The die-to-die interconnect system 186' also includes a plurality of solder connectors 189 connecting the distal ends of the conductive posts 188 to at least one second transistor gate pad 173, at least one second transistor source pad 179, and at least one second transistor drain pad 176.

[0077] Next reference Figure 2C The diagram shows a cross-sectional side view of power amplifier assembly 100", which differs from power amplifier assembly 100" except for the die-to-die interconnect systems 186, 186". Figure 2A The same. More specifically, Figure 2CThe power amplifier assembly 100" includes one or more third embodiments of the die-to-die interconnect system 186". The die-to-die interconnect system 186" includes a plurality of rigid conductive posts 188' (e.g., copper posts), the proximal ends of which are rigidly connected (e.g., sintered or brazed) to at least one second transistor gate pad 173, at least one second transistor source pad 179, and at least one second transistor drain pad 176 of a signal and ground interface 164. The die-to-die interconnect system 186" also includes a plurality of solder connectors 189' that connect the distal ends of the conductive posts 188' to a first contact pad 143, a second contact pad 144, and a third contact pad 145 of a die mounting interface 142.

[0078] Basically, in Figure 2B and 2C In each of the embodiments shown, the die-to-die interconnect system 186', 186" includes at least one first conductive post 188 or 188' connected between at least one first contact pad 143 and at least one second transistor gate pad 173, at least one second conductive post 188 or 188' connected between at least one second contact pad 144 and at least one second transistor source pad 179, and at least one third conductive post 188 and 188' connected between at least one third contact pad 145 and at least one second transistor drain pad 176.

[0079] As mentioned above, and will be combined later Figure 8 To be discussed in more detail Figure 1 , 2A The power amplifier components 100, 100', and 100" of 2B and 2C are configured such that when components 100, 100', and 100" are incorporated into a larger electronic system, the input wire bond 106 and the output wire bond 107 are provided with connection to the system substrate (e.g., system substrate 801). Figure 8 The first semiconductor die is electrically connected to receive an input signal (via input lead bonding 106) and provide an output signal (via output lead bonding 107). According to one or more alternative embodiments, the first semiconductor die may be modified to alternatively receive the input signal and provide the output signal at an end located on the bottom surface 112 of the first semiconductor die. Figure 3 , 4A These embodiments are described in detail in sections 4B and 4C.

[0080] Figure 3 A top view of a power amplifier assembly 300, 300', or 300" according to one or more embodiments is shown. For enhanced understanding, Figure 3 Should be with Figure 4A , 4B View simultaneously with 4C Figure 4A , 4B And 4C shows Figure 3 Three side cross-sectional views of several embodiments of power amplifier assemblies 300, 300', 300" along line 4-4. Power amplifier assemblies 300, 300', or 300" are similar in many respects to power amplifier assemblies 100, 100', 100". The difference between power amplifier assemblies 100, 100', 100" and power amplifier assemblies 300, 300', 300" lies in the first semiconductor die 110 of assemblies 100, 100', 100". Figure 1 , 2A (2B, 2C) and the first semiconductor die 110' of components 300, 300', 300" Figure 3 , 4A The differences between 4B and 4C.

[0081] Similar to power amplifier assemblies 100, 100', and 100" respectively, power amplifier assemblies 300, 300', and 300" include a first semiconductor die 110' and a second semiconductor die 150, which are physically and electrically coupled together via die-to-die interconnect systems 186, 186', or 186". Figure 4A , 4B (4C). The first semiconductor die 110' includes a first transistor 130 (corresponding to a first amplification stage), and the second semiconductor die 150 includes a second transistor 170 (corresponding to a second amplification stage). The first transistor 130 and the second transistor 170 are electrically coupled in a cascaded arrangement to provide a two-stage power amplifier implemented in power amplifier assemblies 300, 300', 300"

[0082] The first semiconductor die 110' in power amplifier assemblies 300, 300', and 300" has many similarities to the first semiconductor die 110 in power amplifier assemblies 100, 100', and 100" . For the sake of brevity, the above combination will not be repeated here. Figure 1 , 2A The above description provides a detailed description of similar or identical characteristics and features of the semiconductor die 110 (including various alternative embodiments) discussed in sections 2B and 2C. Instead, it combines... Figure 1 , 2A The detailed descriptions of similar or identical characteristics and features of the semiconductor die 110 discussed in sections 2B and 2C are intended to be incorporated into Figure 3 , 4A This description includes 4B and 4C.

[0083] First, we will summarize the similar or identical features. (This is in contrast to the first semiconductor die 100.) Figure 1 , 2ASimilar to 2B and 2C, the first semiconductor die 110' includes a mounting surface 111, an opposite bottom surface 112, a first transistor 130, and a die mounting interface 142. The first transistor 130 includes a first transistor gate terminal 131, a first transistor drain terminal 134, and a plurality of drain regions (not shown), source regions (not shown), channel regions (not shown), and a gate (not shown) overlying the channel regions. According to one or more embodiments, the first semiconductor die 110' may further include an interstage matching circuit 141 electrically coupled between the first transistor 130 and the die mounting interface 142. The die mounting interface 142 includes at least one first contact pad 143, at least one second contact pad 144, and at least one third contact pad 145.

[0084] The first semiconductor die 110' also includes a substrate semiconductor substrate 116 and a multilayer structure 118 formed on the substrate semiconductor substrate 116. According to one or more embodiments, the first transistor 130 may be a silicon-based FET (e.g., an LDMOS FET) or another type of FET. Therefore, according to one or more embodiments, the substrate semiconductor substrate 116 may include one or more layers of a first semiconductor material (e.g., a material selected from silicon, silicon carbide (SiC), or other materials). Ideally, the substrate semiconductor substrate 116 is formed of a high-resistivity material (e.g., a high-resistivity silicon material with a resistivity exceeding about 520 Ω / cm and possibly approaching or exceeding 1 MΩ / cm).

[0085] First Semiconductor Chip 100 ( Figure 1 , 2A 2B, 2C) and the first semiconductor die 110' ( Figure 3 , 4A The significant difference between 4B and 4C is that, in die 110', the first die input terminal 125' and the first die output terminal 127' are located at the bottom surface 112 of the first semiconductor die 110', rather than at the mounting surface 111 (as with die 110). Figure 1 , 2A 2B, 2C).

[0086] More specifically, the conductive layer 124' on the bottom surface of the substrate semiconductor substrate 116 is patterned to include a first conductive feature corresponding to the first die input terminal 125', a second conductive feature 126' corresponding to the ground reference node, and a third conductive feature corresponding to the first die output terminal 127'. According to an embodiment, the first die input terminal 125' is located near a first side of the first semiconductor die 110', the first die output terminal 127' is located near the opposite second side of the semiconductor die 110', and the second conductive feature 126' is located between terminals 125' and 127'. The first conductive feature 125' and the second conductive feature 126' are separated by a first non-conductive region 128, and the second conductive feature 126' and the third conductive feature 127' are separated by a second non-conductive region 129. In other words, the conductive layer 124' is patterned such that the conductive features 125', 126', and 127' are electrically separated on the bottom surface 112 by non-conductive gaps.

[0087] Therefore, the first die input terminal 125' and the first die output terminal 127' are exposed at the bottom surface 112 of the first semiconductor die 110', rather than at the mounting surface 111. The first die input terminal 125' and the first die output terminal 127' are each configured to allow the first die 110' (and power amplifier assemblies 300, 300', 300") to be surface-mounted to the system substrate and to receive and generate signals at the bottom surface 112 of the die 110'. Finally, as will be discussed later... Figure 9 As described, when power amplifier components 300, 300', 300" are integrated into a larger electronic system, a first conductive feature (first die input terminal 125') can be coupled to an input terminal (e.g., terminal 991, Figure 9 The second conductive feature 126' can be coupled to the system ground structure (which in turn is coupled to the system ground reference voltage or another DC voltage), and the third conductive feature (first die output terminal 127') can be coupled to the output bonding pad or terminal (e.g., bonding pad 992, Figure 9 ).

[0088] To provide a suitable electrical connection between the first die input terminal 125' and the first transistor 130, the substrate semiconductor substrate 116 includes at least one first conductive TSV 140' extending between the surfaces of the substrate semiconductor substrate 116. According to one or more embodiments, the first TSV 140' is an insulating via because it is a signal-carrying via (i.e., a conductive via lined with a dielectric material to insulate the conductive via from the substrate semiconductor substrate 116). Figures 4A-4CAs shown, the first die input terminal 125' is electrically connected to the first transistor gate terminal 131 through at least one first conductive TSV 140' and the conductive portions of one or more patterned conductive layers 119, 120 of the multilayer structure 118.

[0089] Similarly, to provide a suitable electrical connection between the first die output terminal 127' and at least one third contact pad 145 of the die mounting interface 142, the substrate semiconductor substrate 116 includes at least one second conductive TSV 147' extending between the surfaces of the substrate semiconductor substrate 116. Likewise, according to one or more embodiments, the second TSV 147' is an insulating via because it is a signal-carrying via. Figures 4A-4C As shown, the first die output terminal 127' is electrically connected to at least one third contact pad 145 through at least one second conductive TSV 147' and the conductive portions of one or more patterned conductive layers 119, 120 of the multilayer structure 118.

[0090] The first semiconductor die 110' also includes a die mounting interface 142 at a mounting surface 111, the die mounting interface 142 including at least one first contact pad 143, at least one second contact pad 144, and at least one third contact pad 145. Similarly, the first contact pad 142, the second contact pad 144, and the third contact pad 145 are all arranged within a perimeter (in... Figure 5A and 5B (Represented by the dashed box labeled 142). The perimeter defines the area where the second semiconductor die 150 is flip-chip mounted to the first semiconductor die 110'.

[0091] As described above, at least one first contact pad 143 is electrically coupled to the first die drain terminal 134 (possibly via interstage impedance matching circuit 141), and at least one second contact pad 144 is electrically coupled via a conductive path (including one or more TSVs 146) to a second conductive feature 126' of the conductive layer 124 located at the bottom of the first semiconductor die 110' (e.g., to a ground reference node). According to one or more embodiments, at least one third contact pad 145 is electrically coupled to the first die output terminal 127' (via a second TSV 147').

[0092] The second semiconductor die 150 in power amplifier assemblies 300, 300', and 300" can be the same as the second semiconductor die 150 in power amplifier assemblies 100, 100', and 100" . For the sake of brevity, the above combination will not be repeated here. Figure 1 , 2A All the various characteristics and features of the semiconductor die 150 (including various alternative embodiments) discussed in sections 2B and 2C. Instead, the above combines... Figure 1, 2A The detailed descriptions of the various characteristics and features of the semiconductor die 150 discussed in sections 2B and 2C are intended to be incorporated into Figure 3 , 4A This description includes 4B and 4C.

[0093] In short, the second semiconductor die 150 includes a second die interface surface 151, a second surface 152 opposite to the second die interface surface 151, a signal and ground interface 164, and a second transistor 170. Furthermore, a brief reference is made to... Figure 7A , Figure 7A This is a side cross-sectional view of an embodiment of the second semiconductor die 150, which includes a substrate semiconductor substrate 156 and a multilayer structure 158 formed on the substrate semiconductor substrate 156.

[0094] Also refer to Figure 3 , 4A 4B and 4C, the second transistor 170 is integrally formed within the second semiconductor die 150, and the second transistor 170 includes a second transistor gate terminal 171 and a second transistor drain terminal 174, and a drain region (e.g., drain region 175, Figure 6A ), source pole region (e.g., source pole region 178, Figure 6A ), the channel region (unlabeled), and multiple gates (e.g., gate 172) covering the channel region. Figure 6A ).

[0095] The proximal end of the gate is electrically coupled to the gate terminal 171 of the second transistor, and the proximal end of the drain region is electrically coupled to the drain terminal 174 of the second transistor. According to one or more embodiments, the source region is electrically coupled to a ground reference node (e.g., the conductive layer 124 of the first semiconductor die 110) via a signal and ground interface 164, a die-to-die interconnect system 186, 186' or 186" and a first semiconductor die 110' (specifically, the second contact pad 144 of the die mounting interface 142 and one or more TSVs 146 of the first semiconductor die 110').

[0096] According to one or more embodiments, the signal and ground interface 164 includes at least one second transistor gate pad 173, at least one second transistor drain pad 176, and at least one second transistor source pad 179. To provide electrical connections between the gate, drain, and source regions and conductive pads at the second die interface surface 151, the second transistor gate terminal 171 is coupled to the second transistor gate pad 173, the second transistor drain terminal 174 is coupled to the second transistor drain pad 176, and the second transistor source region (e.g., source region 178) is coupled to the second transistor gate pad 173. Figure 7A It is coupled to the source pad 179 of the second transistor.

[0097] Similarly, as discussed above, the second semiconductor die 150 and the first semiconductor die 110' are connected via a die-to-die interconnect system (e.g., one of systems 186, 186', 186"). Figure 4A , 4B (4C) Physically and electrically coupled together. Specifically, the signal and ground interface 164 of the second semiconductor die 150 is physically and electrically coupled to the die mounting interface 142 of the first semiconductor die 110'.

[0098] Figure 4A , 4B The cross-sectional views of 4C show three different embodiments of die-to-die interconnect systems 186, 186', and 186" respectively. First refer to... Figure 4A The image shows a cross-sectional side view of a power amplifier assembly 300, which includes one or more first embodiments of a die-to-die interconnect system 186. The die-to-die interconnect system 186 includes a plurality of direct solder connections 187, including a first direct solder connection between at least one second transistor gate pad 173 and at least one first contact pad 143, a second direct solder connection between at least one second transistor source pad 179 and at least one second contact pad 144, and a third direct solder connection between at least one second transistor drain pad 176 and at least one third contact pad 145.

[0099] Next reference Figure 4B The image shows a cross-sectional side view of a power amplifier assembly 300', which includes one or more second embodiments of a die-to-die interconnect system 186'. The die-to-die interconnect system 186' includes a plurality of rigid conductive posts 188 (e.g., copper posts) with proximal ends rigidly connected (e.g., sintered or brazed) to first contact pads 143, second contact pads 144, and third contact pads 145 of a die mounting interface 142. The die-to-die interconnect system 186' also includes a plurality of solder connectors 189 connecting the distal ends of the conductive posts 188 to at least one second transistor gate pad 173, at least one second transistor source pad 179, and at least one second transistor drain pad 176.

[0100] Next reference Figure 4CThe image shows a cross-sectional side view of a power amplifier assembly 300", which includes one or more third embodiments of a die-to-die interconnect system 186". The die-to-die interconnect system 186 includes a plurality of rigid conductive posts 188' (e.g., copper posts) with proximal ends rigidly connected (e.g., sintered or brazed) to at least one second transistor gate pad 173, at least one second transistor source pad 179, and at least one second transistor drain pad 176 of a signal and ground interface 164. The die-to-die interconnect system 186 also includes a plurality of solder connectors 189' that connect the distal ends of the conductive posts 188' to a first contact pad 143, a second contact pad 144, and a third contact pad 145 of a die mounting interface 142.

[0101] Now we will combine Figure 5A and 5B A more detailed illustration of the first semiconductor dies 110, 110' of an embodiment depicting a prominent die mounting interface 142 is provided. More specifically, Figure 5A An illustration is provided according to one or more embodiments. Figure 1 A top view of the first semiconductor die 110 or 110' of power amplifier assemblies 100", 100", 300", and 300" of power amplifier assemblies of 3, 2A, 2C, 4A, and 4C. (See above for reference.) Figure 1 , 2A The points discussed in 2C, 4A, and 4C, as well as those discussed in 2C, 4A, and 4C, and ... as well as those discussed in Figure 5A As shown, the first semiconductor dies 110 and 110' include a die mounting interface 142, which includes a plurality of contact pads 143-145 exposed at the mounting surface 111 of the first semiconductor dies 110 and 110'.

[0102] More specifically, the die mounting interface 142 includes a two-dimensional array of contact pads 143-145, the two-dimensional array including at least one row 501 of the first contact pads 143 and at least one row 502 of the second contact pads 144. Figure 5A Two rows are shown in the diagram) and at least one row 503 of the third contact pad 145, all of which are contained within a perimeter (in Figure 5A (represented by a dashed box in the image), the perimeter defines the area where the second semiconductor die (e.g., die 150) can be flip-chip mounted onto the first semiconductor dies 110, 110'.

[0103] According to some embodiments, each of the first, second, and third contact pads 143-145 can be formed by a clearly patterned portion of the uppermost patterned conductive layer of the stacked structure of dies 110, 110' (e.g., a patterned portion of layer 120). Figure 2A , 2C4A, 4C) are formed. Alternatively, some or all of the first contact pads 143 may be formed by a single first patterned conductive feature 543 of the uppermost patterned conductive layer, some or all of the second contact pads 144 may be formed by a single second patterned conductive feature 544 of the uppermost patterned conductive layer, and some or all of the third contact pads 145 may be formed by a single third patterned conductive feature 543 of the uppermost patterned conductive layer. In such an embodiment, each of the first contact pads 143 may be defined as a single conductive feature 543 through the uppermost dielectric material layer (e.g., layer 122, ...). Figure 2A , 2C Each of the second contact pads 144 can be defined as a portion of the opening exposed in the uppermost dielectric layer of a single conductive feature 544, and each of the third contact pads 145 can be defined as a portion of the opening exposed in the uppermost dielectric layer of a single conductive feature 545.

[0104] In this embodiment, the uppermost dielectric layer serves as a solder mask, spacing the exposed first, second, and third contact pads 143-145 from each other at the mounting surfaces 111 of dies 110, 110'. The solder mask function of the uppermost dielectric layer helps prevent shorting the pads 143-145 together when solder is applied to the exposed contact pads 143-145 and reflowed to physically couple the second semiconductor die (e.g., die 150) to the first semiconductor dies 110, 110'. According to one or more embodiments, when the second die (e.g., die 150) is flip-chip mounted to the first semiconductor dies 110, 110', the location of the first contact pad 143 is selected to correspond to the corresponding gate bonding pad (e.g., gate bonding pad 173). Figure 6A , 6B Alignment is achieved by selecting the position of the second contact pad 144 to align with the corresponding source bonding pad (e.g., source bonding pad 179). Figure 6A , 6B Alignment is achieved, and the position of the third contact pad 145 is selected to align with the corresponding drain bonding pad (e.g., drain bonding pad 176). Figure 6A , 6B Alignment.

[0105] As discussed above, according to one or more alternative embodiments, multiple conductive pillars (e.g., pillar 188, Figure 2B , 4B This can be electrically coupled to the first, second, and third bonding pads 143-145 of the die mounting interface 142. For illustration, Figure 5B According to one or more embodiments Figure 1A top view of the first semiconductor die 110 or 110' of the power amplifier assemblies 100', 300', or 3, 2B, and 4B.

[0106] According to one or more embodiments, in addition to the conductive post 188 being coupled to Figure 5B In addition to each of the first, second, and third bonding pads 143-145 in the first semiconductor dies 110, 110' Figure 5B The first semiconductor dies 110 and 110' can be with Figure 5A The first semiconductor dies 110 and 110' are identical. (As combined...) Figure 2B and 4B As discussed in detail, the conductive post 188 forms part of the die-to-die interconnect system 186' for physically and electrically coupling a second die (e.g., die 150) to the first dies 110, 110'.

[0107] Now we will combine Figure 6A and 6B A more detailed illustration of the second semiconductor die 150 depicting an embodiment of the prominent signal and ground interface 164 is provided. More specifically, Figure 6A An illustration is provided according to one or more embodiments. Figure 1 A top view of the second semiconductor die 150 of the power amplifier assembly, or 3, 2A, 2B, 4A, and 4B. For enhanced understanding, Figure 6A Should be with Figure 7A View at the same time Figure 7A It shows Figure 6A A side cross-sectional view of the second semiconductor die 150 along line 7A-7A. (As described above...) Figure 1 , 2A The points discussed in 2B, 4A, and 4B, and as well as... Figure 6A and 7A As shown, the second semiconductor die 150 includes a signal and ground interface 164, which includes a plurality of gate pads 173, drain pads 176 and source pads 179, which are exposed at the second die interface surface 151 of the second semiconductor die 150.

[0108] More specifically, the signal and ground interface 164 includes a two-dimensional array of contact pads 173, 176, and 179, said two-dimensional array including at least one row 601 of gate pads 173 and at least one row 602 of source pads 179. Figure 6A (Two lines are shown in the image), and at least one line 603 for drain pad 176.

[0109] According to some embodiments, each of the gate pad 173, drain pad 176, and source pad 179 can be formed by a clearly patterned portion of the uppermost patterned conductive layer of the stacked structure 158 of the die 150 (e.g., a patterned portion of layer 160). Figure 7A Alternatively, some or all of the gate pads 173 may be formed by a single first patterned conductive feature 673 of the uppermost patterned conductive layer, some or all of the source pads 179 may be formed by a single second patterned conductive feature 679 of the uppermost patterned conductive layer, and some or all of the drain pads 176 may be formed by a single third patterned conductive feature 676 of the uppermost patterned conductive layer. In such an embodiment, each of the gate pads 173 may be defined as a single conductive feature 673 through the uppermost dielectric material layer (e.g., layer 162, ...). Figure 7A Each of the source pads 179 can be defined as a portion of the opening exposed in the uppermost dielectric layer of a single conductive feature 679, and each of the drain pads 176 can be defined as a portion of the opening exposed in the uppermost dielectric layer of a single conductive feature 676.

[0110] In such an embodiment, the uppermost dielectric layer serves as a solder mask, separating the exposed gate pad 173, drain pad 176, and source pad 179 from each other at the interface surface 151 of die 150. When solder is applied to the exposed contact pads 173, 176, 179 and reflowed to physically couple the second semiconductor die 150 to the first semiconductor die (e.g., dies 110, 110'), the solder mask function of the uppermost dielectric layer helps prevent the pads 173, 176, 179 from shorting together. According to one or more embodiments, when the second die 150 is flip-chip mounted to the first semiconductor die (e.g., dies 110, 110'), Figure 5A , 5B When the gate pad 173 is positioned relative to the corresponding first contact pad (e.g., pad 143), the position of the gate pad 173 is selected to be adjacent to the first contact pad (e.g., pad 143). Figure 5A , Figure 5B Alignment is achieved by selecting the position of source pad 179 to align with the corresponding second contact pad (e.g., pad 144). Figure 5A , Figure 5B Alignment is achieved, and the position of drain pad 176 is selected to align with the corresponding third contact pad (e.g., pad 145). Figure 5A , Figure 5B Alignment.

[0111] As discussed above, according to one or more alternative embodiments, multiple conductive pillars (e.g., pillar 188', Figure 2C , 4CThe gate bonding pad 173, drain bonding pad 176, and source bonding pad 179 can be electrically coupled to the signal and ground interface 164. For illustration, Figure 6B According to one or more other embodiments Figure 1 A top view of the second semiconductor die 150 of a power amplifier assembly, or a 3C, 2C, or 4C power amplifier assembly. For enhanced understanding, Figure 6B Should be with Figure 7B View at the same time Figure 7B It shows Figure 6B A side cross-sectional view of the second semiconductor die 150 along line 7B-7B.

[0112] According to one or more embodiments, in addition to the conductive post 188' being coupled to Figure 6B In addition to each of the gate pad 173, drain pad 176, and source pad 179 in the second semiconductor die 150 Figure 6B The second semiconductor die 150 can be with Figure 6A The second semiconductor die 150 is the same. (As combined...) Figure 2C and 4C As discussed in detail, the conductive post 188' forms part of the die-to-die interconnect system 186" for physically and electrically coupling the second die 150 to the first die (e.g., dies 110, 110').

[0113] Now we will combine Figure 8-14 The description includes the combination of the aforementioned power amplifier components 100, 100', 100", 300, 300', and 300" ( Figure 1 , 2A Examples of various amplifier systems (-C, 3, 4A-C). It should be understood that, in conjunction with... Figure 8-14 The amplifier system discussed refers only to the aforementioned power amplifier components 100, 100', 100", 300, 300', 300" ( Figure 1 , 2A Several non-limiting examples of applications of (-C, 3, 4A-C) are provided. Those skilled in the art will understand, based on the description herein, how the above power amplifier components can be incorporated into other types of systems.

[0114] Figure 8 A top view of a multi-stage amplifier system 800 according to one or more embodiments is shown. The amplifier system 800 includes a system substrate 801 and power amplifier components 100, 100', 100" (e.g., any embodiment of components 100, 100', 100"). Figure 1 , 2A-2C) and final stage amplifier device 894. System substrate 801 has substrate mounting surface 802 and opposite bottom surface (not shown or marked). For example, system substrate 801 may be a printed circuit board (PCB) or another suitable substrate.

[0115] Multiple conductive wiring traces and pads are formed on a substrate mounting surface 802. For example, the multiple conductive wiring traces and pads may include a portion of a patterned conductive layer on the substrate mounting surface 802. According to one or more embodiments, the multiple conductive wiring traces and pads include an amplifier input terminal 891, an intermediate bonding pad 892, and an amplifier output terminal 893, as well as other features.

[0116] According to one or more embodiments, power amplifier components 100, 100', 100" (e.g., component 100, 100', or 100"). Figure 1 , 2A -2C) Physically coupled to the substrate mounting surface 802 and electrically coupled between the amplifier input terminal 891 and the intermediate bonding pad 892. The power amplifier assemblies 100, 100', 100" include a first semiconductor die 110 and a second semiconductor die 150, as combined Figure 1 and 2A -2C is described in detail.

[0117] According to one or more embodiments, in order to couple the power amplifier assemblies 100, 100', 100" to the substrate mounting surface 802, the conductive underlayer (e.g., layer 124) of the first semiconductor die 110 of the power amplifier assemblies 100, 100', 100" is used. Figure 2A-2C This can be physically coupled to one or more conductive structures (e.g., traces, conductive coins, and / or conductive vias) in or on the system substrate 801. As previously described, the conductive underlayer (e.g., layer 124, ...) can be physically coupled to one or more conductive structures (e.g., traces, conductive coins, and / or conductive vias) in or on the system substrate 801. Figure 2A-2C ) can correspond to the ground reference node of components 100, 100', 100" and said ground reference node can be coupled to the system ground reference (e.g., the above-described conductive structure in system substrate 801).

[0118] To electrically couple power amplifier assemblies 100, 100', 100" to amplifier input 891, a first end of one or more input wire bonds 106 is connected to amplifier input 891, and a second end of the input wire bonds 106 is connected to the first die input 125 (bonding pad) of power amplifier assemblies 100, 100', 100" . Similarly, to electrically couple power amplifier assemblies 100, 100', 100" to intermediate bonding pad 892, a first end of one or more output wire bonds 107 is connected to the first die output 127 (bonding pad), and a second end of the output wire bonds 107 is connected to intermediate bonding pad 892.

[0119] The final stage amplifier device 894 may include an input lead 895, an output lead 896, and a power transistor 897 electrically coupled between the input lead 895 and the output lead 896. The final stage amplifier device 894 can be coupled to the substrate mounting surface 802 by connecting the input lead 895 and the output lead 896 to conductive pads (not labeled) at the substrate mounting surface 802. The input lead 895 can be electrically coupled to an intermediate bonding pad 892 via the conductive pad therewith and optionally via an interstage matching circuit 898. The output lead 896 can be electrically coupled to the amplifier output terminal 893 via the conductive pad therewith.

[0120] The multi-stage amplifier system 800 includes three amplification stages coupled in a cascaded arrangement. More specifically, the system 800 includes a first transistor (e.g., transistor 130) integrated in a first semiconductor die 110. Figure 1 , 2A The first amplification stage corresponding to (-C, 5A, 5B) and the second transistor (e.g., transistor 170) integrated in the second semiconductor die 150. Figure 1 , 2A The second amplification stage corresponds to (-C, 6A, 6B). Finally, the system 800 includes a third amplification stage corresponding to the power transistor 897 in the final stage amplifier device 894.

[0121] although Figure 8 Although not shown, the multistage amplifier system 800 may also include various bias circuits, control circuits, and other circuit systems mounted on the system substrate 801 and electrically coupled to the power amplifier assemblies 100, 100', 100" and / or the final stage amplifier device 894.

[0122] Figure 9A top view of a multistage amplifier system 900 according to one or more other embodiments is shown. The amplifier system 900 includes a system substrate 901 and power amplifier components 300, 300', 300" (e.g., any embodiment of components 300, 300', 300"). Figure 3 , 4A -4C) and final stage amplifier device 994. System substrate 901 has substrate mounting surface 902 and opposite bottom surface (not shown or marked). For example, system substrate 901 can be a PCB or other suitable substrate.

[0123] Multiple conductive wiring traces and pads are formed on the substrate mounting surface 902. For example, the multiple conductive wiring traces and pads may include a portion of a patterned conductive layer on the substrate mounting surface 902. According to one or more embodiments, the multiple conductive wiring traces and pads include an amplifier input terminal 991, an intermediate bonding pad 992, and an amplifier output terminal 993, as well as other features.

[0124] According to one or more embodiments, power amplifier components 300, 300', 300" (e.g., component 300, 300', or 300"). Figure 3 , 4A -4C) Physically coupled to the substrate mounting surface 902, and electrically coupled between the amplifier input terminal 991 and the intermediate bonding pad 992. The power amplifier assemblies 300, 300', 300" include a first semiconductor die 110' and a second semiconductor die 150, as combined Figure 3 and 4A -4C is described in detail.

[0125] According to one or more embodiments, in order to couple the power amplifier assemblies 300, 300', 300" to the substrate mounting surface 902, the conductive underlayer (e.g., layer 124') of the first semiconductor die 110' of the power amplifier assemblies 300, 300', 300" is used. Figures 4A-4C This can be physically coupled to one or more conductive structures (e.g., traces, conductive coins, and / or conductive vias) in or on the system substrate 901. As previously described, the conductive underlayer (e.g., layer 124') can be physically coupled to one or more conductive structures (e.g., traces, conductive coins, and / or conductive vias). Figures 4A-4C ) can correspond to the ground reference node of components 300, 300', 300" and said ground reference node can be coupled to the system ground reference (e.g., the conductive structure in the system substrate 901 described above).

[0126] In order to electrically couple the power amplifier assemblies 300, 300', 300" to the amplifier input terminal 991, the bottom surface (e.g., surface 112) of the first semiconductor die 110' is connected. Figure 4AThe first die input terminal 125' at (-C) is connected (e.g., soldered) to the amplifier input terminal 991 (or to another pad coupled to terminal 991). Similarly, to electrically couple the power amplifier assemblies 300, 300', 300" to the intermediate bonding pad 992, the bottom surface of the first semiconductor die 110' (e.g., surface 112, Figure 4A The first die output terminal 127' at -C) is connected (e.g., soldered) to the intermediate bonding pad 992.

[0127] The final stage amplifier device 994 may include an input lead 995, an output lead 996, and a power transistor 997 electrically coupled between the input lead 995 and the output lead 996. The final stage amplifier device 994 can be coupled to the substrate mounting surface 902 by connecting the input lead 995 and the output lead 996 to conductive pads (not labeled) at the substrate mounting surface 902. The input lead 995 can be electrically coupled to an intermediate bonding pad 992 via the conductive pad therewith and optionally via an interstage matching circuit 998. The output lead 996 can be electrically coupled to the amplifier output terminal 993 via the conductive pad therewith.

[0128] The multi-stage amplifier system 900 includes three amplification stages coupled in a cascaded arrangement. More specifically, the system 900 includes a first transistor (e.g., transistor 130) integrated in a first semiconductor die 110'. Figure 3 , 4A The first amplification stage corresponding to (-C, 5A, 5B) and the second transistor (e.g., transistor 170) integrated in the second semiconductor die 150. Figure 3 , 4A The second amplification stage corresponds to (-C, 6A, 6B). Finally, the system 900 includes a third amplification stage corresponding to the power transistor 997 in the final stage amplifier device 994.

[0129] although Figure 9 Although not shown, the multistage amplifier system 900 may also include various bias circuits, control circuits, and other circuit systems mounted on the system substrate 901 and electrically coupled to the power amplifier assemblies 300, 300', 300" and / or the final stage amplifier device 994.

[0130] Figure 8 and 9Single-path multistage power amplifiers 800 and 900 are depicted, in which embodiments of amplifier assemblies 100, 100', 100", 300, 300', 300" are incorporated. In other embodiments, embodiments of amplifier assemblies 100, 100', 100", 300, 300', 300" can be incorporated into other types of power amplifiers, including multi-path multistage power amplifiers. For example, as a non-limiting example, embodiments of amplifier assemblies 100, 100', 100", 300, 300', 300" can be incorporated into a Dougherty power amplifier, such as by combining... Figure 10 and 11 Discussed.

[0131] First refer to Figure 10 The image shows a top view of a Dougherty power amplifier module 1000 according to one or more embodiments, the Dougherty power amplifier module 1000 including a first power amplifier assembly 100-1 for a carrier amplifier (e.g., a first instance of any one of power amplifier assemblies 100, 100', 100"). Figure 1 , 2A -2C) and a second power amplifier assembly 100-2 for a peak amplifier (e.g., a second instance of any one of power amplifier assemblies 100, 100', 100"). Figure 1 , 2A -2C). Although Figure 10 Specifically shown are power amplifier assemblies 100-1 and 100-2 (corresponding to assemblies 100, 100', and 100") including first die input terminals 125-1 and 125-2 and first die output terminals 127-1 and 127-2 configured for attaching wire bonding terminals 106-1, 106-2, 107-1, and 107-2. Figure 1 , 2A -2C), but it should be understood that the Dougherty power amplifier module 1000 can be modified to include input bonding pads and output bonding pads configured to be electrically coupled to the first die input and the first die output at the bottom surfaces of the first power amplifier assembly and the second power amplifier assembly (e.g., module 1000 can be modified to include two instances of power amplifier assemblies 300, 300', and 300"). Figure 3 , 4A -4C).

[0132] The Dougherty power amplifier module 1000 is housed on a module substrate 1001 (e.g., a PCB or other substrate) having a module mounting surface 1002 and an opposite bottom surface (not shown or marked). Module 1000 also includes an amplifier input 1025, a power divider 1048, a carrier amplifier path 1081 (referred to as the "carrier amplifier assembly") having a carrier amplifier in the form of a first power amplifier assembly 100-1, a peak amplifier path 1083 (referred to as the "peak amplifier assembly") having a peak amplifier in the form of a second power amplifier assembly 100-2, an output combination circuit 1049 having a combination node 1085, an output impedance transformer 1099, and an amplifier output 1027, among others.

[0133] In short, during operation of the Dougherty power amplifier module 1000, the power divider 1048 is configured to receive an input RF signal from the amplifier input 1025 at the power divider input (unlabeled). The power divider 1048 is further configured to split the power of the input RF signal into a carrier input RF signal and a peak input RF signal, respectively, at a first power divider output and a second power divider output (unlabeled). In this way, the power divider 1048 is configured to provide the carrier input RF signal to the carrier amplification path 1081 and the peak input RF signal to the peak amplification path 1083. According to an embodiment, the power divider 1048 is configured to generate the carrier input RF signal and the peak input RF signal with a desired phase difference (typically approximately 90 degrees) between them.

[0134] The carrier amplification path 1081 includes a carrier input matching network (IMN) (unlabeled) and a carrier amplifier component 100-1. Similarly, the peak amplification path 1083 includes a peak IMN (unlabeled) and a peak amplifier component 100-2. Both the carrier IMN and the peak IMN may include, for example, a low-pass or band-pass circuit configured as a T or π impedance matching network, although other matching network topologies are also contemplated. Regardless of the configuration, the IMN progressively increases the circuit impedance, bringing it closer to the source impedance.

[0135] According to one or more embodiments, and as described above, the carrier amplifier is implemented as a first instance of carrier amplifier assembly 100-1 (e.g., a power amplifier assembly 100, 100', 100"). Figure 1 , 2A -2C), and the peak amplifier is implemented as peak amplifier assembly 100-2 (e.g., a second instance of any one of power amplifier assemblies 100, 100', 100"). Figure 1 , 2A-2C). Therefore, each of the carrier amplifier assembly 100-1 and the peak amplifier assembly 100-2 includes a first semiconductor die 110-1, 110-2 having input terminals 125-1, 125-2, integrated first transistors 130-1, 130-2, and output terminals 127-1, 127-2. Each of the carrier amplifier assembly 100-1 and the peak amplifier assembly 100-2 also includes a second semiconductor die 150-1, 150-2 having integrated second transistors 170-1, 170-2. Basically, the first transistors 130-1, 130-2 and the second transistors 170-1, 170-2 are coupled in a cascaded arrangement between the input terminals 125-1, 125-2 and the output terminals 127-1, 127-2. Figure 1 and 2A As discussed in detail in -2C, second semiconductor dies 150-1 and 150-2 are flip-chip mounted to first semiconductor dies 110-1 and 110-2. Furthermore, each of the first semiconductor dies 110-1 and 110-2 is coupled to module mounting surface 1002 (e.g., ...). Figure 2A , 4A The conductive bottom layer 124 (or 124') is coupled to the conductive features at the module mounting surface 1002.

[0136] The carrier amplifier assembly 100-1 receives the carrier input RF signal through its input terminal 125-1, provides two-stage amplification through the first transistor 130-1 and the second transistor 170-1, and generates the amplified carrier RF signal at the output terminal 127-1. Similarly, the peak amplifier assembly 100-2 receives the peak input RF signal through its input terminal 125-2, provides two-stage amplification through the first transistor 130-2 and the second transistor 170-2, and generates the amplified peak RF signal at the output terminal 127-2.

[0137] The amplified carrier RF signal is then transmitted to the combination node 1085 via the output combination circuit 1049. The output combination circuit 1049 is configured to apply a phase shift (e.g., approximately 90 degrees in some embodiments) to the amplified carrier RF signal and also provides impedance reversal. In the illustrated embodiment, the output combination circuit 1049 includes a series coupling circuit comprising an output lead bond 107-1 between the output terminal 127-1 of the carrier amplifier assembly 100-1 and a first terminal of the transmission line 1084, the transmission line 1084, and an additional lead bond 1007 between the second terminal of the transmission line 1084 and the combination node 1085. In the illustrated embodiment, the combination node 1085 corresponds to the output terminal 127-2 of the peak amplifier assembly 100-2. In other embodiments, the output combination circuit 1049 and / or the combination node 1084 may be configured differently.

[0138] The amplified carrier RF signal and the peak RF signal are combined (in phase) at the combination node 1085 and transmitted through the output lead bond 107-2 between the output terminal 127-2 of the peak amplifier assembly 100-2 and the first terminal of the output impedance transformer 1099. The amplified output RF signal is then transmitted to the amplifier output terminal 1027 through the output impedance transformer 1099.

[0139] The Dougherty power amplifier module 1000 depicts a symmetrical, non-inverting Dougherty power amplifier with a 90 / 0 output combination circuit 1049. "Symmetrical" means that the size ratio of the carrier amplifier to the peak amplifier is 1:1. According to other embodiments, the Dougherty power amplifier module can be "asymmetrical," meaning that the size ratio of the carrier amplifier to the peak amplifier is not 1:1 (e.g., the ratio could be 1:2 or other values). "Non-inverting" means that the peak input RF signal (at the input of the peak amplifier) ​​is delayed by approximately 90 degrees from the carrier input RF signal (at the input of the carrier amplifier) ​​to compensate for the approximately 90-degree phase delay of the amplified carrier output RF signal applied between the carrier amplifier output and the combination node 1085. According to other embodiments, the Dougherty power amplifier module can have an "inverting" configuration, wherein the carrier input RF signal is delayed by approximately 90 degrees from the peak input RF signal. A “90 / 0” output combination circuit means that approximately 90 degrees of electrical length couples the carrier amplifier’s inherent drain terminal to the combination node 1085, and approximately 0 degrees of electrical length couples the peak amplifier’s inherent drain terminal to the combination node 1085. According to other embodiments, the Dougherty power amplifier module may have output combination circuits with different electrical lengths between the carrier amplifier’s inherent drain terminal and the peak amplifier’s inherent drain terminal and the combination node (e.g., the amplifier may have a 90 / 180 output combination circuit, or output combination circuits with different configurations).

[0140] Next reference Figure 11 The image shows a top view of another embodiment of the Dougherty power amplifier module 1100, which includes alternative embodiments of power amplifier assemblies 100-3 (e.g., modified embodiments of power amplifier assemblies 100, 100', 100"). Figure 1 , 2A -2C), the power amplifier assembly 100-3 embodies a two-stage drive amplifier with dual inputs and dual outputs. Similarly, although Figure 11 Specifically shown is a power amplifier assembly 100-3 (consistent with assemblies 100, 100', 100") comprising first die input terminals 125-1, 125-2 and first die output terminals 127-1, 127-2 configured for attaching wire bonding terminals 106-1, 106-2, 107-1, 107-2. Figure 1 , 2A -2C), but it should be understood that the Dougherty power amplifier module 1100 can be modified to include input bonding pads and output bonding pads configured to be electrically coupled to the first die input and the first die output at the bottom surface of the power amplifier assembly 100-3 (e.g., the module 1100 can be modified to include modified embodiments of power amplifier assemblies 300, 300', 300"). Figure 3 , 4A -4C).

[0141] The Dougherty power amplifier module 1100 is housed on a module substrate 1101 (e.g., a PCB or other substrate) having a module mounting surface 1102 and an opposite bottom surface (not shown or marked). Module 1100 also includes an amplifier input 1125, a power divider 1148, a carrier amplifier path 1181, a peak amplifier path 1183, an output combination circuit 1149 with a combination node 1185, an output impedance transformer 1199, and an amplifier output 1127, among others. As will be described in more detail below, each of the carrier amplifier path 1181 and the peak amplifier path 1183 includes a two-stage drive amplifier, and the two-stage drive amplifier is implemented on the power amplifier assembly 100-3. Furthermore, each of the carrier amplifier path 1181 and the peak amplifier path 1183 includes a final stage amplifier, and the final stage amplifier is implemented in a final stage amplifier device 1150.

[0142] According to one or more embodiments, the power amplifier assembly 100-3 is as described above. Figure 1 , 2A -2C power amplifier components 100, 100', 100" are modified versions. Specifically, power amplifier component 100-3 includes a first semiconductor die 110" and two second semiconductor dies 150-1 and 150-2. The first semiconductor die 110" can be combined with the above. Figure 1 , 2A The die 110 discussed in -2C, 5A, and 5B is substantially the same, except that the first semiconductor die 110 of component 100-3 includes two side-by-side instances (copies) of the circuitry included in the previously described embodiments of die 110.

[0143] The first semiconductor die 110" is coupled to the module mounting surface 1102 (e.g., a conductive underlayer at the bottom of die 110" is coupled to one or more conductive features at the module mounting surface 1102). Furthermore, the power amplifier assembly 110-3 includes two second semiconductor dies 150-1 and 150-2, which are flip-chip mounted to the mounting surface of the first semiconductor die 110". Each of the two second semiconductor dies 150-1 and 150-2 can be coupled with... Figure 1 , 2A The second semiconductor die 150 discussed in -2C, 6A, 6B, 7A and 7B are basically the same.

[0144] More specifically, power amplifier assembly 100-3 includes a first two-stage driver amplifier with an input terminal 125-1, an integrated first transistor 130-1, a second semiconductor die 150-1 with an integrated second transistor 170-1, and an output terminal 127-1. The first transistor 130-1 and the second transistor 170-1 are coupled in a cascaded arrangement between the input terminal 125-1 and the output terminal 127-1. Additionally, power amplifier assembly 110-3 includes a second two-stage driver amplifier with an input terminal 125-2, an integrated first transistor 130-2, a second semiconductor die 150-2 with an integrated second transistor 170-2, and an output terminal 127-2. The first transistor 130-2 and the second transistor 170-2 are coupled in a cascaded arrangement between the input terminal 125-2 and the output terminal 127-2.

[0145] The final stage amplifier device 1150 can also be mounted to the module mounting surface 1102. According to one or more embodiments, the final stage amplifier device 1150 is a surface mount device including a package body (not labeled). The device 1150 further includes a first input lead 1171-1 and a second input lead 1171-2, a first output lead 1176-1 and a second output lead 1176-2 coupled to the package body, and a first power transistor 1170-1 and a second power transistor 1170-2 (also referred to as the final stage carrier amplifier and the final stage peak amplifier, respectively). The first input lead 1171-1, the first power transistor 1170-1, and the first output lead 1176-1 form part of a carrier amplifier path 1181. According to an embodiment, the first input lead 1171-1 is electrically coupled to the input terminal (e.g., the gate terminal) of the first power transistor 1170-1, and the output terminal (e.g., the drain terminal) of the first power transistor 1170-1 is electrically coupled to the first output lead 1176-1. Similarly, the second input lead 1171-2, the second power transistor 1170-2, and the second output lead 1176-2 form part of the peak amplifier path 1183. According to an embodiment, the second input lead 1171-2 is electrically coupled to the input terminal (e.g., the gate terminal) of the second power transistor 1170-2, and the output terminal (e.g., the drain terminal) of the second power transistor 1170-2 is electrically coupled to the second output lead 1176-2.

[0146] In short, during operation of the Dougherty power amplifier module 1100, the power divider 1148 is configured to receive an input RF signal from the amplifier input 1125 at the power divider input (unlabeled). The power divider 1148 is further configured to split the power of the input RF signal into a carrier input RF signal and a peak input RF signal, respectively, at a first power divider output and a second power divider output (unlabeled). In this way, the power divider 1148 is configured to provide the carrier input RF signal to the carrier amplification path 1181 and the peak input RF signal to the peak amplification path 1183. According to an embodiment, the power divider 1148 is configured to generate the carrier input RF signal and the peak input RF signal with a desired phase difference (typically approximately 90 degrees) between them.

[0147] The carrier amplification path 1181 includes a carrier input matching network (IMN) (unlabeled), a first two-stage driver amplifier implemented in the power amplifier assembly 100-3 between input 125-1 and output 127-1, an inter-carrier matching network (ISM, unlabeled), and a final-stage carrier amplifier 1170-1 implemented in the final-stage amplification device 1150 between input lead 1171-1 and output lead 1176-1. Similarly, the peak amplification path 1183 includes a peak IMN (unlabeled), a second two-stage driver amplifier implemented in the power amplifier assembly 100-3 between input 125-2 and output 127-2, a peak ISM (unlabeled), and a final-stage peak amplifier 1170-2 implemented in the final-stage amplification device 1150 between input lead 1171-2 and output lead 1176-2.

[0148] The carrier IMN and peak IMN, as well as the carrier ISM and peak ISM, can each include, for example, low-pass or band-pass circuits configured as T or π impedance matching networks, although other matching network topologies are also expected. Regardless of the configuration, the IMN and ISM gradually increase the circuit impedance.

[0149] The carrier amplification path 1181 receives the carrier input RF signal through input terminal 125-1, provides two stages of amplification through first transistor 130-1 and second transistor 170-1 (corresponding to the first two-stage drive amplifier in component 100-3), and generates an amplified carrier RF signal at output terminal 127-1. Then, the amplified carrier RF signal is transmitted to the first input lead 1171-1 of the final stage amplification device 1150 via carrier ISM. A third stage of amplification is performed by the final stage carrier amplifier 1170-1, and a further amplified carrier RF signal is generated at the first output lead 1176-1 of the final stage amplification device 1150.

[0150] Similarly, peak amplification path 1183 receives the peak input RF signal through input terminal 125-2, provides two stages of amplification through first transistor 130-2 and second transistor 170-2 (corresponding to the second two-stage drive amplifier in component 100-3), and generates an amplified peak RF signal at output terminal 127-2. The amplified peak RF signal is then transmitted to the second input lead 1171-2 of the final stage amplification device 1150 via peak ISM. Third-stage amplification is performed by the final stage peak amplifier 1170-2, and a further amplified peak RF signal is generated at the second output lead 1176-2 of the final stage amplification device 1150.

[0151] The amplified carrier RF signal and peak RF signal are then transmitted to the combination node 1185 via the output combination circuit 1149. The output combination circuit 1149 is configured to apply a phase shift to the amplified carrier RF signal (e.g., in some embodiments, approximately 90 degrees of phase shift between the drain of amplifier 1170-1 and node 1185) and a phase shift to the amplified peak RF signal (e.g., in some embodiments, approximately 180 degrees of phase shift between the drain of amplifier 1170-2 and node 1185). Furthermore, the output combination circuit 1149 is configured to provide impedance inversion. The amplified carrier RF signal and peak RF signal are combined (in phase) at the combination node 1185 and transmitted to the amplifier output 1127 via the output impedance transformer 1199.

[0152] The Dougherty power amplifier module 1100 depicts a symmetrical, non-inverting Dougherty power amplifier with a 90 / 180 output combination circuit 1149. According to other embodiments, the Dougherty power amplifier module may be asymmetrical and / or inverting, and / or the output combination circuit may have different electrical lengths between the inherent drain terminals of the carrier amplifier and the inherent drain terminals of the peak amplifier and the combination node. Furthermore, although the Dougherty power amplifier module 1100 includes two drive amplifiers implemented on a single power amplifier assembly 100-3, alternative embodiments may utilize two separate power amplifier assemblies (e.g., two instances of assemblies 100, 100', or 100"). Figure 1 , 2A -2C) is used to provide the function of two drive amplifiers.

[0153] Complete amplifier designs for high-power applications typically require a heat dissipation system to provide a thermal path for the heat generated by one or more power transistors in the system, keeping it away from the semiconductor device in which these power transistors are integrated. This article includes Figure 12-14 Several example embodiments of heat dissipation systems are provided for use with various embodiments of power amplifier assemblies 100, 100', 100", 300, 300', 300", 100-1, 100-2, 100-3.

[0154] Figure 12 A side cross-sectional view of a multi-stage amplifier system 1200 with a top-side cooling arrangement according to one or more embodiments is shown. The amplifier system 1200 includes a system substrate 1201 and power amplifier components 100, 100', 100" (e.g., any embodiment of components 100, 100', 100"). Figure 1 , 2A -2C). The system substrate 1201 has a substrate mounting surface 1202 and an opposite bottom surface 1203. For example, the system substrate 1201 may be a PCB or other suitable substrate.

[0155] Multiple conductive wiring traces and pads are formed on the substrate mounting surface 1202. For example, the multiple conductive wiring traces and pads may include a portion of a patterned conductive layer on the substrate mounting surface 1202. According to one or more embodiments, the multiple conductive wiring traces and pads include an amplifier input terminal 1291 and an amplifier output terminal 1293, as well as other features.

[0156] According to one or more embodiments, power amplifier components 100, 100', 100" (e.g., component 100, 100', or 100"). Figure 1 , 2A -2C) Physically coupled to the substrate mounting surface 1202, and electrically coupled between the amplifier input terminal 1291 and the amplifier output terminal 1293. The power amplifier assemblies 100, 100', 100" include a first semiconductor die 110 and a second semiconductor die 150, as combined Figure 1 and 2A -2C is described in detail.

[0157] According to one or more embodiments, in order to couple power amplifier assemblies 100, 100', 100" to substrate mounting surface 1202, the conductive bottom layer 124 of the first semiconductor die 110 of the power amplifier assemblies 100, 100', 100" can be physically coupled to a ground terminal 1224 on the mounting surface 1202 of the system substrate 1201. As previously described, the conductive bottom layer 124 of the die 110 can correspond to a ground reference node of the assemblies 100, 100', 100". According to one or more embodiments, a conductive layer (unmarked) at the bottom surface 1203 of the system substrate 1201 can correspond to a system ground reference, and the conductive bottom layer 124 of the die 110 can be electrically coupled to the system ground reference through the ground terminal 1224 and one or more conductive vias (unmarked) extending between the mounting surface 1202 and the bottom surface 1203 of the system substrate 1201.

[0158] To electrically couple power amplifier assemblies 100, 100', 100" to amplifier input 1291, a first end of one or more input wire bonds 106 is connected to amplifier input 1291 (or to a trace / pad coupled to end 1291), and a second end of the input wire bonds 106 is connected to a first die input 125 (bonding pad) of power amplifier assemblies 100, 100', 100" . Similarly, to electrically couple power amplifier assemblies 100, 100', 100" to amplifier output 1293, a first end of one or more output wire bonds 107 is connected to a first die output 127 (bonding pad), and a second end of the output wire bonds 107 is connected to amplifier output 1293 (or to a trace / pad coupled to end 1293).

[0159] The multistage amplifier system 1200 includes two amplification stages coupled in a cascaded arrangement. More specifically, the system 1200 includes a first amplification stage corresponding to a first transistor 130 integrated in a first semiconductor die 110, and a second amplification stage corresponding to a second transistor 170 integrated in a second semiconductor die 150.

[0160] The second transistor 170 in the second semiconductor die 150 may be a relatively high-power transistor that generates a large amount of heat. According to one or more embodiments, a heat sink 1280 may be coupled to the upper surface of the second semiconductor die 150 to dissipate heat from the second semiconductor die 150. Thermal paste (or another conductive medium) may be disposed between the upper surface of the second semiconductor die 150 and the heat sink 1280. According to one or more embodiments, the heat sink 1280 may contact and clamp into place with the upper surface. Alternatively, other attachment methods may be used to couple the heat sink 1280 to the second semiconductor die 150.

[0161] Figure 12 The arrangement shown represents a top-side cooling arrangement, in which heat generated by the second semiconductor die 150 is removed by a heat dissipation structure (e.g., heat sink 1280) coupled to the "top" of the power amplifier assemblies 100, 100', 100" . The top-side cooling arrangement may be advantageous in some cases because it can reduce the size of the entire system in which the amplifier system 1200 is incorporated.

[0162] Figure 13 A side cross-sectional view of a multistage amplifier system 1300 with a top-side cooling arrangement according to one or more other embodiments is shown. The amplifier system 1300 includes a system substrate 1301 and power amplifier components 300, 300', 300" (e.g., any embodiment of components 300, 300', 300"). Figure 3 , 4A-4C). The system substrate 1301 has a substrate mounting surface 1302 and an opposite bottom surface 1303. For example, the system substrate 1301 may be a PCB or other suitable substrate.

[0163] Multiple conductive wiring traces and pads are formed on the substrate mounting surface 1302. For example, the multiple conductive wiring traces and pads may include a portion of a patterned conductive layer on the substrate mounting surface 1302. According to one or more embodiments, the multiple conductive wiring traces and pads include an amplifier input terminal 1391, an amplifier output terminal 1393, and a ground terminal 1324 located between the amplifier input terminal 1391 and the amplifier output terminal 1393, as well as other features.

[0164] According to one or more embodiments, power amplifier components 300, 300', 300" (e.g., component 300, 300', or 300"). Figure 3 , 4A -4C) Physically coupled to the substrate mounting surface 1302, and electrically coupled between the amplifier input terminal 1391 and the amplifier output terminal 1393. The power amplifier assemblies 300, 300', 300" include a first semiconductor die 110' and a second semiconductor die 150, as combined Figure 3 and 4A -4C (details described in detail). According to one or more embodiments, a non-conductive encapsulation material 1390 may be disposed above the mounting surface of the first semiconductor die 110' and around the sidewalls of the second semiconductor die 150 to provide relatively flat top surfaces of the assemblies 300, 300', 300"". Preferably, the surface of the second semiconductor die 150 is exposed at the flat top surfaces of the assemblies 300, 300', 300"".

[0165] Such as combination Figure 3 , 4AAs discussed in -4C, the conductive substrate 124' at the bottom of the power amplifier assemblies 300, 300', 300" can be patterned to provide a first die input terminal 125', a conductive feature 126' corresponding to a ground reference node, and a first die output terminal 127'. According to one or more embodiments, in order to physically and electrically couple the power amplifier assemblies 300, 300', or 300" to the system substrate 1301, the first die input terminal 125' can be physically coupled (e.g., soldered) to the amplifier input terminal 1391 (or coupled to a trace / pad coupled to terminal 1391), the first die output terminal 127' can be physically coupled (e.g., soldered) to the amplifier output terminal 1393 (or coupled to a trace / pad coupled to terminal 1393), and the conductive feature 126' can be physically coupled (e.g., soldered) to the ground terminal 1324. As previously described, the conductive feature 126' of die 110' may correspond to a ground reference node of component 300, 300', or 300". According to one or more embodiments, a conductive layer (unmarked) at the bottom surface 1303 of system substrate 1301 may correspond to a system ground reference, and the conductive feature 126' of die 110' may be electrically coupled to the system ground reference through one or more conductive vias (unmarked) extending between the mounting surface 1302 and the bottom surface 1303 of system substrate 1301.

[0166] The multistage amplifier system 1300 includes two amplification stages coupled in a cascaded arrangement. More specifically, the system 1300 includes a first amplification stage corresponding to a first transistor 130 integrated in a first semiconductor die 110', and a second amplification stage corresponding to a second transistor 170 integrated in a second semiconductor die 150.

[0167] Similarly, the second transistor 170 in the second semiconductor die 150 can be a relatively high-power transistor that generates a significant amount of heat. According to one or more embodiments, to dissipate heat from the second semiconductor die 150, an optional hot inserter 1382 having an embedded coin (or thermal via) and a heat sink 1380 can be coupled to the top surface of the components 300, 300', 300" in particular to the exposed upper surface of the second semiconductor die 150. According to one or more embodiments, the hot inserter 1382 (if used) and the heat sink 1380 can contact and clamp into place with the top surface of the components 300, 300', 300" in one or more embodiments. Alternatively, other attachment methods can be used to couple the hot inserter 1382 (if used) and the heat sink 1380 to the components 300, 300', 300" in another manner.

[0168] same, Figure 13The arrangement shown represents a top-side cooling arrangement, in which heat generated by the second semiconductor die 150 is removed by a heat dissipation structure (e.g., heat sink 1380) coupled to the "top" of the power amplifier assemblies 300, 300', 300" . As previously mentioned, a top-side cooling arrangement may be advantageous in certain situations because it can reduce the size of the entire system in which the amplifier system 1300 is incorporated.

[0169] at last, Figure 14 A side cross-sectional view of a multistage amplifier system 1400 with a bottom-side cooling arrangement according to one or more other embodiments is shown. The amplifier system 1400 includes a system substrate 1401 and power amplifier components 300, 300', 300" (e.g., any embodiment of components 300, 300', 300"). Figure 3 , 4A -4C). The system substrate 1401 has a substrate mounting surface 1402 and an opposite bottom surface 1403. For example, the system substrate 1401 may be a PCB or other suitable substrate. According to one or more embodiments, the system substrate 1401 also includes a thermally conductive coin 1482 (or a plurality of thermal vias) extending between the mounting surface 1402 and the bottom surface 1403.

[0170] Multiple conductive wiring traces and pads are formed on the substrate mounting surface 1402. For example, the multiple conductive wiring traces and pads may include a portion of a patterned conductive layer on the substrate mounting surface 1402. According to one or more embodiments, the multiple conductive wiring traces and pads include an amplifier input terminal 1491, an amplifier output terminal 1493, and a ground terminal 1424 located between the amplifier input terminal 1491 and the amplifier output terminal 1493, as well as other features.

[0171] According to one or more embodiments, power amplifier components 300, 300', 300" (e.g., component 300, 300', or 300"). Figure 3 , 4A -4C) Physically coupled to the substrate mounting surface 1402, and electrically coupled between the amplifier input terminal 1491 and the amplifier output terminal 1493. The power amplifier assemblies 300, 300', 300" include a first semiconductor die 110' and a second semiconductor die 150, as combined Figure 3 and 4A -4C (details described in detail). According to one or more embodiments, a non-conductive encapsulation material 1490 may be disposed above the mounting surface of the first semiconductor die 110' and around the sidewalls of the second semiconductor die 150 to provide relatively flat surfaces for the assemblies 300, 300', 300"". Preferably, the surface of the second semiconductor die 150 is exposed at the flat surfaces of the assemblies 300, 300', 300"".

[0172] Such as combination Figure 3 , 4A As discussed in -4C, the conductive substrate 124' at the bottom of the power amplifier assemblies 300, 300', 300" can be patterned to provide a first die input terminal 125', a conductive feature 126' corresponding to a ground reference node, and a first die output terminal 127'. To physically couple the power amplifier assemblies 300, 300', 300" to the system substrate 1401, the outer surface of the package material 1490 and the second semiconductor die 150 contacts the ground terminal 1424, thus securing the assemblies 300, 300', 300" and the system substrate 1401 together.

[0173] To electrically couple power amplifier assemblies 300, 300', 300" to amplifier input 1491, a first end of one or more input wire bonds 106 is connected to amplifier input 1491 (or to a trace / pad coupled to end 1491), and a second end of the input wire bonds 106 is connected to the first die input 125' (bonding pad) of power amplifier assemblies 300, 300', 300" . Similarly, to electrically couple power amplifier assemblies 300, 300', 300" to amplifier output 1493, a first end of one or more output wire bonds 107 is connected to the first die output 127' (bonding pad), and a second end of the output wire bonds 107 is connected to amplifier output 1493 (or to a trace / pad coupled to end 1493).

[0174] The multistage amplifier system 1400 includes two amplification stages coupled in a cascaded arrangement. More specifically, the system 1400 includes a first amplification stage corresponding to a first transistor 130 integrated in a first semiconductor die 110', and a second amplification stage corresponding to a second transistor 170 integrated in a second semiconductor die 150.

[0175] Similarly, the second transistor 170 in the second semiconductor die 150 can be a relatively high-power transistor that generates a large amount of heat. According to one or more embodiments, when components 300, 300', 300" are coupled to system substrate 1401, the exposed surface of the second semiconductor die 150 is in thermal contact with a thermally conductive coin 1482 in system substrate 1401. A heat sink 1480 can be coupled to (e.g., clamped to) the bottom surface 1403 of system substrate 1401. In this way, Figure 14 The arrangement shown represents a bottom-side cooling arrangement, in which heat generated by the second semiconductor die 150 is removed by a heat dissipation structure (e.g., heat sink 1480) coupled to the “bottom” of the system substrate 1401.

[0176] In summary, one or more embodiments of a power amplifier assembly include a first semiconductor die and a second semiconductor die. The first semiconductor die is formed of a first semiconductor material and includes a mounting surface, a first die input terminal, a first die output terminal, a first transistor, and a die mounting interface. The die mounting interface is located at the mounting surface and includes at least one first contact pad, at least one second contact pad, and at least one third contact pad. The first transistor is integrally formed within the first semiconductor die and includes a first transistor gate terminal electrically coupled to the first die input terminal and a first transistor drain terminal electrically coupled to the at least one first contact pad of the die mounting interface.

[0177] The second semiconductor die is formed of a second semiconductor material, and the second semiconductor die is physically and electrically coupled to the die mounting interface at the mounting surface of the first semiconductor die. The second semiconductor die includes a second die interface surface and a second transistor. The second transistor is integrally formed within the second semiconductor die, and the second transistor includes a second transistor gate terminal coupled to at least one second transistor gate pad located at the second die interface surface, a second transistor source region coupled to at least one second transistor source pad located at the second die interface surface, and a second transistor drain terminal coupled to at least one second transistor drain pad located at the second die interface surface. The at least one second transistor gate pad is physically and electrically coupled to the at least one first contact pad, the at least one second transistor source pad is physically and electrically coupled to the at least one second contact pad, and the at least one second transistor drain pad is physically and electrically coupled to the at least one third contact pad.

[0178] According to one or more other embodiments, a die-to-die interconnect system physically and electrically couples the first semiconductor die and the second semiconductor die together. According to some embodiments, the die-to-die interconnect system includes a plurality of direct solder connections between the at least one first contact pad, the at least one second contact pad, and the at least one third contact pad and the at least one second transistor gate pad, the at least one second transistor source pad, and the at least one second transistor drain pad. According to other embodiments, the die-to-die interconnect system includes at least one first conductive post connected between the at least one first contact pad and the at least one second transistor gate pad; at least one second conductive post connected between the at least one second contact pad and the at least one second transistor source pad; and at least one third conductive post connected between the at least one third contact pad and the at least one second transistor drain pad.

[0179] According to one or more other embodiments, the first die input terminal is located at the mounting surface of the first semiconductor die and includes a first bonding pad configured to connect to one or more input lead bonding pads, and the first die output terminal is located at the mounting surface of the first semiconductor die and includes a second bonding pad configured to connect to one or more output lead bonding pads.

[0180] According to one or more other embodiments, the first semiconductor die further includes a first conductive feature, a second conductive feature, and a third conductive feature, the first conductive feature, the second conductive feature, and the third conductive feature being formed by a first portion, a second portion, and a third portion of a patterned conductive layer at the bottom surface of the first semiconductor die. The first conductive feature corresponds to an input terminal of the first die, the second conductive feature corresponds to a ground reference node, and the third conductive feature corresponds to an output terminal of the first die. The first conductive feature and the second conductive feature are separated by a first non-conductor region at the bottom surface, and the second conductive feature and the third conductive feature are separated by a second non-conductor region at the bottom surface. A first conductive through-substrate via electrically couples the gate terminal of the first transistor to the first conductive feature. A second conductive through-substrate via electrically couples the at least one second contact pad to the second conductive feature. A third conductive through-substrate via electrically couples the at least one third contact pad to the third conductive feature.

[0181] One or more embodiments of a multi-stage amplifier system include a system substrate and a power amplifier assembly. The system substrate has a top surface, an amplifier input, and an amplifier output. The power amplifier assembly is coupled to the top surface of the substrate and includes a first semiconductor die and a second semiconductor die.

[0182] The first semiconductor die is formed of a first semiconductor material and includes a mounting surface, a bottom surface, a first die input terminal electrically coupled to the amplifier input terminal, a first die output terminal electrically coupled to the amplifier output terminal, a first transistor, and a die mounting interface. The die mounting interface is located at the mounting surface and includes at least one first contact pad, at least one second contact pad, and at least one third contact pad. The first transistor is integrally formed within the first semiconductor die and includes a first transistor gate terminal electrically coupled to the first die input terminal and a first transistor drain terminal electrically coupled to the at least one first contact pad of the die mounting interface.

[0183] The second semiconductor die is formed of a second semiconductor material and is physically and electrically coupled to the die mounting interface at the mounting surface of the first semiconductor die. The second semiconductor die includes a second die interface surface, a second surface opposite to the second die interface surface, and a second transistor. The second transistor is integrally formed within the second semiconductor die and includes a second transistor gate terminal coupled to at least one second transistor gate pad located at the second die interface surface, a second transistor source region coupled to at least one second transistor source pad located at the second die interface surface, and a second transistor drain terminal coupled to at least one second transistor drain pad located at the second die interface. The at least one second transistor gate pad is physically and electrically coupled to the at least one first contact pad, the at least one second transistor source pad is physically and electrically coupled to the at least one second contact pad, and the at least one second transistor drain pad is physically and electrically coupled to the at least one third contact pad.

[0184] The connecting lines shown in the various figures contained herein are intended to illustrate exemplary functional relationships and / or physical couplings between various elements. It should be noted that many alternative or additional functional relationships or physical connections may exist in embodiments of this subject matter. Furthermore, certain terms may be used herein for illustrative purposes only and are therefore not intended to be limiting, and the terms “first,” “second,” and other such numerical terms relating to structures do not imply order or sequence unless the context clearly indicates otherwise.

[0185] As used herein, a “node” refers to any internal or external reference point, connection point, junction, signal line, conductive element, etc., where a given signal, logic level, voltage, data mode, current, or quantity exists. Furthermore, two or more nodes can be implemented by a single physical element (and even if received or output at a common node, two or more signals can be multiplexed, modulated, or otherwise distinguished).

[0186] The above description refers to elements, nodes, or features that are “connected” or “coupled” together. As used herein, unless explicitly stated otherwise, “connected” means that one element is directly engaged to (or directly connected to) another element, and not necessarily mechanically engaged to (or directly connected to) another element. Similarly, unless explicitly stated otherwise, “coupled” means that one element is directly or indirectly engaged to (or directly or indirectly electrically connected to, or otherwise connected to) another element, and not necessarily mechanically engaged. Therefore, although the schematic diagrams shown in the accompanying drawings depict an exemplary arrangement of elements, additional intermediate elements, devices, features, or components may be present in embodiments of the depicted subject matter.

[0187] As used herein, the terms “exemplary” and “example” mean “serving as an example, instance, or illustration.” Any embodiment described herein as exemplary or illustrative should not necessarily be construed as preferred or advantageous over other embodiments. Furthermore, there is no intention to be bound by any express or implied theory presented in the foregoing technical field, background art, or specific embodiments.

[0188] While at least one exemplary embodiment has been presented in the detailed description above, it should be understood that numerous variations exist. It should also be understood that the one or more exemplary embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. Rather, the detailed description above will provide those skilled in the art with a convenient roadmap for implementing the one or more embodiments described. It should be understood that various changes can be made to the function and arrangement of the elements without departing from the scope defined by the claims, which include equivalents known and foreseeable at the time of filing this patent application.

Claims

1. A power amplifier assembly, characterized in that, include: A first semiconductor die formed of a first semiconductor material, the first semiconductor die including a mounting surface, a first die input terminal, a first die output terminal, a first transistor, and a die mounting interface, wherein... The die mounting interface is located on the mounting surface, and the die mounting interface includes at least one first contact pad, at least one second contact pad, and at least one third contact pad. The first transistor is integrally formed within the first semiconductor die, and the first transistor includes a first transistor gate terminal electrically coupled to the input terminal of the first die and a first transistor drain terminal electrically coupled to the at least one first contact pad of the die mounting interface; as well as A second semiconductor die formed of a second semiconductor material, wherein the second semiconductor die is physically and electrically coupled to the die mounting interface at the mounting surface of the first semiconductor die, and the second semiconductor die includes a second die interface surface and a second transistor, wherein... The second transistor is integrally formed within the second semiconductor die, and the second transistor includes a second transistor gate terminal coupled to at least one second transistor gate pad located on the surface of the second die interface, a second transistor source region coupled to at least one second transistor source pad located on the surface of the second die interface, and a second transistor drain terminal coupled to at least one second transistor drain pad located on the surface of the second die interface. The at least one second transistor gate pad is physically and electrically coupled to the at least one first contact pad. The at least one second transistor source pad is physically and electrically coupled to the at least one second contact pad, and The at least one second transistor drain pad is physically and electrically coupled to the at least one third contact pad.

2. The power amplifier assembly according to claim 1, characterized in that: The first semiconductor material of the first semiconductor die is selected from the group of semiconductor materials composed of silicon and silicon carbide; and The second semiconductor material of the second semiconductor die is selected from the group of semiconductor materials composed of gallium nitride, gallium arsenide, gallium phosphide, indium phosphide and indium antimonide.

3. The power amplifier assembly according to claim 1, characterized in that, In addition, including: A die-to-die interconnect system that physically and electrically couples a first semiconductor die and a second semiconductor die together, wherein the die-to-die interconnect system includes a plurality of direct solder connections between the at least one first contact pad, the at least one second contact pad and the at least one third contact pad and the at least one second transistor gate pad, the at least one second transistor source pad and the at least one second transistor drain pad.

4. The power amplifier assembly according to claim 1, characterized in that, In addition, including: A die-to-die interconnect system that physically and electrically couples a first semiconductor die and a second semiconductor die together, wherein the die-to-die interconnect system includes... At least one first conductive post is connected between the at least one first contact pad and the at least one second transistor gate pad. At least one second conductive post, the at least one second conductive post being connected between the at least one second contact pad and the at least one second transistor source pad, and At least one third conductive post is connected between the at least one third contact pad and the at least one second transistor drain pad.

5. The power amplifier assembly according to claim 1, characterized in that, The first semiconductor die further includes: The bottom surface is opposite to the mounting surface; A grounding reference node, wherein the grounding reference node is located on the bottom surface, and A conductive through-substrate via electrically couples the at least one second contact pad to the ground reference node.

6. The power amplifier assembly according to claim 5, characterized in that: The ground reference node includes a conductive layer at the bottom surface of the first semiconductor die; The first die input terminal is located at the mounting surface of the first semiconductor die and includes a first bonding pad configured to connect to one or more input lead bonding pads; and The first die output terminal is located at the mounting surface of the first semiconductor die and includes a second bonding pad configured to connect to one or more output lead bonding pads.

7. The power amplifier assembly according to claim 6, characterized in that: The second bonding pad and the at least one third contact pad form a portion of a single conductive feature.

8. The power amplifier assembly according to claim 5, characterized in that, The first semiconductor die further includes: A first conductive feature is formed by a first portion of a patterned conductive layer at the bottom surface of the first semiconductor die, wherein the first conductive feature corresponds to the input terminal of the first die. The second conductive feature is formed by a second portion of the patterned conductive layer, wherein the first conductive feature and the second conductive feature are separated by a first non-conductor region at the bottom surface, and wherein the second conductive feature corresponds to the ground reference node; The third conductive feature is formed by a third portion of the patterned conductive layer, wherein the second conductive feature and the third conductive feature are separated by a second non-conductor region at the bottom surface, and wherein the third conductive feature corresponds to the first die output terminal; The first conductive through-substrate via electrically couples the gate terminal of the first transistor to the first conductive feature. A second conductive through-substrate via electrically couples the at least one second contact pad to the second conductive feature; and A third conductive through-substrate via electrically couples the at least one third contact pad to the third conductive feature.

9. The power amplifier assembly according to claim 1, characterized in that, The first semiconductor die further includes: An impedance matching circuit is electrically connected between the drain terminal of the first transistor and at least one first contact pad of the die mounting interface.

10. A multi-stage amplifier system, characterized in that, include: A system substrate, the system substrate including a top surface of the substrate, an amplifier input terminal and an amplifier output terminal; A power amplifier assembly coupled to the top surface of the substrate, wherein the power amplifier assembly includes a first semiconductor die and a second semiconductor die, and wherein... The first semiconductor die is formed of a first semiconductor material, and the first semiconductor die includes a mounting surface, a bottom surface, a first die input terminal electrically coupled to the input terminal of the amplifier, a first die output terminal electrically coupled to the output terminal of the amplifier, a first transistor, and a die mounting interface, wherein... The die mounting interface is located on the mounting surface, and the die mounting interface includes at least one first contact pad, at least one second contact pad, and at least one third contact pad. The first transistor is integrally formed within the first semiconductor die, and the first transistor includes a first transistor gate terminal electrically coupled to the input terminal of the first die and a first transistor drain terminal electrically coupled to the at least one first contact pad of the die mounting interface; as well as The second semiconductor die is formed of a second semiconductor material, wherein the second semiconductor die is physically and electrically coupled to the die mounting interface at the mounting surface of the first semiconductor die, and the second semiconductor die includes a second die interface surface, a second surface opposite to the second die interface surface, and a second transistor, wherein... The second transistor is integrally formed within the second semiconductor die, and the second transistor includes a second transistor gate terminal coupled to at least one second transistor gate pad located on the surface of the second die interface, a second transistor source region coupled to at least one second transistor source pad located on the surface of the second die interface, and a second transistor drain terminal coupled to at least one second transistor drain pad located on the surface of the second die interface. The at least one second transistor gate pad is physically and electrically coupled to the at least one first contact pad. The at least one second transistor source pad is physically and electrically coupled to the at least one second contact pad, and The at least one second transistor drain pad is physically and electrically coupled to the at least one third contact pad.

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