A low parasitic high frequency parallel switch die structure circuit
By employing a low-parasitic, high-frequency parallel switch die structure and using discrete source modules and grounding vias, the problem of poor isolation in traditional switching circuits under high-frequency conditions is solved. This achieves improved isolation and grounding performance without increasing area or losses, and is suitable for various semiconductor process platforms and switching structures.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NO 55 INST CHINA ELECTRONIC SCI & TECHNOLOGYGROUP CO LTD
- Filing Date
- 2026-01-30
- Publication Date
- 2026-06-05
AI Technical Summary
Traditional switching circuits have poor isolation under high-frequency conditions, which leads to signal leakage, affects system performance, and increases insertion loss and switching time. It is impossible to improve isolation without increasing the circuit area.
It adopts a low parasitic high-frequency parallel switch die structure, and optimizes the grounding impedance when the die is turned on by designing discrete source modules and grounding holes, forming a signal path of "microstrip-common node-microstrip" or "microstrip-parallel switch die-microstrip" to improve isolation.
Without increasing circuit area and insertion loss, it significantly improves the isolation of switching circuits, suppresses high-frequency signal leakage, and improves grounding performance. It is suitable for various semiconductor process platforms and switching structures.
Smart Images
Figure CN122159841A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of basic electrical components, specifically to a low-parasitic high-frequency parallel switch die structure circuit. Background Technology
[0002] In electronic communication systems, switching transistors serve as components that control the on / off state of switching branches, allowing signals to be in either a conducting or isolated state in different switching branches. They have wide applications in communication and measurement systems. The main technical specifications of switching circuits include: operating bandwidth, insertion loss, isolation, switching time, and area.
[0003] However, as the operating frequency increases, the high-frequency isolation of the switching circuit deteriorates, leading to signal leakage between different switching branches. This causes the receiving branch components to burn out during large signal transmission and the receiving noise to worsen during small signal reception. Traditional methods to improve the isolation of switching circuits include: (1) increasing the number and size of parallel switching transistors; (2) increasing the size of series transistors. While these methods can increase the switching isolation to a limited extent, they also significantly increase the insertion loss when the switching circuit is turned on, increase the area of the switching circuit, and worsen indicators such as switching time. This seriously affects the overall transmission efficiency and receiving noise, and reduces the detection distance and receiving sensitivity of the entire system. Summary of the Invention
[0004] To address these shortcomings, the present invention aims to effectively reduce the parasitic effects of the die by adopting a low-parasitic high-frequency parallel switch die structure. This optimizes the die's impedance to ground when it is on, enabling the switching circuit to achieve a significant improvement in high isolation during turn-off without increasing insertion loss. At the same time, it does not increase the area or switching time of the switching circuit, thus showing promising application prospects.
[0005] To address the problems in the existing technology, the technical solution adopted by this invention is as follows: A low-parasitic high-frequency parallel switch die structure circuit includes at least two microstrips and at least one parallel switch die. The parallel switch die includes at least one parallel switch die unit, which consists of a drain module, two gate modules, two source modules, a drain terminal D, and at least two gate terminals. The gate modules and source modules are arranged sequentially on either side of the drain module, with the drain terminal D located at one end of the parallel switch die. The source modules are grounded through a ground hole, and the gate modules are led out through the gate terminals. In the low parasitic high frequency parallel switch die structure circuit, the drain terminal D of the parallel switch die is connected to the common node between two adjacent microstrips, and the signal path formed is "microstrip-common node-microstrip". Alternatively, in the low parasitic high-frequency parallel switch die structure circuit, the parallel switch dies are connected in parallel between two adjacent microstrips, forming part of the main signal path, and the resulting signal path is "microstrip-parallel switch die-microstrip". Alternatively, the low-parasitic high-frequency parallel switch die structure circuit may be a combination in which some parallel switch dies are connected in parallel between two adjacent microstrips and the drain terminal D of some parallel switch dies is connected to a common node between two adjacent microstrips.
[0006] Preferably, the low-parasitic high-frequency parallel switch die structure circuit includes n+1 microstrips and n parallel switch dies, where 1≤n≤20 is an integer. The connection method of the low-parasitic high-frequency parallel switch die structure circuit is as follows: one end of the first microstrip is connected to the RF port RF1, and the other end is connected to the common node of the drain terminal D of the first parallel switch die and one end of the second microstrip. The other end of the second microstrip is connected to the common node of the drain terminal D of the second parallel switch die and one end of the third microstrip. The microstrips are connected in this order. The other end of the i-th microstrip is connected to the common node of the drain terminal D of the i-th parallel switch die and one end of the (i+1)-th microstrip. The other end of the (i+1)-th microstrip is connected to the RF port RF2, where i=1, 2, …, n.
[0007] Preferably, all n parallel switch chips are located on the same side of the microstrip.
[0008] Preferably, the low parasitic high-frequency parallel switch die structure circuit includes m+1 microstrips and 2m parallel switch dies, and the 2m parallel switch dies are symmetrically connected on the common node between the m and m+1 microstrips of two adjacent microstrips, and m=1,2,…,n.
[0009] Preferably, the parallel switch die is composed of k parallel switch die units, where 1 ≤ k ≤ 10.
[0010] More preferably, when k is an integer of 2≤k≤10, adjacent parallel switch die units share the source module between them, and the drain module of each parallel switch die unit is connected to the same drain terminal D.
[0011] Preferably, the gate module has a multi-gate structure, the number of gates is G and 1≤G≤10 is an integer, and each gate is independently provided with a gate terminal.
[0012] Preferably, the multi-gate structure is a dual-gate structure or a triple-gate structure.
[0013] Preferably, the number of ground holes j in the source module is an integer 1 ≤ j ≤ 10, and the shape of the ground holes is elliptical, circular, square or polygonal.
[0014] A switching device comprising a low parasitic high-frequency parallel switch die structure circuit as described in any of the preceding claims. Beneficial effects
[0015] Compared to traditional parallel switch die structure circuits, this invention provides a parallel switch die structure circuit scheme that maintains excellent conduction and grounding characteristics and low parasitic parameters under high-frequency conditions. Through an innovative structural design of discrete sources and grounding vias, it achieves significant structural and performance innovations while maintaining the basic performance of traditional switch dies. It effectively overcomes the key challenges of grounding performance degradation and isolation reduction under high-frequency conditions, possessing comprehensive advantages such as simple structure, process compatibility, and adjustable performance. It is suitable for communication, radar, and measurement systems with strict requirements for high-frequency isolation and grounding characteristics. It has the following effects: Optimized isolation performance: In the parallel switch die structure circuit of this invention, a discrete source-level module design is adopted. While ensuring that other indicators are normal and meet the requirements, the signal isolation between each switch branch is significantly improved. The maximum point isolation can be improved by more than 60%, thereby effectively suppressing high-frequency signal leakage.
[0016] Grounding performance advantages: Compared with the traditional parallel switch die structure, the die structure with discrete source and discrete grounding hole adopted in this invention exhibits better grounding continuity and low impedance characteristics when the switch branch is in the off state (i.e. when the switch die is on), thereby making the switch circuit based on this structure have higher isolation and stronger overall anti-interference capability.
[0017] Process and structural universality: The proposed method is not dependent on specific semiconductor processes or switching device types, and can be widely applied to various process platforms such as silicon-based and compound semiconductors (such as GaAs and GaN). It is suitable for various switching structures such as lateral or vertical, and has good technology portability and adaptability.
[0018] Scalable design: The number of discrete source modules in the circuit can be flexibly adjusted and optimized according to the actual switching circuit performance indicators (such as isolation, insertion loss, power capacity, etc.). It can be increased to further improve performance, or it can be simplified appropriately to control complexity and cost, reflecting a high degree of design freedom and system adaptability. Attached Figure Description
[0019] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort. In the drawings: Figure 1 The circuit diagram of the low parasitic high frequency parallel switch die structure shown in Embodiment 1 of the present invention is shown. Figure 2(a) is a circuit diagram of n parallel switch chips and n+1 microstrips combined, with the n parallel switch chips located on one side of the main signal microstrip, as shown in Embodiment 2 of the present invention. Figure 2(b) is a circuit diagram of 2m parallel switch chips and m+1 microstrips combined in Embodiment 2 of the present invention, with the 2m parallel switch chips located on both sides of the main signal microstrip. Figure 3 (a) is a structural diagram of the parallel switch die shown in Embodiment 3 of the present invention, in which both gate module 1 and gate module 2 are dual-gate structures and the gate terminals are respectively led out to the outside; Figure 3 (b) is a structural diagram of the parallel switch die shown in Embodiment 3 of the present invention, in which both gate module 1 and gate module 2 are three-gate structures and the gate terminals are respectively led out to the outside; Figure 4 This is a structural diagram of the parallel switch die shown in Embodiment 4 of the present invention, in which both the source module 1 and the gate module 2 adopt two elliptical ground holes. Figure 5 (a) is a structural diagram of the parallel switch die 1 shown in Embodiment 5 of the present invention, which includes two parallel switch die units, and adjacent source modules in the parallel switch die units are shared, drain modules are connected together to form drain terminal D, and gate modules are led out through gate terminals respectively. Figure 5 (b) is a structural diagram of the parallel switch die 1 shown in Embodiment 5 of the present invention, which includes k parallel switch die units, and adjacent source modules in the parallel switch die units are shared, drain modules are connected together to form drain terminal D, and gate modules are led out through gate terminals respectively. Figure 6(a) is a circuit diagram of a parallel switch die shown in Embodiment 6 of the present invention, in which the entire drain module is connected in parallel to the circuit and the source module and gate module are separated on both sides of the circuit. Figure 6(b) is a circuit diagram of n parallel switch dies in Embodiment 6 of the present invention, in which the entire drain module is connected in parallel to the circuit and the source module and gate module are separated on both sides of the circuit. Figure 7This is a circuit diagram of a low parasitic high-frequency parallel switch chip structure, which is composed of parallel switch chip 1 and parallel switch chip 2 combined in different access methods, as shown in Embodiment 7 of the present invention. Figure 8 The diagram shows a comparison of the isolation versus frequency between the conventional high-frequency parallel switch die structure circuit and the low-parasitic high-frequency parallel switch die structure circuit in Example 1. Figure 9 This is a circuit diagram of a traditional parallel switch chip structure. Detailed Implementation
[0020] The present invention will be further illustrated below with reference to the accompanying drawings and specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. After reading this invention, any modifications of the invention in various equivalent forms by those skilled in the art will fall within the scope defined by the appended claims.
[0021] The fabrication process of the low-parasitic high-frequency parallel switch die structure circuit of this invention employs GaN, GaAs, CMOS, InP, SOI, or SiGe processes, all of which are conventional technologies in the field. These are not the focus of this invention; only the circuit fabrication needs to be achieved. Example
[0022] like Figure 1 As shown, the low parasitic high-frequency parallel switch die structure circuit consists of microstrip 1, microstrip 2, parallel switch die 1, radio frequency port RF1 and radio frequency port RF2. One end of microstrip 1 is connected to radio frequency port RF1, and the other end is connected to the common terminal of the drain terminal D of parallel switch die 1 and one end of microstrip 2. The other end of microstrip 2 is connected to radio frequency port RF2.
[0023] The parallel switch die 1 includes a parallel switch die unit composed of a drain module 1, a gate module 1, a gate module 2, a source module 1, a source module 2, a drain terminal D, a gate terminal G1, and a gate terminal G2. The parallel switch die unit is centered on the drain module 1, with gate modules 1 and 2 on both sides respectively. One end of each gate module is led out through gate terminal G1 and gate terminal G2 respectively. A source module is provided on the outer side of each gate module 1 and gate module 2, and the two source modules are directly grounded through a ground hole. Example
[0024] As shown in Figure 2(a), the low parasitic high-frequency parallel switch die structure circuit includes n parallel switch dies and n+1 microstrip combinations (n ≤ 20 integers), with all n parallel switch dies located on one side of the microstrip combination. One end of the RF port RF1 is connected to one end of microstrip 1, and the other end of microstrip 1 is connected to the common terminal of the drain terminal D of parallel switch die 1 and one end of microstrip 2. The other end of microstrip 2 is connected to the common terminal of the drain terminal D of parallel switch die 2 and one end of microstrip 3, and so on. The other end of microstrip n is connected to the common terminal of the drain terminal D of parallel switch die n and one end of microstrip n+1, and the other end of microstrip n+1 is connected to the RF port RF2.
[0025] As shown in Figure 2(b), the low parasitic high-frequency parallel switch die structure circuit includes 2m parallel switch dies and m+1 microstrip combinations (m ≤ 20 integers), with the 2m parallel switch dies equally located on both sides of the main signal microstrip. One end of the RF port RF1 is connected to one end of microstrip 1, and the other end of microstrip 1 is connected to the common terminal of the drain terminal D of the parallel switch die 1 on both sides and one end of microstrip 2. The other end of microstrip 2 is connected to the common terminal of the drain terminal D of the parallel switch die 2 on both sides and one end of microstrip 3, and so on. The other end of microstrip m is connected to the common terminal of the drain terminal D of the parallel switch die m on both sides and one end of microstrip m+1, and the other end of microstrip m+1 is connected to the RF port RF2.
[0026] In practical applications, the components can be combined as needed. In a low-parasitic-frequency parallel switch die structure circuit, some of the parallel switch dies can be located on one side of the main signal microstrip, while the other part can be located on both sides of the main signal microstrip. Example
[0027] Based on Example 1, the structure was further optimized.
[0028] like Figure 3 As shown in (a), gate module 1 and gate module 2 in the parallel switch die are both dual-gate structures, and gate terminals G11, G12, G21 and G22 are led out to the outside respectively.
[0029] like Figure 3 As shown in (b), gate module 1 and gate module 2 in the parallel switch die are both three-gate structures, and the gate terminals are led out to the outside respectively.
[0030] In practical use, the gate modules can be combined as needed. They can be independently selected from single-gate, double-gate, triple-gate, or G-gate (integers of 1≤G≤10), and the gate terminals can be led out separately or connected together before being led out. Example
[0031] Based on Example 1, the structure was further optimized.
[0032] like Figure 4 As shown, source module 1 and source module 2 in the parallel switch die both use two elliptical ground holes.
[0033] In actual use, the components can be combined as needed. The shape of the ground hole inside source module 1 or source module 2 is not fixed. It can be elliptical, circular, square or polygonal, and the number of ground holes must be at least 1. The number of ground holes in the source module can be increased by j (an integer from 1 to j to 10). Example
[0034] like Figure 5 As shown in (a), the parallel switch die 1 consists of two parallel switch die units, and adjacent source modules in the parallel switch die units are shared, the drain modules are connected together to form the drain terminal D, and the gate modules are led out through the gate terminals respectively.
[0035] like Figure 5 As shown in (b), the parallel switch die 1 consists of k (1≤k≤10 integers) parallel switch dies, and adjacent source modules in the parallel switch dies are shared, the drain modules are connected together to form the drain terminal D, and the gate modules are led out through the gate terminals respectively.
[0036] In practical use, they can be combined as needed. Each parallel switch die can be composed of different numbers of parallel switch die units. Adjacent source modules in the parallel switch die units are shared, drain modules are connected together to form drain terminal D, and gate modules can be led out separately or connected together and then led out through gate terminals. Example
[0037] As shown in Figure 6(a), a parallel switch die is connected to the circuit with the entire drain module in parallel, and the source module and gate module are separated on both sides of the circuit and connected between the two microstrips.
[0038] As shown in Figure 6(b), n parallel switching dies are connected to the circuit in parallel with the entire drain module, and the source module and gate module are separated on both sides of the circuit, and are alternately connected in the middle of n+1 microstrips (n≤20 integers). Example
[0039] like Figure 7As shown, the low parasitic high-frequency parallel switch die structure circuit consists of microstrip 1, microstrip 2, microstrip 3, parallel switch die 1, parallel switch die 2, RF port RF1, and RF port RF2. One end of microstrip 1 is connected to RF port RF1, and the other end is connected to the common terminal of the drain terminal D of parallel switch die 1 and one end of microstrip 2. The other end of microstrip 2 is connected to the common terminal of the entire drain module of parallel switch die 2 and one end of microstrip 3. The other end of microstrip 3 is connected to RF port RF2.
[0040] In practical applications, combinations can be made as needed. In the low parasitic high-frequency parallel switch die structure circuit, some parallel switch dies are connected between adjacent microstrips with the drain terminal D, and the entire drain module of some parallel switch dies is connected between adjacent microstrips to form any number of new combinations.
[0041] Figure 9 The conventional parallel switch die structure circuit comprises microstrip 1, microstrip 2, conventional parallel switch die 1, RF port RF1, and RF port RF2. One end of microstrip 1 is connected to RF port RF1, and the other end is connected to the common terminal of the drain terminal D of parallel switch die 1 and one end of microstrip 2. The other end of microstrip 2 is connected to RF port RF2. The conventional parallel switch die 1 comprises a drain module 1, gate module 1, gate module 2, source module 1, source module 2, ground via module 1, drain terminal D, gate terminal G1, and gate terminal G2. The conventional parallel switch die unit is centered on drain module 1, with gate module 1 and gate module 2 on both sides. One end of each gate module is led out through gate terminal G1 and gate terminal G2, respectively. Gate module 1 and gate module 2 are connected to a ground via module 1 and then grounded through the ground via.
[0042] Figure 8 This demonstrates a circuit utilizing the low-parasitic high-frequency parallel switch die structure from Example 1 and a conventional parallel switch die structure (structure as shown in Example 1). Figure 9 The relationship between isolation and frequency was investigated (as shown in the figure), and the results are as follows. Figure 8 As shown in the figure, the isolation improved by approximately 5 dB overall between frequencies F1 and F2, with the improvement becoming more pronounced at higher frequencies: an improvement of approximately 15 dB at frequency F2, representing an increase of over 60%. Similarly, tests using the circuits from Examples 6 and 7 also showed significant improvements.
[0043] The above detailed description of the present invention is for illustrative purposes only and is not intended to limit the technical solutions described in the embodiments of the invention. Those skilled in the art can still modify or make equivalent substitutions to the present invention to achieve the same technical effect; as long as the usage requirements are met, they are all within the protection scope of the present invention.
Claims
1. A low-parasitic high-frequency parallel switch die structure circuit, characterized in that, It includes at least two microstrips and at least one parallel switching die; The parallel switch die includes at least one parallel switch die unit, which consists of a drain module, two gate modules, two source modules, a drain terminal D, and at least two gate terminals. The gate modules and source modules are arranged sequentially on either side of the drain module, with the drain terminal D located at one end of the parallel switch die. The source modules are grounded through a ground hole, and the gate modules are led out through the gate terminals. In the low parasitic high frequency parallel switch die structure circuit, the drain terminal D of the parallel switch die is connected to the common node between two adjacent microstrips, and the signal path formed is "microstrip-common node-microstrip". Alternatively, in the low parasitic high-frequency parallel switch die structure circuit, the parallel switch dies are connected in parallel between two adjacent microstrips, forming part of the main signal path, and the resulting signal path is "microstrip-parallel switch die-microstrip". Alternatively, the low-parasitic high-frequency parallel switch die structure circuit may be a combination in which some parallel switch dies are connected in parallel between two adjacent microstrips and the drain terminal D of some parallel switch dies is connected to a common node between two adjacent microstrips.
2. The low parasitic high-frequency parallel switch die structure circuit according to claim 1, characterized in that, The low-parasitic high-frequency parallel switch die structure circuit includes n+1 microstrips and n parallel switch dies, where 1≤n≤20 is an integer. The connection method of the low-parasitic high-frequency parallel switch die structure circuit is as follows: one end of the first microstrip is connected to the RF port RF1, and the other end is connected to the common node of the drain terminal D of the first parallel switch die and one end of the second microstrip. The other end of the second microstrip is connected to the common node of the drain terminal D of the second parallel switch die and one end of the third microstrip. The connections are made in this order. The other end of the i-th microstrip is connected to the common node of the drain terminal D of the i-th parallel switch die and one end of the (i+1)-th microstrip. The other end of the (i+1)-th microstrip is connected to the RF port RF2, where i=1, 2,…, n.
3. The low parasitic high-frequency parallel switch die structure circuit according to claim 2, characterized in that, All n parallel switch chips are located on the same side of the microstrip.
4. The low parasitic high-frequency parallel switch die structure circuit according to claim 2, characterized in that, The low parasitic high-frequency parallel switch die structure circuit includes m+1 microstrips and 2m parallel switch dies, and the 2m parallel switch dies are symmetrically connected to the common node between the m and m+1 microstrips of two adjacent microstrips, where m=1, 2, …, n.
5. The low parasitic high-frequency parallel switch die structure circuit according to claim 1, characterized in that, The parallel switch die is composed of k parallel switch die units, where 1 ≤ k ≤ 10.
6. The low parasitic high-frequency parallel switch die structure circuit according to claim 5, characterized in that, When k is an integer of 2≤k≤10, adjacent parallel switch die units share the source module between them, and the drain module of each parallel switch die unit is connected to the same drain terminal D.
7. The low parasitic high-frequency parallel switch die structure circuit according to any one of claims 1-6, characterized in that, The gate module has a multi-gate structure, and the number of gates is G, which is an integer where 1 ≤ G ≤ 10. Each gate is independently provided with a gate terminal.
8. The low parasitic high-frequency parallel switch die structure circuit according to claim 7, characterized in that, The multi-gate structure is either a double-gate structure or a triple-gate structure.
9. The low-parasitic high-frequency parallel switch die structure circuit according to claims 1-8, characterized in that, The number of ground holes j in the source module is an integer 1 ≤ j ≤ 10, and the shape of the ground holes is elliptical, circular, square or polygonal.
10. A switching device, characterized in that, The circuit includes a low parasitic high-frequency parallel switch die structure as described in any one of claims 1 to 9.