Block structure decision generation circuitry based on memristive modulation

Abstract

The application discloses a block structure decision generation circuit system based on memristor modulation, which comprises a stimulation and action module, a reward and punishment module, a bias module and a 0% stimulation module. The third port of the stimulation and action module logic AND gate U3 and U4 is connected with the first port of the reward and punishment module logic OR gate U5. The third port of the reward and punishment module amplifier OP14 and the third port of the reward and punishment module amplifier OP15 are connected with the second port of the stimulation and action module adder SUM10 and the second port of the stimulation and action module adder SUM11. The third port of the stimulation and action module amplifier OP3 and the third port of the stimulation and action module amplifier OP7 are connected with the first port of the 0% stimulation module E1 and the first port of the 0% stimulation module E2. The fourth port of the 0% stimulation module control switch S6 and the fourth port of the 0% stimulation module control switch S7 are connected with the first port of the stimulation and action module adder SUM10 and the first port of the stimulation and action module adder SUM11. The purpose of achieving the cooperation of stimulation, bias, action and reward in a single structure, keeping stable decision under 0% visual stimulation condition, introducing expected bias in the decision loop and still being able to make a selection without external input is achieved.

Description

Technical Field

[0001] This invention relates to the fields of neuromorphic computing, memristor circuits, and autonomous decision control, specifically to a block-structure decision generation circuit system based on memristor modulation. Background Technology

[0002] Most existing neuromorphic decision-making methods rely on single stimulus-driven approaches, lacking integration of internal states and failing to simulate the closed-loop decision-making chain of "stimulus-action-reward" in real intelligent agents. Furthermore, traditional methods cannot maintain stable behavior under low-contrast, ambiguous stimuli, or completely absent external stimuli, while biological agents can make decisions in such environments by relying on internal predictive biases and past reward and punishment experiences.

[0003] Meanwhile, existing research typically relies solely on reward-driven decision-making, lacking a unified model for factors such as negative feedback, memory decay, and residual bias; furthermore, it has not implemented a block-structured decision-making framework in circuit systems that integrates multiple modules, including visual stimuli, expectation bias, action generation, and rewards and punishments.

[0004] Therefore, it is necessary to provide a decision-making method and circuit structure that can complete multiple modules under a unified system, handle low-contrast inputs, generate expected biases, and make adaptive adjustments based on rewards and punishments. Summary of the Invention

[0005] The purpose of this invention is to address the problems of existing decision-making systems being unable to achieve synergistic effects of stimulus, bias, action, and reward / punishment modules in a single structure, and the difficulty in maintaining stable decision-making under low contrast or even 0% visual stimulation conditions; at the same time, it addresses the problem that existing methods cannot introduce expected bias into the decision-making loop to enable the system to make choices even without external input.

[0006] To address the aforementioned problems, this invention proposes a block-structure decision generation circuit system based on memristor modulation, comprising:

[0007] The stimulus and action module, reward and punishment module, bias module, and 0% stimulus module are connected. The third ports of the AND gates U3 and U4 of the stimulus and action module are connected to the first port of the OR gate U5 of the reward and punishment module. The reward and punishment module is connected to the second ports of the adders SUM10 and SUM11 of the stimulus and action module through the third ports of amplifiers OP14 and OP15. The stimulus and action module is connected to the first ports of E1 and E2 of the 0% stimulus module through the third ports of amplifiers OP3 and OP7. The 0% stimulus module is connected to the first ports of the adders SUM10 and SUM11 of the stimulus and action module through the fourth ports of control switches S6 and S7.

[0008] In the preferred embodiment, the stimulus and action module includes a left-side stimulus and action module and a right-side stimulus and action module;

[0009] The left-side stimulation and action module includes: the Stimulation_Left terminal receives the input signal; the first output port of the Stimulation_Left terminal is connected to the input port of the voltage comparator; the output port of the voltage comparator is connected to the first port of the NAND gate U1; the second output port of the Stimulation_Left terminal is connected to the second port of the NAND gate U1; the third port of the NAND gate U1 is connected to the input port of the first 1 kΩ resistor; the output terminal of the first 1 kΩ resistor is connected to the negative port of the operational amplifier OP1; the positive port of the operational amplifier OP1 is connected to the ground wire; the output terminal of the first 1 kΩ resistor is also connected to the input terminal of a 200Ω resistor; the output terminal of the 200Ω resistor is connected to the output terminal of the operational amplifier OP1; the output terminals of the 200Ω resistor and the operational amplifier OP1 are connected to the first port of the adder SUM1; and the Stimulation_Left... The third output terminal of the adder is connected to the second port of the adder SUM1. The third port of the adder SUM1 is connected to the positive input terminal of the non-volatile memristor M1. The negative output terminal of the non-volatile memristor M1 is connected to the negative port of the operational amplifier OP2. The positive port of the operational amplifier OP2 is connected to the ground wire. The output port of the operational amplifier OP2 is connected to the input port of the second 1 kΩ resistor. The negative output terminal of the non-volatile memristor M1 and the negative port of the operational amplifier OP2 are connected to the input terminal of the 300Ω resistor. The output terminal of the 300Ω resistor is connected to the output port of the operational amplifier OP2 and the input port of the second 1 kΩ resistor. The output terminal of the second 1 kΩ resistor is connected to the negative port of the operational amplifier OP3. The positive port of the operational amplifier OP3 is connected to the ground wire. The output terminal of the kΩ resistor, the negative terminal of the operational amplifier OP3, and the input terminal of the 300Ω resistor are connected. The output terminal of the 300Ω resistor and the output terminal of the operational amplifier OP3 are connected to the positive terminal of the comparator OP4. The negative terminal of the comparator OP4 is connected to a 0.23V voltage source for the reference voltage. The first port of the comparator OP4 is connected to the ground wire. The second port of the comparator OP4 is connected to a 2V voltage source. The output port of the comparator OP4 outputs the left action determination signal Action_Left.

[0010] The structure of the right-side stimulus and action module is the same as that of the left-side stimulus and action module.

[0011] In the preferred embodiment, the reward / penalty module includes: Terminal A1 connected to the first input port of AND gate U3; Terminal Action_Left connected to the second input port of AND gate U3; the output port of AND gate U3 connected to the first input port of OR gate U5; Terminal A2 connected to the first input port of AND gate U4; Terminal Action_Right connected to the second input port of AND gate U4; the output port of AND gate U4 connected to the second input port of OR gate U5; the output port of OR gate U5 connected to the positive terminal of non-volatile memristor M3; the negative terminal of volatile memristor M3 connected to the input port of a 5 kΩ resistor; the output port of the 5 kΩ resistor connected to the negative terminal of operational amplifier OP9; the positive terminal of operational amplifier OP9 connected to ground; the negative terminal of operational amplifier OP9 connected to the input port of a third 1 kΩ resistor; and the output port of operational amplifier OP9 connected to the output port of the third 1 kΩ resistor and the input port of a fourth 1 kΩ resistor. The output port of the 1 kΩ resistor is connected to the negative port of operational amplifier OP10, the positive port of operational amplifier OP10 is connected to ground, the output port of operational amplifier OP10 is connected to the output port of the fifth 1 kΩ resistor, the input port of the fifth 1 kΩ resistor is connected to the negative port of operational amplifier OP10, the output port of operational amplifier OP10 is connected to the positive port of comparator OP11, the negative port of comparator OP7 is connected to a 0.1 V reference voltage source, the first power supply port of comparator OP11 is connected to a 2 V voltage source, the second power supply port of comparator OP11 is connected to a −2 V voltage source, and the output port of comparator OP11 outputs the action determination signal Action_Output; Action_Output is connected to the first port of adder SUM3, Resting... The potential terminal is connected to the second port of adder SUM3; the output port of adder SUM3 is connected to the first input port of AND gate U5; the output port of adder SUM1 is connected to the first input port of AND gate U8; terminal A1 is connected to the second input port of AND gate U8; terminal A2 is connected to the second input port of AND gate U9; the output port of AND gate U8 is connected to the control port of switch S3; the output port of AND gate U9 is connected to the control port of switch S4; the output port of adder SUM3 is connected to the input port of comparator T5.The second A1 terminal is connected to the first input port of the AND gate U6. The second input port of the AND gate U6 is connected to the output port of the comparator T5. The output port of the AND gate U6 is connected to the control port of the switch S1. The output port of the switch S1 is connected to the input terminal of the sixth 1 kΩ resistor. The output terminal of the sixth 1 kΩ resistor is connected to the negative terminal of the operational amplifier OP12. The positive terminal of the operational amplifier OP12 is connected to the ground wire. The output port of the operational amplifier OP12 is connected to the output port of the 500 Ω resistor. The input port of the 500 Ω resistor is connected to the negative terminal of the operational amplifier OP12 and the sixth 1 kΩ resistor. The output of the kΩ resistor is connected; the output port of operational amplifier OP12 is connected to the first port of adder SUM4; the output port of switch S3 is connected to the second port of adder SUM4; the output port of adder SUM4 is connected to the first port of adder SUM5; the output port of adder SUM5 is connected to the positive port of non-volatile memristor M4; the negative port of non-volatile memristor M4 is connected to the negative port of operational amplifier OP13; the positive port of operational amplifier OP13 is connected to ground; the output port of operational amplifier OP13 is connected to the output port of 500Ω resistor; the input port of 500Ω resistor is connected to the negative port of operational amplifier OP10; the output port of operational amplifier OP10 is connected to the input port of the seventh 1 kΩ resistor; the output port of the seventh 1 kΩ resistor is connected to the negative port of operational amplifier OP13; the positive port of operational amplifier OP13 is connected to ground; the output port of operational amplifier OP14 outputs the left reward / penalty signal R / P_Left; the eighth 1 The input terminal of the 1 kΩ resistor is connected to the negative terminal of the operational amplifier OP14, the output terminal of the eighth 1 kΩ resistor is connected to the output terminal of the operational amplifier OP14, the input terminal of the ninth 1 kΩ resistor is connected to the positive terminal and ground of the operational amplifier OP14, and the output terminal of the ninth 1 kΩ resistor is connected to the output terminal of the operational amplifier OP14.The third A2 terminal is connected to the second input port of AND gate U7. The first input port of AND gate U7 is connected to the output port of comparator T5. The output port of AND gate U7 is connected to the control port of switch S2. The output port of switch S2 is connected to the input port of the 11 kΩ resistor. The output port of the 11 kΩ resistor is connected to the negative terminal of operational amplifier OP15. The positive terminal of operational amplifier OP15 is connected to the ground wire. The output port of operational amplifier OP15 is connected to the output port of a 500 Ω resistor. The input port of the Ω resistor is connected to the negative port of operational amplifier OP15. The output port of operational amplifier OP15 is connected to the first port of adder SUM6. The output port of switch S4 is connected to the second port of adder SUM6. The output port of adder SUM6 is connected to the first port of adder SUM7. The penalty signal P_Right is connected to the second port of adder SUM7. The output port of adder SUM7 is connected to the positive port of non-volatile memristor M5. The negative port of non-volatile memristor M5 is connected to the negative port of operational amplifier OP11. The positive port of operational amplifier OP11 is connected to the ground wire. The output port of operational amplifier OP16 is connected to the output port of the 500 Ω resistor. The input port of the 500 Ω resistor is connected to the negative port of operational amplifier OP16. The output port of operational amplifier OP16 is connected to the input port of the eleventh 1kΩ resistor. The output port of the 1 kΩ resistor is connected to the negative port of operational amplifier OP17, and the positive port of operational amplifier OP17 is connected to the ground wire. The output port of operational amplifier OP17 outputs the left reward signal R_Right and the punishment signal P_Right. The input port of the twelfth 1 kΩ resistor is connected to the output port of the eleventh 1 kΩ resistor and the negative port of operational amplifier OP17. The output port of the twelfth 1 kΩ resistor is connected to the output port of operational amplifier OP17. The input port of the thirteenth 1 kΩ resistor is connected to the positive port of operational amplifier OP17, and the output port of the thirteenth 1 kΩ resistor is connected to the output port of operational amplifier OP17. The output port of operational amplifier OP3 in the left stimulus and action module is VL, and the output port of operational amplifier OP3 in the right stimulus and action module is VR.

[0012] In the preferred embodiment, the 0% stimulation module includes: the VL terminal connected to the positive input port IN+ of device E1, the negative input port IN− of device E1 connected to the ground wire, the positive output port OUT+ of device E1 connected to the input port of the thirteenth 1 kΩ resistor, the output port of the thirteenth 1 kΩ resistor connected to the negative output port OUT− of device E1, and the positive output port OUT+ of device E1 serving as the output terminal of signal VT-1_L; the VR terminal connected to the positive input port IN+ of device E2, the negative input port IN− of device E2 connected to the ground wire, the positive output port OUT+ of device E2 connected to the first port of the fourteenth 1 kΩ resistor, the second port of the fourteenth 1 kΩ resistor connected to the negative output port OUT− of device E2, and the positive output port OUT+ of device E2 serving as the output terminal of signal VT-1_R; the VT-1_R terminal connected to the input terminal of the fifteenth 1 kΩ resistor, the output terminal of the fifteenth 1 kΩ resistor connected to the positive port of operational amplifier OP19, the VT-1_L terminal connected to the input terminal of the sixteenth 1 kΩ resistor, and the output terminal of the sixteenth 1 kΩ resistor connected to the positive port of operational amplifier OP19. The output terminal of the 1kΩ resistor is connected to the negative terminal of operational amplifier OP19. The positive terminal of operational amplifier OP19 is connected to the input terminal of the seventeenth 1kΩ resistor. The output terminal of the seventeenth 1kΩ resistor is connected to the ground wire. The output port of operational amplifier OP14 is connected to the output port of the eighteenth 1kΩ resistor. The input port of the eighteenth 1kΩ resistor is connected to the negative terminal of operational amplifier OP19. The output port of operational amplifier OP19 is connected to the positive input port IN+ of device E4. The negative input port IN− of device E4 is connected to the ground wire. The positive output port OUT+ of device E4 is connected to the input port of the nineteenth 1kΩ resistor. The output port of the nineteenth 1kΩ resistor is connected to the ground wire. The negative output port OUT− of device E4 is connected to the output port of the nineteenth 1kΩ resistor and the ground wire. The positive output port OUT+ of device E4 and the nineteenth 1kΩ resistor are connected to the ground wire. The input port of the kΩ resistor is connected to the first port of adder SUM9; the third A1 terminal is connected to the first input port of logic NOR gate U10; the fourth A2 terminal is connected to the second input port of logic NOR gate U10; the output port of logic NOR gate U10 is connected to the first port of adder SUM6; the Reseting potential terminal is connected to the second port of adder SUM6; the output port of adder SUM6 is connected to the control port of switch S5; the output port of switch S5 is connected to the input terminal of the 21 kΩ resistor; the output terminal of the 21 kΩ resistor is connected to the second port of adder SUM9; the output port of adder SUM9 is connected to the input port of switch S6; the first port of switch S7 is connected to a 2 V voltage source; the second port of switch S7 is connected to the ground wire; and the output port of switch S7 outputs the right-side output signal V0_R.The input terminal of the 1 kΩ resistor (phase 21) is connected to the second port of switch S7, and the output terminal of the 1 kΩ resistor (phase 21) is connected to the output port of switch S7. The VT-1_R terminal is connected to the input terminal of the 1 kΩ resistor (phase 22), and the output terminal of the 1 kΩ resistor (phase 22) is connected to the negative port of operational amplifier OP15. The VT-1_L terminal is connected to the input terminal of the 1 kΩ resistor (phase 23), and the output terminal of the 1 kΩ resistor (phase 23) is connected to the positive port of operational amplifier OP18. The input terminal of the 1 kΩ resistor (phase 24) is connected to the output terminal of the 1 kΩ resistor (phase 23) and the positive port of operational amplifier OP18. The output terminal of the 1 kΩ resistor (phase 24) is connected to the ground wire. The input terminal of the 1 kΩ resistor (phase 25) is connected to the output terminal of the 1 kΩ resistor (phase 22) and the negative port of operational amplifier OP18. The output terminal of the 1 kΩ resistor (phase 25) is connected to the output terminal of operational amplifier OP18. The output port of operational amplifier OP18 is connected to the positive input port IN+ of device E3. The negative input port IN− of device E3 is connected to the ground wire. The positive output port OUT+ of device E3 is connected to the positive input port IN+ of device E3. The input terminal of the 1 kΩ resistor is connected to the ground wire. The output terminal of the 1 kΩ resistor is connected to the negative output port OUT− and negative input port IN− of device E3. The positive output port OUT+ of device E3 is connected to the first port of adder SUM8. The second port of adder SUM8 is connected to the input port of switch S6. The third port of adder SUM8 is connected to the second port of adder SUM6. The first port of switch S6 is connected to a 2 V voltage source. The second port of switch S6 is connected to the ground wire. The input terminal of the 1 kΩ resistor is connected to the output port of switch S6. The output terminal of the 1 kΩ resistor is connected to the ground wire. The output port of switch S6 outputs the left-side output signal V0_L.

[0013] In the preferred embodiment, the bias module includes: a stimulus probability Pleft bias value; if Pleft is greater than 0.5, the visual stimulus comes from the left side, and a bias voltage is applied to the left pathway in the stimulus and action module; if Pleft is less than 0.5, the visual stimulus comes from the right side, and a bias voltage is applied to the right pathway in the stimulus and action module; if Pleft=0.5, no bias voltage needs to be applied to the stimulus and action module.

[0014] The beneficial effects of this invention are as follows:

[0015] 1. This invention constructs a complete closed-loop circuit system consisting of a stimulus and action module, a bias module, a reward and punishment module, and a 0% stimulus module, enabling dynamic interaction between perception, prediction, and feedback, thereby generating decision-making behavior with adaptive characteristics and significantly improving the biological realism and stability of the decision-making model.

[0016] 2. This invention introduces a 0% stimulus module, which generates effective decision-making drivers through memory and internal inference. Even when visual cues are missing or extremely weak, it can maintain reliable action output and improve the system's adaptability in uncertain situations.

[0017] 3. This invention proposes a law that the decision-making reaction time increases with the increase of the decrease in memristor, so that the path with the greater change in resistance produces a more stable and accurate response, providing an interpretable mechanism for simulating biological reaction time characteristics.

[0018] 4. The reward and punishment module designed in this invention can simultaneously strengthen another path when one path is punished, so that the learning process is balanced, thus maintaining the reliability of decision-making under low contrast conditions and avoiding system misjudgment due to weak stimulation.

[0019] 5. The effectiveness of this invention has been successfully verified in block-structured visual decision-making tasks, and further extended to autonomous navigation and obstacle avoidance scenarios, indicating that the decision-making system has good adaptive control capabilities and application potential in complex, dynamic, and uncertain environments. Attached Figure Description

[0020] Figure 1 This is a schematic diagram illustrating the state evolution characteristics of a volatile memristor.

[0021] Figure 2 This is a graph showing the resistance change of a non-volatile memristor.

[0022] Figure 3 This is a schematic diagram of the block structure visual recognition task proposed in this invention;

[0023] Figure 4 This is a schematic diagram of the overall framework of the block structure decision circuit based on memristor modulation proposed in this invention;

[0024] Figure 5 A schematic diagram of the circuit structure for the stimulation and action module;

[0025] Figure 6 This is a schematic diagram of the output response curves of the motion output module under different pulse signal drives;

[0026] Figure 7 This is a circuit diagram of the reward and punishment module;

[0027] Figure 8 This is a schematic diagram of the dynamic response results of the reward and punishment output module;

[0028] Figure 9 This is a schematic diagram of the circuit structure of the 0% stimulation module of the present invention;

[0029] Figure 10 The output response curve of the 0% stimulation module under pulse input;

[0030] Figure 11 This is a schematic diagram of the complete circuit structure of the present invention;

[0031] Figure 12 A schematic diagram illustrating the dynamic response of stimuli, memristor, and motor output in different experiments;

[0032] Figure 13 This is a schematic diagram showing the changes in memristor resistance of non-volatile memristor M1 and non-volatile memristor M2 during 20 trials.

[0033] Figure 14 For P left A schematic diagram of the dynamic response process of decision-making under the condition of 0.2;

[0034] Figure 15 For P left A schematic diagram showing the trajectory of memristor state changes over time in different functional modules under condition 0.2;

[0035] Figure 16 This is a schematic diagram showing the resistance changes of non-volatile memristors M1 and M2 over 20 trials.

[0036] Figure 17 This is a schematic diagram of the dynamic response curve of the reward and punishment module;

[0037] Figure 18 For P left A schematic diagram of the dynamic response process of decision-making under the condition of 0.8;

[0038] Figure 19 For P left Trajectory of memristor state change over time in different functional modules under condition =0.8;

[0039] Figure 20 This is a schematic diagram showing the resistance changes of non-volatile memristors M1 and M2 over 20 trials. Detailed Implementation

[0040] Example 1:

[0041] This invention provides a block-structure decision generation circuit system based on memristor modulation, comprising:

[0042] Stimulus and action modules, including left-side stimulus and action modules and right-side stimulus and action modules;

[0043] The left-side stimulation and action module includes: the Stimulation_Left terminal receives the input signal; the first output port of the Stimulation_Left terminal is connected to the input port of the voltage comparator; the output port of the voltage comparator is connected to the first port of the NAND gate U1; the second output port of the Stimulation_Left terminal is connected to the second port of the NAND gate U1; the third port of the NAND gate U1 is connected to the input port of the first 1 kΩ resistor; the output terminal of the first 1 kΩ resistor is connected to the negative port of the operational amplifier OP1; the positive port of the operational amplifier OP1 is connected to the ground wire; the output terminal of the first 1 kΩ resistor is also connected to the input terminal of a 200Ω resistor; the output terminal of the 200Ω resistor is connected to the output terminal of the operational amplifier OP1; the output terminals of the 200Ω resistor and the operational amplifier OP1 are connected to the first port of the adder SUM1; and the Stimulation_Left... The third output terminal of the adder is connected to the second port of the adder SUM1. The third port of the adder SUM1 is connected to the positive input terminal of the non-volatile memristor M1. The negative output terminal of the non-volatile memristor M1 is connected to the negative port of the operational amplifier OP2. The positive port of the operational amplifier OP2 is connected to the ground wire. The output port of the operational amplifier OP2 is connected to the input port of the second 1 kΩ resistor. The negative output terminal of the non-volatile memristor M1 and the negative port of the operational amplifier OP2 are connected to the input terminal of the 300Ω resistor. The output terminal of the 300Ω resistor is connected to the output port of the operational amplifier OP2 and the input port of the second 1 kΩ resistor. The output terminal of the second 1 kΩ resistor is connected to the negative port of the operational amplifier OP3. The positive port of the operational amplifier OP3 is connected to the ground wire. The output terminal of the kΩ resistor, the negative terminal of the operational amplifier OP3, and the input terminal of the 300Ω resistor are connected. The output terminal of the 300Ω resistor and the output terminal of the operational amplifier OP3 are connected to the positive terminal of the comparator OP4. The negative terminal of the comparator OP4 is connected to a 0.23V voltage source for the reference voltage. The first port of the comparator OP4 is connected to the ground wire. The second port of the comparator OP4 is connected to a 2V voltage source. The output port of the comparator OP4 outputs the left action determination signal Action_Left.

[0044] The right-side stimulus and action module has the same circuitry as the left-side stimulus and action module;

[0045] The reward and punishment module includes: Terminal A1 is connected to the first input port of AND gate U3; the Action_Left terminal is connected to the second input port of AND gate U2; the output port of AND gate U3 is connected to the first input port of OR gate U5; terminal A2 is connected to the first input port of AND gate U4; the Action_Right terminal is connected to the second input port of AND gate U4; the output port of AND gate U4 is connected to the second input port of OR gate U5; the output port of OR gate U5 is connected to the positive terminal of non-volatile memristor M3; the negative terminal of volatile memristor M3 is connected to the input port of a 5 kΩ resistor; the output port of the 5 kΩ resistor is connected to the negative terminal of operational amplifier OP9; the positive terminal of operational amplifier OP5 is connected to ground; the negative terminal of operational amplifier OP9 is connected to the input port of a third 1 kΩ resistor; the output port of operational amplifier OP9 is connected to the output port of the third 1 kΩ resistor and the input port of a fourth 1 kΩ resistor; the fourth 1 kΩ resistor... The output port of the kΩ resistor is connected to the negative port of operational amplifier OP10, the positive port of operational amplifier OP6 is connected to the ground wire, the output port of operational amplifier OP10 is connected to the output port of the fifth 1 kΩ resistor, the input port of the fifth 1 kΩ resistor is connected to the negative port of operational amplifier OP10, the output port of operational amplifier OP10 is connected to the positive port of comparator OP11, the negative port of comparator OP11 is connected to a 0.1 V reference voltage source, the first power supply port of comparator OP11 is connected to a 2 V voltage source, the second power supply port of comparator OP11 is connected to a −2 V voltage source, and the output port of comparator OP7 outputs the action determination signal Action_Output.

[0046] The Action_Output terminal is connected to the first port of adder SUM3; the Resting potential terminal is connected to the second port of adder SUM3; the output port of adder SUM3 is connected to the first input port of AND gate U8; the output port of adder SUM3 is connected to the first input port of AND gate U9; the A1 terminal is connected to the second input port of AND gate U8; the second A2 terminal is connected to the second input port of AND gate U9; the output port of AND gate U8 is connected to the control port of switch S3; the output port of AND gate U9 is connected to the control port of switch S4; the output port of adder SUM3 is connected to the input port of comparator T5.

[0047] The second A1 terminal is connected to the first input port of the AND gate U6. The second input port of the AND gate U6 is connected to the output port of the comparator T5. The output port of the AND gate U6 is connected to the control port of the switch S1. The output port of the switch S1 is connected to the input terminal of the sixth 1 kΩ resistor. The output terminal of the sixth 1 kΩ resistor is connected to the negative terminal of the operational amplifier OP12. The positive terminal of the operational amplifier OP12 is connected to the ground wire. The output port of the operational amplifier OP12 is connected to the output port of the 500 Ω resistor. The input port of the 500 Ω resistor is connected to the negative terminal of the operational amplifier OP12 and the output terminal of the sixth 1 kΩ resistor. The output port of the operational amplifier OP12 is connected to the first port of the adder SUM4. The output port of the switch S3 is connected to the second port of the adder SUM4. The output port of the adder SUM4 is connected to the first port of the adder SUM5.

[0048] The output port of adder SUM5 is connected to the positive port of non-volatile memristor M4. The negative port of non-volatile memristor M4 is connected to the negative port of operational amplifier OP13. The positive port of operational amplifier OP13 is connected to ground. The output port of operational amplifier OP13 is connected to the output port of a 500 Ω resistor. The input port of the 500 Ω resistor is connected to the negative port of operational amplifier OP13. The output port of operational amplifier OP13 is connected to the input port of the seventh 1 kΩ resistor. The output port of the seventh 1 kΩ resistor is connected to the negative port of operational amplifier OP14. The positive port of operational amplifier OP14 is connected to ground. The output port of operational amplifier OP14 outputs the left reward / penalty signal R / P_Left. The input terminal of the eighth 1 kΩ resistor is connected to the negative port of operational amplifier OP14. The output terminal of the eighth 1 kΩ resistor is connected to the output terminal of operational amplifier OP14. The input terminal of the ninth 1 kΩ resistor is connected to the positive port and ground of operational amplifier OP14. The kΩ resistor output terminal is connected to the output port of the operational amplifier OP14;

[0049] The third A2 terminal is connected to the second input port of AND gate U7. The first input port of AND gate U7 is connected to the output port of comparator T5. The output port of AND gate U7 is connected to the control port of switch S2. The output port of switch S2 is connected to the input port of the 11 kΩ resistor. The output port of the 11 kΩ resistor is connected to the negative terminal of operational amplifier OP15. The positive terminal of operational amplifier OP15 is connected to the ground wire. The output port of operational amplifier OP15 is connected to the output port of a 500 Ω resistor. The input port of the Ω resistor is connected to the negative port of operational amplifier OP15. The output port of operational amplifier OP15 is connected to the first port of adder SUM6. The output port of switch S4 is connected to the second port of adder SUM6. The output port of adder SUM6 is connected to the first port of adder SUM7. The penalty signal P_Right is connected to the second port of adder SUM7. The output port of adder SUM7 is connected to the positive port of non-volatile memristor M5. The negative port of non-volatile memristor M5 is connected to the negative port of operational amplifier OP16. The positive port of operational amplifier OP16 is connected to ground. The output port of operational amplifier OP16 is connected to the output port of the 500 Ω resistor. The input port of the 500 Ω resistor is connected to the negative port of operational amplifier OP16. The output port of operational amplifier OP16 is connected to the input port of the eleventh 1kΩ resistor. The output port of the 1 kΩ resistor is connected to the negative port of the operational amplifier OP17. The positive port of the operational amplifier OP13 is connected to the ground wire. The output port of the operational amplifier OP17 outputs the left reward signal R_Right and the penalty signal P_Right. The input port of the 12th 1 kΩ resistor is connected to the output port of the 11th 1 kΩ resistor and the negative port of the operational amplifier OP17. The output port of the 12th 1 kΩ resistor is connected to the output port of the operational amplifier OP17. The input port of the 13th 1 kΩ resistor is connected to the positive port of the operational amplifier OP17. The output port of the 13th 1 kΩ resistor is connected to the output port of the operational amplifier OP17.

[0050] The operational amplifier OP3 in the left stimulus and action module outputs VL, while the right stimulus and action module outputs VR.

[0051] The 0% stimulation module includes: The VL terminal is connected to the positive input port IN+ of device E1; the negative input port IN− of device E1 is connected to the ground wire; the positive output port OUT+ of device E1 is connected to the input port of the thirteenth 1 kΩ resistor; the output port of the thirteenth 1 kΩ resistor is connected to the negative output port OUT− of device E1; the positive output port OUT+ of device E1 serves as the output terminal of signal VT-1_L; the VR terminal is connected to the positive input port IN+ of device E2; the negative input port IN− of device E2 is connected to the ground wire; the positive output port OUT+ of device E2 is connected to the first port of the fourteenth 1 kΩ resistor; the second port of the fourteenth 1 kΩ resistor is connected to the negative output port OUT− of device E2; the positive output port OUT+ of device E2 serves as the output terminal of signal VT-1_R; the VT-1_R terminal is connected to the input terminal of the fifteenth 1 kΩ resistor; the output terminal of the fifteenth 1 kΩ resistor is connected to the positive terminal of operational amplifier OP14; the VT-1_L terminal is connected to the input terminal of the sixteenth 1 kΩ resistor; the sixteenth 1... The output terminal of the 1kΩ resistor is connected to the negative terminal of operational amplifier OP19. The positive terminal of operational amplifier OP19 is connected to the input terminal of the seventeenth 1kΩ resistor. The output terminal of the seventeenth 1kΩ resistor is connected to the ground wire. The output port of operational amplifier OP14 is connected to the output port of the eighteenth 1kΩ resistor. The input port of the eighteenth 1kΩ resistor is connected to the negative terminal of operational amplifier OP19. The output port of operational amplifier OP19 is connected to the positive input port IN+ of device E4. The negative input port IN− of device E4 is connected to the ground wire. The positive output port OUT+ of device E3 is connected to the input port of the nineteenth 1kΩ resistor. The output port of the nineteenth 1kΩ resistor is connected to the ground wire. The negative output port OUT− of device E4 is connected to the output port of the nineteenth 1kΩ resistor and the ground wire. The positive output port OUT+ of device E4 and the nineteenth 1kΩ resistor are connected to the ground wire. The input port of the kΩ resistor is connected to the first port of adder SUM9; the third A1 terminal is connected to the first input port of logic NOR gate U10; the fourth A2 terminal is connected to the second input port of logic NOR gate U10; the output port of logic NOR gate U10 is connected to the first port of adder SUM6; the Reseting potential terminal is connected to the second port of adder SUM6; the output port of adder SUM6 is connected to the control port of switch S5; the output port of switch S5 is connected to the input terminal of the 21 kΩ resistor; the output terminal of the 21 kΩ resistor is connected to the second port of adder SUM9; the output port of adder SUM9 is connected to the input port of switch S7; the first port of switch S7 is connected to a 2 V voltage source; the second port of switch S7 is connected to the ground wire; and the output port of switch S7 outputs the right-side output signal V0_R.The input terminal of the 1 kΩ resistor (twenty-first) is connected to the second port of switch S7, and the output terminal of the 1 kΩ resistor (twenty-first) is connected to the output port of switch S7. The VT-1_R terminal is connected to the input terminal of the 1 kΩ resistor (twenty-second), and the output terminal of the 1 kΩ resistor (twenty-second) is connected to the negative port of operational amplifier OP18. The VT-1_L terminal is connected to the input terminal of the 1 kΩ resistor (twenty-third), and the output terminal of the 1 kΩ resistor (twenty-third) is connected to the positive port of operational amplifier OP18. The input terminal of the 1 kΩ resistor (twenty-fourth) is connected to the output terminal of the 1 kΩ resistor (twenty-third) and the positive port of operational amplifier OP18. The output terminal of the 1 kΩ resistor (twenty-fourth) is connected to the ground wire. The input terminal of the 1 kΩ resistor (twenty-fifth) is connected to the output terminal of the 1 kΩ resistor (twenty-second), and the negative port of operational amplifier OP18. The output terminal of the 1 kΩ resistor (twenty-fifth) is connected to the output terminal of operational amplifier OP18. The output port of operational amplifier OP18 is connected to the positive input port IN+ of device E3. The negative input port IN− of device E3 is connected to the ground wire. The positive output port OUT+ of device E3 is connected to the 1 kΩ resistor (twenty-fifth)... The input terminal of the 1 kΩ resistor is connected. The output terminal of the 1 kΩ resistor is connected to the negative output port OUT− of device E3, the negative input port IN− of device E3, and the ground wire. The positive output port OUT+ of device E3 is connected to the first port of adder SUM8. The second port of adder SUM8 is connected to the input port of switch S6. The third port of adder SUM8 is connected to the second port of adder SUM7. The first port of switch S6 is connected to a 2 V voltage source. The second port of switch S6 is connected to the ground wire. The input terminal of the 1 kΩ resistor is connected to the output port of switch S6. The output terminal of the 1 kΩ resistor is connected to the ground wire. The output port of switch S6 outputs the left output signal V0_L.

[0052] Bias module: The magnitude of the stimulus probability Pleft bias. If Pleft is greater than 0.5, the visual stimulus comes from the left side, and a bias voltage is applied to the left pathway in the stimulus and action module. If Pleft is less than 0.5, the visual stimulus comes from the right side, and a bias voltage is applied to the right pathway in the stimulus and action module. If Pleft=0.5, no bias voltage needs to be applied to the stimulus and action module.

[0053] The left-side stimulation signal A1 and the input signal Stimulation_Left are simultaneously fed into the first and second ports of the logic NAND gate U1. The output signal from the third port of U1 is fed into the inverting input of operational amplifier OP1 through a 1 kΩ resistor. The non-inverting input of OP1 is grounded. OP1 and the 200 Ω resistor in the feedback loop form an inverting amplifier that inverts the polarity and scales the amplitude of the input voltage. Its output voltage is superimposed with the input signal Stimulation_Left in adder SUM1 and applied to the input of non-volatile memristor M1. Its output is connected to the inverting input of operational amplifier OP2. The non-inverting input of OP2 is grounded and forms a voltage amplification stage through a 300 Ω feedback resistor, converting the voltage change on M1 into an output signal with appropriate amplitude. The output of OP2 is then fed into the inverting input of operational amplifier OP3 through a 1 kΩ series resistor. The non-inverting input of operational amplifier OP3 is grounded and also uses a 300 Ω feedback resistor to further amplify and shape the voltage from the stimulation path. The output signal of OP3 is directly connected to the non-inverting input of comparator OP4. The inverting input of comparator OP4 is connected to a 0.23V reference voltage source. When the input voltage, determined by the stimulus and memristor weights, exceeds 0.23V, comparator OP4 outputs a high level of approximately 2V; when the voltage is below this threshold, comparator OP4 outputs a low level close to 0V. The output of comparator OP4 is labeled as the left-side action determination signal Action_Left, serving as the decision signal for the left-side action channel.

[0054] Stimulus and action modules, as well as reward and punishment modules: such as Figure 5 and Figure 7 As shown, the stimulus and action module and the reward and punishment module include: AND gates U2, U3, AND gates U6~U9, OR gate U5, operational amplifiers OP1~OP3, comparator OP4, operational amplifiers OP9~OP17, adders SUM1, SUM3~SUM7, control switches S1~S4, PMOS transistors, volatile memristor M3, non-volatile memristor M4, non-volatile memristor M5, one 0.1V voltage source, one 1V voltage source, one -2V voltage source, and several resistors;

[0055] In the stimulus and action module, the left and right stimulus signals output by the stimulus and action module are denoted as A1 and A2, respectively, and the two action determination signals of the stimulus and action module are Action_Left and Action_Right, respectively.

[0056] First, the correctness of the action is determined by AND gates U1 and U2: AND gate U1 receives two inputs: the left stimulus signal A1 and the left action judgment signal Action_Left. AND gate U1 outputs a high level if and only if the left visual stimulus is valid and the final action output also selects the left side. Similarly, AND gate U2 receives the right stimulus signal A2 and the right action judgment signal Action_Right. It outputs a high level when the right stimulus and right action are consistent. Then, the two signals are combined by OR gate U5. The output signal of OR gate U5 is applied to the input port of volatile memristor M3, connected in series with a 5 kΩ resistor on its right end. This causes a sudden drop in the internal resistance of M3 during the brief moment of reward occurrence, effectively providing a momentary boost to the subsequent action current. The output signal of the amnesic resistor M3 enters the inverting input of operational amplifier OP9, whose non-inverting input is grounded. A voltage amplification signal is formed through a 1 kΩ feedforward resistor and a 1 kΩ feedback resistor. The output of operational amplifier OP9 is then fed into the inverting input of operational amplifier OP10 through a 1 kΩ series resistor. Operational amplifier OP10 uses a non-inverting input grounded structure for amplification to ensure that the transient enhancement characteristics of the reward signal are fully amplified and stabilized into a decision-driving voltage. The output signal of operational amplifier OP10 is connected to the non-inverting input of comparator OP11, whose inverting input is fixed at a reference voltage of -0.1 V. For the input voltage obtained after reward-penalty adjustment, if it is greater than 0.1 V, comparator OP11 outputs +2 V, and the high-level signal is defined as the decision output signal Action_Output; if it is lower than this threshold, it outputs a low level of -2 V.

[0057] Therefore, under the adjustment of reward and punishment signals, the final action judgment voltage of the system is completed by comparator OP11. In the stimulus and action module, the decision output signal Action_Output and the external resting potential are connected to adder SUM3. Adder SUM3 performs the superposition of the two signals, and its output voltage is sent to logic AND gates U6 and U7. Another signal is directly connected to the gate of PMOS transistor T5 to control the conduction state of the resting potential compensation branch: when the output of adder SUM3 is low (corresponding to Action_Output being low), T5 is turned on, and the external resting potential is input to the left node through a series 1 kΩ resistor to provide a slight baseline bias for the system; when the output of SUM3 is high (corresponding to Action_Output being validly high), T5 is turned off, the compensation branch is disconnected, and the resting potential no longer affects the subsequent judgment. The left stimulus signal A1 and the right stimulus signal A2 from the stimulus and action module are fed together with the output of SUM3 into two logic AND gates U8 and U9. After logic operation, two judgment signals are obtained: the left action is correct and the right action is correct. The left judgment signal drives the control switches S1 and S3 of the upper branch, and the right judgment signal drives the control switches S2 and S4 of the lower branch. When one side is judged as correct, the corresponding control switch S1 or S2 is turned on, and a 1 V reward voltage is sent to the non-inverting input of the operational amplifier OP12 or operational amplifier OP15 through a 1 kΩ resistor. When the judgment is incorrect, the other set of control switches S3 or S4 is turned on, and a 1 V penalty voltage is sent to the input of the corresponding operational amplifier. The reward / penalty results output from operational amplifiers OP12 and OP15 are superimposed at adders SUM4 and SUM5 with the right-side penalty signal P_Right and the left-side penalty signal P_Left, forming a combined reward / penalty voltage for the left and right paths. This voltage is then applied to one end of non-volatile memristors M4 and M5 to achieve long-term modulation of the weights of the left and right decision paths. The other end of the memristors is connected to operational amplifiers OP13 and OP16, whose outputs are amplified by feedback from 500 Ω and 1 kΩ resistors to convert the state changes of the non-volatile memristors into stable voltage signals. The amplified signals from operational amplifiers OP13 and OP16 are then fed into operational amplifiers OP14 and OP17, with the outputs denoted as reward / penalty signals R / P_Left and R / P_Right, respectively. These signals serve as the final reward / penalty modulation results for the left and right paths, feeding back to the stimulus and action module and the bias module to strengthen the effective voltage in the correct direction and suppress the path weights in the wrong direction, thus completing memory- and feedback-based reward / penalty learning at the circuit level.

[0058] 0% stimulation module: such as Figure 9As shown, the 0% stimulation module includes: behavioral models ABM1~ABM4, differential amplifiers OP18 and OP19, control switches S5~S7, one 1V voltage source, two 2V voltage sources, a logic OR gate U10, adders SUM6~SUM8, and several resistors. Based on the voltage of the left and right pathways... and The previous cycle's outputs were processed by behavioral models ABM1 and ABM2 respectively. and These voltages originate from the outputs of the stimulus and action modules and are connected to delay units ABM1 and ABM2 respectively in the 0% module. The input of each delay unit is connected to the input port of the previous cycle, and the output is buffered by a 1 kΩ resistor before being sent to the node used for difference judgment in the current cycle, enabling the circuit to accurately extract the effective voltage of the previous cycle. The delay voltages of the left and right paths... and The signals are then fed into a differential calculation system consisting of differential amplifiers OP18 and OP19. OP18 generates the left-high-right-low directional bias signal, while OP19 generates the right-high-left-low directional bias signal. Both employ a dual-input single-output structure, with the left and right voltages fed to their inverting and non-inverting inputs via 1 kΩ resistors. A 1 kΩ resistor is also connected in the feedback branch to linearly amplify the voltage difference between the left and right sides from the previous cycle. The output of differential amplifier OP18 is further fed into behavioral model ABM3, where it undergoes internal conversion and is then sent to adder SUM8 via a 1 kΩ resistor to form a bias signal. The output of differential amplifier OP19, after processing by behavioral model ABM4, is sent to adder SUM9 via a 1 kΩ resistor to form a left-biased bias signal from the previous cycle. Meanwhile, the left stimulus signal A1 and the right stimulus signal A2 of the current cycle are first input to the OR gate U10. When both inputs are 0 (i.e., the visual stimulus contrast is 0%), the OR gate U10 outputs a high level, which is sent to adder SUM6 as a 0% visual stimulus state detection signal. The other input of SUM6 is the resting potential, which is injected into the adder SUM6 node after passing through a 1 kΩ resistor and control switch S5. When the output of the OR gate U10 is high (detecting a 0% visual stimulus state), control switch S5 is turned on, thus allowing the resting potential to enter adder SUM6; when there is visual input, the output of the OR gate U10 is low, and control switch S5 is turned off. The output voltage of adder SUM6 constitutes the internal bias baseline for this cycle and is sent to adders SUM8 and SUM9 respectively, for superposition with the directional deviation results output by behavioral models ABM3 and ABM4. In adder SUM8, the rightward bias voltage from the previous cycle is added to the resting potential baseline V0 via the signal output from behavioral model ABM3. When this path becomes positively dominant, the output of adder SUM8 further controls switch S6, turning it on and injecting a 2V voltage source through a 1kΩ resistor into the output bias voltage V0_R. This port represents the internal bias voltage selected to the right by the system in the 0% visual stimulation state. Similarly, in adder SUM9, when the leftward bias signal from the previous cycle is dominant, the output of adder SUM9 turns on control switch S7, outputting a 2V voltage source through a 1kΩ resistor to the bias voltage V0_L, which serves as the internal bias voltage selected to the left by the system in the 0% visual stimulation state.

[0059] The connection methods between modules include: such as complete circuits Figure 11As shown, the stimulus and action module first generates a left action decision signal (Action_Left) and a right action decision signal (Action_Right) based on the input visual stimulus contrast signal. These two signals are directly used as inputs to the stimulus and action module to determine the direction selection of the action in the current cycle. Simultaneously, the multi-stage amplification link within the stimulus and action module also outputs the left and right path voltages (VL and VR), respectively. These two signals not only participate in the voltage processing of the stimulus and action module but also serve as inputs to the 0% stimulus module, used to extract the path state of the previous cycle and perform direction inference under no-stimulus conditions. The stimulus and action module outputs the final action decision signal (Action_Output) via comparator OP11, whose signal polarity represents the final behavioral direction selected by the system. The Action_Output signal is sent to the reward and punishment module as the core basis for reward and punishment judgment. It works together with the left stimulus signal A1 and the right stimulus signal A2 to determine whether the action is correct. Based on this judgment, the reward and punishment module generates two reward and punishment signals, R / P_Left and R / P_Right, which are written into the left and right channels through non-volatile memristors M4 and M5, making the decision-making system gradually sensitive to the correct direction and gradually suppressing the wrong direction. The 0% stimulus module obtains the left and right channel voltages VL and VR from the stimulus and action module in the previous cycle. When it detects that the visual input left stimulus signal A1 and right stimulus signal A2 are both low in the current cycle (i.e., the visual stimulus contrast is 0%), it automatically activates the internal delay and bias mechanism to generate two internal bias voltages, V0_L and V0_R. These two bias signals will provide a memory trend for the action direction in the next cycle based on the state of the previous cycle, which is used to maintain the continuity of behavior under the condition of no external input. The left and right reward / punishment signals R / P_Left and R / P_Right from the reward / punishment module, the bias voltages V0_L and V0_R from the 0% stimulus module, and the bias voltage from the bias module are all superimposed on the stimulus and action modules. By adjusting the resistance of the non-volatile memristor M1, adaptive behavior control is achieved. Ultimately, these superimposed voltages collectively influence the weighted result of the stimulus and action modules, enabling the system to make multimodal decisions based on historical experience, the current stimulus, and the no-stimulus bias when the next stimulus arrives.

[0060] The stimulation and action module includes: an input switch array, a logic NAND gate U1, an operational amplifier OP1, a non-volatile memristor M1, and an amplification and comparison unit composed of OP2, OP3, and OP4. The visual stimulation signal enters the logic NAND gate U1 through the input switch. The output of U1 is sent to the operational amplifier OP1 to switch between the excitation state and the negative reset voltage. The output of OP1 is connected to the positive terminal of the non-volatile memristor M1 to adjust the resistance value of M1 according to the amplitude of the input voltage. The output of M1 is further amplified sequentially by operational amplifiers OP2 and OP3, and compared with a fixed threshold voltage in comparator OP4. Finally, the left / right action precursor signal is output as the input of the stimulation and action module.

[0061] The stimulus and action module includes two parallel weighted amplification branches, comparators OP4 and OP8, and AND gates U3 and U4. The action precursor voltages from the left and right stimulus and action modules are fed into the two cascaded operational amplifier structures, and the gain is set by a fixed resistor. The amplified voltages are converted into positive and negative outputs in comparators OP4 and OP8, with the positive output representing the left action and the negative output representing the right action. AND gates U3 and U4 receive the action result and the stimulus direction signal, respectively, and generate the left action judgment signal Action_Left and the right action judgment signal Action_Right.

[0062] The 0% stimulation module includes behavioral models ABM1 and ABM2, differential amplifiers OP18 and OP19, behavioral models ABM3 and ABM4, a resting potential injection adder SUM6, a control switch S5, and bias output control switches S8 and S9. Behavioral models ABM1 and ABM2 perform delay processing on the left and right visual inputs from the previous cycle and output them to differential amplifiers OP18 and OP19, respectively, to calculate the left-right voltage difference from the previous cycle. The differential signal is processed by ABM3 and ABM4. After conversion, the signals are sent to adders SUM9 and SUM9 respectively. When the visual stimulus contrast is detected to be 0%, the logic OR gate U10 turns on the control switch S5, injecting the resting potential into SUM6 to form an internal bias voltage V0. V0 is sent to adders SUM8 and SUM9 respectively, and superimposed with the deviation voltage of the previous cycle. When the output of SUM8 or SUM9 exceeds the threshold, the corresponding control switch S6 or S7 turns on, outputting the bias voltage V0_L or V0_R, which is used to generate the direction of movement under conditions of no visual input.

[0063] The bias module uses non-volatile memristors to record long-term directional bias. The stimulation signal gradually changes the resistance values ​​of memristors M4 and M5 during the learning process, so that it can still give directional decision output based on long-term statistical information under conditions of weak or absent vision.

[0064] The system employs both volatile memristors (VMs) and non-volatile memristors (NVMs). The volatile memristors (VMs) are used to implement short-term synaptic plasticity and rapid potential reset, while the non-volatile memristors (NVMs) are used to record stable long-term associations. Through the coordinated operation of the two types of memristors, the system achieves unified processing of transient stimulus inputs and cross-cycle memory biases, thereby possessing biological-like learning and decision-making capabilities.

[0065] Example 2:

[0066] This invention proposes a block-structure decision generation method based on memristor state modulation. By constructing stimulus and action modules, bias modules, reward and punishment modules, and 0% stimulus modules, the system can complete the entire decision-making process from external stimuli and internal prediction to action selection and feedback regulation.

[0067] To achieve multi-stage learning, prediction, and behavior regulation, this invention introduces two types of memristors in different modules: one is a volatile memristor, which has natural fallback and fast reset characteristics, and is mainly used in this system to reset short-term states, simulating the short-term memory function of neurons. Its formula is:

[0068]

[0069] In this model, v represents the voltage applied across the device, and i represents the resulting current. The conduction mechanism within the memristor is composed of two competing channels: Schottky conduction channels and tunneling conduction channels. Their relative contribution is described by the state variable x, which is normalized to the interval [0, 1]. x = 0 represents a conduction state completely dominated by the Schottky barrier, while x = 1 represents a conduction state completely dominated by the tunneling effect. Values ​​between these two represent a mixed dominance of the two channels. In this model, parameter α characterizes the height of the Schottky barrier; the larger the value, the higher the Schottky barrier and the more significant the obstruction to charge carriers. Parameter γ describes the height of the tunneling barrier, and its magnitude determines the ease with which electrons pass through the tunneling channel. The depletion layer width in the Schottky region is represented by parameter β, while the effective tunneling distance in the tunneling path is given by parameter δ. Both directly affect the characteristics of charge carrier transport paths. The parameter λ is used to adjust the influence of the applied voltage on the relative weights of the two types of conductive channels, so that Schottky conduction and tunneling conduction exhibit different dominance at different voltages. In the evolution equation of the state variables, τ is the diffusion constant, which determines the response speed of the state variables to external disturbances, while ε measures the retention ability of the conductive channels, that is, how easily the system maintains its current conductive state. Among them, the material dependence coefficients σ and θ are related to the parameters ε and τ, respectively, and are used to reflect the differences in retention and diffusion characteristics of different material systems.

[0070] Furthermore, η1 and η2 are used to characterize the different manifestations of interface effects under forward and reverse bias, enabling the model to accurately reflect the asymmetry of the device under different polarity voltages. All of the above parameters are positive values ​​and are determined by the inherent properties of the material, independent of the state variable x. The model also includes a window function to constrain the evolution of the state variable, ensuring that its range of variation remains within a physically reasonable range and avoiding unrealizable state transitions.

[0071] Another type is the non-volatile memristor, which has the ability to retain information for a long time. It is used to store stable memories related to learning, so that it can maintain internal bias and reward / punishment traces even after the stimulus disappears, providing continuous impetus for subsequent decisions.

[0072] Memristors satisfy the following formula:

[0073]

[0074] in, It is the minimum memristor value. This is the maximum memristor value. The normalized thickness of the conducting region of the memristor is a state variable. Its derivative is the derivative formula for the state variable:

[0075]

[0076] in, and These represent the voltage threshold function and the window function, respectively.

[0077] and The derivative is as follows:

[0078]

[0079]

[0080] in, and These represent the positive and negative threshold voltages, respectively. When the voltage applied to the non-volatile memory exceeds its positive threshold, the memristor value decreases; conversely, when the voltage drops below the negative threshold, the memristor value increases. These two types of memristors are allocated in the system according to their function: state modulation and expectation bias updates in the stimulus path primarily rely on non-volatile memristors to ensure that learned weights are retained for extended periods; transient adjustments in the inhibition path and reward / punishment loop mostly employ volatile memristors, enabling the system to re-enter a sensitive state in new task phases and preventing historical information from interfering with the new learning process.

[0081] The stimulus and action module converts visual signals of varying contrast into changes in memristor state. High-contrast stimuli significantly alter the non-volatile memristor, while low-contrast stimuli cause only slight changes, thus mapping perceived intensity to an internally adjustable parameter. The bias module, based on historical experience gained from rewards, maintains and updates the bias through the non-volatile memristor. When the current input matches a previously reinforced stimulus, the state shifts towards reinforcement; conversely, when the input deviates from past experience, the state shifts towards inhibition, thus correcting expectations. The stimulus and action module weights the input signal according to the magnitude of the memristor state in the stimulus path and executes a reward action when the weighted result exceeds a threshold; otherwise... The system executes a punishment action, transforming the state change into a specific behavior. The reward and punishment module applies positive or negative adjustments based on external feedback, strengthening the rewarded path through the non-volatile memristor and weakening the punished path through the volatile memory circuit, thus forming directional learning. Under no-stimulus conditions, the 0% stimulus module generates internal driving force through the combined effect of expectation bias and reward and punishment traces, enabling the system to still have a selection tendency even when there is no input. The decision output module processes the signals from the stimulus, expectation, and reward and punishment pathways in a unified manner, and generates the final action instruction based on the comprehensive result, thereby realizing the cyclical update of stimulus, bias, action, reward and punishment, and memory in a coherent system.

[0082] Example 3:

[0083] This invention first employs a threshold memristor as the core device for simulating synaptic connections between neurons. The specific structural parameters, initial state, and model parameters of the memristor are shown in Table 1. In this invention, all plastic synapses are composed of this type of threshold memristor. By applying different voltages, various plastic behaviors such as enhancing, inhibiting, and maintaining the synaptic weight can be achieved.

[0084] The volatile memristor (VM) used in this invention is mainly used to realize the short-term plasticity of biological synapses and undertakes the core function of automatic reset throughout the decision-making cycle. When an external input is applied to the VM, its resistance drops rapidly in a very short time, equivalent to a momentary increase in synaptic weight; after the input is removed, the VM gradually recovers to its initial resistance through natural decay, realizing automatic reset of the potential state. This ensures that the system maintains consistent initial conditions between trials, avoiding interference from historical voltage residues in subsequent decision outputs. Therefore, in the overall structure of this invention, the main function of the volatile memristor is not to store long-term information, but to maintain the stability of circuit operation through short-term changes and rapid reset mechanisms. The parameter settings for the VM in this invention are shown in Table 1, and are as follows: Figure 1 The method is used to test its characteristics. Specifically, periodic square wave voltage pulses are applied to the VM, such as... Figure 1As shown, its resistance drops rapidly during the pulse and gradually recovers after the pulse is removed, exhibiting typical volatile memory characteristics. To further analyze its dynamic behavior, the VM was connected to series resistors of 5 kΩ and 1 kΩ respectively. The results show that the smaller the series resistor, the more significant the drop in the effective resistance of the VM during the pulse, while the recovery speed is slower, and it can provide a higher instantaneous voltage for the subsequent circuit in the next stage. The above parameter dependence indicates that the configuration of the VM has a significant impact on its reset speed and short-time response amplitude, and can be flexibly adjusted according to the functional requirements of different modules.

[0085] Table 1

[0086] parameter Parameter settings Parameter settings

[0087] The non-volatile memristor (NVM) used in this invention is primarily used to achieve long-term plasticity in biological neural systems. Its core function is to stably maintain synaptic weights even after learning has ended, ensuring that the system retains long-term memory traces across multiple trials and does not automatically decay due to interruptions in external stimuli. Unlike volatile memristors that handle short-term memory and automatic reset, the NVM's resistance change is continuous, allowing it to record stable correlation information in the stimulus-bias-reward process. This is a crucial foundation for achieving long-term bias, decision stability, and rapid relearning in this invention. Figure 2 The test method shown applies voltage signals of different amplitudes, and typical threshold-dependent behavior can be observed: when the applied voltage exceeds its positive threshold voltage... When the voltage is below its negative threshold, the resistance of the NVM decreases significantly, indicating an increase in synaptic weight; while when the voltage is below its negative threshold... When the resistance increases, it indicates that the synaptic weight is suppressed. Simulation results are as follows: Figure 2 The above-described threshold-controlled bidirectional modulation process is clearly demonstrated, proving that NVM can perform the function of stable memory in the decision loop of this invention and can gradually form reliable correlation weights.

[0088] The decision-making circuit constructed in this invention is based on the synergistic mechanism of two types of memristors: the volatile memristor (VM) generates transient weight changes under short-term stimulation and automatically returns to its initial state after the stimulus is removed, simulating short-term memory and rapid potential reset; the non-volatile memristor (NVM) is used to record stable correlations, and its resistance changes can be maintained for a long time after the stimulus ends, thereby achieving long-term storage of expected biases and reward / punishment results. The combined use of these two types of memristors enables the circuit proposed in this invention to simultaneously process instantaneous perceptual input and long-term statistical information, thus possessing the core functional characteristics of learning, prediction, and decision-making in biological systems.

[0089] Building upon this, the decision circuit of this invention references the block-structured visual discrimination task widely used in neuroscience research in its functional design, using it as the basic framework for behavioral modeling. This task consists of multiple "blocks" with different statistical conditions, each block containing multiple consecutive trials with a fixed probability of stimulus appearance. For example, the probability of a stimulus appearing on the left side... These represent different statistical environments: stimuli in the current block mainly appear on the left, have equal probability on both sides, or mainly appear on the right. In each trial, such as... Figure 3 As shown, the experimental subjects needed to determine the direction of the rotating wheel based on the presented visual stimulus contrast (including five levels: 100%, 25%, 12.5%, 6.5%, and 0%). When the visual stimulus contrast was high, the stimulus provided clear directional information, and the behavioral decision was usually quite accurate. As the contrast gradually decreased, the visual cues became blurred, and the error rate increased significantly. Under the condition of 0% visual stimulus contrast, due to the complete lack of directional information, the behavioral response exhibited an almost random characteristic, and the decision was mainly influenced by the prior probability that had been maintained in the current block for a long time. The entire behavioral process can be divided into two consecutive stages. The first stage is the pre-experiment stage, in which no expectation bias mechanism is introduced, and the decision relies entirely on the visual input itself. For example, under the condition of 0% visual stimulus contrast, since the visual information does not provide any directionality, the system's judgment in this stage exhibits an equal probability distribution. The second stage is the learning and generation stage, during which expectation bias mechanism and reward and punishment feedback mechanism are gradually introduced. By continuously receiving feedback, the system can gradually understand the statistical regularity within the current block and form an internal bias, thus enabling it to make more accurate judgments even under low visual stimulus contrast or even 0% visual stimulus contrast conditions, rather than relying entirely on visual stimuli. This task structure provides complete behavioral logic for the circuit simulation of this invention, enabling the relationship between the stimulus and action modules, the bias module, and the reward and punishment module to be verified within a unified framework.

[0090] like Figure 4 As shown, the decision-making circuit of this invention consists of four functional modules: a stimulus and action module, a bias module, and a reward and punishment module. These four modules are connected in a closed loop, collectively forming a brain-like decision-making structure with learning, prediction, and selection capabilities.

[0091] like Figure 5As shown, the stimulation and action module of this invention is illustrated using the left-side pathway as an example, with the input signal in the form of continuous pulse voltage. The left-side part of the circuit is used to implement the dynamic modulation mechanism of the non-volatile memristor M1: when an external stimulation pulse is applied to this path, and its amplitude exceeds the threshold voltage of the non-volatile memristor, the resistance of the non-volatile memristor M1 will decrease with the voltage action, corresponding to the enhancement of synaptic weight, making the action in this direction easier to trigger. When the input signal disappears, the circuit automatically applies a negative voltage, causing the resistance of the non-volatile memristor M1 to gradually increase, thereby weakening the effectiveness of this path and reducing the probability of it triggering action output. The logic NAND gate U1 and operational amplifier OP1 are used to switch the input signal and adjust the voltage amplitude to ensure a smooth transition between excitation input and inhibition reset. Thus, this part of the circuit is not used for long-term information storage, but rather to realize dynamic synaptic plasticity with rapid reversibility and potential recovery function, allowing the weights to be adjusted in real time according to changes in visual input, thus better conforming to the adaptive adjustment mechanism in actual behavior. The right-side part of the circuit constitutes the action selection path. The signal from the left path is amplified by two operational amplifiers and then sent to a threshold comparison unit for comparison with a preset judgment threshold. When the amplified potential exceeds the set threshold, the comparator outputs a high-level signal, which indicates the final output of a left-direction action. Figure 6 The output of the module under external pulse stimulation is shown. The state of the non-volatile memristor is dynamically modulated with the input voltage. When its output amplitude reaches the threshold condition, it can generate the final high-level action signal.

[0092] As shown in Figure 7, the reward / punishment module in this invention is used to evaluate the correctness of the action output and to enhance or suppress the weights of the left and right pathways based on the evaluation results, thereby achieving behavior learning and correction. This module mainly consists of a logic discrimination unit, an operational amplifier, a volatile memristor, and reward / punishment voltages. In this invention, the left and right visual inputs, after being processed by the stimulus and action module, are denoted as A1 and A2, respectively, representing the current input potentials of the left and right pathways. Simultaneously, the stimulus and action module generates left and right action output signals. and The reward and punishment module first uses a logical AND gate to determine whether the actions are consistent. Its correctness can be given by the following formula:

[0093]

[0094]

[0095] The circuit considers the action correct only if the input direction is the same as the action direction and both are high. Subsequently, the left and right correctness signals are combined by a logic OR gate to obtain the overall correct signal.

[0096]

[0097] The synthesized correct signal is input to a volatile memristor. In this module, the volatile memristor is used to record short-term memory of action feedback; its state is modulated by changes in the input voltage, exhibiting transient characteristics of stimulus enhancement and recovery after removal. Its dynamics are described below:

[0098]

[0099] Where α and β are rate coefficients, This is the positive threshold voltage of the memristor. When a reward signal appears, the resistance of the volatile memristor drops rapidly, temporarily increasing the weight of this pathway; when there is no signal input, the volatile memristor spontaneously returns to its ground state, simulating short-term memory decay in biological neurons. The final output of the action selection is generated by a cascaded operational amplifier structure, which, after passing through a comparator, produces a left or right decision output:

[0100]

[0101] To avoid the resting potential from influencing the judgment, this invention employs a compensation circuit to restore the resting potential to zero, ensuring the stability of the decision threshold. Based on this, the reward / penalty module evaluates the correctness of the action. If the action is correct, the corresponding pathway generates a reward signal.

[0102]

[0103]

[0104] If the operation is incorrect, the negative voltage output by the operation is converted to a positive voltage by an inverter, and then compared with the input signal to generate a penalty signal.

[0105] , .

[0106] The reward signal enhances the weight of the corresponding path with a positive voltage; the penalty signal suppresses the selected erroneous path with a negative voltage. Simultaneously, this invention introduces a cross-enhancement mechanism, which, while penalizing one side, additionally strengthens the other side, accelerating the weakening of the weight in the erroneous direction and the enhancement of the weight in the correct direction. Its expression is:

[0107]

[0108] Where ξ is the penalty inhibition factor, used to control the degree to which the penalty reduces the weight of the pathway. As shown in Figure 8, under the input conditions of the block structure, the closed-loop dynamic characteristics of this module are as follows: the first row displays visual stimuli that alternate between left and right with different contrasts; the second row gives the corresponding action output; the third row shows the transient resistance change of the volatile memristor, used to simulate the short-term memory of action evaluation; the bottom two rows show the changing patterns of reward and penalty signals respectively: when correct, a positive reward voltage is generated; when incorrect, not only is a negative penalty applied to the incorrect pathway, but another pathway is also enhanced at the same time, realizing cross-correction.

[0109] like Figure 9 As shown, the 0% stimulation module designed in this invention is used to simulate the mechanism by which the system automatically generates the current action direction based on the memory of the previous round of decisions when there is no visual input. By performing delay extraction, differential calculation, bias superposition, and threshold judgment on the left and right voltages, the inheritance and utilization of the previous round of decision results are realized, enabling the circuit to still produce deterministic output under no-stimulation conditions. In order to reproduce the relationship between the previous round of visual input and action, this embodiment calls the behavior model ABM module in PSPICE, and uses the Laplace delay function to delay the input voltage to realize the extraction of the voltage of the previous cycle. This delay module records the left and right voltages of the previous cycle as follows: and The relationship can be obtained from the following formula:

[0110]

[0111] Where T is the duration of a single cycle. The circuit reads this delayed voltage during the current cycle and uses it as the input basis for judging the current 0% visual stimulus contrast. Specifically, the left and right voltage signals are processed by the ABM1 and ABM2 modules to calculate the voltage difference, which is then combined with the signal to ultimately determine which direction receives a stronger bias for selection. The decision logic is as follows:

[0112] Calculation of voltage difference between left and right paths: When the current input is detected to be in a 0% visual stimulus contrast state (the output of logic OR gate U4 is high), the circuit first calculates the voltage difference between the left and right paths in the previous cycle to determine which path was more dominant in the previous cycle. The voltage difference calculation is as follows:

[0113]

[0114] If the voltage on the left is higher, then Conversely, the voltage difference on the right side is positive.

[0115] Bias voltage superposition: To simulate the internal bias behavior under no-stimulus conditions, this invention further introduces a static bias voltage V0, provided by the control switch S5 terminal in the circuit. This bias voltage is used to adjust the comparison result, ensuring that the circuit retains its inherent selection bias even when visual stimulation is completely absent. The bias superposition formula is:

[0116]

[0117] V0 can be set according to the prior probability of the task block to achieve a selection trend that is biased towards the left or right.

[0118] Final direction determination: The circuit determines the final direction of action by judging the sign of the biased voltage. The specific formula is as follows:

[0119]

[0120] When the left path bias voltage is greater than zero, the comparator outputs a high level, driving the left action path; if the right path bias voltage is greater than zero, it outputs the right action result.

[0121] like Figure 10 As shown, during the time interval of 18 s to 19.5 s, the system enters a 0% visual stimulus contrast state. At this time, no effective visual input is provided from the outside. The 0% stimulus module of this invention automatically starts, extracting the left and right voltage values ​​stored in the previous cycle through the delay unit and generating a selection bias accordingly. Due to the delay voltage of the left path in the previous cycle... Higher, while the delay voltage of the right-side path is higher. The voltage difference is relatively low. After substituting the voltage difference into the decision logic and superimposing it with the bias, the bias voltage in the left direction is found to be positive. According to the selection judgment condition, when the bias voltage is greater than zero, the corresponding direction is considered more advantageous. Therefore, the final decision action output by the system in this period is determined to be to the left, realizing autonomous decision-making based on internal memory bias under conditions of no visual input.

[0122] As shown in Figure 11, the decision-making circuit of this invention consists of a stimulus and action module, a bias module, a reward and punishment module, and a 0% stimulus module. Each module works collaboratively with a memristor as its core. The stimulus and action module converts visual inputs of different contrasts into voltage signals of varying amplitudes and generates short-term weight changes through a volatile memristor. The bias module relies on a non-volatile memristor to record long-term memories, enabling the system to provide directional tendencies based on past biases even under low-contrast or 0% visual stimulus contrast conditions. The stimulus and action module weights and integrates the stimulus and bias voltages and outputs behavioral decisions after threshold calculation. The reward and punishment module applies enhancing or suppressing voltages based on feedback and provides cross-regulation, thereby reinforcing correct directions and suppressing incorrect directions. The entire system forms a closed loop from input, bias, action to learning feedback, giving the decision-making process a biological-like directional selection capability.

[0123] based on Figure 11 The decision circuit structure shown in this invention was modeled and simulated in PSPICE to verify its decision-making and learning capabilities in a block-structured visual discrimination task. The simulation consisted of three phases: a base experiment without bias, a learning experiment under left-side prior probability (Pleft = 0.8), and a learning experiment under right-side prior probability (Pleft = 0.2). Each phase included 20 independent trials, each lasting 1.5 seconds. Visual stimuli were represented by square wave voltages of different contrasts, including 5 V, 1.25 V, 0.625 V, 0.3125 V, and 0 V, corresponding to visual stimulus contrasts from 100% to 0%.

[0124] In the initial stage, no bias module was introduced, and the system relied solely on the stimulus and action modules for judgment. Figure 12 The simulation results for this stage are shown: Simulation_left represents the input voltage signal; Memristance represents the resistance change of M1 / M2; Action represents the final output voltage of the system. The top represents the left and right visual inputs, the middle represents the resistance change of the non-volatile memristors M1 and M2, and the bottom represents the action signal output by the system. Under these conditions, when the visual stimulus contrast decreases, the amplitude of the memristor resistance change is significantly weakened, causing the action channel to be unable to form a stable directional advantage. This results in a large number of incorrect judgments in the output, exhibiting random decision-making characteristics, which is consistent with the behavior under no-expectation conditions.

[0125] Figure 13The study demonstrates the differences in the magnitude of resistance changes in a non-volatile memristor across 20 trials. Larger resistance drops correspond to more thorough stimulus processing, resulting in longer and more accurate behavioral responses; while smaller resistance changes typically imply insufficient stimulus accumulation and shorter response times, making incorrect choices more likely. Significantly smaller resistance drops were observed in trials 7, 13, and 14, corresponding to erroneous decisions, further indicating a positive relationship between the magnitude of memristor state changes and decision accuracy.

[0126] With the introduction of the bias module and the setting of a higher left-side prior probability, i.e., Pleft = 0.8, the overall dynamic behavior of the system is shown in Figure 14. Figure 14 In the diagram, Simulation_left represents the input voltage signal; A1 / A2 represent the left / right stimulus signals; Action_Output represents the output signal of the action module; VT-1_L / VT-1_R represent the left / right voltage signals of the previous cycle; V0_L / V0_R represent the 0% stimulus appearing on the left / right side; and Action represents the final output voltage of the system. Left and right visual stimuli are applied alternately with different contrasts, and the stimulus and action modules output the processed left and right channel voltage signals respectively. When the visual stimulus contrast is 0% (e.g., 18-19.5 s and 28.5-30 s), there is no effective input to either the left or right channels, but the 0% stimulus module still provides the correct directional judgment based on its internal bias. This indicates that even in the absence of external visual cues, the system can still output stable decision results based on bias and memory.

[0127] Figure 15 The study demonstrates the changing patterns of memristor states in different modules. In the stimulus and action module, the resistance of the non-volatile memristor decreases periodically under repeated stimulation, reflecting a gradual increase in synaptic effectiveness. In the reward and punishment module, the volatile memristor maintains its rapid response and recovery characteristics, automatically returning to its initial state after input removal, reflecting the formation and decay of short-term memory. In the bias module, the non-volatile memristor exhibits a smoother and more continuous decrease in resistance, used to record long-term biases, enabling the system to still choose the optimal direction under low-contrast conditions.

[0128] Figure 16 The results further show that in 20 trials, the two key non-volatile memristors maintained a significant decreasing resistance trend and no erroneous outputs were observed. This indicates that the bias module can effectively guide the system to form a consistent directional preference under the condition of Pleft = 0.8, enabling it to maintain stable and accurate decision-making behavior under different stimulus intensities.

[0129] To highlight the necessity of the reward and punishment module in learning, Figure 17The system response without the reward / punishment module is presented. When the left-side stimulus is weak, the system is prone to misjudgment due to insufficient synaptic modulation. With the reward / punishment module added, correct behavior triggers a reward signal, and incorrect behavior triggers a punishment signal, resulting in cross-modulation of the two paths, strengthening the correct path and gradually weakening the incorrect path. Simulation results show that this mechanism significantly improves judgment ability under weak stimulus conditions, allowing decision-making performance to be continuously optimized through repeated trials, demonstrating adaptive learning characteristics based on reward / punishment feedback.

[0130] Given that the system prior is set to be biased to the right, i.e., Pleft = 0.2, the dynamic behavior of the overall circuit is as follows: Figure 18 As shown. Figure 18 The results show that under the alternating effects of visual stimuli at different contrast levels, the system consistently outputs a stable right-side decision, indicating that the bias module has successfully participated in the circuit operation, ensuring that the judgment result maintains a consistent directional tendency under various stimulus conditions. Figure 19 In the stimulus and action modules, the resistance of the non-volatile memristors decreases periodically with each test, indicating that synaptic efficacy gradually strengthens under repeated stimulation. The volatile memristors in the reward / punishment module maintain their rapid response and recovery characteristics to support short-term plasticity. Meanwhile, the non-volatile memristors in the bias module exhibit a smoother and more continuous decrease in resistance, used to record long-term biases, enabling the system to maintain a clear direction even under weak or no stimulation. Figure 20 In summary, the memristor decrease in the right channel was significantly greater than that in the left channel, and no incorrect selections were observed in twenty trials. This indicates that under strong bias conditions, the circuit's decision-making is primarily driven by the bias signal, rather than entirely dependent on immediate stimuli. This ensures stable and accurate behavioral output under varying visual intensities, fully demonstrating the robust decision-making capability of this invention under the influence of long-term memory and expectation.

[0131] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the present invention. Various changes and modifications can be made to the present invention without departing from its spirit and scope. All such changes and modifications fall within the scope of the present invention as claimed, which is defined by the appended claims and their equivalents.

Claims

1. A block-structure decision generation circuit system based on memristor modulation, characterized in that, include: The stimulus and action module, reward and punishment module, bias module, and 0% stimulus module are connected. The third ports of the AND gates U3 and U4 of the stimulus and action module are connected to the first port of the OR gate U5 of the reward and punishment module. The reward and punishment module is connected to the second ports of the adders SUM10 and SUM11 of the stimulus and action module through the third ports of amplifiers OP14 and OP15. The stimulus and action module is connected to the first ports of E1 and E2 of the 0% stimulus module through the third ports of amplifiers OP3 and OP7. The 0% stimulus module is connected to the first ports of the adders SUM10 and SUM11 of the stimulus and action module through the fourth ports of control switches S6 and S7.

2. The block-structure decision generation circuit system based on memristor modulation according to claim 1, characterized in that, The stimulus and action module includes a left-side stimulus and action module and a right-side stimulus and action module; The left-side stimulation and action module includes: the Stimulation_Left terminal receives the input signal; the first output port of the Stimulation_Left terminal is connected to the input port of the voltage comparator; the output port of the voltage comparator is connected to the first port of the NAND gate U1; the second output port of the Stimulation_Left terminal is connected to the second port of the NAND gate U1; the third port of the NAND gate U1 is connected to the input port of the first 1 kΩ resistor; the output terminal of the first 1 kΩ resistor is connected to the negative port of the operational amplifier OP1; the positive port of the operational amplifier OP1 is connected to the ground wire; the output terminal of the first 1 kΩ resistor is also connected to the input terminal of a 200Ω resistor; the output terminal of the 200Ω resistor is connected to the output terminal of the operational amplifier OP1; the output terminals of the 200Ω resistor and the operational amplifier OP1 are connected to the first port of the adder SUM1; and the Stimulation_Left... The third output terminal of the adder is connected to the second port of the adder SUM1. The third port of the adder SUM1 is connected to the positive input terminal of the non-volatile memristor M1. The negative output terminal of the non-volatile memristor M1 is connected to the negative port of the operational amplifier OP2. The positive port of the operational amplifier OP2 is connected to the ground wire. The output port of the operational amplifier OP2 is connected to the input port of the second 1 kΩ resistor. The negative output terminal of the non-volatile memristor M1 and the negative port of the operational amplifier OP2 are connected to the input terminal of the 300Ω resistor. The output terminal of the 300Ω resistor is connected to the output port of the operational amplifier OP2 and the input port of the second 1 kΩ resistor. The output terminal of the second 1 kΩ resistor is connected to the negative port of the operational amplifier OP3. The positive port of the operational amplifier OP3 is connected to the ground wire. The output terminal of the kΩ resistor, the negative terminal of the operational amplifier OP3, and the input terminal of the 300Ω resistor are connected. The output terminal of the 300Ω resistor and the output terminal of the operational amplifier OP3 are connected to the positive terminal of the comparator OP4. The negative terminal of the comparator OP4 is connected to a 0.23V voltage source for the reference voltage. The first port of the comparator OP4 is connected to the ground wire. The second port of the comparator OP4 is connected to a 2V voltage source. The output port of the comparator OP4 outputs the left action determination signal Action_Left. The structure of the right-side stimulus and action module is the same as that of the left-side stimulus and action module.

3. The block-structure decision generation circuit system based on memristor modulation according to claim 1, characterized in that, The reward and punishment module includes: Terminal A1 is connected to the first input port of AND gate U3; the Action_Left terminal is connected to the second input port of AND gate U3; the output port of AND gate U3 is connected to the first input port of OR gate U5; terminal A2 is connected to the first input port of AND gate U4; the Action_Right terminal is connected to the second input port of AND gate U4; the output port of AND gate U4 is connected to the second input port of OR gate U5; the output port of OR gate U5 is connected to the positive terminal of non-volatile memristor M3; the negative terminal of volatile memristor M3 is connected to the input port of a 5 kΩ resistor; the output port of the 5 kΩ resistor is connected to the negative terminal of operational amplifier OP9; the positive terminal of operational amplifier OP9 is connected to ground; the negative terminal of operational amplifier OP9 is connected to the input port of a third 1 kΩ resistor; the output port of operational amplifier OP9 is connected to the output port of the third 1 kΩ resistor and the input port of the fourth 1 kΩ resistor; the fourth 1 kΩ resistor... The output port of the 1 kΩ resistor is connected to the negative port of operational amplifier OP10, the positive port of operational amplifier OP10 is connected to ground, the output port of operational amplifier OP10 is connected to the output port of the fifth 1 kΩ resistor, the input port of the fifth 1 kΩ resistor is connected to the negative port of operational amplifier OP10, the output port of operational amplifier OP10 is connected to the positive port of comparator OP11, the negative port of comparator OP7 is connected to a 0.1 V reference voltage source, the first power supply port of comparator OP11 is connected to a 2 V voltage source, the second power supply port of comparator OP11 is connected to a −2 V voltage source, and the output port of comparator OP11 outputs the action determination signal Action_Output; Action_Output is connected to the first port of adder SUM3, Resting... The potential terminal is connected to the second port of adder SUM3; the output port of adder SUM3 is connected to the first input port of AND gate U5; the output port of adder SUM1 is connected to the first input port of AND gate U8; terminal A1 is connected to the second input port of AND gate U8; terminal A2 is connected to the second input port of AND gate U9; the output port of AND gate U8 is connected to the control port of switch S3; the output port of AND gate U9 is connected to the control port of switch S4; the output port of adder SUM3 is connected to the input port of comparator T5.The second A1 terminal is connected to the first input port of the AND gate U6. The second input port of the AND gate U6 is connected to the output port of the comparator T5. The output port of the AND gate U6 is connected to the control port of the switch S1. The output port of the switch S1 is connected to the input terminal of the sixth 1 kΩ resistor. The output terminal of the sixth 1 kΩ resistor is connected to the negative terminal of the operational amplifier OP12. The positive terminal of the operational amplifier OP12 is connected to the ground wire. The output port of the operational amplifier OP12 is connected to the output port of the 500 Ω resistor. The input port of the 500 Ω resistor is connected to the negative terminal of the operational amplifier OP12 and the sixth 1 kΩ resistor. The output of the kΩ resistor is connected; the output port of operational amplifier OP12 is connected to the first port of adder SUM4; the output port of switch S3 is connected to the second port of adder SUM4; the output port of adder SUM4 is connected to the first port of adder SUM5; the output port of adder SUM5 is connected to the positive port of non-volatile memristor M4; the negative port of non-volatile memristor M4 is connected to the negative port of operational amplifier OP13; the positive port of operational amplifier OP13 is connected to ground; the output port of operational amplifier OP13 is connected to the output port of 500Ω resistor; the input port of 500Ω resistor is connected to the negative port of operational amplifier OP10; the output port of operational amplifier OP10 is connected to the input port of the seventh 1 kΩ resistor; the output port of the seventh 1 kΩ resistor is connected to the negative port of operational amplifier OP13; the positive port of operational amplifier OP13 is connected to ground; the output port of operational amplifier OP14 outputs the left reward / penalty signal R / P_Left; the eighth 1 The input terminal of the 1 kΩ resistor is connected to the negative terminal of the operational amplifier OP14, the output terminal of the eighth 1 kΩ resistor is connected to the output terminal of the operational amplifier OP14, the input terminal of the ninth 1 kΩ resistor is connected to the positive terminal and ground wire of the operational amplifier OP14, and the output terminal of the ninth 1 kΩ resistor is connected to the output terminal of the operational amplifier OP14.The third A2 terminal is connected to the second input port of AND gate U7. The first input port of AND gate U7 is connected to the output port of comparator T5. The output port of AND gate U7 is connected to the control port of switch S2. The output port of switch S2 is connected to the input port of the 11 kΩ resistor. The output port of the 11 kΩ resistor is connected to the negative terminal of operational amplifier OP15. The positive terminal of operational amplifier OP15 is connected to the ground wire. The output port of operational amplifier OP15 is connected to the output port of a 500 Ω resistor. The input port of the Ω resistor is connected to the negative port of operational amplifier OP15. The output port of operational amplifier OP15 is connected to the first port of adder SUM6. The output port of switch S4 is connected to the second port of adder SUM6. The output port of adder SUM6 is connected to the first port of adder SUM7. The penalty signal P_Right is connected to the second port of adder SUM7. The output port of adder SUM7 is connected to the positive port of non-volatile memristor M5. The negative port of non-volatile memristor M5 is connected to the negative port of operational amplifier OP11. The positive port of operational amplifier OP11 is connected to the ground wire. The output port of operational amplifier OP16 is connected to the output port of the 500 Ω resistor. The input port of the 500 Ω resistor is connected to the negative port of operational amplifier OP16. The output port of operational amplifier OP16 is connected to the input port of the eleventh kΩ resistor. The output port of the 1 kΩ resistor is connected to the negative port of operational amplifier OP17, and the positive port of operational amplifier OP17 is connected to the ground wire. The output port of operational amplifier OP17 outputs the left reward signal R_Right and the punishment signal P_Right. The input port of the twelfth 1 kΩ resistor is connected to the output port of the eleventh 1 kΩ resistor and the negative port of operational amplifier OP17. The output port of the twelfth 1 kΩ resistor is connected to the output port of operational amplifier OP17. The input port of the thirteenth 1 kΩ resistor is connected to the positive port of operational amplifier OP17, and the output port of the thirteenth 1 kΩ resistor is connected to the output port of operational amplifier OP17. The output port of operational amplifier OP3 in the left stimulus and action module is VL, and the output port of operational amplifier OP3 in the right stimulus and action module is VR.

4. The block structure decision generation circuit system based on memristor modulation according to claim 1, characterized in that, The 0% stimulation module includes: The VL terminal is connected to the positive input port IN+ of device E1; the negative input port IN− of device E1 is connected to the ground wire; the positive output port OUT+ of device E1 is connected to the input port of the thirteenth 1 kΩ resistor; the output port of the thirteenth 1 kΩ resistor is connected to the negative output port OUT− of device E1; the positive output port OUT+ of device E1 serves as the output terminal of signal VT-1_L; the VR terminal is connected to the positive input port IN+ of device E2; the negative input port IN− of device E2 is connected to the ground wire; the positive output port OUT+ of device E2 is connected to the first port of the fourteenth 1 kΩ resistor; the second port of the fourteenth 1 kΩ resistor is connected to the negative output port OUT− of device E2; the positive output port OUT+ of device E2 serves as the output terminal of signal VT-1_R; the VT-1_R terminal is connected to the input terminal of the fifteenth 1 kΩ resistor; the output terminal of the fifteenth 1 kΩ resistor is connected to the positive terminal of operational amplifier OP19; the VT-1_L terminal is connected to the input terminal of the sixteenth 1 kΩ resistor; and the sixteenth 1 kΩ resistor... The output terminal of the 1kΩ resistor is connected to the negative terminal of operational amplifier OP19. The positive terminal of operational amplifier OP19 is connected to the input terminal of the seventeenth 1kΩ resistor. The output terminal of the seventeenth 1kΩ resistor is connected to the ground wire. The output port of operational amplifier OP14 is connected to the output port of the eighteenth 1kΩ resistor. The input port of the eighteenth 1kΩ resistor is connected to the negative terminal of operational amplifier OP19. The output port of operational amplifier OP19 is connected to the positive input port IN+ of device E4. The negative input port IN− of device E4 is connected to the ground wire. The positive output port OUT+ of device E4 is connected to the input port of the nineteenth 1kΩ resistor. The output port of the nineteenth 1kΩ resistor is connected to the ground wire. The negative output port OUT− of device E4 is connected to the output port of the nineteenth 1kΩ resistor and the ground wire. The positive output port OUT+ of device E4 and the nineteenth 1kΩ resistor are connected to the ground wire. The input port of the kΩ resistor is connected to the first port of adder SUM9; the third A1 terminal is connected to the first input port of logic NOR gate U10; the fourth A2 terminal is connected to the second input port of logic NOR gate U10; the output port of logic NOR gate U10 is connected to the first port of adder SUM6; the Reseting potential terminal is connected to the second port of adder SUM6; the output port of adder SUM6 is connected to the control port of switch S5; the output port of switch S5 is connected to the input terminal of the 21 kΩ resistor; the output terminal of the 21 kΩ resistor is connected to the second port of adder SUM9; the output port of adder SUM9 is connected to the input port of switch S6; the first port of switch S7 is connected to a 2 V voltage source; the second port of switch S7 is connected to the ground wire; and the output port of switch S7 outputs the right-side output signal V0_R.The input terminal of the 1 kΩ resistor (twenty-first) is connected to the second port of switch S7, and the output terminal of the 1 kΩ resistor (twenty-first) is connected to the output port of switch S7. The VT-1_R terminal is connected to the input terminal of the 1 kΩ resistor (twenty-second), and the output terminal of the 1 kΩ resistor (twenty-second) is connected to the negative port of operational amplifier OP15. The VT-1_L terminal is connected to the input terminal of the 1 kΩ resistor (twenty-third), and the output terminal of the 1 kΩ resistor (twenty-third) is connected to the positive port of operational amplifier OP18. The input terminal of the 1 kΩ resistor (twenty-fourth) is connected to the output terminal of the 1 kΩ resistor (twenty-third) and the positive port of operational amplifier OP18. The output terminal of the 1 kΩ resistor (twenty-fourth) is connected to the ground wire. The input terminal of the 1 kΩ resistor (twenty-fifth) is connected to the output terminal of the 1 kΩ resistor (twenty-second), and the negative port of operational amplifier OP18. The output terminal of the 1 kΩ resistor (twenty-fifth) is connected to the output terminal of operational amplifier OP18. The output port of operational amplifier OP18 is connected to the positive input port IN+ of device E3. The negative input port IN− of device E3 is connected to the ground wire. The positive output port OUT+ of device E3 is connected to the 1 kΩ resistor (twenty-fifth)... The input terminal of the 1 kΩ resistor is connected to the ground wire. The output terminal of the 1 kΩ resistor is connected to the negative output port OUT− and negative input port IN− of device E3. The positive output port OUT+ of device E3 is connected to the first port of adder SUM8. The second port of adder SUM8 is connected to the input port of switch S6. The third port of adder SUM8 is connected to the second port of adder SUM6. The first port of switch S6 is connected to a 2 V voltage source. The second port of switch S6 is connected to the ground wire. The input terminal of the 1 kΩ resistor is connected to the output port of switch S6. The output terminal of the 1 kΩ resistor is connected to the ground wire. The output port of switch S6 outputs the left-side output signal V0_L.

5. The block structure decision generation circuit system based on memristor modulation according to claim 1, characterized in that, The bias module includes: the stimulus probability Pleft bias value. When Pleft is greater than 0.5, the visual stimulus comes from the left side, and a bias voltage is applied to the left pathway in the stimulus and action module. When Pleft is less than 0.5, the visual stimulus comes from the right side, and a bias voltage is applied to the right pathway in the stimulus and action module. When Pleft=0.5, no bias voltage needs to be applied to the stimulus and action module.

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