Low-latency subsampled phase-locked loop

Abstract

The present disclosure relates to low-latency sub-sampling phase-locked loop. The invention relates to an apparatus, such as a sub-sampling phase-locked loop (PLL), comprising a digitally controlled oscillator (DCO), a digital phase detector, and a digital filter. The DCO generates a first signal having a phase based on a second signal provided to the DCO. The digital phase detector generates a third signal representing a phase offset between a reference clock signal and the first signal. The digital filter generates the second signal by filtering out high-frequency fluctuations in the third signal.

Description

Technical Field

[0001] This invention relates to a low-delay sub-sampling relay type digital phase-locked loop device and method. Background Technology

[0002] A phase-locked loop (PLL) is a control system that receives an input signal and generates an output signal with a fixed phase relative to the input signal. PLLs can be used to implement functions such as clock synchronization, demodulation, frequency synthesis, clock multipliers, and signal recovery from noisy communication channels. Therefore, PLLs are implemented in many signal processing applications. For example, PLLs can provide signals with a stable phase to circuits used in radio, wireless communication, radar, microprocessors, and grid-connected converters. The components used to construct a PLL often generate noise in the output signal, which can negatively impact the PLL's performance. Summary of the Invention

[0003] According to one embodiment, an apparatus includes a digitally controlled oscillator (DCO), a digital phase detector, and a digital filter. The DCO is configured to generate a first signal having a phase based on a second signal provided to the DCO. The digital phase detector is configured to generate a third signal representing a phase offset between a reference clock signal and the first signal. The digital filter is configured to generate the second signal by filtering out spectral components from the third signal.

[0004] Optionally, the digital phase detector is configured to generate a third signal representing a fixed positive value in response to the first signal generated by the DCO representing a value greater than zero, and wherein the digital phase detector is configured to generate the third signal representing a fixed negative value in response to the first signal generated by the DCO representing a value less than zero.

[0005] Optionally, the digital phase detector is configured to receive the first signal as an output from the DCO.

[0006] Optionally, the digital phase detector is configured to generate quantization noise. The quantization noise represents the difference between the value represented by the third signal and the value of the probability density function at the phase offset, wherein the probability density function represents the statistical distribution of the sampled phase determined based on the phase noise in the reference clock signal.

[0007] Optionally, the digital filter is configured such that the device has a bandwidth corresponding to the minimum value of the phase noise of the device.

[0008] Optionally, the device further includes a frequency-locked loop (FLL). The FLL is connected to the DCO and configured to generate a fourth signal representing the difference between a reference frequency of a harmonic of the reference clock signal and the output frequency of the first signal generated by the DCO. The DCO is configured to modify the output frequency of the first signal based on the fourth signal.

[0009] Optionally, the FLL and the DCO are configured to maintain the output frequency of the first signal within the capture range of the reference frequency.

[0010] Optionally, the DCO is configured in a first operating mode to modify the output frequency of the first signal in response to the fourth signal provided by the FLL, and wherein the DCO is configured in a second operating mode to generate the first signal having a phase determined based on the second signal provided to the DCO.

[0011] Optionally, the FLL operates in the first operating mode in response to a frequency difference between a harmonic of the reference frequency and the output frequency of the first signal exceeding a threshold frequency difference corresponding to the capture range.

[0012] According to an embodiment, a method includes: generating a first signal having a phase based on a second signal provided to the DCO at a digitally controlled oscillator (DCO); generating a third signal representing a phase offset between a reference clock signal and the first signal at a digital phase detector; and generating the second signal at a digital filter by filtering out spectral components in the third signal.

[0013] Optionally, generating the third signal includes generating the third signal representing a fixed positive value in response to the first signal generated by the DCO representing a value greater than zero.

[0014] Optionally, generating the third signal includes generating the third signal representing a fixed negative value in response to the first signal generated by the DCO representing a value less than zero.

[0015] Optionally, the method further includes receiving the first signal as an output from the DCO at the digital phase detector.

[0016] Optionally, the method further includes: at the digital phase detector, generating quantization noise based on the difference between the value represented by the third signal and the value of the probability density function at the phase offset, wherein the probability density function represents a statistical distribution of the sampled phase determined based on the phase noise in the reference clock signal.

[0017] Optionally, the method further includes: generating a fourth signal at a frequency-locked loop (FLL) connected to the DCO, the fourth signal representing the difference between a reference frequency of a harmonic of a reference clock frequency and the output frequency of the first signal generated by the DCO; and modifying the output frequency of the first signal at the DCO based on the fourth signal.

[0018] Optionally, the method further includes: using the FLL and the DCO to maintain the output frequency of the first signal within the capture range of the reference frequency.

[0019] Optionally, modifying the output frequency of the first signal includes modifying the output frequency of the first signal in response to the fourth signal provided by the FLL in a first operating mode, and wherein generating the first signal includes generating the first signal having a phase determined based on the second signal provided to the DCO in a second operating mode.

[0020] Optionally, the method further includes: in the first operating mode, activating the FLL in response to a frequency difference between the reference frequency and the output frequency of the first signal exceeding a threshold frequency difference corresponding to the capture range.

[0021] According to one embodiment, a sub-sampling phase-locked loop (PLL) includes: a digitally controlled oscillator (DCO), a quantizer, and a loop filter. The DCO is configured to generate a first signal having a phase determined based on a second signal provided to the DCO. The quantizer is configured to generate a third signal, the third signal representing a value of +1 in response to a sampled value of the first signal having a value greater than zero, and representing a value of -1 in response to a sampled value of the first signal having a value less than zero. The loop filter is configured to generate the second signal in response to receiving the third signal from the quantizer. The loop filter is a low-pass filter.

[0022] Optionally, the sub-sampling PLL further includes a frequency-locked loop (FLL). The FLL is configured to provide a fourth signal to the DCO. The fourth signal represents the difference between the reference frequency of the harmonics of the reference clock signal and the output frequency of the first signal generated by the DCO. The DCO is configured to modify the output frequency of the first signal based on the fourth signal, such that the output frequency remains within the capture range of the reference frequency of the harmonics of the reference clock signal. Attached Figure Description

[0023] The present disclosure can be better understood by referring to the accompanying drawings, which will make its numerous features and advantages clear to those skilled in the art. The same reference numerals are used in different drawings to indicate similar or identical items.

[0024] Figure 1 A processing system including a subsampled phase-locked loop (PLL) is shown according to some embodiments.

[0025] Figure 2 The diagram shows a graph of a signal generated by a digitally controlled oscillator (DCO) according to some embodiments, and a graph of an error function for sampling by a digital relay-type (bang-bang) phase detector.

[0026] Figure 3 A graph showing the expected value of the output of a digital relay-type phase detector that samples the signal generated by the DCO in a PLL according to some embodiments.

[0027] Figure 4 A graph showing the quantization error generated by a digital relay-type phase detector according to some embodiments is shown.

[0028] Figure 5 A graph showing the phase noise contribution in a PLL with an optimally selected bandwidth, according to some embodiments.

[0029] Figure 6 A graph showing the phase noise contribution in a low-bandwidth PLL with bandwidth below the optimal bandwidth according to some embodiments is shown.

[0030] Figure 7 A graph showing the phase noise contribution in a high-bandwidth PLL with a bandwidth greater than the optimal bandwidth according to some embodiments is shown.

[0031] Figure 8 The graphs show the effects of phase noise on different time delays according to some embodiments.

[0032] Figure 9 A processing system according to some embodiments is shown, the processing system including a sub-sampling digital relay type PLL connected to a frequency-locked loop (FLL).

[0033] Figure 10 A circuit for performing a loop update is shown according to some embodiments. Detailed Implementation

[0034] A typical analog PLL circuit includes a phase detector, a loop filter, and a voltage-controlled oscillator (VCO). In operation, the phase detector receives a reference signal, and the goal of the PLL is to lock the phase of the output signal generated by the VCO to the phase of the reference signal. The output signal is fed back to the phase detector via a frequency divider, which compares the phase of the (divided) output signal with the phase of the input reference signal. The phase detector generates a voltage proportional to the phase difference between the two signals (i.e., the time difference between correlated edges in the case of a rectangular signal, or the time difference between correlated zero-crossings in the case of a sinusoidal signal). For example, the phase detector can generate a negative voltage to slow down the VCO if the output signal leads the input reference signal, and a positive voltage to speed up the VCO if the output signal lags the input reference signal. The amplitude of the voltage generated by the phase detector is proportional to the magnitude of the phase difference between the two signals. The loop filter is a low-pass filter that stabilizes the voltage by filtering out high-frequency components. The VCO receives the filtered voltage and modifies the phase of its output signal based on the signal received from the loop filter. For example, in response to a positive voltage indication output signal lagging behind the input reference signal, the VCO accelerates by shifting the phase of the output signal forward, and conversely, in response to a negative voltage indication output signal leading the input reference signal, the VCO slows down.

[0035] Many applications, including radio and radar applications, benefit from the use of PLLs with low in-band phase noise. As used herein, the term "in-band" refers to frequencies below the cutoff frequency of the PLL's total phase transfer function. The phase transfer function attenuates out-of-band signals above the cutoff frequency and is transparent to in-band signals below the cutoff frequency. Phase noise is typically generated by the reference clock signal provided to: the phase detector in the PLL, the VCO, the loop filter, the time-to-digital (TDC) and digital-to-time (DTC) converters, and the charge pump typically included to control the voltage of the signals in the PLL. The in-band phase noise generated at the PLL output by the noise in the reference clock signal is equal to the product of the reference clock signal noise and the ratio of the reference clock frequency to the VCO frequency. In the case of analog subsampled PLLs, the gain of the phase detector and the corresponding loop gain can be relatively large, which may require the inclusion of large loop filter capacitors to provide sufficient phase margin for the stabilizing loop. However, large loop filter capacitors are difficult to implement in integrated designs. Alternatively, a pulse generator can be used to apply current from a charge pump to the loop filter for a time limit that is a fraction of the reference time interval of the phase detector. Implementing pulsed current in this way typically requires larger resistor values ​​in the loop filter, which can degrade phase noise performance due to their noise contribution.

[0036] Subsampled relay-type digital PLLs improve phase noise performance by reducing phase noise generated by the phase detector and loop filter, and by eliminating components including charge pumps, TDC / DTCs, and frequency dividers that generate noise or delay in conventional PLLs. A subsampled relay-type digital PLL includes a digital phase detector, a digital loop filter, and a digitally controlled oscillator (DCO) instead of a VCO. As used herein, the term "subsampled" refers to a PLL that includes a phase detector that samples the output signal generated by the oscillator directly at a time indicated by a reference clock signal. Therefore, a subsampled PLL does not require or includes a frequency divider in the feedback path from the VCO to the phase detector. The term "relay-type (bang-bang)" refers to a digital phase detector that generates an output of +1 (or some other fixed positive value) in response to a sampled output of the DCO being greater than zero and an output of -1 (or some other fixed negative value) in response to a sampled output of the DCO being less than zero. Depending on the implementation, the digital phase detector may provide an output of +1 or -1 in response to a sampled output equal to zero. Phase noise (jitter) in the reference clock signal produces a statistical distribution of the sampled phase, which varies continuously from +1 to -1, and is referred to as the error function. The phase detector samples the phase of the output signal at sampling times determined by the reference clock signal, and thus samples points in the error function. Therefore, there exists a first probability that the phase detector samples +1 and a second probability that the phase detector samples -1. The first and second probabilities are determined by the phase offset between the reference clock signal and the DCO signal, and they sum to one. The quantization noise introduced by the phase detector is equal to the difference between the actual output of the phase detector (e.g., +1 or -1) and the value of the error function at the phase offset. Quantization noise typically contributes several decibels (dB) to the in-band phase noise, which is much smaller than the noise level in a conventional PLL. Furthermore, conventional phase detectors include a TDC that contributes thermal noise, which is not generated by the digital phase detector.

[0037] A digital phase detector provides a digital signal representing a phase shift (e.g., +1 or -1) to a digital loop filter, which filters out high-frequency spectral components from the digital signal. The DCO receives the filtered digital signal and modifies the phase of its output signal based on the signal received from the digital loop filter. In some embodiments, the digital loop filter is configured such that the bandwidth of the subsampled relay digital PLL corresponds to a minimum of phase noise or jitter. As discussed herein, the subsampled relay digital PLL generates less phase noise than a conventional PLL. Furthermore, the subsampled relay digital PLL can support a larger bandwidth than a conventional PLL. One disadvantage is that the subsampled relay digital PLL can lock to the phase of any harmonic of the reference clock signal. To address this, a frequency-locked loop (FLL) can be connected to the DCO and used to maintain the DCO's oscillator frequency within the capture range of the desired harmonic of the reference clock signal. As used herein, the term "capture range" refers to the frequency range around the desired harmonic frequency within which the subsampled relay digital PLL locks the phase of its output signal to the phase of the desired harmonic frequency. Reference frequency The typical capture range is When the frequency offset is within the ADPLL's capture range, the DCO control switches from FLL mode to sub-sampling ADPLL mode, the capture range of which can be limited by a loop configuration. Small intervals. The settling time can be reduced by decreasing the frequency offset toward zero. In some embodiments, the FLL remains active or is activated after a predetermined time interval to monitor the state of the ADPLL. In some embodiments, the FLL is operable or activated in response to a frequency difference between the frequency of the reference clock signal and the frequency of the DCO exceeding a threshold frequency difference corresponding to the capture range of the reference clock signal frequency.

[0038] Figure 1 A processing system 100 including a subsampled phase-locked loop (PLL) 102 is shown according to some embodiments. The subsampled PLL 102 includes a phase detector 104, a loop filter 106, and a frequency-locked loop (DCO) 108. In the illustrated embodiment, the subsampled PLL 102 is connected to a frequency-locked loop (FLL) 110. The control of the phase detector 104, loop filter 106, DCO 108, and FLL 110 is implemented in the digital domain. Therefore, information is processed in the phase detector 104, loop filter 106, DCO 108, and FLL 110 and transmitted between them as digital information (e.g., bits, bytes, words, etc.). The DCO 108 operates in the analog domain.

[0039] Phase detector 104 is implemented as a "relay-type" phase detector that generates an output in digital word form representing a value of +1 or -1 based on sampled values ​​of the input signal. Phase detector 104 receives a reference clock signal 112 and samples a feedback signal 114 (also referred to herein as the second signal 114) on each cycle of the reference clock signal. In some embodiments, phase detector 104 samples the feedback signal 114 on either the rising or falling edge of the reference clock signal 112. Phase detector 104 generates an output value of +1 in response to a sampled value of the feedback signal 114 being greater than zero, and generates an output value of -1 in response to a sampled value of the feedback signal 114 being less than zero. Depending on the embodiment, phase detector 104 may generate an output value of +1 or -1 in response to a sampled value of the feedback signal 114 being equal to zero.

[0040] Loop filter 106 receives the output generated by phase detector 104. Loop filter 106 has a low-pass characteristic, thus filtering out high-frequency spectral components in the signal received from phase detector 104. As discussed herein, some embodiments of loop filter 106 are configured such that the bandwidth of subsampling PLL 102 corresponds to the minimum of the phase noise or jitter generated by the components of subsampling PLL 102. The filtered signal generated by loop filter 106 is provided to DCO 108, which generates or modifies the phase or frequency of output signal 116 (also referred to herein as first signal 116) based on the filtered signal received from loop filter 106.

[0041] The output signal 116 from DCO 108 is fed back to phase detector 104 as feedback signal 114. Therefore, phase detector 104 directly samples signal 116 as the output from DCO 108. The feedback path between DCO 108 and phase detector 104 does not include an entity that modifies the phase or frequency of feedback signal 114. This contrasts with a conventional or “sampled” PLL, which includes a frequency divider in the feedback path between DCO 108 and phase detector 104 to modify the frequency of feedback signal 114. For example, a frequency divider can reduce the frequency of the feedback signal. A frequency divider (if present) can contribute phase noise, and removing a frequency divider from the feedback path reduces the phase noise generated in sub-sampled PLL 102. In some embodiments, partial frequency division is performed on output signal 116, for example, instead of dividing to a reference level, it is divided to a more manageable frequency, such as reducing the frequency of output signal 116 by a factor of eight.

[0042] Subsampling PLL 102 can generate a lock-in condition for any frequency of the output signal 116, where any frequency is a harmonic of the frequency of the reference clock signal 112. Therefore, FLL 110 is connected to DCO 108 in a feedback loop that keeps the frequency of DCO 108 near a preferred harmonic of the frequency of the reference clock signal 112. In some embodiments, FLL 110 keeps the frequency of DCO 108 within the capture range of the reference clock signal 112. Reference Frequency The capture range can be Alternatively, a smaller interval around the desired harmonic of the reference signal may be defined by the loop configuration. In some embodiments, FLL 110 compares the frequency of the reference clock signal 112 with the frequency of the output signal 116. For example, FLL 110 may measure the difference between the frequency of the reference clock signal 110 and the frequency of the output signal 116. Based on the comparison, FLL 110 generates a control signal 118 (also referred to herein as the fourth signal 118) that is provided to DCO 108. The state of FLL 110 may be stored when the frequency of the reference clock signal is within the capture range of the preferred harmonic and the PLL switches to subsampling operation mode.

[0043] The subsampling PLL 102 can operate in two modes, distinguished by a control signal used by the DCO 108 to generate or modify the output signal 116. In a first mode, the DCO 108 receives a control signal 117 (also referred to herein as the third signal 117) generated by the phase detector 104 and the loop filter 106. The DCO 108 uses this control signal to generate or modify the output signal 116 based on the phase difference between the feedback signal 114 and the reference clock signal 112. In the second mode, the DCO 108 receives a control signal generated by the FLL 110 and uses this control signal to generate or modify the output signal 116 based on the frequency difference between the reference clock signal 112 and the output signal 116. When the subsampling PLL 102 operates in the first mode, the FLL 110 can switch to an idle or standby mode. However, in some embodiments, the FLL 110 can monitor the output signal 116 to detect interference in the output signal 116. For example, FLL 110 can trigger a transition from the first mode to the second mode in response to detecting that a frequency change in the output signal 116 falls outside the capture range of a preferred harmonic of the reference clock signal 112.

[0044] Figure 2 A graph 200 shows a signal 205 generated by a DCO according to some embodiments, and a graph 210 shows a probability density function 215 for sampling by a digital relay phase detector. The sampling method shown is... Figure 1Some embodiments of the phase detector 104 shown are implemented. The horizontal axis of graphs 200 and 210 indicates the phase offset between the reference clock signal and the signal 205 generated by the DCO. The vertical axis of graph 200 indicates the probability of detecting a certain offset of the signal generated by the DCO, for example, the DCO generates a signal with a value of -1.0 at the negative phase and a value of +1.0 at the positive phase. If a value is detected on the negative side of the x-axis, the output value is called -1, and if a value is detected on the positive side, the value is called 1.

[0045] The digital relay-type phase detector directly samples signal 205 as the output from the DCO, and the timing of the sampling is determined by the phase offset between the reference clock signal and signal 205. If the reference clock signal lags behind signal 205, the digital relay-type phase detector samples a value of -1.0, and if the reference clock signal leads signal 205, the digital relay-type phase detector samples a value of +1.0. In the illustrated embodiment, the digital relay-type phase detector samples signal 205 at sampling point 220 corresponding to a phase offset of -2, so the sampled value of signal 205 may be -1.0. However, phase noise in the reference clock signal introduces jitter into the sampling timing. Therefore, even if the reference clock signal lags behind signal 205, the digital relay-type phase detector can still sample a value of +1.0. Conversely, even if the reference clock signal leads signal 205, the digital relay-type phase detector can still sample a value of -1.0.

[0046] The probability density function 215 indicates the probability of sampling a value of +1.0 or -1.0, which varies with the actual phase offset between the reference clock signal and signal 205. In the illustrated embodiment, the error function 215 has a peak at a phase offset of -2, which is the actual phase offset between the reference clock signal and signal 205. However, jitter in the reference clock signal causes the probability density function 215 to extend across the phase offset range. The probability of sampling a value of -1.0 from signal 205 for an actual phase offset of -2 is equal to the probability of sampling a value of +1.0 across the phase offset range under the error function 215. The area of ​​the integral over a phase shift to 0.0. The probability of sampling a value of +1.0 from signal 205 with respect to an actual phase shift of -2 is equal to the probability density function 215 over a period from 0.0 to 0.0. The area integraled by the phase shift. Therefore, the expected value of the sample value generated and output by the digital relay phase detector changes continuously with the phase shift.

[0047] Figure 3A graph 300 shows the expected value 305 of the output of a digital relay-type phase detector sampling a signal generated by the DCO in a PLL according to some embodiments. The horizontal axis of graph 300 indicates the phase shift, and the vertical axis of graph 300 indicates the expected value 305 varying from -1.0 to +1.0. The expected value 305 can be linearized at or near the operating point of the PLL (e.g., at or near the phase shift of 0.0) using a Taylor approximation. The derivative 310 of the Taylor approximation of the expected value 305 at the operating point reflects the phase detector gain of the digital relay-type phase detector, which can be calculated as:

[0048]

[0049] in It is the expected value calculated from the probability density function and output from the digital relay phase detector, and This refers to the jitter at the digital relay-type phase detector. The jitter includes contributions from reference clock jitter and DCO jitter in closed-loop mode. A smaller jitter contribution results in a larger phase detector gain. and loop gain.

[0050] If the phase detector gain is Then the open-loop phase transfer function ( This can be expressed as:

[0051]

[0052] Closed-loop transfer function ( ) can be obtained from the open-loop phase transfer function ( ) Calculate and express as:

[0053]

[0054] These equations imply a reference period or time interval ( This affects the loop gain, causing an increase in the reference time interval (which reduces the reference frequency) to increase the loop gain. Therefore, the phase margin can be optimized, for example, by optimizing bandwidth, phase margin, jitter, etc.

[0055] If the reference phase noise and DCO phase noise are constant over the process, voltage, temperature, and tuning range, then only an optimized setting needs to be provided to the loop filter of the sub-sampling relay phase detector, and this setting should be sufficient. However, if the reference or DCO phase noise depends on one or more of these parameters, then calibration is required to optimize the loop bandwidth. In some embodiments, calibration is performed using production tests that directly measure the phase noise or other methods, such as measuring the bandwidth and performing bandwidth calibration during circuit startup.

[0056] Figure 4 A graph 400 illustrates the quantization error generated by a digital relay-type phase detector according to some embodiments. The horizontal axis of graph 400 indicates the phase offset, and the vertical axis indicates the value 405 generated by the digital relay-type phase detector. The generated values ​​range from -1.0 at negative phase offsets to +1.0 at positive phase offsets. Graph 400 also includes an error function 410 generated by phase noise at the digital relay-type phase detector. The quantization error generated by the digital relay-type phase detector is determined by the difference between the value 405 and the error function 410. The total quantization error is equal to the difference between the values ​​405 and +1.0. arrive The integral of the difference.

[0057] Figure 5 A graph 500 is shown illustrating the phase noise contribution in a PLL with an optimally selected bandwidth according to some embodiments. The horizontal axis of graph 500 indicates the frequency on a logarithmic scale. Furthermore, the vertical axis of graph 500 indicates the phase noise on the logarithmic scale. .

[0058] Curve 502 represents the unfiltered phase noise of the reference clock signal, and curve 504 represents the unfiltered phase noise amplified by gain 506, which is the ratio of the oscillator frequency to the reference clock frequency (e.g., ...). The value is determined. Curve 508 represents the unfiltered oscillator phase noise. Curve 510 represents the low-pass filter characteristic of the PLL, which is applied to the amplified reference clock phase noise (curve 504). Curve 512 represents the high-pass filter characteristic applied to the oscillator phase noise (curve 508). Curve 516 represents the filtered reference clock phase noise, and curve 518 represents the filtered oscillator phase noise. Curve 520 represents the total phase noise generated by the PLL.

[0059] For a given level of reference clock phase noise (curves 502, 504) and oscillator phase noise (curve 508), the optimal bandwidth for minimum jitter can be found at point 522, which is close to the offset frequency, where the reference phase noise (curve 504) is multiplied by the ratio of the oscillator frequency to the reference clock frequency. The reference phase noise (curves 502, 504) intersects with the oscillator phase noise characteristics. At higher frequencies, the reference phase noise is suppressed by the low-pass characteristics of the loop filter. In the illustrated embodiment, the loop filter attenuates the reference phase noise by a higher order (e.g., -40 dB / dec) than the oscillator phase noise characteristics (e.g., -20 dB / dec), such that the oscillator phase noise (curve 508) dominates outside the loop bandwidth. The oscillator phase noise (curve 508) is overcompensated for this component by the high-pass characteristics of the loop, so that in the illustrated embodiment, only the reference phase noise contribution for in-band phase noise is retained.

[0060] Figure 6 A graph 600 illustrates the phase noise contribution in a low-bandwidth PLL with bandwidth below the optimal bandwidth according to some embodiments. The horizontal axis of graph 600 indicates the frequency on a logarithmic scale. Furthermore, the vertical axis of graph 600 indicates the phase noise on the logarithmic scale. .

[0061] Curve 602 represents the unfiltered phase noise of the reference clock signal, and curve 604 represents the unfiltered phase noise amplified by gain 606, which is the ratio of the oscillator frequency to the reference clock frequency (e.g., ...). The value is determined. Curve 608 represents the unfiltered oscillator phase noise. Curve 610 represents the low-pass filter characteristics of the PLL applied to the amplified reference clock phase noise (curve 604). Curve 612 represents the high-pass filter characteristics of the PLL applied to the oscillator phase noise (curve 608). Relative to Figure 5 The corresponding curves 510 and 512 shown in the figure, and curve 610 indicate the attenuation of the low-pass filter characteristics compared to Figure 5 The low-pass filter characteristic of curve 510 shown in the diagram begins at a low frequency. Curve 616 represents the filtered reference clock phase noise, and curve 618 represents the filtered oscillator phase noise. Curve 620 represents the total phase noise generated by the PLL.

[0062] exist Figure 6 In the embodiment shown, the bandwidth of the PLL, determined by the cutoff frequency of the PLL's low-pass characteristic, is lower than... Figure 5 The optimal value is shown. Therefore, the oscillator contribution to phase noise (indicated by curve 618) is addressed by the high-pass filter characteristics at lower frequencies but is suppressed at higher levels than the reference phase noise contribution (as indicated by curve 616). Thus, the oscillator is the primary contributor to the phase noise and jitter of the PLL. Shaded area 622 indicates... Figure 6 The total phase noise of the embodiment shown is Figure 5The difference between the (relatively small) total phase noise in the embodiment shown.

[0063] Figure 7 A graph 700 is shown illustrating the phase noise contribution in a high-bandwidth PLL with less than the optimal bandwidth according to some embodiments. The horizontal axis of graph 700 indicates the frequency on a logarithmic scale. Furthermore, the vertical axis of graph 700 indicates the phase noise on the logarithmic scale. .

[0064] Curve 702 represents the unfiltered phase noise of the reference clock signal, and curve 704 represents the unfiltered phase noise amplified by gain 706, which is the ratio of the oscillator frequency to the reference clock frequency (e.g., ...). The value is determined. Curve 708 represents the unfiltered oscillator phase noise. Curve 710 represents the low-pass filter characteristics of the PLL applied to the amplified reference clock phase noise (curve 704). Curve 712 represents the high-pass filter characteristics of the PLL applied to the oscillator phase noise (curve 708). Relative to Figure 5 The corresponding curves 510 and 512 shown, and curve 710 indicate the attenuation of the low-pass filter characteristics compared to... Figure 5 The low-pass filter characteristic of curve 510 shown in the diagram begins at a high frequency. Curve 716 represents the filtered reference clock phase noise, and curve 718 represents the filtered oscillator phase noise. Curve 720 represents the total phase noise generated by the PLL.

[0065] exist Figure 7 In the embodiment shown, the bandwidth of the PLL, determined by the cutoff frequency of the PLL's low-pass characteristic, is higher than... Figure 5 The optimal value is shown. Therefore, the oscillator contribution to phase noise (indicated by curve 718) is suppressed to a lower level than the reference phase noise contribution (indicated by curve 716), but low-pass filtering of the reference phase noise contribution (indicated by curve 716) occurs at a higher frequency. The higher cutoff frequency causes the reference phase noise contribution (indicated by curve 716) to dominate both phase noise contribution and jitter. Shaded area 722 indicates... Figure 7 The total phase noise of the embodiment shown is Figure 5 The difference between the (relatively small) total phase noise in the embodiment shown.

[0066] In some embodiments, a large loop bandwidth can significantly reduce in-band phase noise, especially at the edge of projects where other components are already conceivable in available technology. For a given reference phase noise level and a given phase noise generated by the oscillator, there exists an optimal bandwidth for the system that results in the total phase noise or jitter being at or near a minimum. For larger oscillator phase noise or lower reference phase noise, the optimal bandwidth is at a larger loop bandwidth.

[0067] Subsampling or sampling PLLs can be designed to provide large bandwidth. In both cases, the loop gain can be large to support the large bandwidth provided in the PLL. Furthermore, configuring the phase detector to produce a large gain, and correspondingly a large loop gain, helps reduce the phase noise contribution of the charge pump (if present). All-digital PLLs can also be used to provide large loop bandwidth. The noise contribution to an all-digital PLL is typically dominated by reference phase noise, oscillator phase noise, and, in some cases, quantization noise. However, the potential bandwidth of an all-digital PLL can be limited by time delay. For example, if the bandwidth of an all-digital PLL is too large, the delay in the feedforward and feedback paths has a significant impact on the phase noise characteristics of the all-digital PLL.

[0068] Figure 8 A graph 800 illustrates the effect of phase noise on different time delays according to some embodiments. The horizontal axis of graph 800 indicates the frequency on a logarithmic scale. Furthermore, the vertical axis of graph 800 indicates the phase noise on the logarithmic scale. .

[0069] Delay significantly affects the total phase noise characteristics, and therefore also affects jitter. In the illustrated embodiment, curve 802 represents the phase noise varying with frequency for a delay of 0. Curve 804 represents the phase noise varying with frequency for a delay of 0.5. Curve 806 represents the phase noise varying with frequency for a delay of 1.0. Curve 808 represents the phase noise varying with frequency for a delay of 1.5. As the delay changes from 0 to 1.5, the total phase noise increases by 13 dB, and the jitter doubles because the largest impact on jitter is attributed to the change in loop bandwidth.

[0070] Some embodiments of subsampled digital relay PLLs described herein can address the latency issues of conventional all-digital PLL systems. For example, the oscillator signal is directly sampled in the subsampled architecture (e.g., as the output from the DCO), thus eliminating latency in the feedback path. Furthermore, loop filters can be designed to avoid, reduce, or eliminate latency in the feedforward path. Some embodiments of subsampled digital relay PLLs can be configured with a higher reference frequency.

[0071] Figure 9 A processing system 900 according to some embodiments is shown, the processing system 900 including a subsampled digital relay phase-locked loop (PLL) 902 connected to a frequency-locked loop (FLL) 904. The subsampled digital relay PLL 902 includes a relay-type phase detector 906, a loop filter 908, and a DCO 910, and these entities operate as discussed herein. The subsampled digital relay PLL 902 and FLL 904 are implemented in... Figure 1 In some embodiments of the processing system 100.

[0072] In the illustrated embodiment, FLL 904 includes adders 911, 912 and registers 913, 914. FLL 904 also includes a counter 916, a quantizer 918, and a loop filter 920. Controller 922 and FLL 904 are used to selectively activate the loop filter, as discussed herein. In operation, FLL 904 receives a reference clock signal 924 and a signal 926 generated by DCO 910. Some embodiments of FLL 904 and subsampled digital relay PLL 902 operate in two modes: FLL control mode and phase detector control mode. In phase detector control mode, DCO 910 receives control signals generated by relay-type phase detector 906 and loop filter 908. The control signals are used to generate or modify the operation of DCO 910, as discussed herein. In FLL control mode, DCO 910 receives control signals generated by FLL 904, and DCO 910 modifies its behavior based on the control signals, as discussed herein. Some embodiments of the FLL 904 can switch to an idle or standby mode during phase detector control mode. The FLL 904 can monitor the output signal 926 to detect interference in the output signal 926, as discussed herein.

[0073] In some embodiments, the subsampled digital relay PLL 902 switches from phase detector control mode to FLL control mode upon startup of the subsampled digital relay PLL 902 or in response to a change from one frequency to another. In FLL control mode, the frequency of signal 926 is measured by measuring the number of pulses within a counting window (as determined using counter 916). The counting window may correspond to a reference clock interval. The result is provided as a feedback word (FBW) to registers 913, 914. T compares the FBW with the frequency control word (FCW) 928 provided to FLL 904. FCW 928 represents, for example, the expected number of DCO clock pulses or intervals within the counting window of the reference clock interval. Controller 922 determines the difference between FCW 928 and FBW, where FBW indicates the difference between the actual oscillator frequency and the desired oscillator frequency. The controller 922 then provides a representation difference ( The signal 930 is used to update the loop filter 920. In some embodiments, the quantizer 918 updates the DCO 910 with discrete frequency steps: increasing the step size if the DCO 910 is found to be too slow, or decreasing the step size if the DCO 910 is found to be too fast. Implementing the quantizer 918 can cause the system to stabilize more quickly. The frequency resolution of the frequency measurement can be increased by averaging or by using a larger measurement interval. If a larger measurement interval is chosen, then the counter samples are not obtained at the time interval indicated by the reference clock signal 924, but at intervals equal to multiples of the time interval indicated by the reference clock signal 924.

[0074] The transition between FLL control mode and phase detector control mode can be triggered by meeting different criteria. FLL 904 maintains control of DCO 910 until the frequency offset between the actual frequency and the desired frequency (…) The condition is met until the loop control is switched from FLL control mode to phase detector control mode.

[0075] In the first embodiment, the transition from the FLL control node to the phase detector control mode occurs at a fixed time interval after the system transitions from the phase detector control mode to the FLL control mode. This time interval can be determined based on whether the loop is updated linearly or discretely. When determining the time interval, the maximum possible tuning range and potential safety margin can also be considered.

[0076] In the second embodiment, the transition from FLL control mode to phase detector control mode is determined based on the actual frequency difference. For example, controller 922 can determine the frequency offset ( And in response to frequency shift ( If the capture range is less than that of the sub-sampling digital relay type PLL 902, it switches to phase detector control mode. The maximum capture range is [value missing]. However, due to the characteristics of the loop filter 908 and the loop bandwidth, the actual capture range can be smaller than this maximum value. The frequency step size of the DCO 910 can be smaller than the capture range of the sub-sampling digital relay type PLL 902.

[0077] In the third embodiment, the system implements a dead zone smaller than the capture range of the sub-sampling digital relay PLL 902, which automatically takes over control and stabilizes in phase detector control mode in the absence of additional input from the controller 922.

[0078] When the phase detector control mode is active, the FLL loop state can be frozen. However, in some embodiments, the FLL loop can still monitor the frequency of signal 926 to detect other harmonics that might switch the loop to the reference clock signal 924 or interference that could cause the sub-sampled ADPLL to unlock. Measurements used to monitor the frequency of signal 926 can occur in parallel with or continuously with the phase detector control mode, at intervals determined based on the error detection time requested by the system, or at other time intervals. If the frequency difference... If the threshold or dead zone is exceeded, the FLL904 is reactivated by switching to FLL control mode and providing a control signal to the DCO 910 until the system returns to lockout. For example, the FLL 904 can be reactivated in response to severe interference in the loop caused by undervoltage and in response to changes in the FCW 928.

[0079] Some embodiments of subsampled digital relay PLLs described herein avoid, reduce, or eliminate phase noise contributions from entities such as charge pumps or analog loop filters present in conventional subsampled or sampled PLLs. Subsampled digital relay PLLs receive noise contributions from DCO quantization and quantization noise from relay-type phase detectors. Some embodiments of the DCO are configured to reduce DCO quantization noise to a negligible level, for example, using noise shaping via ΔΣ modulation. Relay-type quantization noise is dominated by reference phase noise, which is typically on the same order of magnitude as the reference phase clock noise and may have a marginal impact on in-band phase noise. If the phase noise of the reference clock is improved, the in-band phase noise will be improved accordingly. Under comparable conditions, the in-band phase noise level achievable using subsampled digital relay PLLs is lower than that of conventional subsampled PLLs.

[0080] In some embodiments, the delay of the subsampled digital relay PLL can be kept small because there is no delay in the feedback path and the feedforward path delay can be maintained at a negligible level. The effects of sampling along the direct path including the relay phase detector can be controlled to maintain the alignment of the DCO updates and avoid glitches.

[0081] Figure 10 A circuit 1000 for performing loop updates is shown according to some embodiments. The circuit 1000 is implemented in a sub-sampling PLL 1002, for example... Figure 1 The sub-sampling PLL 102 shown is Figure 9 Some embodiments of the sub-sampling digital relay type PLL902 shown are illustrated.

[0082] The subsampling PLL 1002 includes a phase detector 1004, a loop filter 1006, and a DCO 1008, which operate as described herein. The phase detector 1004 receives a reference clock signal 1010, and the DCO 1008 generates an output signal 1012. The circuit 1000 also includes a set of flip-flops 1014, 1015, and 1016, collectively referred to herein as "flip-flops 1014-1016". The reference clock signal 1010 is provided as an input to flip-flops 1014, and the output signal 1012 is used as an update signal for flip-flops 1014-1016. On each cycle of the output signal 1012, the value stored in flip-flop 1014 is copied to flip-flop 1015, and the value stored in flip-flop 1015 is copied to flip-flop 1016. The outputs of flip-flops 1015 and 1016 are inversely proportional to each other and provided to an AND gate 1018. The value generated by AND gate 1018 is provided to register 1020, which receives an enable or activation signal from output signal 1012. In some embodiments, AND gate 1018 is used for rising or falling edge detection.

[0083] In the illustrated embodiment, loop filter 1006 is configured to reduce or eliminate delay. In this case, the amount of delay introduced by DCO 1008 depends on the propagation delay in the feedforward path, including the setup time (plus margin) for updating register 1020 of DCO 1008. An update pulse can be derived from the reference clock signal 1010 using a clock derived from DCO 1008 via rising edge detection. This can be the DCO clock itself or a divided clock. Depending on the ratio of the frequency of signal 1012 generated by DCO 1008 to the frequency of the reference clock signal 1010, the effective delay can be maintained as a fraction of the reference period, such that the delay does not affect the overall loop characteristics. Flip-flops 1014 and 1015 are included before the rising edge detection performed at AND gate 1018 to avoid metastability.

[0084] The illustrated embodiment of the subsampled PLL 1002 does not include a frequency divider in the feedback path. However, in some embodiments, if the output clock needs to be phase-aligned with the reference clock signal 1010, one or more frequency dividers may be implemented in the feedback path. If the divided DCO frequency is higher than the frequency of the reference clock signal 1010, the resulting system will have the characteristics of a subsampled digital relay PLL. The frequency divider effectively reduces the DCO gain in the loop. In some embodiments, if the resulting frequency tuning range of the divided signal is smaller than... In this case, an FLL may not be needed to lock onto the subsampled BB-ADPLL. However, an FLL may be necessary to speed up the locking process. If the divider's output frequency is comparable to the frequency of the reference clock signal 1010, the system approximates a sampled digital relay PLL, the difference being that in a subsampled digital relay PLL, the reference clock samples the divider signal, while a sampled digital relay PLL uses the divided signal to sample the reference clock. Similar or identical performance can be expected.

[0085] It should be noted that not all of the activities or elements described in the general description above are necessary; a particular activity or device may not be required as a part; and one or more additional activities or elements may be performed in addition to those described. Furthermore, the listed order of activities is not necessarily the order in which they are performed. Additionally, concepts have been described with reference to specific embodiments. However, those skilled in the art will understand that various modifications and changes can be made without departing from the scope of this disclosure as set forth in the appended claims. Therefore, the specification and drawings should be viewed in an illustrative rather than restrictive sense, and all such modifications are contemplated to be included within the scope of this disclosure.

[0086] The foregoing description of specific embodiments has described benefits, other advantages, and solutions to the problem. However, these benefits, advantages, solutions to the problem, and any features that may bring any benefit, advantage, or solution to the forefront or make more prominent should not be construed as key, necessary, or essential features of any or all claims. Furthermore, the embodiments disclosed above are illustrative only, as the disclosed subject matter can be modified and practiced in different but equivalent ways that will be apparent to those skilled in the art benefiting from the teachings herein. No limitation is intended to be made on the details of the constructions or designs shown herein other than those described in the appended claims. Therefore, it will be apparent that the embodiments disclosed above may be altered or modified, and all such changes are considered to be within the scope of the disclosed subject matter. Therefore, the protection sought herein is set forth in the appended claims.

Claims

1. A device, characterized in that, The device includes: A digitally controlled oscillator (DCO), the DCO being configured to generate a first signal having a phase based on a second signal provided to the DCO; A digital phase detector configured to generate a third signal representing a phase offset between a reference clock signal and the first signal; and A digital filter configured to generate the second signal by filtering out spectral components from the third signal.

2. The device according to claim 1, characterized in that, The digital phase detector is configured to generate a third signal representing a fixed positive value in response to the first signal generated by the DCO representing a value greater than zero, and wherein the digital phase detector is configured to generate the third signal representing a fixed negative value in response to the first signal generated by the DCO representing a value less than zero.

3. The device according to claim 2, characterized in that, The digital phase detector is configured to receive the first signal as an output from the DCO.

4. The device according to claim 1, characterized in that, The device further includes: A frequency-locked loop (FLL), connected to the DCO and configured to generate a fourth signal representing the difference between the reference frequency of the harmonics of the reference clock signal and the output frequency of the first signal generated by the DCO, and The DCO is configured to modify the output frequency of the first signal based on the fourth signal.

5. A method, characterized in that, The method includes: A first signal with a phase based on a second signal provided to the DCO is generated at the digitally controlled oscillator (DCO); A third signal representing the phase offset between the reference clock signal and the first signal is generated at the digital phase detector; and The second signal is generated at the digital filter by filtering out the spectral components of the third signal.

6. The method according to claim 5, characterized in that, The method further includes: The first signal is received at the digital phase detector as an output from the DCO.

7. The method according to claim 5, characterized in that, The method further includes: A fourth signal is generated at the frequency-locked loop (FLL) connected to the DCO, the fourth signal representing the difference between the reference frequency of the harmonic of the reference clock frequency and the output frequency of the first signal generated by the DCO; and The output frequency of the first signal is modified at the DCO based on the fourth signal.

8. The method according to claim 7, characterized in that, The method further includes: The FLL and DCO are used to maintain the output frequency of the first signal within the capture range of the reference frequency.

9. A sub-sampling phase-locked loop (PLL), characterized in that, The sub-sampling PLL includes: A digitally controlled oscillator (DCO) configured to generate a first signal having a phase determined based on a second signal provided to the DCO; A quantizer configured to generate a third signal, the third signal representing a value of +1 in response to a sampled value of the first signal having a value greater than zero and representing a value of -1 in response to a sampled value of the first signal having a value less than zero; and A loop filter configured to generate the second signal in response to receiving the third signal from the quantizer, wherein the loop filter is a low-pass filter.

10. The sub-sampling PLL according to claim 9, characterized in that, The sub-sampling PLL further includes: A frequency-locked loop (FLL) is configured to provide a fourth signal to the DCO, wherein the fourth signal represents the difference between the reference frequency of a harmonic of a reference clock signal and the output frequency of the first signal generated by the DCO. The DCO is configured to modify the output frequency of the first signal based on the fourth signal, such that the output frequency remains within the capture range of the reference frequency of the harmonics of the reference clock signal.

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