Double-edge sampling circuit, sampling method, integrated circuit chip and electronic device

Abstract

The application relates to a double-edge sampling circuit, a sampling method, an integrated circuit chip and an electronic device. The circuit comprises a first D flip-flop, an XOR gate and a second D flip-flop; a first input end of the XOR gate is connected to an original clock signal, a second input end is connected to an output end of the first D flip-flop, and output ends are respectively connected to a clock end of the first D flip-flop and a clock end of the second D flip-flop; a data input end of the second D flip-flop is used for receiving a to-be-sampled data signal, and an output end outputs a sampling result. The circuit structure is simple, only standard logic units are needed, the whole process works in a single clock domain, cross-clock-domain synchronization processing is not needed, the sub-stable state risk is effectively eliminated, and the data sampling efficiency and system timing reliability are significantly improved.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and in particular to a dual-edge sampling circuit, a sampling method, an integrated circuit chip, and an electronic device. Background Technology

[0002] With the rapid development of digital communication technology and the continuous improvement of data transmission rates, traditional single-edge sampling methods are no longer sufficient to meet the demands of high-speed data transmission. In high-speed interface designs, such as DDR memory interfaces and high-speed serial communication, it is often necessary to sample data on both the rising and falling edges of the clock signal to improve data throughput.

[0003] Currently, there are two common methods for implementing dual-edge sampling: one is to use two independent clock domains to sample at the rising and falling edges respectively, but this method requires synchronization across clock domains, which increases design complexity and may introduce metastability risks; the other is to use a dedicated dual-edge sampling circuit, but existing dual-edge sampling circuits usually require additional logic circuits or complex clock generation mechanisms, resulting in increased circuit area and power consumption. Summary of the Invention

[0004] Therefore, it is necessary to provide a dual-edge sampling circuit, sampling method, integrated circuit chip, and electronic device to address the above-mentioned technical problems. This device can achieve dual-edge data sampling within a single clock domain without the need for cross-clock domain synchronization, and features a simple structure and stable timing.

[0005] A dual-edge sampling circuit includes a first D flip-flop, an XOR gate, and a second D flip-flop;

[0006] The first input of the XOR gate is connected to the original clock signal, and the second input is connected to the output of the first D flip-flop. The output of the XOR gate is connected to the clock terminals of the first D flip-flop and the second D flip-flop, respectively. The data input terminal of the second D flip-flop is used to receive the data signal to be sampled, and the output terminal outputs the sampling result; The XOR gate generates a sampling clock signal that produces a valid transition on both the rising and falling edges of the original clock signal based on the logical XOR operation between the original clock signal and the output signal of the first D flip-flop, thereby driving the second D flip-flop to sample the data signal to be sampled on both edges of the original clock signal.

[0007] In one embodiment, both the first D flip-flop and the second D flip-flop are rising-edge triggered D flip-flops.

[0008] In one embodiment, the sampling clock signal generates effective transition pulses at the rising and falling edges of the original clock signal, and the pulse width satisfies the setup and hold time requirements of the second D flip-flop.

[0009] In one embodiment, the inverted output of the first D flip-flop is connected to the data input of the first D flip-flop, so that the output signal of the first D flip-flop has a propagation delay of a single flip-flop relative to the original clock signal.

[0010] A dual-edge sampling method, characterized in that it further includes: The original clock signal is input to the first input terminal of the XOR gate; The output signal of the first D flip-flop is fed back to the second input of the XOR gate; The original clock signal and the output signal of the first D flip-flop are XORed by the XOR gate to generate a sampling clock signal. The sampling clock signal is provided to the clock terminals of the first D flip-flop and the second D flip-flop; The second D flip-flop is controlled to sample the data signal to be sampled at the rising and falling edges of the original clock signal according to the sampling clock signal.

[0011] This application also provides an integrated circuit chip that integrates the above-mentioned dual-edge sampling circuit.

[0012] This application also provides an electronic device, including a main control unit, a storage unit, and the aforementioned dual-edge sampling circuit, disposed between the main control unit and the storage unit.

[0013] The aforementioned dual-edge sampling circuit, sampling method, integrated circuit chip, and electronic equipment utilize the output feedback of the first D flip-flop to compare the original clock signal in real time with the XOR gate. Leveraging the inherent propagation delay characteristic of a single-stage D flip-flop, precise sampling pulses are generated on both the rising and falling edges of the clock, directly driving the second D flip-flop to complete dual-edge data capture. The entire circuit operates strictly within a single synchronous clock domain, completely avoiding cross-clock domain synchronization links, eliminating metastability risks at the source, and significantly improving timing reliability and system stability in high-speed scenarios. At the same time, only one XOR gate and two D flip-flops from the standard cell library are needed to achieve the complete function. The structure is simple and compact, requiring no special processes or customized modules, effectively saving chip area and static power consumption, and the sampling timing relationship is clear and explicit. Attached Figure Description

[0014] Figure 1 This is a block diagram of a dual-edge sampling circuit in one embodiment; Figure 2This is a pulse timing diagram of a dual-edge sampling circuit in one embodiment; Figure 3 This is a circuit diagram of a dual-edge sampling circuit in one embodiment. Detailed Implementation

[0015] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0016] The dual-edge sampling circuit provided in this application, such as Figure 1 As shown, it includes a first D flip-flop 101, an XOR gate 102, and a second D flip-flop 103. Wherein: The first input terminal of the XOR gate 102 is connected to the original clock signal terminal CLK, and the second input terminal of the XOR gate 102 is connected to the output terminal Q of the first D flip-flop 101. The output terminal OUT of the XOR gate 102 is connected to the clock terminal CLK of the first D flip-flop 101 and the clock terminal CLK of the second D flip-flop 103. The data input terminal D of the second D flip-flop 103 is used to receive the data signal DATA to be sampled, and the output terminal Q outputs the sampling result.

[0017] The working principle of this dual-edge sampling circuit is as follows: XOR gate 102 generates a sampling clock signal that produces a valid transition on both the rising and falling edges of the original clock signal based on the logical XOR operation between the original clock signal CLK and the output signal Q of the first D flip-flop 101. This sampling clock signal drives the second D flip-flop 103 to sample the data signal DATA on both the rising and falling edges of the original clock signal, thereby realizing dual-edge sampling.

[0018] In this embodiment, the core of the dual-edge sampling circuit lies in generating a dual-edge sampling clock signal through the feedback structure of an XOR gate. Specifically, the original clock signal CLK is first input to the first input terminal of the XOR gate 102, while the output signal Q of the first D flip-flop 101 is fed back to the second input terminal of the XOR gate 102. Since the clock terminal of the first D flip-flop 101 is connected to the output terminal of the XOR gate 102, the output signal Q of the first D flip-flop 101 has a propagation delay of one D flip-flop relative to the original clock signal CLK.

[0019] When the original clock signal CLK transitions, due to the delay in the output signal Q of the first D flip-flop 101, the input signal of the XOR gate 102 changes, resulting in a valid transition on both the rising and falling edges of CLK. The specific timing is as follows... Figure 2 As shown: At the rising edge of CLK, the output signal Q of the first D flip-flop 101 has not yet changed and remains at a low level, while the output signal OUT of the XOR gate 102 changes from a low level to a high level. At the falling edge of CLK, the output signal Q of the first D flip-flop 101 has jumped to a high level, and the output signal OUT of the XOR gate 102 has jumped from a high level to a low level.

[0020] Thus, the output signal OUT of the XOR gate 102 generates a valid transition on both the rising and falling edges of CLK, forming a clock signal for dual-edge sampling. This clock signal drives the second D flip-flop 103 to sample the data signal DATA on both the rising and falling edges of CLK, thereby achieving dual-edge sampling.

[0021] In one embodiment, both the first D flip-flop 101 and the second D flip-flop 103 are rising-edge triggered D flip-flops.

[0022] In this embodiment, both the first D flip-flop 101 and the second D flip-flop 103 are rising-edge triggered D flip-flops. Figure 1 As shown, when the output signal OUT of the XOR gate 102 changes on the rising edge of CLK, both the first D flip-flop 101 and the second D flip-flop 103 will respond to the rising edge trigger, realizing data sampling. By using rising edge triggered D flip-flops, it can be ensured that data can be sampled stably on both the rising and falling edges of the clock signal.

[0023] In one embodiment, the sampling clock signal generates effective transition pulses at the rising and falling edges of the original clock signal, and the pulse width meets the setup and hold time requirements of the second D flip-flop.

[0024] In this embodiment, the output signal OUT of the XOR gate 102 generates valid transition pulses at the rising and falling edges of CLK. The pulse width is determined by the propagation delay of the first D flip-flop 101, typically about half a clock cycle. This pulse width must meet the setup and hold time requirements of the second D flip-flop 103 to ensure the correctness of data sampling. For example, when the CLK period is 10ns, the pulse width is approximately 5ns, satisfying the typical setup time t_setup = 0.5ns and hold time t_hold = 0.3ns requirements of a D flip-flop.

[0025] In one embodiment, the inverted output of the first D flip-flop is connected to the data input of the first D flip-flop, so that the output signal of the first D flip-flop has a propagation delay of a single flip-flop relative to the original clock signal.

[0026] In this embodiment, the inverting output Q' of the first D flip-flop 101 is connected to the data input D of the first D flip-flop 101, forming a simple oscillation structure. This connection method allows the output signal Q of the first D flip-flop 101 to have a propagation delay of one D flip-flop relative to the original clock signal CLK, providing the necessary timing difference for the XOR gate 102, thereby generating effective transitions on both the rising and falling edges of CLK.

[0027] In one embodiment, the entire circuit operates within a single synchronous clock domain, eliminating the need for cross-clock domain synchronization. In this embodiment, the entire dual-edge sampling circuit operates within a single CLK clock domain, with all circuit components using the same clock signal CLK. This design avoids the complexity of cross-clock domain synchronization, reduces design difficulty and metastability risks, while simultaneously improving the reliability and stability of data sampling.

[0028] In one embodiment, a specific circuit diagram of a dual-edge sampling circuit is provided. The core of this circuit consists of an XOR gate, a first D flip-flop DFF1, and a second D flip-flop DFF2. Figure 3 The schematic diagram of the specific circuit implementation shows the signal connections as follows: Input signal terminals: trigger signal terminal START_VAL, delay control signal terminal DELAY, pulse width reference signal terminal OFFTIME; Reset mechanism: The reset terminals RST_N of the first D flip-flop DFF1 and the second D flip-flop DFF2 are connected to the low-level active reset signal terminal RST_N; Key links: The first input of the XOR gate is connected to the output Q of the first D flip-flop DFF1, and the second input is connected to the original clock signal CLK_org. The output of the XOR gate is connected to the clock input CLK_out of the first D flip-flop DFF1 and the second D flip-flop DFF2; The data input terminal D of the first D flip-flop DFF1 is connected to its inverting output terminal. ; DELAY and OFFTIME are connected to the feedback path via a logic combination unit, and work together with the output signal of the first D flip-flop DFF1.

[0029] The work process is described as follows: Initial state: When the reset signal RST_N is valid, the outputs Q of DFF1 and DFF2 are both low, and the XOR gate output is low; Triggering phase: After RST_N is released, when START_VAL has a rising edge, it is synchronously sampled by DFF1, and its output Q jumps to a high level, causing the signals at the two input terminals of the XOR gate to be different, outputting a high-level pulse, triggering DFF1 output Q to jump to a high level; Pulse width maintenance phase: The high level output of DFF1, through the feedback loop, works together with DELAY and OFFTIME through the logic combination unit to maintain the high level output of the XOR gate, so that the sampling clock signal remains high; the pulse width is precisely set by the logic relationship between DELAY and OFFTIME. End phase: After the preset pulse width time is reached, the feedback signal changes, causing the XOR gate output to jump to a low level, the DFF1 output Q to be reset to a low level, and the sampling clock signal ends.

[0030] In one embodiment, a dual-edge sampling method is provided, comprising: simultaneously inputting an original clock signal to the clock terminal of a first D flip-flop and the first input terminal of an XOR gate; using the first D flip-flop to latch a fixed level at the edge of the original clock signal to generate a feedback signal with a clock period delay; performing an XOR operation on the original clock signal and the feedback signal by the XOR gate to generate a dual-edge valid sampling clock; and controlling a second D flip-flop to latch the data signal to be sampled at the rising and falling edges of the original clock signal according to the dual-edge valid sampling clock.

[0031] The specific steps of the dual-edge sampling method are as follows: The original clock signal CLK is simultaneously input to the clock terminal CLK of the first D flip-flop 101 and the first input terminal of the XOR gate 102; The first D flip-flop 101 latches a fixed level at the CLK edge, generating a feedback signal Q with a clock cycle delay; XOR gate 102 performs an XOR operation on CLK and Q to generate a dual-edge valid sampling clock signal OUT. The second D flip-flop 103 latches the data signal to be sampled DATA on the rising and falling edges of CLK according to the sampling clock signal OUT, thereby realizing dual-edge sampling.

[0032] In one embodiment, an integrated circuit chip is provided, which integrates the above-described dual-edge sampling circuit.

[0033] In this embodiment, the dual-edge sampling circuit is integrated into the I / O interface module of the integrated circuit chip. This integrated circuit chip can be a processor, a memory controller, or a communication chip, where the dual-edge sampling circuit is used to process high-speed data input. For example, in a DDR memory controller, the dual-edge sampling circuit is used to implement dual-edge sampling when reading data, thereby improving the data transfer rate.

[0034] In one embodiment, an electronic device is provided, including a main control unit, a storage unit, and a dual-edge sampling circuit as described above, disposed between the main control unit and the storage unit.

[0035] In this embodiment, the electronic device includes a main control unit, a storage unit, and a dual-edge sampling circuit. The dual-edge sampling circuit is located on the data path between the main control unit and the storage unit, and is used to perform dual-edge sampling on the data read from the storage unit. For example, in smartphones or servers, the dual-edge sampling circuit can improve the data read speed of the memory controller, thereby improving the overall system performance.

[0036] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0037] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A dual-edge sampling circuit, characterized in that, Includes a first D flip-flop, an XOR gate, and a second D flip-flop; The first input of the XOR gate is connected to the original clock signal, and the second input is connected to the output of the first D flip-flop. The output of the XOR gate is connected to the clock terminals of the first D flip-flop and the second D flip-flop, respectively. The data input terminal of the second D flip-flop is used to receive the data signal to be sampled, and the output terminal outputs the sampling result; The XOR gate generates a sampling clock signal that produces a valid transition on both the rising and falling edges of the original clock signal based on the logical XOR operation between the original clock signal and the output signal of the first D flip-flop, thereby driving the second D flip-flop to sample the data signal to be sampled on both edges of the original clock signal.

2. The dual-edge sampling circuit according to claim 1, characterized in that, Both the first D flip-flop and the second D flip-flop are rising-edge triggered D flip-flops.

3. The dual-edge sampling circuit according to claim 1, characterized in that, The sampling clock signal generates effective transition pulses at the rising and falling edges of the original clock signal, and the pulse width meets the setup and hold time requirements of the second D flip-flop.

4. The dual-edge sampling circuit according to claim 1, characterized in that, The inverting output of the first D flip-flop is connected to the data input of the first D flip-flop, so that the output signal of the first D flip-flop has a propagation delay of a single flip-flop relative to the original clock signal.

5. A dual-edge sampling method, characterized in that, Also includes: The original clock signal is input to the first input terminal of the XOR gate; The output signal of the first D flip-flop is fed back to the second input of the XOR gate; The original clock signal and the output signal of the first D flip-flop are XORed by the XOR gate to generate a sampling clock signal. The sampling clock signal is provided to the clock terminals of the first D flip-flop and the second D flip-flop; The second D flip-flop is controlled to sample the data signal to be sampled at the rising and falling edges of the original clock signal according to the sampling clock signal.

6. An integrated circuit chip, characterized in that, It integrates a dual-edge sampling circuit as described in any one of claims 1 to 4.

7. An electronic device, characterized in that, include: Main control unit; Storage unit; And a dual-edge sampling circuit as described in any one of claims 1 to 4, disposed between the main control unit and the storage unit.

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