Low-density parity-check code decoding method based on graph neural network

Abstract

The application provides a low-density parity-check code decoding method and device based on a graph neural network, which comprises the following steps: step 1, constructing a factor graph comprising variable nodes, check nodes and edge relationships, and mapping log-likelihood ratio information of a received signal to initial embedding of the variable nodes; step 2, generating message features according to node embedding, node degree and iteration step length, and constructing attention weights for each edge to measure the importance of the message; step 3, inputting the message features and the attention weights into a gated recurrent unit to update the residual of the edge weight, and feeding back the updated edge weight to the graph structure; step 4, weighting and aggregating the messages from the adjacent nodes according to the edge weight, calculating the updated embedding of the variable nodes and the check nodes, and performing gated modulation combined with the check result; step 5, repeating steps 2 to 4 until a preset iteration number or a decoding convergence condition is reached, and mapping the final variable node embedding to a decoding result to realize LDPC code word recovery. By introducing the attention mechanism and the gated residual update into the message passing process, the application realizes adaptive modeling of the contribution degree of different edge messages, dynamically remembers the historical state, thereby improving the decoding performance and the convergence speed; meanwhile, the application can effectively reduce the bit error rate and is suitable for high-speed reliable data transmission scenarios in a 5G / 6G wireless communication system.

Description

Technical Field

[0001] This invention relates to the field of communication and signal processing, and in particular to a low-density parity-check code decoding method and apparatus based on graph neural networks. Background Technology

[0002] Low-density parity-check (LDPC) codes are a widely used error-correcting coding technique in modern communication systems, capable of reducing the bit error rate through iterative decoding. Traditional LDPC decoding methods are typically based on the Belief Propagation (BP) algorithm, which decodes by iteratively passing probability information between variable nodes and parity nodes. In the BP algorithm, the message passing process is highly dependent on the factor graph structure, and the computational overhead increases exponentially with the code length.

[0003] Existing backpropagation (BP) decoding methods suffer from several problems. Firstly, under conditions of short code lengths or high-noise channels, BP decoding is prone to error flooring, significantly reducing decoding performance. Secondly, BP decoding typically employs fixed message update rules, making it difficult to adaptively adjust the information contribution of different edges, resulting in slow convergence and numerous iterations. Furthermore, traditional methods underutilize statistical information such as factor graph structural features and node degree distribution, impacting decoding efficiency and performance.

[0004] In recent years, some studies have attempted to apply deep learning methods to LDPC decoding, simulating the message passing process by training neural networks. However, existing methods still face problems such as unstable model training, insufficient structural expressive power, and complex hardware implementation; at the same time, performance degradation is common in high-noise scenarios and dynamic channel environments. Summary of the Invention

[0005] The purpose of this invention is to address the problems of high error rate, slow convergence speed and lack of adaptive capability in existing low-density parity check code decoding methods under high noise conditions, and to provide a low-density parity check code decoding method and apparatus based on graph neural networks, so as to improve decoding accuracy and reduce computational complexity.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] A low-density parity-check code decoding method based on graph neural networks, comprising:

[0008] Step S1: Construct a factor graph representing the LDPC code structure, model the variable nodes, check nodes and edge relationships, and map the log-likelihood ratio of the received signal to the initial embedding of the variable nodes.

[0009] Step S2: Generate message features based on node embedding, node degree, and iteration step size, and construct attention weights for each edge to measure the importance of different messages;

[0010] Step S3: Input the message features and attention weights into the gated recurrent unit, perform residual update of the edge weights, and feed the updated edge weights back to the factor graph;

[0011] Step S4: Perform weighted aggregation of adjacent node messages according to edge weights, update the embedding of variable nodes and verification nodes, and perform gated modulation based on the verification results;

[0012] Step S5: Repeat steps S2-S4 until the preset number of iterations or decoding convergence conditions are reached, and output the symbol decision result of the variable node embedding and the combined edge weight.

[0013] Furthermore, the initial embedding of variable nodes in step S1 From the log-likelihood ratio Generates through learnable linear or nonlinear mappings.

[0014] Furthermore, in step S2, the iteration step size is represented by a positional encoding, which is a sine / cosine function or a learnable embedding.

[0015] Furthermore, in step S2, the attention weights are determined using dot product attention, a learnable matching function, or a softmax normalization strategy.

[0016] Furthermore, the residual update of the edge weights in step S3 specifically includes: mapping the edge state to candidate edge weights through a learnable mapping. And by using an activation function to restrict the value to A residual fusion strategy is adopted to perform residual fusion between the candidate edge weights and the edge weights of the previous iteration to obtain the updated edge weights. .

[0017] 1. The low-density parity-check code decoding method according to claim 5, characterized in that the activation function is a function, and the updated edge weights The is:

[0018] ;

[0019] ;

[0020] ;

[0021] in, For MLP functions, The Sigmoid activation function is used. The output of the gated loop unit represents the internal state of the edge. Control the ratio of historical data to candidate values ​​in the fusion process. is the input vector of the gating unit. For gate function mapping

[0022] Furthermore, step S4 uses weighted sum, weighted average, maximum or minimum value form, combined with residual connection and normalization operations, to perform weighted aggregation of adjacent node messages.

[0023] Furthermore, the embedded representation of the updated variable node and the check node in step S4 is as follows:

[0024] ;

[0025] in, For historical residuals; For learnable mapping functions, It is a gated modulation signal.

[0026] Furthermore, the gated modulation signal for:

[0027] ;

[0028] in, The result of the current iteration verification. This is a gated function.

[0029] A low-density parity-check code decoding device based on graph neural networks, comprising:

[0030] The graph construction module is used to construct a factor graph representing the LDPC code structure, modeling variable nodes, check nodes and edge relationships, and mapping the log-likelihood ratio of the received signal to the initial embedding of the variable nodes.

[0031] The message generation module and attention calculation module generate message features based on node embedding, node degree and iteration step size, and construct attention weights for each edge to measure the importance of different messages.

[0032] The edge weight update module is used to input message features and attention weights into the gated loop unit, perform residual updates of edge weights, and feed the updated edge weights back to the factor graph.

[0033] The aggregation update module and the gating modulation module perform weighted aggregation of adjacent node messages according to edge weights, update the embedding of variable nodes and verification nodes, and perform gating modulation based on the verification results.

[0034] The output module is used to output the final symbol decision results and edge weights of the embedded variable nodes.

[0035] Compared with existing technologies, the beneficial effects of this invention are as follows: By introducing an attention mechanism and gated residual update into the message passing process, this invention achieves adaptive modeling of the contribution of different side messages and dynamically memorizes historical states, thereby improving decoding performance and convergence speed. Regarding the code length and code rate used for model training, under different channel conditions, the model described in this invention can reduce the bit error rate by 8%-13% compared to traditional LDPC decoders during the decoding process. Simultaneously, this model has good generalization ability; for two different codeword cases—one with the same code rate but different code lengths and the other with the same code length but different code rates—this model can still effectively reduce the bit error rate by 5%-12% under different channel conditions. This invention can effectively reduce the bit error rate and is suitable for high-speed and reliable data transmission scenarios in 5G / 6G wireless communication systems. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a flowchart illustrating the low-density parity check code decoding method based on graph neural networks according to the present invention.

[0038] Figure 2 This is a flowchart of step S2 provided in an embodiment of the present invention.

[0039] Figure 3 The bit error rate simulation curves of the low-density parity-check code decoding method based on graph neural networks provided in the embodiments of this application under the same code rate but different code length conditions.

[0040] Figure 4 The simulation curves of the bit error rate of the low-density parity-check code decoding method based on graph neural networks provided in the embodiments of this application under the same code length but different code rates. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to its embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the scope of protection of the invention.

[0042] Combination Figure 1 This invention provides a low-density parity-check (LDPC) decoding method based on graph neural networks, comprising:

[0043] Step S1: Construct a factor graph representing the LDPC code structure, modeling variable nodes, check nodes, and edge relationships, and mapping the log-likelihood ratio of the received signal to the initial embedding of the variable nodes; specifically including:

[0044] (1) Constructing the factor graph and initializing the embedding: Based on the verification matrix Construct a bipartite graph , where the set of variable nodes , Verification node set edge set , will receive signal Convert to log-likelihood ratio (LLR):

[0045]

[0046] in, To receive a given signal Under the condition of, the bits sent The probability is 1. To receive a given signal Under the condition of, the bits sent The probability that it is 0.

[0047] (2) Map LLR to the initial embedding of variable nodes Initial embedding of variable nodes From the log-likelihood ratio Generated through learnable linear or nonlinear mappings:

[0048]

[0049] (3) The initial values ​​of the edge weights in the factor graph can be set as fixed constants or generated based on coarse estimates. By default, they are fixed as constant 1.

[0050] (4) Based on the verification matrix Construct a bipartite graph , where the set of variable nodes , Verification node set edge set .

[0051] Step S2: Generate message features based on node embedding, node degree, and iteration step size, and construct attention weights for each edge to measure the importance of different messages. The iteration step size is represented by positional encoding, which is a sine / cosine function or a learnable embedding. The attention weights are calculated using dot product attention, a learnable matching function, or a softmax normalization strategy. Figure 2 Specifically, it includes:

[0052] (1) Constructing node message features: For any variable node or verification node, its embedding vector can be represented as The degree of a node can be expressed as The iteration step size can be expressed as This invention combines the above-mentioned information to form a node feature description vector to obtain the message representation that the node needs to propagate in the current iteration. This combination method can be a linear combination, a nonlinear combination, or a learnable mapping method, as shown below:

[0053]

[0054] in, Embedding for variable nodes, For node degree, The iteration step size, It can be a multilayer perceptron (MLP) or a linear mapping, used to extract latent structural semantics and dynamic feature information.

[0055] (2) Constructing edge attention weights: Attention weights measure the contribution of an edge to information transmission and are used for edge weight updates. For any edge... This invention constructs edge features based on the message representations of two nodes connected by an edge, and further calculates the corresponding attention weight for each edge through an attention mechanism to reflect the contribution of that edge to the state update of the target node in the current iteration. The attention allocation strategy can employ a matching function, a dot product function, or a normalization strategy, and its general form can be expressed as:

[0056]

[0057] in, For the node message characteristics of nodes i and j, This is the attention weight generation function, used to measure the node weights. With nodes The relevance and importance of information transmission between them.

[0058] To improve the comparability between different edges, this invention normalizes the generated attention weights so that the sum of the weights of all edges in the neighborhood of a node is 1, thereby implementing a weighted competition mechanism between edges. Its general form can be expressed as:

[0059]

[0060] in Represents nodes The set of adjacent nodes, It is a normalized exponential function.

[0061] Step S3: Input the message features and attention weights into the gated recurrent unit, perform residual updates of the edge weights, and feed the updated edge weights back to the factor graph.

[0062] Step S3 updates the internal state of the edges using a gated recurrent unit (GRU) over time. This ensures that the edge weights not only depend on the current message and attention information but also retain historical residual information from previous iterations, thereby achieving dynamic memory and stable control of the iteration process. The updated edge weights can be used as short-term weighting coefficients in this node update or as long-term memory for reference in subsequent iterations.

[0063] (1) Construct the input vector of the gated unit The message features are concatenated with attention weights and optional edge residual information.

[0064]

[0065] in For node status, As a historical residue, For node degree, For iteration step size embedding, function For learnable nonlinear mappings

[0066] (2) Concatenate message features with attention weights to form the gating unit input:

[0067]

[0068] (2) GRU is a parameterized gating unit responsible for fusing the current input with the historical state and outputting the new edge internal state. :

[0069]

[0070] in, This represents the internal state of the edge in the previous round.

[0071] (3) Mapping edge states to candidate edge weights through learnable mapping And the value range is guaranteed by using an activation function, such as using sigmoid to limit the value to a certain range. :

[0072]

[0073] in, The candidate edge weights, For MLP output functions, This is the activation function.

[0074] (4) Adopt the residual fusion strategy to perform residual fusion of candidate edge weights with the edge weights of the previous iteration to obtain the final edge weights. :

[0075]

[0076]

[0077] in, For the final edge weight, For gate function mapping, The ratio of historical data to candidate values ​​is controlled and integrated.

[0078] Step S4: Perform weighted aggregation of neighboring node messages based on edge weights, update the embeddings of variable nodes and verification nodes, and perform gated modulation based on the verification results. The node message aggregation operation uses weighted sums, weighted averages, maximum values, or minimum values, and can be combined with residual connections and normalization operations. The gated modulation signal is calculated from the node neighborhood verification results and is used to suppress the propagation of error messages and enhance correct information. Specifically, it includes:

[0079] (1) Perform weighted message aggregation on variable nodes or verification nodes:

[0080]

[0081]

[0082] in, For variable node information, To verify node information, For edge weights, For messages passed between nodes.

[0083] (2) Based on the aggregation results, the node embedding is updated:

[0084]

[0085] in, For historical residuals; For a learnable mapping function, MLP, residual network, or lightweight GNN layers can be used; This is a gated modulation signal, calculated from the current verification result, which can be used to suppress error messages or enhance reliable messages, and is represented as:

[0086]

[0087] in The result of the current iteration verification. It is a gated function (such as Sigmoid or tanh).

[0088] Step S5: Repeat the above message generation, edge weight update and node update operations until the preset number of iterations or decoding convergence conditions are reached, and output the decision and edge weight combination.

[0089] For each variable node According to the final embedding Generate decision probability or log-likelihood ratio (LLR):

[0090]

[0091] in, It can be a learnable mapping function or a linear mapping, and can output a scalar value representing the decoding probability.

[0092] Judgment symbol generation:

[0093]

[0094] in, For log-likelihood ratio information, This is the final decision codeword. Through this mapping, continuous embedded states are converted into discrete bits, achieving the actual decoding output.

[0095] The main purpose of step S5 is to map the node embedding states obtained by the iterative graph neural network into actual output decoding bits, and to effectively fuse the coarse and fine edge weights to make full use of prior estimation and iterative optimization information, thereby improving decoding accuracy and reliability.

[0096] Step S5 achieves the fusion of the final output of iterative decoding and edge weights through node embedding mapping, edge weight combination, and gating decision, organically combining coarse estimation information with iterative optimization information, improving the accuracy and stability of LDPC decoding, and taking into account both convergence speed and hardware implementation feasibility.

[0097] To verify the performance of the LDPC decoding model proposed in this invention, simulation tests were conducted under different channel conditions and codeword characteristics. The simulation results are shown in the figure below. Figures 3-4 . Figures 3-4 This indicates that, for the code length and code rate used for model training, the model described in this invention can reduce the bit error rate by 8%-13% during the decoding process under different channel conditions. Furthermore, this model exhibits good generalization ability; for two different codeword scenarios—one with the same code rate but different code lengths and the other with the same code length but different code rates—this model can still effectively reduce the bit error rate by 5%-12% under different channel conditions.

[0098] This embodiment also provides an LDPC decoding device based on a graph neural network, comprising:

[0099] The graph construction module is used to construct a factor graph representing the LDPC code structure, modeling variable nodes, check nodes and edge relationships, and mapping the log-likelihood ratio of the received signal to the initial embedding of the variable nodes.

[0100] The message generation module and attention calculation module generate message features based on node embedding, node degree and iteration step size, and construct attention weights for each edge to measure the importance of different messages.

[0101] The edge weight update module is used to input message features and attention weights into the gated loop unit, perform residual updates of edge weights, and feed the updated edge weights back to the factor graph.

[0102] The aggregation update module and the gating modulation module perform weighted aggregation of adjacent node messages according to edge weights, update the embedding of variable nodes and verification nodes, and perform gating modulation based on the verification results.

[0103] The output module is used to output the final symbol decision results and edge weights of the embedded variable nodes.

[0104] The edge weight update module includes a gated loop unit and a residual fusion unit, which are used to dynamically adjust edge weights and retain historical information to improve iteration stability.

[0105] The output module maps node embeddings to log-likelihood ratios or decision bits, and performs phase or bit compensation on the signal in conjunction with the final edge weights.

[0106] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features of the invention herein.

Claims

1. A low-density parity-check code decoding method based on graph neural networks, characterized in that, include: Step S1: Construct a factor graph representing the LDPC code structure, model the variable nodes, check nodes and edge relationships, and map the log-likelihood ratio of the received signal to the initial embedding of the variable nodes. Step S2: Generate message features based on node embedding, node degree, and iteration step size, and construct attention weights for each edge to measure the importance of different messages; Step S3: Input the message features and attention weights into the gated recurrent unit, perform residual update of the edge weights, and feed the updated edge weights back to the factor graph; Step S4: Perform weighted aggregation of adjacent node messages according to edge weights, update the embedding of variable nodes and verification nodes, and perform gated modulation based on the verification results; Step S5: Repeat steps S2-S4 until the preset number of iterations or decoding convergence conditions are reached, and output the symbol decision result of the variable node embedding and the combined edge weight.

2. The low-density parity-check code decoding method according to claim 1, characterized in that, Initial embedding of variable nodes in step S1 From the log-likelihood ratio Generates through learnable linear or nonlinear mappings.

3. The low-density parity-check code decoding method according to claim 1, characterized in that, In step S2, the iteration step size is represented by a positional encoding, which is a sine / cosine function or a learnable embedding.

4. The low-density parity-check code decoding method according to claim 1, characterized in that, In step S2, the attention weights are determined using dot product attention, a learnable matching function, or a softmax normalization strategy.

5. The low-density parity-check code decoding method according to claim 1, characterized in that, Step S3, which involves performing residual updates on edge weights, specifically includes mapping edge states to candidate edge weights using learnable mappings. And by using an activation function to restrict the value to A residual fusion strategy is adopted to perform residual fusion between the candidate edge weights and the edge weights of the previous iteration to obtain the updated edge weights. .

6. The low-density parity-check code decoding method according to claim 5, characterized in that, The activation function is a function that updates the edge weights. The is: ； ； ； in, For MLP functions, The Sigmoid activation function is used. The output of the gated loop unit represents the internal state of the edge. Control the ratio of historical data to candidate values ​​in the fusion process. is the input vector of the gating unit. For gate function mapping 7. The low-density parity-check code decoding method according to claim 1, characterized in that, Step S4 uses weighted sum, weighted average, maximum or minimum value form, combined with residual connection and normalization operations, to perform weighted aggregation of adjacent node messages.

8. The low-density parity-check code decoding method according to claim 1, characterized in that, The embedded representation of the updated variable node and check node in step S4 is as follows: ； in, For historical residuals; For learnable mapping functions, It is a gated modulation signal.

9. The low-density parity check code decoding method according to claim 8, characterized in that, The gated modulation signal for: ； in The result of the current iteration verification. This is a gated function.

10. A low-density parity-check code decoding apparatus for implementing the method of any one of claims 1-9, characterized in that, include: The graph construction module is used to construct a factor graph representing the LDPC code structure, modeling variable nodes, check nodes and edge relationships, and mapping the log-likelihood ratio of the received signal to the initial embedding of the variable nodes. The message generation module and attention calculation module generate message features based on node embedding, node degree and iteration step size, and construct attention weights for each edge to measure the importance of different messages. The edge weight update module is used to input message features and attention weights into the gated loop unit, perform residual updates of edge weights, and feed the updated edge weights back to the factor graph. The aggregation update module and the gating modulation module perform weighted aggregation of adjacent node messages according to edge weights, update the embedding of variable nodes and verification nodes, and perform gating modulation based on the verification results. The output module is used to output the final symbol decision results and edge weights of the embedded variable nodes.

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