Analog-to-digital converter and image sensor device comprising the same

Abstract

An image sensor apparatus can include: an image pixel configured to generate a pixel signal based on light; a ramp generator including: a ramp source circuit configured to generate an original ramp signal; a drive source circuit configured to generate a drive source signal; a bandwidth control circuit configured to generate a drive signal by adjusting a bandwidth of the drive source signal; and a ramp buffer circuit configured to generate a ramp signal corresponding to the original ramp signal based on the drive signal; a comparison amplifier configured to generate a comparison output signal based on the pixel signal and the ramp signal; and an analog-to-digital conversion circuit configured to generate a digital signal corresponding to the light based on the comparison output signal.

Description

Cross-reference to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0172828, filed on November 27, 2024, with the Korean Intellectual Property Office, and Korean Patent Application No. 10-2024-0202589, filed on December 31, 2024, the entire contents of each of which are incorporated herein by reference. Technical Field

[0002] This application relates to analog-to-digital converters and image sensor devices including such analog-to-digital converters. Background Technology

[0003] Image sensor devices can convert light into digital signals. For example, an image sensor device may include image pixels and an analog-to-digital converter.

[0004] Image pixels can convert light into analog voltage signals based on power supply voltage. Accordingly, if the power supply voltage includes noise, the analog voltage signal generated by the image pixels may also include noise. Summary of the Invention

[0005] An analog-to-digital converter (ADC) connected to image pixels may include a ramp generator that generates a reference ramp signal. The ADC can generate a digital signal based on a comparison between an analog voltage signal and the reference ramp signal. Therefore, if noise included in the analog voltage signal is appropriately compensated based on the reference ramp signal, the noise included in the digital signal generated by the image sensor device can be minimized. However, even if noise included in the analog voltage signal is appropriately compensated based on the reference ramp signal, the digital signal generated by the image sensor device may still include a significant noise component.

[0006] Some aspects of this disclosure provide an image sensor device with improved compensation capabilities to eliminate noise from the image sensor output.

[0007] According to some embodiments of this disclosure, an image sensor device can be provided. The image sensor device may include: image pixels configured to generate pixel signals based on light; a ramp generator including: a ramp source circuit configured to generate an original ramp signal; a drive source circuit configured to generate a drive source signal; a bandwidth control circuit configured to generate a drive signal by adjusting the bandwidth of the drive source signal; a ramp buffer circuit configured to generate a ramp signal corresponding to the original ramp signal based on the drive signal; a comparator amplifier configured to generate a comparator output signal based on the pixel signal and the ramp signal; and an analog-to-digital converter circuit generating a digital signal corresponding to light based on the comparator output signal.

[0008] According to some embodiments of this disclosure, an image sensor device can be provided. The image sensor device may include: an image pixel array including: a first image pixel configured to operate based on a voltage level of a power line and configured to generate a first pixel signal corresponding to a voltage level of a first floating diffusion node; and a ramp generator configured to operate based on a voltage level of a power line and generate a first reference ramp signal corresponding to the first pixel signal, wherein the ramp generator includes: a drive source circuit configured to generate a drive source signal based on a capacitor replication circuit corresponding to a first electrical parasitic capacitance between the power line and the first floating diffusion node and a first floating diffusion capacitance of the first floating diffusion node; a first bandwidth control circuit configured to generate a first drive signal by adjusting the bandwidth of the drive source signal; and a first ramp buffer circuit configured to generate the first reference ramp signal based on the first drive signal.

[0009] According to some embodiments of this disclosure, an analog-to-digital converter (ADC) may be provided. The ADC may include: a ramp generator configured to generate a ramp signal based on a power supply voltage supplied from a power line; a comparator amplifier configured to generate a comparator output signal based on the ramp signal and a pixel signal supplied from an image pixel; and an ADC circuit configured to generate a digital signal based on the comparator output signal, wherein the ramp generator includes a bandwidth control circuit configured to adjust a second effective bandwidth of a second frequency response between the power supply voltage and the ramp signal based on a first effective bandwidth of a first frequency response between the power supply voltage and the pixel signal. Attached Figure Description

[0010] Figure 1 This is a block diagram illustrating an example of an image sensor device.

[0011] Figure 2 It shows in more detail Figure 1 A block diagram of the various parts of an image sensor device.

[0012] Figure 3 It shows in more detail Figure 2 Diagrams of the various parts.

[0013] Figure 4 It shows Figure 2 A diagram illustrating an example of a ramp generator.

[0014] Figure 5 This is a diagram showing an example of a driver source circuit.

[0015] Figure 6 This is a diagram illustrating an example of the function of a bandwidth control circuit.

[0016] Figure 7 This is a diagram illustrating an example of the function of a bandwidth control circuit.

[0017] Figure 8 This is a graph showing an example of comparing the voltage levels of the output signals.

[0018] Figure 9 This is a graph illustrating an example of the power supply rejection ratio (PSRR) of an image sensor device.

[0019] Figure 10 and Figure 11 This is a diagram illustrating an example of a bandwidth control circuit.

[0020] Figure 12 This is a diagram showing an example of an analog-to-digital converter.

[0021] Figure 13 This is a diagram showing a portion of an example of an image sensor device.

[0022] Figure 14 This is a block diagram illustrating an example of an electronic device that includes a multi-camera module.

[0023] Figure 15 This is a block diagram showing an example of a camera module. Detailed Implementation

[0024] It should be understood that various changes and modifications can be made to the examples described herein without departing from the scope and spirit of this disclosure. Furthermore, for clarity and brevity, descriptions of some well-known functions and structures have been omitted in the following description.

[0025] In the detailed description, the components described by the terms "driver," "block," etc., will be implemented through software, hardware, or a combination thereof. For example, software can be machine code, firmware, embedded code, and application software. Hardware can include circuits, electronic circuits, processors, computers, integrated circuit cores, pressure sensors, microelectromechanical systems (MEMS), passive components, or a combination thereof.

[0026] Figure 1 This is a block diagram illustrating an example of an image sensor device. (See reference...) Figure 1 The image sensor device 100 may include an image pixel array 110, a line decoder 120, an analog-to-digital converter 130, and a sensor controller 140.

[0027] The image pixel array 110 may include a plurality of image pixels arranged in the row and column directions, for example, Figure 2As shown. Each of the multiple image pixels can generate a pixel signal SPX in response to the control of the line decoder 120. For example, each of the multiple image pixels can generate a reset pixel signal or a data pixel signal. Each of the multiple image pixels can output the generated pixel signal SPX through the data line DL. The pixel signal SPX can be in the form of an analog voltage.

[0028] The line decoder 120 can be connected to the image pixel array 110 via multiple signal lines. The line decoder 120 can provide a reset signal RX, a transfer signal TX, and a select signal SEL to each of the multiple image pixels via multiple signal lines.

[0029] Analog-to-digital converter 130 can be connected to image pixel array 110 via data line DL. Analog-to-digital converter 130 can convert pixel signals SPX into digital signals DS. For example, analog-to-digital converter 130 can convert the voltage level (e.g., analog voltage) of data line DL into a digital signal DS by sampling the voltage level of data line DL. For example, analog-to-digital converter 130 can generate the digital signal DS by performing CDS (correlated double sampling) operation based on a reset pixel signal and data pixel signals provided via data line DL.

[0030] The image pixel array 110 and the analog-to-digital converter 130 can share a power supply line PSL. For example, both the image pixel array 110 and the analog-to-digital converter 130 can receive the power supply voltage VDD through a single power supply line PSL. However, the power configuration is not limited to this, and the image pixel array 110 and the analog-to-digital converter 130 can be configured to receive the power supply voltage VDD from a single power supply circuit, or to receive the power supply voltage VDD from different power supply lines that are directly or indirectly connected to each other.

[0031] The power supply voltage VDD provided via the power line PSL may include noise. For example, the power supply voltage VDD may not maintain a constant voltage level, but may rise and fall slightly. In this case, the pixel signal SPX output from the image pixel array 110 may also include noise. The analog-to-digital converter 130 can compensate for the noise included in the pixel signal SPX based on the power supply voltage VDD. In this case, the noise of the image corresponding to the digital signal DS can be minimized. A more detailed configuration and operation of the analog-to-digital converter 130 will be described in detail below.

[0032] The sensor controller 140 can control the overall operation of the image sensor device 100. For example, the sensor controller 140 can control the operating timing of the line decoder 120 and the analog-to-digital converter 130.

[0033] Figure 2 It shows in more detail Figure 1 A block diagram of a portion of an image sensor device. Although Figure 2 A plurality of image pixels PX are shown arranged along the first pixel row to the fourth pixel row and the first pixel column to the fourth pixel column of the image pixel array 110, but the number of rows / columns is not limited thereto. For example, the image pixel array 110 may be extended in the row direction and / or the column direction, and the image pixel array 110 may also include a plurality of image pixels.

[0034] Reference Figure 1 and Figure 2 The image sensor device 100 may include an image pixel array 110 and an analog-to-digital converter 130. The image pixel array 110 may include a plurality of image pixels PX. Among the plurality of image pixels PX, image pixels located in a first pixel column may be connected to a first data line DL1, image pixels located in a second pixel column may be connected to a second data line DLb, image pixels located in a third pixel column may be connected to a third data line DLc, and image pixels located in a fourth pixel column may be connected to a fourth data line DLd.

[0035] In some implementations, image pixels within the same pixel row of the image pixel array 110 can be connected to the line decoder 120 via the same signal lines. For example, image pixels within the same pixel row can share signal lines. Accordingly, image pixels PX within the same pixel row can receive the same signals from the line decoder 120. For example, image pixels PX within a first pixel row can share the reset signal RX, the transfer signal TX, and the select signal SEL.

[0036] Each of a plurality of image pixels PX can generate a pixel signal SPX based on a reset signal RX and a transmission signal TX. Each of the plurality of image pixels PX can output the pixel signal SPX via a connected data line DL. For example, each of the plurality of image pixels PX can output the pixel signal SPX in response to a selection signal SEL.

[0037] In some implementations, the pixel signal SPX output by each image pixel PX can be a reset pixel signal generated by a reset operation or a data pixel signal generated by a transmission operation.

[0038] In some embodiments, image pixels included in a single pixel row may share a reset signal RX, a transfer signal TX, and a select signal SEL. Therefore, image pixels included in a pixel row may simultaneously generate pixel signals SPX and simultaneously output pixel signals SPX to the data line DL. In this case, the pixel signal SPX generated by the image pixels PX included in a pixel row may include noise with values ​​corresponding to each other. Therefore, if the analog-to-digital converter 130 does not compensate for the noise components of the pixel signal SPX, horizontal noise may appear in the image represented by multiple digital signals DS. Some embodiments of this disclosure include an analog-to-digital converter 130 that compensates for the noise components of the pixel signal SPX, as detailed below.

[0039] The first current source CSa to the fourth current source CSd can be connected to the first data line DLa to the fourth data line DLd, respectively. Each of the first current sources CSa to the fourth current source CSd can be a constant current source. However, the circuit configuration is not limited to this implementation of the first current source CSa to the fourth current source CSd.

[0040] The analog-to-digital converter 130 may include a ramp generator 131, a first comparator amplifier 132a to a fourth comparator amplifier 132d, and a first analog-to-digital conversion circuit 133a to a fourth analog-to-digital conversion circuit 133d.

[0041] Each of the first comparator amplifiers 132a to the fourth comparator amplifiers 132d (or differential amplifiers) can correspond to a different pixel column. For example, the first comparator amplifiers 132a to the fourth comparator amplifiers 132d can be connected to the first data line DLa to the fourth data line DLd, respectively.

[0042] The ramp generator 131 can generate a ramp signal RMP. The ramp generator 131 can provide the ramp signal RMP to each of the first comparator amplifiers 132a to the fourth comparator amplifiers 132d.

[0043] In some implementations, the ramp signal RMP can be a signal with a linearly decreasing voltage level. However, the scope of this disclosure is not limited to a specific waveform of the ramp signal RMP. For example, the ramp signal RMP can be implemented as a linearly increasing voltage.

[0044] In some implementations, the ramp generator 131 may also be referred to as a ramp generation circuit.

[0045] Each of the first comparator amplifiers 132a to the fourth comparator amplifiers 132d can receive a pixel signal SPX from the connected data line DL and a ramp signal RMP from the ramp generator 131. Each of the first comparator amplifiers 132a to the fourth comparator amplifiers 132d can generate a comparator output signal SCO by amplifying the difference between the received pixel signal SPX and the ramp signal RMP. That is, the ramp signal RMP can be used as a reference voltage signal for the voltage levels of the first data line DL1 to the fourth data line DLd. For example, the first comparator amplifier 132a can generate a first comparator output signal SCOa based on the ramp signal RMP and the first pixel signal SPXa. In this way, the first comparator amplifiers 132a to the fourth comparator amplifiers 132d can generate first comparator output signals SCOa to fourth comparator output signals SCOd respectively based on the first pixel signal SPXa to the fourth pixel signal SPXd.

[0046] In some implementations, the ramp signal RMP may also be referred to as the reference ramp signal.

[0047] The ramp generator 131 may include a bandwidth control circuit 131_3 (sometimes referred to as a frequency response control circuit or a spectrum control circuit). The ramp generator 131 can adjust the bandwidth of the noise component included in the ramp signal RMP based on the bandwidth control circuit 131_3. For example, the ramp generator 131 can adjust the bandwidth of the noise component included in the ramp signal RMP according to the frequency band of the noise component included in the pixel signal SPX, based on the bandwidth control circuit 131_3. In this case, since the noise included in the ramp signal RMP can correspond to the noise included in each of the first pixel signals SPXa to the fourth pixel signal SPXd, the noise component included in the first comparison output signals SCOa to the fourth comparison output signals SCOd can be reduced or minimized.

[0048] The first ADC circuit 133a to the fourth ADC circuit 133d can respectively receive the first comparison output signal SCOa to the fourth comparison output signal SCOd. The first ADC circuit 133a to the fourth ADC circuit 133d can respectively generate the first digital signal DSa to the fourth digital signal Dsd based on the first comparison output signal SCOa to the fourth comparison output signal SCOd. For example, each ADC circuit in the first ADC circuit 133a to the fourth ADC circuit 133d can generate the digital signal DS based on the duration for which the voltage level of the received comparison output signal SCO is higher than a specific voltage level. However, the scope of this disclosure is not limited to the specific manner or method by which each ADC circuit in the first ADC circuit 133a to the fourth ADC circuit 133d generates the digital signal DS based on the voltage level of the comparison output signal SCO.

[0049] In some embodiments, when the noise components included in the first comparison output signals SCOa to the fourth comparison output signals SCOd are reduced or minimized, the noise components included in the first digital signals DSa to the fourth digital signals Dsd can also be reduced or minimized. Therefore, according to some embodiments of this disclosure, the noise (e.g., horizontal noise) included in the image generated based on the first digital signals DSa to the fourth digital signals Dsd can be reduced or minimized.

[0050] Figure 3 It shows in more detail Figure 2 Some configuration diagrams are shown. (Refer to...) Figure 3 The operation of the image sensor device 100 corresponding to the first pixel column will be described in more detail.

[0051] Additionally, for ease of explanation, the image pixel PX is assumed below to have a 4TR-1PD (4 transistors, 1 photodiode) structure. However, the scope of this disclosure is not limited thereto, and each image pixel PX included in the image pixel array 110 can be implemented in various forms, such as a 5TR-2PD (5 transistors, 2 photodiodes) structure, a 6TR-3PD (6 transistors, 3 photodiodes) structure, etc.

[0052] Image pixel PX can respond to the reset signal RX, the transmission signal TX, and the selection signal SEL received from the line decoder 120, and output the first pixel signal SPXa through the first data line DLa. Image pixel PX can receive the power supply voltage VDD from the power supply line PSL.

[0053] An image pixel PX may include a photodiode PD, a transfer transistor TT, a reset transistor RT, a drive transistor DT, and a select transistor ST. The photodiode PD can generate charge in response to light received from an external source (i.e., it can convert photons into electrons).

[0054] A transfer transistor TT can be connected between a photodiode PD and a floating diffusion node FD. The transfer transistor TT can operate in response to a transfer signal TX from the line decoder 120. For example, the transfer transistor TT can be turned on in response to the transfer signal TX. In this case, charge can move from the photodiode PD to the floating diffusion node FD, and the voltage level of the floating diffusion node FD can be reduced.

[0055] A floating diffusion capacitor (CFD) can be formed between the floating diffusion node (FD) and the ground voltage (VSS). For example, the floating diffusion capacitor can be connected in hardware between the floating diffusion node (FD) and the ground voltage (VSS), or a parasitic capacitance can be formed between the floating diffusion node (FD) and the ground voltage (VSS). In this case, the voltage level of the floating diffusion node (FD) can be maintained based on the voltage level stored in the floating diffusion capacitor (CFD). However, the scope of this disclosure is not limited to this specific method of forming the floating diffusion capacitor (CFD).

[0056] A reset transistor RT can be connected between the power supply voltage VDD and the floating diffusion node FD. The reset transistor RT can operate in response to a reset signal RX from the line decoder 120. For example, the reset transistor RT can be turned on in response to the reset signal RX. In this case, the voltage level of the floating diffusion node FD can be increased based on the power supply voltage VDD.

[0057] The driving transistor DT can be connected between the power supply voltage VDD and the intermediate node MN. The driving transistor DT can operate in response to the voltage of the floating diffusion node FD. For example, the gate terminal of the driving transistor DT can be connected to the floating diffusion node FD. The driving transistor DT can generate a first pixel signal SPXa based on the voltage of the floating diffusion node FD. For example, the driving transistor DT can be used as a source follower, with its input terminal connected to the floating diffusion node FD. The driving transistor DT can provide the first pixel signal SPXa to the intermediate node MN.

[0058] The select transistor ST can be connected between the intermediate node MN and the first data line DLa. The select transistor ST can operate in response to the select signal SEL. For example, the select transistor ST can be turned on in response to the select signal SEL. In this case, the first pixel signal SPXa can be provided to the first data line Dla.

[0059] In some implementations, the operation of charging the floating diffusion node FD based on the power supply voltage VDD can be referred to as a reset operation.

[0060] In some implementations, the operation of reducing the voltage of the floating diffusion node FD by transferring charge from the photodiode PD to the floating diffusion node FD can be referred to as a transfer operation.

[0061] In some implementations, the first pixel signal SPXa generated by the driving transistor DT based on the voltage of the floating diffusion node FD charged through a reset operation can be referred to as the reset pixel signal.

[0062] In some implementations, the first pixel signal SPXa generated by the driving transistor DT based on the voltage reduced by the transmission operation of the floating diffusion node FD can be referred to as the data pixel signal.

[0063] A parasitic electrical capacitance CPV can form between the floating diffusion node FD and the power supply voltage VDD. Accordingly, the voltage level of the floating diffusion node FD can fluctuate due to fluctuations in the power supply voltage VDD. In other words, if noise is present in the power supply voltage VDD, the voltage level of the floating diffusion node FD may fluctuate unexpectedly. In this case, the first pixel signal SPXa generated based on the voltage level of the floating diffusion node FD may also include noise.

[0064] The ramp generator 131 can receive a power supply voltage VDD from the power supply line PSL. The ramp generator 131 can generate a ramp signal RMP based on the power supply voltage VDD, which includes noise corresponding to the noise included in the first pixel signal SPXa. For example, the ramp generator 131 can control the bandwidth of the frequency response between the power supply voltage VDD and the ramp signal RMP based on the frequency response between the power supply voltage VDD and the first pixel signal SPXa, based on the bandwidth control circuit 131_3. For example, the ramp generator 131 can control the effective bandwidth of the frequency response between the power supply voltage VDD and the ramp signal RMP based on the effective bandwidth determined based on the frequency response between the power supply voltage VDD and the first pixel signal SPXa, based on the bandwidth control circuit 131_3. A more detailed configuration and operation of the ramp generator 131 will be described in detail below.

[0065] The first input terminal of the first comparator amplifier 132a can be connected to the first comparator input node NCPI1, the second input terminal of the first comparator amplifier 132a can be connected to the second comparator input node NCPI2, and the output terminal of the first comparator amplifier 132a can be connected to the comparator output node NCPO. The first comparator input node NCPI1 can be connected to the ramp generator 131, and the second comparator input node NCPI2 can be connected to the first data line Dla. The comparator output node NCPO can be connected to the first ADC circuit 133a.

[0066] The first comparator amplifier 132a can receive the ramp signal RMP through the first comparator input node NCPI1 and the first pixel signal SPXa through the second comparator input node NCPI2. The first comparator amplifier 132a can generate a first comparator output signal SCOa based on the difference between the ramp signal RMP and the first pixel signal SPXa. The first comparator amplifier 132a can output the first comparator output signal SCOa to the comparator output node NCPO.

[0067] In some embodiments, when the noise components included in the ramp signal RMP and the first pixel signal SPXa correspond to each other, the noise components included in the difference between the ramp signal RMP and the first pixel signal SPXa can be minimized. For example, if the ramp signal RMP and the first pixel signal SPXa include the same noise component, then the difference between the ramp signal RMP and the first pixel signal SPXa may not include that noise component. In this case, the first comparator amplifier 132a can generate the first pixel signal SCOa by canceling the noise components included in the ramp signal RMP and the first pixel signal SPXa. Therefore, according to some embodiments of this disclosure, the influence of power supply voltage VDD noise can be reduced.

[0068] Figure 4 A ramp generator (e.g., is shown) Figure 3 A diagram illustrating an example of a ramp generator. (See also...) Figures 1 to 4 The ramp generator 131 may include a ramp source circuit 131_1, a drive source circuit 131_2, a bandwidth control circuit 131_3, and a ramp buffer circuit RBF.

[0069] The ramp source circuit 131_1 can generate a raw ramp signal RMP_raw. In some embodiments, the raw ramp signal RMP_raw can be a signal whose voltage level decreases over time.

[0070] In some embodiments, the ramp source circuit 131_1 may include a variable current source and a variable resistor connected between the power supply voltage VDD and the ground voltage VSS. In this case, the ramp source circuit 131_1 may generate the raw ramp signal RMP_raw based on the voltage level of the node between the variable current source and the variable resistor. However, the scope of this disclosure is not limited to this particular manner in which the ramp source circuit 131_1 generates the raw ramp signal RMP_raw.

[0071] The ramp buffer circuit RBF can generate the ramp signal RMP based on the original ramp signal RMP_raw. The ramp buffer circuit RBF can include a buffer transistor BFT and a current source transistor CST.

[0072] In some implementations, the buffer transistor BFT and the current source transistor CST can be implemented as p-channel metal-oxide-semiconductor (PMOS) transistors. However, the types of transistors that implement the ramp buffer circuit RBF are not limited to those described above.

[0073] A current source transistor (CST) can be connected between the buffer output node NBFO and the supply voltage VDD. The gate terminal of the CST can be connected to the bandwidth control output node NBCO. The CST can receive a drive signal DVS through the bandwidth control output node NBCO. The CST can operate as a current source based on the voltage level of the drive signal DVS. For example, the CST can provide the current required for the operation of the buffer transistor BFT based on the drive signal DVS.

[0074] A buffer transistor BFT can be connected between the buffer output node NBFO and the ground voltage VSS. The buffer transistor BFT can operate based on the current supplied from the current source transistor CST. For example, the buffer transistor BFT can operate as a source follower, generating a ramp signal RMP based on the current supplied from the current source transistor CST and the original ramp signal RMP_raw. More specifically, the gate terminal of the buffer transistor BFT can receive the original ramp signal RMP_raw. In this case, the buffer transistor BFT can output the ramp signal RMP corresponding to the original ramp signal RMP_raw to the first comparator input node NCPI1 through the buffer output node NBFO.

[0075] The ramp signal RMP (i.e., the voltage at the buffer output node NBFO) can vary depending on the magnitude of the current supplied from the current source transistor CST. The amount of current supplied by the current source transistor CST to the buffer transistor BFT can vary depending on the voltage level of the drive signal DVS. Therefore, if the drive signal DVS correctly reflects the noise component of the power supply voltage VDD, the ramp signal RMP can include a noise component corresponding to the noise component in the pixel signal SPX.

[0076] The driving source circuit 131_2 can operate based on the power supply voltage VDD. The driving source circuit 131_2 can generate a driving source signal DVS_src, which reflects or represents the noise component of the power supply voltage VDD. For example, the driving source circuit 131_2 may include a capacitor replication circuit CRC. The capacitor replication circuit CRC can be implemented based on the power supply voltage VDD to reflect or represent the noise component generated in the floating diffusion node FD due to the electrical parasitic capacitance CPV of the image pixel PX in the driving source signal DVS_src. The driving source circuit 131_2 can provide the driving source signal DVS_src to the bandwidth control input node NBCI.

[0077] The bandwidth control circuit 131_3 can control the bandwidth of the drive source signal DVS_src. For example, the bandwidth control circuit 131_3 can generate the drive signal DVS by decreasing or increasing the bandwidth of the drive source signal DVS_src. The bandwidth control circuit 131_3 can adjust the bandwidth of the drive source signal DVS_src so that the frequency response between the power supply voltage VDD and the ramp signal RMP corresponds to the frequency response between the power supply voltage VDD and the first pixel signal SPXa.

[0078] When the ramp generator 131 is implemented to directly provide the raw ramp signal RMP_raw to the first comparison input node NCPI1, the voltage level of the first comparison input node NCPI1 can change due to the coupling between the comparison output node NCPO and the first comparison input node NCPI1. In this case, since the noise components included in the first pixel signal SPXa can be reflected or embodied in the first comparison output signal SCOa, the image generated by the image sensor device 100 may include horizontal noise. In contrast, according to some embodiments of this disclosure, instead of directly providing the raw ramp signal RMP_raw to the first comparison input node NCPI1, a ramp signal RMP is provided to the first comparison input node NCPI1. In this case, the voltage level change of the first comparison input node NCPI1 can be reduced due to the coupling between the comparison output node NCPO and the first comparison input node NCPI1. Accordingly, the first comparison amplifier 132a can compensate (e.g., remove) the noise components included in the first pixel signal SPXa based on the ramp signal RMP, thereby reducing the horizontal noise of the image generated by the image sensor device 100.

[0079] Figure 5 It shows the driving source circuit (e.g., Figure 4 A diagram illustrating an example of the driving source circuit (see example). Figures 1 to 5 The driving source circuit 131_2 may include a bias current source BCS, a first transistor TR1, a capacitor replication circuit CRC, a second transistor TR2, and a third transistor TR3.

[0080] The bias current source BCS can be connected between the supply voltage VDD and the first node N1. The bias current source BCS can provide bias current to the first node N1.

[0081] The first transistor TR1 can be connected between the first node N1 and the ground voltage VSS. The gate terminal of the first transistor TR1 can be connected to the second node N2. The second node N2 can be connected to the first node N1.

[0082] The capacitor replication circuit CRC can be connected to the second node N2. The capacitor replication circuit CRC can provide the noise component of the power supply voltage VDD to the second node N2. For example, the capacitor replication circuit CRC may include a power parasitic capacitance replication capacitor CPVR and a floating diffuse capacitance replication capacitor CFDR. The power parasitic capacitance replication capacitor CPVR can be connected between the power supply voltage VDD and the second node N2. The floating diffuse capacitance replication capacitor CFDR can be connected between the second node N2 and the ground voltage VSS.

[0083] The capacitance ratio of the electrical parasitic capacitance replica capacitor CPVR to the floating diffusion capacitance replica capacitor CFDR can correspond to (e.g., substantially match) the capacitance ratio of the electrical parasitic capacitance CPV to the floating diffusion capacitance CFD within image pixel PX. In this case, the amount by which the noise component of the power supply voltage VDD provides (e.g., affects) the second node N2 can be as much as the amount by which the noise component of the power supply voltage VDD provides (e.g., affects) the floating diffusion node FD.

[0084] In some embodiments, the capacitance ratio of the parasitic capacitance replication capacitor CPVR to the floating diffusion capacitance replication capacitor CFDR can be determined based on the capacitance ratio of the parasitic capacitance CPV to the floating diffusion capacitance CFD for each of the plurality of image pixels PX included in the image pixel array 110. For example, the capacitance ratio of the parasitic capacitance replication capacitor CPVR to the floating diffusion capacitance replication capacitor CFDR can be determined as the average of the capacitance ratios of the parasitic capacitance CPV to the floating diffusion capacitance CFD for the plurality of image pixels PX. However, the scope of this disclosure is not limited to this particular manner of determining the capacitance ratio of the parasitic capacitance replication capacitor CPVR to the floating diffusion capacitance replication capacitor CFDR. For example, the capacitance ratio of the parasitic capacitance replication capacitor CPVR to the floating diffusion capacitance replication capacitor CFDR can be determined based on the capacitance ratio of the parasitic capacitance CPV to the floating diffusion capacitance CFD for a representative image pixel PX; or it can be determined based on the average of the capacitance ratios of the parasitic capacitance CPV to the floating diffusion capacitance CFD for the image pixels PX included in each pixel row.

[0085] In some embodiments, each of the electrical parasitic capacitance replication capacitor CPVR and the floating diffusion capacitance replication capacitor CFDR can be implemented as a variable capacitor. In this case, the capacitance of each of the electrical parasitic capacitance replication capacitor CPVR and the floating diffusion capacitance replication capacitor CFDR can be determined based on simulation results of the electrical parasitic capacitance CPV and the floating diffusion capacitance CFD performed for image pixels PX during the production stage of the image sensor device 100. However, the scope of this disclosure is not limited thereto.

[0086] The second transistor TR2 can be connected between the third node N3 and the ground voltage VSS. The gate terminal of the second transistor TR2 can be connected to the second node N2. Therefore, the first transistor TR1 and the second transistor TR2 can form a current mirror. For example, the magnitude of the current flowing from the third node N3 through the second transistor TR2 to the ground voltage VSS can be determined based on the magnitude of the current of the bias current source BCS and the magnitude of the noise component of the power supply voltage VDD.

[0087] The third transistor TR3 can be connected between the power supply voltage VDD and the third node N3. The gate terminal of the third transistor TR3 can be connected to the bandwidth control input node NBCI. The third node N3 can be connected to the bandwidth control input node NBCI. In this case, the voltage level of the bandwidth control input node NBCI can be determined based on the magnitude of the current flowing from the third node N3 through the second transistor TR2 to the ground voltage VSS. Accordingly, the voltage level of the bandwidth control input node NBCI (i.e., the drive source signal DVS_src) may include the noise component of the power supply voltage VDD.

[0088] When the drive source signal DVS_src is directly supplied to the gate terminal of the current source transistor CST, noise components in a specific frequency band of the power supply voltage VDD may be non-uniformly included in the ramp signal RMP and the first pixel signal SPXa. For example, the difference between the frequency response from the power supply voltage VDD to the ramp signal RMP and the frequency response from the power supply voltage VDD to the first pixel signal SPXa may be very large in a specific frequency band. In this case, since noise components in a specific frequency band may be included in the first comparison output signal SCOa (e.g., since the noise components are not canceled between the ramp signal RMP and the first pixel signal SPXa), the image generated by the image sensor device 100 may include noise.

[0089] On the other hand, according to some embodiments of this disclosure, the bandwidth control circuit 131_3 can provide a drive signal DVS generated by adjusting the bandwidth of the drive source signal DVS_src to the gate terminal of the current source transistor CST. In this case, noise components of all frequency bands of the power supply voltage VDD can be included substantially equally in the ramp signal RMP and the first pixel signal SPXa. For example, the amplitude of the frequency response from the power supply voltage VDD to the ramp signal RMP and the amplitude of the frequency response from the power supply voltage VDD to the first pixel signal SPXa can have similar values ​​or substantially match in all frequency bands (e.g., all frequency bands of interest for noise cancellation). In this case, since the first comparator amplifier 132a can appropriately compensate (e.g., cancel) the noise components of all frequency bands of the power supply voltage VDD, the noise in the image generated by the image sensor device 100 can be significantly reduced.

[0090] In some implementations, the supply voltage VDD connected to each of the bias current source BCS, the power parasitic capacitance replica capacitor CPVR, and the third transistor TR3 can be provided from the power line PSL. However, the circuit configuration is not limited to this, and for example, the supply voltage VDD connected only to the power parasitic capacitance replica capacitor CPVR can be provided from the power line PSL.

[0091] In some embodiments, the third transistor TR3 and the current source transistor CST can form a current mirror. For example, the magnitude of the current generated by the current source transistor CST can be determined based on the magnitude of the current flowing from the supply voltage VDD through the third transistor TR3 to the third node N3 and the magnitude of the bandwidth controlled by the bandwidth control circuit 131_3. However, the scope of this disclosure is not limited thereto.

[0092] In some embodiments, the first transistor TR1 and the second transistor TR2 can be implemented as n-channel metal-oxide-semiconductor (NMOS) transistors. The third transistor TR3 can be implemented as a PMOS (p-channel metal-oxide-semiconductor) transistor. However, the types of transistors used to implement the driving source circuit 131_2 are not limited to the types described above.

[0093] Figure 6 This is a diagram illustrating an example of the function of a bandwidth control circuit. Figure 6 The horizontal axis represents the frequency on a logarithmic scale, and the vertical axis represents the magnitude of the frequency response in decibels. For example, Figure 6 This can correspond to a Bode amplitude diagram, which approximates the amplitude of the frequency response.

[0094] Reference Figures 1 to 6 When the power supply voltage VDD is the input signal and the ramp signal RMP is the output signal, the frequency response is referred to as the first frequency response REF_FREQ1. When the power supply voltage VDD is the input signal and the pixel signal SPX (e.g., the first pixel signal SPXa) is the output signal, the frequency response is referred to as the second frequency response REF_FREQ2. The first frequency response REF_FREQ1 represents the frequency response between the power supply voltage VDD and the ramp signal RMP, and the second frequency response REF_FREQ2 represents the frequency response between the power supply voltage VDD and the pixel signal SPX. In other words, the first frequency response REF_FREQ1 indicates the degree of influence of the noise component included in the power supply voltage VDD on the ramp signal RMP, and the second frequency response REF_FREQ2 indicates the degree of influence of the noise component included in the power supply voltage VDD on the pixel signal SPX.

[0095] The bandwidth control circuit 131_3 can use bandwidth reduction schemes (e.g., low-pass filtering, band-pass filtering, etc.) to adjust the bandwidth of the drive source signal DVS_src. For example, the bandwidth control circuit 131_3 can adjust the first effective bandwidth BWEF1 of the first frequency response REF_FREQ1 based on the second effective bandwidth BWEF2 of the second frequency response REF_FREQ2 by reducing the bandwidth of the drive source signal DVS_src. An example of how the bandwidth control circuit 131_3 adjusts the first effective bandwidth BWEF1 will be described in more detail below.

[0096] When the bandwidth control circuit 131_3 does not control the bandwidth BW, the first frequency response REF_FREQ1 is shown as a dashed line. For example, when the drive source signal DVS_src is directly supplied to the gate terminal of the current source transistor CST or when the bandwidth control input node NBCI and the bandwidth control output node NBCO are short-circuited, the first frequency response REF_FREQ1 is shown as a dashed line.

[0097] Referring to the curve shown by the dashed line, in the frequency band below the first corner frequency FCN1 of the first frequency response REF_FREQ1, the amplitude of the first frequency response REF_FREQ1 is basically the first amplitude Ma (more precisely, close to the value of the first amplitude Ma). In the frequency band above the first corner frequency FCN1, the amplitude of the first frequency response REF_FREQ1 decreases as the frequency increases.

[0098] The second frequency response REF_FREQ2 is shown as a dashed line. Referring to the graph represented by the dashed line, in the frequency band below the second corner frequency FCN2, the amplitude of the second frequency response REF_FREQ2 is essentially the first amplitude Ma (more precisely, close to the value of the first amplitude Ma). In the frequency band above the second corner frequency FCN2, the amplitude of the second frequency response REF_FREQ2 decreases with increasing frequency.

[0099] The first effective bandwidth BWEF1 can be defined as the bandwidth when the first frequency response REF_FREQ1 has an effective or significant size (e.g., a significantly large size). For example, the first effective bandwidth BWEF1 can be the width of a frequency band where the size of the first frequency response REF_FREQ1 is greater than or equal to the second size Mb. For a more detailed example, the first raw effective bandwidth BWEF1_raw can be represented by the effective bandwidth of the graph shown by the dashed line.

[0100] The second effective bandwidth BWEF2 can be defined as the bandwidth when the second frequency response REF_FREQ2 has an effective or significant size. For example, the second effective bandwidth BWEF2 can be the width of a frequency band whose second frequency response REF_FREQ2 is greater than or equal to the second size Mb.

[0101] In some implementations, the second size Mb may be 3 dB smaller than the first size Ma. However, the scope of this disclosure is not limited to this specific criterion for determining the effective bandwidth. For example, the effective bandwidth may be determined as the width of the frequency band below the corner frequency FCN.

[0102] The first raw effective bandwidth BWEF1_raw can be different from the second raw effective bandwidth BWEF2. In this case, the magnitudes of the first frequency response REF_FREQ1 and the second frequency response REF_FREQ2 can be significantly different from each other in the frequency band corresponding to the difference between the first raw effective bandwidth BWEF1_raw and the second effective bandwidth BWEF2. For example, in the frequency band above the second corner frequency FCN2, the magnitudes of the first frequency response REF_FREQ1 and the second frequency response REF_FREQ2 can be slightly different from each other, but in the frequency band corresponding to the difference between the first raw effective bandwidth BWEF1_raw and the second effective bandwidth BWEF2, the magnitudes of the first frequency response REF_FREQ1 and the second frequency response REF_FREQ2 can be significantly different from each other.

[0103] In other words, the noise frequency component of the power supply voltage VDD (located in a frequency band corresponding to the difference between the first raw effective bandwidth BWEF1_raw and the second effective bandwidth BWEF2) can be included in the pixel signal SPX and the ramp signal RMP with different magnitudes or amplitudes. In this case, the comparison output signal SCO can include the noise component of the power supply voltage VDD.

[0104] When the bandwidth control circuit 131_3 controls or adjusts (e.g., compensates) the bandwidth BW, the first frequency response REF_FREQ1 is shown as a solid line. Referring to the graph shown by the solid line, as the bandwidth control circuit 131_3 reduces the bandwidth of the drive source signal DVS_src, the first original effective bandwidth BWEF1_raw can be reduced according to the second effective bandwidth BWEF2. For example, when the bandwidth control circuit 131_3 reduces the bandwidth of the drive source signal DVS_src, the first original effective bandwidth BWEF1_raw can be reduced to the first compensated effective bandwidth BWEF1_comp.

[0105] The first compensated effective bandwidth BWEF1_comp can be similar to or substantially the same as the second effective bandwidth BWEF2, or otherwise more similar to the second effective bandwidth BWEF2 as the first original effective bandwidth BWEF1_raw. In this case, all or substantially all frequency components of the power supply voltage VDD noise can be included in the pixel signal SPX and the ramp signal RMP with the same magnitude. Therefore, the noise component of the power supply voltage VDD included in the comparison output signal SCO can be significantly reduced.

[0106] In some embodiments, since the bandwidth control circuit 131_3 compensates for the bandwidth of the drive source signal DVS_src, the value of the first compensated effective bandwidth BWEF1_comp can be substantially equal to the value of the second effective bandwidth BWEF2. Furthermore, since the bandwidth control circuit 131_3 compensates for the bandwidth of the drive source signal DVS_src, the value of the second corner frequency FCN2 can be substantially the same as the first corner frequency FCN1. In this way, since the bandwidth control circuit 131_3 compensates for the bandwidth of the drive source signal DVS_src, the first frequency response RSP_FREQ1 and the second frequency response RSP_FREQ2 can have substantially the same amplitude across all frequency bands (and therefore, they can be represented using substantially the same Bode plot).

[0107] Figure 7 This is another example of the functionality of a bandwidth control circuit. Figure 7 The horizontal axis represents the frequency on a logarithmic scale, and the vertical axis represents the magnitude of the frequency response in decibels. For example, Figure 7 This can correspond to a Bode amplitude diagram, which approximates the amplitude of the frequency response.

[0108] Reference Figures 1 to 7 The bandwidth control circuit 131_3 can use a bandwidth extension scheme to adjust the bandwidth of the drive source signal DVS_src. For example, the bandwidth control circuit 131_3 can extend the bandwidth of the drive source signal DVS_src to adjust the first effective bandwidth BWEF1 of the first frequency response REF_FREQ1 according to the second effective bandwidth BWEF2 of the second frequency response REF_FREQ2.

[0109] The descriptions of the first frequency response REF_FREQ1, the second frequency response REF_FREQ2, the first effective bandwidth BWEF1, and the second effective bandwidth BWEF2 are the same as those above. Figure 6 The description is similar, so a detailed description is omitted.

[0110] In other words, with reference Figure 6Unlike the previous description, the bandwidth control circuit 131_3 extends the bandwidth of the drive source signal DVS_src, such that the first compensated effective bandwidth BWEF1_comp is extended according to the second effective bandwidth BWEF2 compared to the first original effective bandwidth BWEF1_raw. For example, when the bandwidth control circuit 131_3 extends the bandwidth of the drive source signal DVS_src, the first original effective bandwidth BWEF1_raw can be extended to the first compensated effective bandwidth BWEF1_comp. In this case, since all frequency components of the power supply voltage VDD noise can be included in the pixel signal SPX and the ramp signal RMP in substantially the same amount, the influence of the power supply voltage VDD noise components on the comparison output signal SCO can be significantly reduced.

[0111] For brevity, the following explanation will use the bandwidth control circuit 131_3 reducing the bandwidth of the drive source signal DVS_src as an example, to compensate the first frequency response REF_FREQ1 according to the second frequency response REF_FREQ2. That is, in the following text, referencing the above... Figure 6 Similarly, it is assumed that the first raw effective bandwidth BWEF1_raw is greater than the first compensated effective bandwidth BWEF1_comp. However, the scope of this disclosure is not limited thereto, and the following description applies equally to configurations with bandwidth expansion rather than reduction.

[0112] Furthermore, the scope of this disclosure is not limited to reference. Figures 6 to 7 The Bode plot is described in the following form. For example, in some implementations, the Bode plot for each frequency response may include two or more corner frequencies.

[0113] Figure 8 This is a diagram illustrating an example of comparing the voltage levels of the output signals. Figure 8 The horizontal axis represents the frequency, and the vertical axis represents the voltage of the comparison output signal SCO.

[0114] In the following text, refer to Figures 1 to 8 Assuming that ramp generator 131 and image pixel PX generate the same voltage, and that the supply voltage VDD includes the same noise component (e.g., 1V) across all frequency bands, accordingly, Figure 8 The comparison output signal SCO indicates the noise component. In this case, if the image pixel PX and the ramp generator 131 operate ideally (e.g., if there is no electrical parasitic capacitance CPV, etc.), the amplitude of the comparison output signal SCO can be "0V" in all frequency bands because the ramp generator 131 and the image pixel PX generate voltages of the same amplitude.

[0115] When the bandwidth control circuit 131_3 does not control the bandwidth of the drive source signal DVS_src, the magnitude of the comparison output signal SCO is shown by the dashed line. Referring to the graph shown by the dashed line, the magnitude of the comparison output signal SCO can be increased in the frequency band above the first corner frequency FCN1. In this case, unlike the ideal operation of the image pixel PX and the ramp generator 131, the noise components in the frequency band above the first corner frequency FCN1 included in the power supply voltage VDD can be amplified by the comparator amplifier 132 and included in the comparison output signal SCO.

[0116] The magnitude of the comparison output signal SCO when the bandwidth control circuit 131_3 controls the bandwidth of the drive source signal DVS_src is represented by the solid line. Referring to the graph shown by the solid line, even in frequency bands higher than the first corner frequency FCN1, the comparison output signal SCO can remain at a magnitude similar to "0V". In this case, similar to the ideal operation of the image pixel PX and the ramp generator 131, the noise component of the pixel signal SPX is canceled out by the noise component of the ramp signal RMP in all frequency bands, so that the comparison output signal SCO may not include (e.g., include very little) the noise component of the power supply voltage VDD.

[0117] Figure 9 This is a graph illustrating an example of the power supply rejection ratio (PSRR) of an image sensor device. Figure 9 The horizontal axis represents frequency, and the vertical axis represents the magnitude of PSRR.

[0118] Reference Figures 1 to 9 PSRR indicates the tolerance of the image sensor device 100 to noise from the power supply voltage VDD. For example, PSRR can be defined based on the following Equation 1.

[0119] Equation 1

[0120] Referring to Equation 1, Indicates the size of PSRR, This represents the noise of the power supply voltage VDD, and This indicates that the noise of the output signal SCO is compared. Therefore, in an ideal scenario, PSRR can have a very high value because... It can be close to "0" and then ignore it. How big is it?

[0121] In some implementations, a larger PSRR can result in less noise included in the comparison output signal SCO. The smaller the PSRR, the greater the noise included in the comparison output signal SCO.

[0122] In some implementations, the target PSRR value PSRR_TG can be used as a criterion for determining whether the noise included in the comparison output signal SCO is small enough to be negligible (e.g., such that the noise is not visible in the image generated by the image sensor device 100). For example, when the PSRR is greater than the target PSRR value PSRR_TG, the noise included in the comparison output signal SCO may be small enough to be negligible. When the PSRR is less than the target PSRR value PSRR_TG, the noise included in the comparison output signal SCO may be too large to be negligible.

[0123] When the bandwidth control circuit 131_3 does not control the bandwidth of the drive source signal DVS_src, the magnitude of PSRR is shown by the dashed line. Referring to the graph shown by the dashed line, in some frequency bands above the first corner frequency FCN1, the magnitude of PSRR can be lower than the target PSRR value PSRR_TG. That is, if the bandwidth control circuit 131_3 does not control the bandwidth of the drive source signal DVS_src, there can be frequency bands where the magnitude of PSRR is lower than the target PSRR value PSRR_TG, and in such frequency bands, the noise of the power supply voltage VDD can be significantly reflected in the comparison output signal SCO. In this case, due to the noise in the comparison output signal SCO, errors may occur in the digital signal DS, and horizontal noise may appear in the image generated by the image sensor device 100.

[0124] When the bandwidth control circuit 131_3 controls the bandwidth of the drive source signal DVS_src, the magnitude of PSRR is shown as a solid line. Referring to the graph shown by the solid line, the magnitude of PSRR in all frequency bands can be greater than the target PSRR value PSRR_TG. In this case, the noise of the comparison output signal SCO in all frequency bands can be sufficiently small to be negligible, and the noise of the image generated by the image sensor device 100 can be significantly reduced.

[0125] Figure 10 and Figure 11 It shows a bandwidth control circuit (e.g., Figure 4 A diagram illustrating an example of a bandwidth control circuit (in the example). See below for reference. Figure 10 This describes an example of the bandwidth control circuit 131_3 being implemented as a first-order low-pass filter, and refers to... Figure 11 The present invention describes an example of the bandwidth control circuit 131_3 being implemented as a second-order low-pass filter. However, the scope of this disclosure is not limited to these circuit types of the bandwidth control circuit 131_3. For example, the bandwidth control circuit 131_3 may be implemented as a high-order low-pass filter, a band-pass filter, or a bandwidth extension circuit.

[0126] First, refer to Figures 1 to 10The bandwidth control circuit 131_3 may include a first resistor R1 and a first bandwidth control capacitor CBWC1.

[0127] The first bandwidth control capacitor CBWC1 can be connected between the first filter node NF1 and the ground voltage VSS. The first resistor R1 can be connected between the bandwidth control input node NBCI and the first filter node NF1. The first filter node NF1 can be connected to the bandwidth control output node NBCO.

[0128] In some embodiments, the first resistor R1 may be a parasitic resistance between the bandwidth control input node NBCI and the first filter node NF1. However, the scope of this disclosure is not limited thereto, and the first resistor R1 may be a resistor intentionally connected between the bandwidth control input node NBCI and the first filter node NF1.

[0129] In some implementations, a resistor may also be connected between the first filter node NF1 and the bandwidth control output node NBCO. However, the scope of this disclosure is not limited thereto.

[0130] The bandwidth control circuit 131_3 can receive the drive source signal DVS_src through the bandwidth control input node NBCI and output the drive signal DVS through the bandwidth control output node NBCO. In other words, the bandwidth control circuit 131_3 can generate the drive signal DVS by performing low-pass filtering on the drive source signal DVS_src.

[0131] When the bandwidth control circuit 131_3 performs low-pass filtering on the drive source signal DVS_src, the degree to which the first frequency response RSP_FREQ1 is adjusted can be determined based on the capacitance of the first bandwidth control capacitor CBWC1. For example, the difference between the first raw effective bandwidth BWEF1_raw and the first compensated effective bandwidth BWEF1_comp can be determined by the capacitance of the first bandwidth control capacitor CBWC1.

[0132] For example, the capacitance of the first bandwidth control capacitor CBWC1 can be determined such that the first compensated effective bandwidth BWEF1_comp becomes similar to the second effective bandwidth BWEF2. For example, the capacitance of the first bandwidth control capacitor CBWC1 can be determined based on the second effective bandwidth BWEF2 and the equivalent resistance between the supply voltage VDD and the first comparator input node NCPI1.

[0133] In some embodiments, the first bandwidth control capacitor CBWC1 can be implemented as a variable capacitor. In this case, the capacitance of the first bandwidth control capacitor CBWC1 can be determined based on simulation results for the second effective bandwidth BWEF2 performed during the production phase of the image sensor device 100. However, the scope of this disclosure is not limited thereto.

[0134] Next, refer to Figures 1 to 9 as well as Figure 11 The bandwidth control circuit 131_3 may include a second resistor R2 and a third resistor R3, as well as a second bandwidth control capacitor CBWC2 and a third bandwidth control capacitor CBWC3.

[0135] The second bandwidth control capacitor CBWC2 can be connected between the second filter node NF2 and ground voltage VSS. The third bandwidth control capacitor CBWC3 can be connected between the third filter node NF3 and ground voltage VSS. The second resistor R2 can be connected between the bandwidth control input node NBCI and the second filter node NF2. The second resistor R2 can also be connected between the second filter node NF2 and the third filter node NF3. The third filter node NF3 can be connected to the bandwidth control output node NBCO.

[0136] The capacitance of each bandwidth control capacitor in the second bandwidth control capacitor CBWC2 and the third bandwidth control capacitor CBWC3 can be determined such that the first compensated effective bandwidth BWEF1_comp becomes similar to the second effective bandwidth BWEF2. The method for determining the capacitance of each bandwidth control capacitor in the second bandwidth control capacitor CBWC2 and the third bandwidth control capacitor CBWC3 is the same as described above. Figure 10 The method described is similar, therefore a detailed description is omitted.

[0137] Figure 12 It shows an analog-to-digital converter (e.g., Figure 1 A diagram illustrating an example configuration of the analog-to-digital converter (ADC). See also... Figures 1 to 12 The analog-to-digital converter 130 can be implemented as Figure 12 The analog-to-digital converter 230 is shown. In the following text, the differences between analog-to-digital converter 130 and analog-to-digital converter 230 will be mainly described, and except for the differences indicated or implied by the context, analog-to-digital converter 230 may be substantially similar to analog-to-digital converter 130.

[0138] The analog-to-digital converter 230 may include a ramp source circuit 131_1, a driver source circuit 131_2, first comparator amplifiers 132a to fourth comparator amplifiers 132d, and first ADC circuits 133a to fourth ADC circuits 133d. The configuration and operation of each of the ramp source circuit 131_1, driver source circuit 131_2, first comparator amplifiers 132a to fourth comparator amplifiers 132d, and first ADC circuits 133a to fourth ADC circuits 133d are as described above. Figures 1 to 11 The configuration and operation are similar, and therefore, detailed descriptions are omitted.

[0139] The analog-to-digital converter 230 may include a bandwidth control circuit 131_3 and a ramp buffer circuit RBF configured for each pixel column. For example, the analog-to-digital converter 230 may include first bandwidth control circuits 131_3a to fourth bandwidth control circuits 131_3d, and first ramp buffer circuits RBFa to fourth ramp buffer circuits RBFd. The first bandwidth control circuits 131_3a to fourth bandwidth control circuits 131_3d and the first ramp buffer circuits RBFa to fourth ramp buffer circuits RBFd correspond to first data lines DLa to fourth data lines DLd, respectively.

[0140] Each of the first bandwidth control circuits 131_3a to the fourth bandwidth control circuits 131_3d can receive a drive source signal DVS_src from the drive source circuit 131_2. The first bandwidth control circuits 131_3a to the fourth bandwidth control circuits 131_3d can generate the first drive signal DVSa to the fourth drive signal DVSd respectively by controlling the bandwidth of the drive source signal DVS_src.

[0141] Each of the first ramp buffer circuits RBFa to the fourth ramp buffer circuit RBFd can receive the original ramp signal RMP_raw from the ramp source circuit 131_1. Each of the first ramp buffer circuits RBFa to the fourth ramp buffer circuit RBFd can receive the first drive signal DVSa to the fourth drive signal DVSd, respectively. Each of the first ramp buffer circuits RBFa to the fourth ramp buffer circuit RBFd can generate the ramp signal RMP based on the received original ramp signal RMP_raw and the drive signal DVS. For example, the first ramp buffer circuits RBFa to the fourth ramp buffer circuit RBFd can generate the first ramp signal RMPa to the fourth ramp signal RMPd, respectively.

[0142] The first comparator amplifiers 132a to the fourth comparator amplifiers 132d can respectively receive the first ramp signal RMPa to the fourth ramp signal RMPd. In this case, the distance between the ramp buffer circuit RBF and the comparator amplifier 132 in each pixel column can be made uniform, and the distance between the bandwidth control circuit 131_3 and the ramp buffer circuit RBF in each pixel column can also be made uniform. Therefore, based on such Figure 12 The configuration shown can reduce errors caused by differences in the physical location of each pixel column between the comparison output signals SCO. However, the scope of this disclosure is not limited thereto.

[0143] In some embodiments, the analog-to-digital converter 230 may include one or more ramp source circuits 131_1 and / or one or more drive source circuits 131_2 for each pixel column. However, the scope of this disclosure is not limited thereto.

[0144] Figure 13 This is a diagram showing a portion of an example of an image sensor device. References will be made below. Figures 1 to 11 and Figure 13 Describes the configuration corresponding to a column of pixels.

[0145] The image sensor device 100 may include an image pixel PX, a ramp generator 231, a bandwidth control circuit BCC, and a comparator amplifier 132a.

[0146] The ramp generator 231 can be referenced above. Figures 4 to 11 The described ramp generator 131 is implemented similarly. For example, ramp generator 231 can generate a ramp signal RMP based on the power supply voltage VDD.

[0147] Image pixel PX can be connected to the first data line Dla. The bandwidth control circuit BCC can be connected between the first data line Dla and the comparator amplifier 132a. The bandwidth control circuit BCC can be referenced above. Figures 4 to 11 The bandwidth control circuit 131_3 described is implemented similarly.

[0148] In other words, the bandwidth control circuit BCC can be connected to the first data line Dla. In this case, the bandwidth control circuit BCC can control the bandwidth of the pixel signal SPX provided from the image pixel PX based on the effective bandwidth of the ramp signal RMP. For example, the bandwidth control circuit BCC can adjust the bandwidth of the pixel signal SPX to make it more similar to the bandwidth of the ramp signal RMP. However, the scope of this disclosure is not limited thereto.

[0149] In some implementations, the first data line DLa may also be connected to a first current source CSa, as previously referenced. Figure 2 However, the scope of this disclosure is not limited thereto.

[0150] For the sake of brevity, Figure 13 An example is typically shown with the bandwidth control circuit BCC connected between the first data line DLa and the second compare input node NCPI2, but the connection configuration of the bandwidth control circuit BCC is not limited to this. For example, the bandwidth control circuit BCC may be connected between the drive transistor DT and the select transistor ST, or between the select transistor ST and the first data line DLa.

[0151] Figure 14 This is a block diagram of an example electronic device that includes a multi-camera module. (See reference...) Figure 14 The electronic device 2000 may include a camera module group 2100, an application processor 2200, a PMIC 2300, and an external memory 2400.

[0152] The camera module group 2100 may include multiple camera modules 2100a, 2100b and 2100c. Figure 14 An electronic device comprising three camera modules 2100a, 2100b, and 2100c is shown, but this disclosure is not limited thereto. In some embodiments, the camera module group 2100 may comprise only two camera modules. Furthermore, in some embodiments, the camera module group 2100 may be modified to comprise “i” camera modules (i being a natural number of 4 or greater).

[0153] Figure 15 It shows in detail Figure 14 The block diagram of the camera module is shown below. Figure 15 The detailed configuration of camera module 2100b is described in more detail, but the following description also applies to the other camera modules 2100a and 2100c.

[0154] Reference Figure 15 The camera module 2100b may include a prism 2105, an optical path folding element (OPFE) 2110, an actuator 2130, an image sensing device 2140, and a storage device 2150.

[0155] The prism 2105 may include a reflective surface 2107 made of reflective material and may change the path of light “L” incident from the outside.

[0156] In some embodiments, prism 2105 can change the path of light "L" incident in the first direction (X) to a second direction (Y) perpendicular to the first direction (X). Furthermore, prism 2105 can change the path of light "L" incident in the first direction (X) to a second direction (Y) perpendicular to the first direction (X-axis) by rotating the reflective surface 2107, made of reflective material, about the central axis 2106 in direction "A" or by rotating the central axis 2106 in direction "B". In this case, OPFE 2110 can move along a third direction (Z) perpendicular to the first direction (X) and the second direction (Y).

[0157] In some implementations, such as Figure 15 As shown, the maximum rotation angle of prism 2105 in the "A" direction can be equal to or less than 15 degrees in the positive A direction and greater than 15 degrees in the negative A direction, but this disclosure is not limited thereto.

[0158] In some embodiments, prism 2105 can be moved within about 20 degrees, between 10 degrees and 20 degrees, or between 15 degrees and 20 degrees in the positive B direction or negative B direction; in this case, prism 2105 can be moved at the same angle in the positive B direction or negative B direction, or can be moved at similar angles within about 1 degree.

[0159] In some embodiments, the prism 2105 can move the reflective surface 2107, made of reflective material, in a third direction (e.g., the Z direction) parallel to the extension direction of the central axis 2106.

[0160] For example, OPFE 2110 may include optical lenses consisting of "m" groups (j being a natural number). These "m" lenses can be moved in a second direction (Y) to change the optical zoom ratio of camera module 2100b. For instance, when the default optical zoom ratio of camera module 2100b is "Z", by moving the "m" optical lenses included in OPFE 2110, the optical zoom ratio of camera module 2100b can be changed to 3Z, 5Z, or a larger optical zoom ratio.

[0161] Actuator 2130 can move OPFE 2110 or optical lens (hereinafter referred to as "optical lens") to a specific position. For example, actuator 2130 can adjust the position of optical lens so that image sensor 2142 is placed at the focal length of optical lens to achieve precise sensing.

[0162] Image sensing device 2140 may include image sensor 2142, control logic 2144, and memory 2146. Image sensor 2142 can sense an image of a target by using light "L" provided by an optical lens.

[0163] In some implementations, the image sensor 2142 may employ the same design described above. Figures 1 to 13 The image sensor device 100 described herein is implemented in a similar manner and can operate in a similar way.

[0164] In some implementations, the image sensor 2142 may include image pixels PX, a ramp generator 131, and a comparator amplifier 132. The image pixels PX and the ramp generator 131 may share a power supply voltage VDD. The image pixels PX may generate pixel signals SPX and the ramp generator 131. The ramp generator 131 may control the frequency response between the power supply voltage VDD and the ramp signal RMP based on the frequency response between the power supply voltage VDD and the pixel signal SPX. For example, the ramp generator 131 may include bandwidth control circuitry 131_3. Control logic 2144 may control the overall operation of the camera module 2100b. For example, control logic 2144 may control the operation of the camera module 2100b based on control signals provided via control signal line CSLb.

[0165] Memory 2146 may store information required for the operation of camera module 2100b, such as calibration data 2147. Calibration data 2147 may include information required by camera module 2100b to generate image data using externally provided light "L". Calibration data 2147 may include, for example, information about the aforementioned rotation, information about the focal length, information about the optical axis, etc. In the case where camera module 2100b is implemented as a multi-state camera (where the focal length varies depending on the position of the optical lens), calibration data 2147 may include the focal length value for each position (or state) of the optical lens and information about autofocus.

[0166] Storage device 2150 can store image data sensed by image sensor 2142. Storage device 2150 can be disposed outside image sensor 2142 and can be implemented in a form where storage device 2150 is stacked together with the sensor chip constituting image sensor 2142. In some embodiments, storage device 2150 can be implemented with electrically erasable programmable read-only memory (EEPROM), but this disclosure is not limited thereto.

[0167] Refer to together Figure 14 and Figure 15 In some embodiments, each of the plurality of camera modules 2100a, 2100b, and 2100c may include an actuator 2130. Therefore, the plurality of camera modules 2100a, 2100b, and 2100c may include the same calibration data 2147 or different calibration data 2147, depending on the operation of the actuator 2130 therein.

[0168] In some embodiments, one of the multiple camera modules 2100a, 2100b and 2100c (e.g. 2100b) may be a folding lens-shaped camera module, including the aforementioned prism 2105 and OPFE 2110, and the remaining camera modules (e.g. 2100a and 2100c) may be vertically shaped camera modules, excluding the aforementioned prism 2105 and OPFE 2110; however, this disclosure is not limited thereto.

[0169] In some implementations, one of the multiple camera modules 2100a, 2100b, and 2100c (e.g., 2100c) may be, for example, a vertically shaped depth camera that extracts depth information using infrared (IR). In this case, the application processor 2200 may merge image data provided from the depth camera with image data provided from any other camera module (e.g., 2100a or 2100b) to generate a three-dimensional (3D) depth image.

[0170] In some embodiments, at least two of the plurality of camera modules 2100a, 2100b, and 2100c (e.g., 2100a and 2100b) may have different fields of view. In this case, at least two of the plurality of camera modules 2100a, 2100b, and 2100c (e.g., 2100a and 2100b) may include different optical lenses, but this disclosure is not limited thereto.

[0171] Furthermore, in some embodiments, the fields of view of the multiple camera modules 2100a, 2100b, and 2100c may be different. In this case, the multiple camera modules 2100a, 2100b, and 2100c may include different optical lenses, but are not limited thereto.

[0172] In some implementations, the multiple camera modules 2100a, 2100b, and 2100c can be configured to be physically separated from each other. That is, the multiple camera modules 2100a, 2100b, and 2100c may not use the sensing area of ​​a single image sensor 2142, but rather the multiple camera modules 2100a, 2100b, and 2100c may each include an independent image sensor 2142.

[0173] return Figure 14 The application processor 2200 may include an image processing device 2210, a memory controller 2220, and internal memory 2230. The application processor 2200 may be implemented separately from the multiple camera modules 2100a, 2100b, and 2100c. For example, the application processor 2200 and the multiple camera modules 2100a, 2100b, and 2100c may be implemented using separate semiconductor chips.

[0174] The image processing device 2210 may include a plurality of sub-image processors 2212a, 2212b and 2212c, an image generator 2214 and a camera module controller 2216.

[0175] The image processing device 2210 may include a plurality of sub-image processors 2212a, 2212b and 2212c, the number of which corresponds to the number of the plurality of camera modules 2100a, 2100b and 2100c.

[0176] Image data generated from camera modules 2100a, 2100b, and 2100c can be provided to corresponding sub-image processors 2212a, 2212b, and 2212c via separate image signal lines ISLa, ISLb, and ISLc, respectively. For example, image data generated from camera module 2100a can be provided to sub-image processor 2212a via image signal line ISLa, image data generated from camera module 2100b can be provided to sub-image processor 2212b via image signal line ISLb, and image data generated from camera module 2100c can be provided to sub-image processor 2212c via image signal line ISLc. This image data transmission can be performed, for example, using a camera serial interface (CSI) based on MIPI (Mobile Industry Processor Interface), but this disclosure is not limited thereto.

[0177] Furthermore, in some implementations, a sub-image processor can be configured to correspond to multiple camera modules. For example, sub-image processor 2212a and sub-image processor 2212c can be implemented as a single unit, rather than being separate from each other, as shown below. Figure 14 As shown; in this case, one of the image data provided from camera module 2100a and camera module 2100c can be selected by a selection element (e.g., a multiplexer), and the selected image data can be provided to the integrated sub-image processor.

[0178] Image data provided to sub-image processors 2212a, 2212b, and 2212c can be provided to image generator 2214. Image generator 2214 can generate an output image based on image generation information or pattern signals by using the image data provided from sub-image processors 2212a, 2212b, and 2212c.

[0179] For example, image generator 2214 can generate an output image by merging at least a portion of image data generated from camera modules 2100a, 2100b, and 2100c, which have different fields of view, based on image generation information or a pattern signal. Furthermore, image generator 2214 can generate an output image by selecting one of the image data generated from camera modules 2100a, 2100b, and 2100c, which have different fields of view, based on image generation information or a pattern signal.

[0180] In some implementations, the image generation information may include a scaling signal or a scaling factor. Furthermore, in some implementations, the mode signal may be, for example, a signal based on a mode selected by the user.

[0181] In some implementations, the image sensor 2142 of each camera module 2100a, 2100b, 2100c can be implemented as described above. Figures 1 to 13 The image sensor device 100 is described. In this case, the impact of power supply voltage VDD noise on the image data generated by each camera module 2100a, 2100b, 2100c can be reduced. Therefore, the horizontal noise HN of the image generated by image generator 2214 can be reduced.

[0182] When the image generation information is a scaling signal (or scaling factor) and camera modules 2100a, 2100b, and 2100c have different fields of view, image generator 2214 can perform different operations depending on the type of scaling signal. For example, when the scaling signal is a first signal, image generator 2214 can merge image data output from camera module 2100a and image data output from camera module 2100c, and generate an output image by using the merged image signal and image data output from camera module 2100b that was not used in the merging operation. When the scaling signal is a second signal different from the first signal, no image data merging operation is performed, and image generator 2214 can select one of the image data output from camera modules 2100a, 2100b, and 2100c respectively, and can output the selected image data as the output image. However, this disclosure is not limited to this, and the way image data is processed can be modified as needed without limitation.

[0183] In some implementations, the image generator 2214 can generate merged image data with increased dynamic range by receiving multiple image data with different exposure times from at least one of multiple sub-image processors 2212a, 2212b and 2212c and performing high dynamic range (HDR) processing on the multiple image data.

[0184] The camera module controller 2216 can provide control signals to camera modules 2100a, 2100b, and 2100c respectively. The control signals generated by the camera module controller 2216 can be provided to the corresponding camera modules 2100a, 2100b, and 2100c respectively through separate control signal lines CSLa, CSLb, and CSLc.

[0185] One of the multiple camera modules 2100a, 2100b, and 2100c can be designated as the master camera (e.g., 2100b) based on image generation information including a scaling signal or a mode signal, and the remaining camera modules (e.g., 2100a and 2100c) can be designated as slave cameras. This designation information can be included in control signals, and these control signals, including the designation information, can be provided to the corresponding camera modules 2100a, 2100b, and 2100c respectively via separate control signal lines CSLa, CSLb, and CSLc.

[0186] Depending on the scaling factor or operating mode signal, the camera module operating as the master camera and the slave camera can be changed. For example, when the field of view of camera module 2100a is larger than that of camera module 2100b and the scaling factor indicates a low scaling rate, camera module 2100b can operate as the master camera, and camera module 2100a can operate as the slave camera. Conversely, when the scaling factor indicates a high scaling rate, camera module 2100a can operate as the master camera, and camera module 2100b can operate as the slave camera.

[0187] In some implementations, the control signals provided from the camera module controller 2216 to each camera module 2100a, 2100b, and 2100c may include a synchronization enable signal. For example, when camera module 2100b is used as the main camera and camera modules 2100a and 2100c are used as slave cameras, the camera module controller 2216 may send a synchronization enable signal to camera module 2100b. Camera module 2100b, equipped with the synchronization enable signal, may generate a synchronization signal based on the provided synchronization enable signal and provide the generated synchronization signal to camera modules 2100a and 2100c via the synchronization signal line SSL. Camera modules 2100b and 2100a and 2100c may be synchronized via the synchronization signal to send image data to application processor 2200.

[0188] In some implementations, the control signals provided from the camera module controller 2216 to each camera module 2100a, 2100b, and 2100c may include mode information based on a mode signal. Based on the mode information, the multiple camera modules 2100a, 2100b, and 2100c may operate in a first operating mode and a second operating mode, depending on the sensing speed.

[0189] In the first operating mode, multiple camera modules 2100a, 2100b, and 2100c can generate image signals at a first speed (e.g., generate image signals at a first frame rate), encode the image signals at a second speed (e.g., encode image signals at a second frame rate higher than the first frame rate), and send the encoded image signals to the application processor 2200. In this case, the second speed can be 30 times or less than the first speed.

[0190] Application processor 2200 can store the received image signal (i.e., the encoded image signal) in built-in memory 2230 or in external memory 2400 located outside application processor 2200. Then, application processor 2200 can read the encoded image signal from memory 2230 or external memory 2400 and decode the encoded image signal, and can display image data generated based on the decoded image signal. For example, one of the sub-image processors 2212a, 2212b, and 2212c of image processing device 2210 can perform decoding and can also perform image processing on the decoded image signal.

[0191] In the second operating mode, multiple camera modules 2100a, 2100b, and 2100c can generate image signals at a third speed (e.g., they can generate image signals at a third frame rate lower than the first frame rate) and send the image signals to the application processor 2200. The image signals provided to the application processor 2200 can be unencoded signals. The application processor 2200 can perform image processing on the received image signals, or it can store the image signals in memory 2230 or external memory 2400.

[0192] The PMIC 2300 can supply power to multiple camera modules 2100a, 2100b, and 2100c respectively, for example, by providing power supply voltage. For example, under the control of the application processor 2200, the PMIC 2300 can provide a first power supply to camera module 2100a via power signal line PSLa, a second power supply to camera module 2100b via power signal line PSLb, and a third power supply to camera module 2100c via power signal line PSLc.

[0193] In response to a power control signal PCON from application processor 2200, PMIC 2300 can generate a power supply corresponding to each of the plurality of camera modules 2100a, 2100b, and 2100c, and can adjust the power supply level. The power control signal PCON can include a power adjustment signal for each operating mode of the plurality of camera modules 2100a, 2100b, and 2100c. For example, the operating mode can include a low-power mode. In this case, the power control signal PCON can include information about the camera module operating in the low-power mode and the set power supply level. The power levels supplied to the plurality of camera modules 2100a, 2100b, and 2100c can be the same or different from each other. Furthermore, the power supply level can change dynamically.

[0194] While this disclosure contains numerous specific implementation details, these details should not be construed as limiting the scope of the claims. Certain features described in the context of standalone embodiments in this disclosure may also be implemented in combination in a single embodiment. Conversely, such features described in the context of a single embodiment may also be implemented individually in multiple embodiments, or in any suitable sub-combination. Furthermore, although the foregoing features may be described as functioning in certain combinations, in some cases, one or more features in the combination may be removed from the combination, and the combination may be for sub-combinations or variations thereof.

[0195] Although examples have been described in detail above, the scope of this disclosure is not limited thereto, and various modifications and improvements made by those skilled in the art also fall within the scope of this disclosure.

Claims

1. An image sensor device, comprising: Image pixels are configured to generate pixel signals based on light; A ramp generator, comprising: The ramp source circuit is configured to generate a first ramp signal; The driver source circuit is configured to generate a driver source signal; A bandwidth control circuit is configured to generate a drive signal by adjusting the bandwidth of the drive source signal; and A ramp buffer circuit is configured to generate a second ramp signal corresponding to the first ramp signal based on the drive signal; The comparator amplifier is configured to generate a comparator output signal based on the pixel signal and the second ramp signal; and An analog-to-digital converter circuit is configured to generate a digital signal corresponding to the light based on the comparison output signal.

2. The image sensor device according to claim 1, wherein, The image pixels are configured to operate based on a power supply voltage provided through a power line, and the ramp generator is configured to operate based on the power supply voltage provided through the power line.

3. The image sensor device according to claim 2, wherein, The image pixels include: A photodiode is configured to receive the light; A transmission transistor is connected between the photodiode and the floating diffusion node, wherein the gate of the transmission transistor is configured to receive a transmission signal; A reset transistor is connected between the power line and the floating diffusion node, wherein the gate of the reset transistor is configured to receive a reset signal; A driving transistor is connected between the power line and the intermediate node, wherein the gate of the driving transistor is configured to receive the voltage level of the floating diffusion node; and A selection transistor is connected between the intermediate node and the data line, wherein the selection transistor is configured to provide the pixel signal to the data line in response to a selection signal.

4. The image sensor device according to claim 3, wherein: The driving source circuit includes a capacitor replication circuit, and The driving source circuit is configured to provide the noise component of the power supply voltage to the driving source signal based on the capacitor replication circuit.

5. The image sensor device according to claim 4, wherein: The capacitor replication circuit includes a first capacitor and a second capacitor connected in series between the power line and ground voltage, and The first capacitance ratio of the capacitance of the first capacitor to the capacitance of the second capacitor is matched with the second capacitance ratio of the capacitance between the power line and the floating diffusion node to the floating diffusion capacitance of the image pixel.

6. The image sensor device according to claim 4, wherein, The driving source circuit is configured to generate the driving source signal based on the bias current source and the capacitor replication circuit.

7. The image sensor device according to claim 1, wherein, The bandwidth control circuit is configured to generate the drive signal by low-pass filtering the drive source signal.

8. The image sensor device according to claim 7, wherein, The bandwidth control circuit includes a low-pass filter configured to perform the low-pass filtering, wherein the low-pass filter includes: A bandwidth control input node is configured to receive the drive source signal; A bandwidth control output node is configured to output the drive signal; and A filter node is connected between the bandwidth control input node and the bandwidth control output node; A bandwidth control capacitor is connected between the filter node and ground voltage.

9. The image sensor device according to claim 8, wherein, The capacitance of the bandwidth control capacitor is determined based on the frequency response between the power supply voltage and the pixel signal.

10. The image sensor device according to claim 1, wherein, The bandwidth control circuit is configured to generate the drive signal by expanding the bandwidth of the drive source signal.

11. The image sensor device according to claim 1, wherein, The ramp buffer circuit includes: The buffered output node is configured to output the second ramp signal; A buffer transistor is connected between the buffer output node and ground voltage, wherein the gate of the buffer transistor is configured to receive the first ramp signal; and A current source transistor is connected between the power supply voltage and the buffer output node, wherein the gate of the current source transistor is configured to receive the drive signal.

12. An image sensor device, comprising: Image pixel array, including first image pixels, The first image pixel is configured to operate based on the power supply voltage provided from the power line. Wherein, the first image pixel is configured to generate a first pixel signal based on the voltage level of the first floating diffusion node, and Specifically, based on the first electrical parasitic capacitance between the power line and the first floating diffusion node, a noise component of the power supply voltage is provided to the first pixel signal; and ramp generator, The ramp generator is configured to operate based on the power supply voltage provided from the power line, and The ramp generator is configured to generate a first reference ramp signal. The ramp generator includes: The driver source circuit is configured to generate a driver source signal. The driving source circuit includes a capacitor replication circuit. The driving source circuit is configured to provide the noise component to the driving source signal based on the capacitor replication circuit. A first bandwidth control circuit is configured to generate a first drive signal by adjusting the bandwidth of the drive source signal, and The first ramp buffer circuit is configured to generate the first reference ramp signal based on the first drive signal.

13. The image sensor device according to claim 12, comprising: A first comparator amplifier is configured to generate a first comparator output signal based on the first pixel signal and the first reference ramp signal; as well as An analog-to-digital converter circuit is configured to generate a digital signal based on the first comparison output signal.

14. The image sensor device according to claim 12, wherein, The first bandwidth control circuit is configured to generate the first drive signal by performing low-pass filtering or bandwidth expansion on the drive source signal.

15. The image sensor device according to claim 12, wherein: The ramp generator includes a ramp source circuit configured to generate a first ramp signal, and The first ramp buffer circuit includes: The buffered output node is configured to output the first reference ramp signal; A buffer transistor is connected between the buffer output node and ground voltage, wherein the gate of the buffer transistor is configured to receive the first ramp signal; and A current source transistor is connected between the power supply line and the buffer output node, wherein the gate of the current source transistor is configured to receive the first drive signal.

16. The image sensor device according to claim 12, wherein: The image pixel array also includes a second image pixel. The second image pixel is configured to operate based on the power supply voltage provided from the power line, and Wherein, the second image pixel is configured to generate a second pixel signal based on the voltage level of the second floating diffusion node; and The ramp generator also includes: The second bandwidth control circuit is configured to generate a second drive signal by adjusting the bandwidth of the drive source signal; and The second ramp buffer circuit is configured to generate a second reference ramp signal based on the second drive signal; The image sensor device also includes: The second comparator amplifier is configured to generate a second comparator output signal based on the second pixel signal and the second reference ramp signal.

17. An analog-to-digital converter, comprising: A ramp generator is configured to generate a ramp signal based on the power supply voltage. A comparator amplifier is configured to generate a comparator output signal based on the ramp signal and a pixel signal provided from an image pixel, wherein the image pixel is configured to operate based on the power supply voltage; and An analog-to-digital converter circuit is configured to generate a digital signal based on the comparison output signal. The ramp generator includes a bandwidth control circuit, which is configured to adjust a second effective bandwidth of a second frequency response between the power supply voltage and the ramp signal based on a first effective bandwidth of a first frequency response between the power supply voltage and the pixel signal.

18. The analog-to-digital converter according to claim 17, wherein: The ramp generator also includes a drive source circuit, a ramp source circuit, and a ramp buffer circuit. The drive source circuit is configured to generate a drive source signal. The ramp source circuit is configured to generate the original ramp signal. The bandwidth control circuit is configured to generate a drive signal by adjusting the bandwidth of the drive source signal, and The ramp buffer circuit is configured to generate the ramp signal based on the original ramp signal and the drive signal.

19. The analog-to-digital converter according to claim 18, wherein, The ramp buffer circuit includes: A buffered output node is configured to output the ramp signal; A buffer transistor is connected between the buffer output node and ground voltage, wherein the gate of the buffer transistor is configured to receive the original ramp signal; and A current source transistor is connected between the power supply voltage and the buffer output node, wherein the gate of the current source transistor is configured to receive the drive signal.

20. The analog-to-digital converter according to claim 19, wherein, The driving source circuit includes: A bias current source is connected between the power supply voltage and the first node; A first transistor includes a first gate terminal connected to a second node, wherein the first transistor is connected between the first node and the ground voltage; The second transistor includes a second gate terminal connected to the second node, wherein the second transistor is connected between the third node and the ground voltage; The third transistor includes a third gate terminal connected to a bandwidth control input node, the drive source signal being output at the bandwidth control input node, wherein the third transistor is connected between the third node and the power supply voltage; A first capacitor is connected between the second node and the power supply voltage; and The second capacitor is connected between the second node and the ground voltage. The first node and the second node are connected to each other, the third node and the bandwidth control input node are connected to each other, and the bandwidth control circuit is connected between the bandwidth control input node and the bandwidth control output node that outputs the drive signal.

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