Multiple-sampling, charge-shared thermometer in a memory device

Abstract

The subject application relates to multi-sampling, charge-sharing thermometers in memory devices. A memory device includes an array of memory cells, a diode having a threshold voltage that changes with temperature, an analog-to-digital converter (ADC), and a pulse generator. The ADC includes a voltage comparator having a positive terminal coupled with the diode. The ADC further includes a first capacitor coupled between a negative terminal of the voltage comparator and ground, and a second capacitor selectively coupled between the first capacitor and a voltage reference node. The second capacitor has a smaller capacitance than a capacitance of the first capacitor. The pulse generator is coupled with the ADC and generates a pulse. The pulse causes the first capacitor to connect to the second capacitor and equalize a charge between the first capacitor and the second capacitor. An inverse of the pulse causes the second capacitor to couple with the voltage reference node to pre-charge the first capacitor.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to multi-sampling, charge-sharing thermometers in memory devices. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] One aspect of this disclosure provides a memory device comprising: an array of memory cells; a diode having a threshold voltage that varies with temperature; an analog-to-digital converter (ADC) coupled to the array and including: a voltage comparator having a positive terminal coupled to the diode; a first capacitor coupled between the negative terminal of the voltage comparator and ground; and a second capacitor selectively coupled between the first capacitor and a voltage reference node, the second capacitor also being coupled to ground and having a capacitance smaller than that of the first capacitor; and a pulse generator coupled to the ADC and generating a pulse, wherein the pulse causes the first capacitor to connect to the second capacitor and equalize the charge between the first and second capacitors, and wherein an inverted signal of the pulse causes the second capacitor to couple to the voltage reference node to precharge the first capacitor.

[0004] Another aspect of this disclosure provides a system comprising: one or more memory dies; a diode having a temperature-dependent threshold voltage; an analog-to-digital converter (ADC) coupled to the one or more memory dies, the ADC including: a voltage comparator having a positive terminal coupled to the diode; a first capacitor coupled between the negative terminal of the voltage comparator and ground; a first switch selectively coupled to the first capacitor; a second switch selectively coupled between the first switch and a voltage reference node; and a second capacitor selectively connected between the first switch and the second switch, the second capacitor also coupled to ground; a pulse generator coupled to the ADC, the pulse generator being configured to generate a pulse that closes the first switch, thereby causing the first and second capacitors to be charged equally; and an inverter coupled between the pulse generator and the second switch, the inverter being configured to output an inverted signal that closes the second switch, thereby causing the second capacitor to be precharged via the voltage reference node.

[0005] Another aspect of this disclosure provides a method of operating a memory device, the memory device comprising: a memory array; a diode having a threshold voltage that varies with temperature; and an analog-to-digital converter (ADC) coupled to the memory array, the ADC comprising: a voltage comparator having a positive terminal coupled to the diode; a first capacitor coupled between the negative terminal of the voltage comparator and ground; and a second capacitor selectively coupled between the first capacitor and a voltage reference node, the second capacitor also being coupled to ground and having a capacitance less than that of the first capacitor, and wherein the method of operating the memory device comprises: directing a pulse generator to generate pulses, wherein the pulses will cause the first capacitor to connect to the second capacitor and equalize the charge between the first and second capacitors; generating an inverted signal from the pulses, the inverted signal causing the second capacitor to couple to the voltage reference node to precharge the first capacitor prior to the equalization of the charge between the first and second capacitors; and tracking the number of values ​​output by the voltage comparator to determine a temperature value of the diode. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of some embodiments thereof.

[0007] Figure 1A This describes an instance computing system including a memory subsystem according to some embodiments.

[0008] Figure 1B This is a block diagram of a memory device communicating with a memory subsystem controller of a memory subsystem according to an embodiment.

[0009] Figure 2A According to at least some embodiments Figure 1A-1B A schematic block diagram of a thermometer.

[0010] Figure 2B According to the embodiments Figure 2A A schematic diagram of a voltage divider.

[0011] Figure 3A Based on at least some embodiments Figure 2A A schematic block diagram of the conversion circuit system in the context of a thermometer.

[0012] Figure 3B It is a graph illustrating the threshold voltage of a diode as it changes relative to the temperature inside a thermometer, according to at least some embodiments.

[0013] Figure 3C According to some embodiments Figure 3A A schematic diagram of an analog-to-digital converter (ADC).

[0014] Figure 3DThis is a schematic block diagram of a counter and extractor for determining temperature from an ADC, according to at least some embodiments.

[0015] Figure 4 Based on at least some embodiments and Figure 3C-3D The diagram is a graph of the waveform associated with the diagram.

[0016] Figure 5A It is a graph illustrating the change of the threshold voltage of a diode relative to temperature according to various embodiments.

[0017] Figure 5B It is a graph illustrating the calibration of the extraction performed by the extractor according to at least some embodiments.

[0018] Figure 6 This is a flowchart of an example method for operating a thermometer of a memory device according to at least some embodiments.

[0019] Figure 7 This is a block diagram of an example computer system in which embodiments of the present disclosure can be operated. Detailed Implementation

[0020] Embodiments of this disclosure are directed to a multi-sampling, charge-sharing thermometer in a memory device. In some memory devices, temperature alters the physical behavior of programmable memory cells within the device. Several temperature-related techniques have been developed to improve the performance of these memory devices, such as NAND or flash memory devices, where these techniques rely on temperature readings. An internal thermometer or other temperature sensor provides a digital code proportional to the actual temperature.

[0021] In some memory devices, the thermometer can provide a digital code when the controller or other control logic requests a temperature value. In this embodiment, the memory device incurs performance compensation when it must wait for the thermometer to determine and provide the digital code. In other embodiments, the thermometer can continuously provide the digital code in the background, ensuring that the digital code corresponding to the temperature value is always current and available. The risk of the latter embodiment is obtaining the digital code during noisy operational phases that can lead to conversion errors. If the digital code is therefore inaccurate, the implementation of enhancement techniques may be degraded.

[0022] This disclosure addresses the above and other drawbacks by providing a thermometer that generates a digital code by averaging temperature transitions performed repeatedly over a large number (e.g., thousands) of transition stages. For example, temperature changes during normal operation of a memory device tend to be relatively slow, for example, less than 10°C per second in practice. Therefore, a transition duration between 20 and 30 ms is fast enough to provide up-to-date temperature information. In some embodiments, one thousand or thousands of transition stages may be repeated to average the effects of any random noise. The circuitry disclosed herein can also be configured to allow the recovery and elimination of systematic errors through calibration of the disclosed thermometer.

[0023] In some embodiments, the memory device includes: an array of memory cells; a diode having a threshold voltage that varies with temperature; and an analog-to-digital converter (ADC) coupled to the array. The ADC may further include: a voltage comparator having a positive terminal coupled to the diode; a first capacitor coupled between the negative terminal of the voltage comparator and ground; and a second capacitor selectively coupled between the first capacitor and a voltage reference node. The second capacitor is also coupled to ground and has a capacitance smaller than that of the first capacitor. The memory device may further include a pulse generator coupled to the ADC and generating pulses. In at least some embodiments, the pulses cause the first capacitor to connect to the second capacitor and equalize the charge between the first and second capacitors. Furthermore, the inverted signal of the pulses causes the second capacitor to couple to the voltage reference node to precharge the first capacitor. A counter set may then count the number of clock cycles and the number of ones output by the comparator. In response to the number of clock cycles reaching a predetermined number, the number of ones may be converted into a temperature value (or digital code), for example, after being decimated by an extractor to remove the previously discussed noise.

[0024] Therefore, the advantages of the systems and methods implemented according to some embodiments of this disclosure include, but are not limited to, means, systems, and methods for providing a thermometer for a memory device to continuously and accurately generate temperature values ​​that can be used in performance enhancement techniques for the memory device. Furthermore, the circuit system can be configured such that noise that may exist within the circuit system over time can be captured and eliminated, thereby enabling multiple samples averaged over time to produce accurate temperature readings. Those skilled in the art will appreciate other advantages of temperature value optimization within the memory device discussed below.

[0025] Figure 1AThis description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or combinations of such media or memory devices. The memory subsystem 110 may be a storage device, a memory module, or a mixture of storage devices and memory modules.

[0026] Memory device 130 may be a non-volatile memory device. An example of a non-volatile memory device is a NAND memory device. A non-volatile memory device is a package of one or more memory dies. Each die may contain one or more planes. Planes may be divided into logic units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane contains a set of physical blocks. Each block contains a set of pages. Each page contains a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states related to the number of bits being stored. Logic states may be represented by binary values ​​such as “0” and “1” or combinations of such values.

[0027] Memory device 130 may consist of bits arranged in a two-dimensional or three-dimensional grid, also referred to as a memory array. Memory cells are etched onto a silicon wafer in an array of columns (hereinafter referred to as bit lines) and rows (hereinafter referred to as word lines). A word line may refer to one or more rows of memory cells in the memory device, which are used in conjunction with one or more bit lines to generate an address for each of the memory cells. The intersection of bit lines and word lines constitutes the address of the memory cell.

[0028] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0029] The computing system 100 may be a computing device, such as a desktop computer, a laptop computer, a web server, a mobile device, a vehicle (e.g., an airplane, drone, train, car or other means of transport), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer contained in a vehicle, industrial equipment or networked business device), or such a computing device containing memory and processing power.

[0030] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to multiple memory subsystems 110 of different types. Figure 1A This describes an example of a host system 120 coupled to a memory subsystem 110. The host system 120 can provide data to be stored at the memory subsystem 110 and can request data to be retrieved from the memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without intermediate components), whether wired or wireless, and includes connections such as electrical, optical, and magnetic connections.

[0031] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). For example, host system 120 uses memory subsystem 110 to write data to and read data from memory subsystem 110.

[0032] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)). The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transferring control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1A The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0033] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0034] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. The crosspoint array of non-volatile memory cells can perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-grid data access array. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without prior erasing. NAND flash memory includes, for example, two-dimensional NAND (2DN NAND) and three-dimensional NAND (3D NAND).

[0035] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used for storing data. In the case of some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0036] While non-volatile memory components, such as 3D cross-point non-volatile memory cell arrays and NAND flash memories (e.g., 2D NAND, 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0037] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0038] The memory subsystem controller 115 may include a processing means comprising one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0039] In some embodiments, local memory 119 may include memory registers that store memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although in Figure 1A The instance memory subsystem 110 in the present disclosure is described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0040] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to perform the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling, garbage collection, error detection and error correction code (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into instructions for accessing the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0041] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0042] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device, which is the original memory device 130 having on-die control logic (e.g., local media controller 135) and a controller for media management within the same memory device package (e.g., memory subsystem controller 115). An example of a managed memory device is a managed NAND (MNAND) device.

[0043] In some embodiments, the memory device 130 includes a thermometer 138 adapted to acquire multiple samples over a series of clock cycles and to average the output over time to continuously provide accurate temperature values ​​that also reduce or eliminate noise associated with the sensor and circuitry of the thermometer 138. The control logic of the local media controller 135 is adapted to direct clock and pulse generation that is functionally coordinated with the hardware of the thermometer 138, except for calibration operations, as will be explained in detail.

[0044] Figure 1B The first device in the form of a presenting memory device 130 and the presenting memory subsystem (e.g., according to the embodiment) are presenting memory devices 130. Figure 1A A simplified block diagram of a second device communicating with a memory subsystem controller 115 in the form of a memory subsystem 110. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, etc. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) may be a memory controller or other external host device.

[0045] Memory device 130 includes an array 104 of memory cells logically arranged in rows and columns. Memory cells in a logical row are typically connected to the same access line (e.g., a word line), while memory cells in a logical column are typically selectively connected to the same data line (e.g., a bit line). A single access line may be associated with memory cells in more than one logical row, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 104 ( Figure 1B (Not shown in the text) can be programmed into one of at least two target data states.

[0046] Row decoding circuitry 108 and column decoding circuitry 111 are provided to decode the address signal. The address signal is received and decoded to access the memory cell array 104. The memory device 130 also includes an input / output (I / O) control circuitry 112 for managing inputs of commands, addresses, and data to the memory device 130, as well as outputs of data and status information from the memory device 130. An address register 114 communicates with the I / O control circuitry 112, as well as the row decoding circuitry 108 and column decoding circuitry 111, to latch the address signal before decoding. A command register 124 communicates with the I / O control circuitry 112 and the local media controller 135 to latch incoming commands.

[0047] A controller (e.g., a local media controller 135 within memory device 130) controls access to memory cell array 104 in response to commands and generates status information for external memory subsystem controller 115. For example, local media controller 135 is configured to perform access operations (e.g., read operations, programming operations, and / or erase operations) on memory cell array 104. Local media controller 135 communicates with row decoding circuitry 108 and column decoding circuitry 111 to control row decoding circuitry 108 and column decoding circuitry 111 in response to addresses.

[0048] The local media controller 135 also communicates with cache register 118 and data register 121. Cache register 118 latches incoming or outgoing data, such as data initiated by the local media controller 135, to temporarily store data while the memory cell array 104 is busy writing or reading other data. During a programming operation (e.g., a write operation), data can be transferred from cache register 118 to data register 121 for transfer to memory cell array 104; then, new data can be latched from I / O control circuitry 112 into cache register 118. During a read operation, data can be transferred from cache register 118 to I / O control circuitry 112 for output to memory subsystem controller 115; then, new data can be transferred from data register 121 to cache register 118. Cache register 118 and / or data register 121 may form a page buffer (e.g., at least a portion thereof) of memory device 130. The page buffer may further include sensing devices, such as a sense amplifier, to sense the data state of the memory cells, for example, by sensing the state of the data lines connected to the memory cells of the memory cell array 104. The status register 122 may communicate with the I / O control circuitry system 112 and the local memory controller 135 to latch status information for output to the memory subsystem controller 115. In some embodiments, the local media controller 135 includes or is coupled to a thermometer 138, which will be discussed in detail.

[0049] Memory device 130 receives control signals from local media controller 135 at memory subsystem controller 115 via control link 132. For example, control signals may include chip enable signal CE#, command latch enable signal CLE, address latch enable signal ALE, write enable signal WE#, read enable signal RE#, and write protection signal WP#. Depending on the nature of memory device 130, additional or alternative control signals (not shown) may be received further via control link 132. In one embodiment, memory device 130 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from memory subsystem controller 115 via multiplexed input / output (I / O) bus 134, and outputs data to memory subsystem controller 115 via I / O bus 134.

[0050] For example, commands can be received at I / O control circuitry system 112 via input / output (I / O) pins [7:0] of I / O bus 134, and then written to command register 124. Addresses can be received at I / O control circuitry system 112 via input / output (I / O) pins [7:0] of I / O bus 134, and then written to address register 114. Data can be received at I / O control circuitry system 112 via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices, and then written to cache register 118. Data can then be written to data register 121 for programming memory cell array 104.

[0051] In this embodiment, cache register 118 may be omitted, and data may be written directly to data register 121. Data may also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. While references may be made to I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connection to memory device 130 via an external device (e.g., memory subsystem controller 115).

[0052] Those skilled in the art should understand that additional circuitry and signals can be provided, and that simplification has been achieved. Figure 1B The memory device 130. It should be understood that, reference Figure 1B The functionality of the various block components described need not be separated from the different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device may be adapted to perform... Figure 1B The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 1B The functionality of a single block component. Additionally, while specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0053] Figure 2A According to at least some embodiments Figure 1A-1BA schematic block diagram of a thermometer 138. In various embodiments, the thermometer 138 includes a backup bandgap circuit 204, a voltage divider circuit 208, a conversion circuit system 212, a diode 213, a counter 218, and an extractor 222 that outputs the measured temperature value. As discussed, the temperature value may be a digital code provided to a local media controller 135, whose control logic can interpret the digital code.

[0054] In at least some embodiments, diode 213 represents a forward-biased p-type / n-type (PN) junction having a threshold voltage (Vd) spanning the depletion region between the n-type and p-type semiconductor regions. This threshold voltage (Vd) varies with temperature and can therefore serve as a temperature sensor for other circuitry within thermometer 138.

[0055] In at least some embodiments, the spare bandgap circuit 204 is adapted to generate a temperature-independent voltage reference, hereinafter referred to as the spare bandgap voltage (V). sb Because the backup bandgap voltage is temperature-independent, the voltage divider circuit 208 can operate at a reliably consistent voltage level to generate high-voltage reference (VH) and low-voltage reference (VL) voltages. The conversion circuit system 212 can then use these high and low voltage reference values ​​to adjust the voltage at the conversion output (d). i The threshold voltage (Vd) of the diode is compared and averaged when the diode is generated.

[0056] In these embodiments, in addition to clock cycles, counter 218 may also track these conversion outputs. After another conversion cycle (which can be quantized by a predetermined number of clock cycles) is completed, extractor 222 can extract the total number of conversion outputs to reduce noise in the final temperature value output by thermometer 138. How these components function will be discussed in more detail.

[0057] Figure 2B According to the embodiments Figure 2A A schematic diagram of the voltage divider circuit 208. In some embodiments, the voltage divider circuit 208 includes a low-current voltage buffer 230 coupled to the resistive voltage divider 232. Because the active phase of temperature transition is significantly shorter than the idle phase, such as Figure 4 As explained, in addition to the low operating current of the voltage divider circuit 208, the voltage divider circuit 208 can also limit the current consumption of the thermometer 138. Furthermore, the resistive voltage divider 232 can generate a high-voltage reference VH and a low-voltage reference VL with low current consumption. The values ​​of VH and VL voltages can be variably set depending on the tap points used by the resistive voltage divider 232.

[0058] Figure 3A Based on at least some embodiments Figure 2AA schematic block diagram of the conversion circuit system 212 in the context of a thermometer. The conversion circuit system 212 may include an oscillator 302, a pulse generator 306, a V diode generator 310, and an analog-to-digital converter (ADC) 314. The oscillator 302 (which may be a low-voltage oscillator) generates a drive... Figure 3C-3D The pulse generator 306 in the other circuit systems described herein has a clock (CLK). The diode generator 310 determines the threshold voltage (Vd) of the diode 213 or other forward-biased PN junction semiconductor device and provides this threshold voltage to the ADC 314. The ADC 314 can operate using one or more combinations of VH and VL values ​​from the voltage divider circuit 208, relative to the threshold voltage (Vd) of the diode 213.

[0059] More specifically, the output of ADC 314 can be understood as the number of values ​​triggered by ADC 314 during this comparison, which can be expressed as the value K in the following equation (1). The value of N in equation (1) is the number of conversions performed during a predetermined number of clock cycles of the clock generated by oscillator 302. Therefore, the total number of conversion outputs can become more accurate as the number of clock cycles increases.

[0060]

[0061] Reference Figure 3C-3D A more detailed discussion of the ADC 314 follows.

[0062] Figure 3B This is a graph illustrating the threshold voltage (Vd) of diode 213 as it changes relative to the temperature within thermometer 138 according to at least some embodiments. For example, it can be observed from this graph that Vd is generally inversely proportional to temperature (T). As explained, the maximum threshold voltage (Vd) corresponds to the minimum temperature (Tmin). max The voltage can be set to be lower than the high-voltage reference (VH). Furthermore, the minimum threshold voltage (Vd) corresponds to the maximum temperature (Tmax). min The voltage can be set to be higher than the low voltage reference (VL). Additionally, in the design of voltage divider 208 ( Figure 2B When selecting the tap position from the resistor divider 232, the voltage VH and VL values ​​can be selected by considering the factors in equations (2) and (3) respectively.

[0063]

[0064]

[0065] Therefore, the voltage of the high voltage reference (VH) can be selected as the maximum value above the threshold voltage, and the voltage of the low voltage reference (VL) can be selected as the minimum value below the threshold voltage.

[0066] Figure 3C According to some embodiments Figure 3A A schematic diagram of the ADC 314. Figure 3D This is a schematic block diagram of a counter 218 and an extractor 222 for determining temperature from an ADC 314, according to at least some embodiments. Figure 4 Based on at least some embodiments and Figure 3C-3D The schematic diagram is associated with a waveform graph. The ADC 314 may include, but is not limited to, a voltage comparator 315, a first capacitor C1, a second capacitor C2, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, and a trigger 305.

[0067] In at least some embodiments, voltage comparator 315 has a positive terminal coupled to diode 213, for example, via V diode generator 310. A first capacitor C1 is coupled between the negative terminal of voltage comparator 315 and ground (GND). A first switch S1 is selectively coupled to the first capacitor C1. A second switch S2 is selectively coupled between the first switch S1 and voltage reference node 320. A second capacitor C0 is selectively connected between the first switch S1 and the second switch S3, and is also coupled to ground. In these embodiments, the second capacitor C0 is smaller than the first capacitor C1. In some embodiments, the first capacitor C1 is much larger than the second capacitor C0.

[0068] In at least some embodiments, oscillator 302 is coupled to pulse generator 306. Oscillator 302 provides a clock for pulse generator 306 to generate pulses (pulse 1). In these embodiments, pulse generator 306 ( Figure 3D The pulse generator 306 is coupled to the ADC 314 and generates a pulse (pulse 1) that closes the first switch S1, thereby causing the first capacitor C1 and the second capacitor C0 to equalize their charges. In these embodiments, the thermometer 138 further includes an inverter 307 coupled between the pulse generator 306 and the second switch S2. Figure 3D Inverter 307 outputs an inverted signal (pulse 1), which closes the second switch S2, thereby causing the second capacitor C0 to be pre-charged via voltage reference node 320. Figure 4 As explained, the inverted signal has a longer inverted pulse than the pulse 1 signal, and therefore a longer precharge period. Once the second capacitor C0 is precharged, the pulse from the pulse 1 signal causes the first switch S1 to close and the second switch S2 to open, thereby causing the charge to be equalized across the first and second capacitors.

[0069] In various embodiments, ADC 314 further includes a third switch S3 selectively coupled between the high-voltage reference (VH) of resistor divider 232 and voltage reference node 320. In these embodiments, resistor divider 232 is driven by a spare bandgap voltage, as discussed. ADC 314 further includes a fourth switch S4 selectively coupled between the low-voltage reference (LH) of resistor divider 232 and voltage reference node 320. Furthermore, the voltage of the low-voltage reference is lower than the voltage of the high-voltage reference. Therefore, during the pre-charge phase, the assertion-converted output (d i (For example, a value) causes the third switch to close to select VH, without asserting the conversion output (!d) i (For example, a zero value) causes the fourth switch to close to select VL to feed into voltage reference node 320. For example... Figure 4 As explained in the text, d i It can typically correspond to a clock (CLK) during at least a portion of the temperature transition.

[0070] In at least some embodiments, the trigger 305 is coupled to the voltage comparator 315 to store the output (d) of the voltage comparator 315. i The output will selectively close the third switch S3, and the output second inverted signal (!di) will selectively close the fourth switch S4, for example, such that only one of the third switch S3 or the fourth switch S4 is closed at a time. In these embodiments, the pulse generator 306 further generates a second pulse (pulse 2). The trigger 305 may store the output (d) of the voltage comparator 315. i And it can be cleared in the absence of a second pulse (pulse 2), as referenced. Figure 4 As explained.

[0071] In an additional specific case regarding the pre-charge phase, when the first switch S1 is open and the second switch S2 is closed, the conversion output d depends on the current stored in the flip-flop 305. i The second capacitor C0 is charged to either the high voltage reference (VH) level or the low voltage reference (VL) level. The voltage across the first capacitor C1 is Vci, which alternates near the threshold voltage (Vd) of diode 213 after the ramp-up period. The charge on the capacitor after the pre-charging phase can be expressed as Q in equation (4). f ,

[0072] Q s =C0·(d i ·VH+(1-d i )·VL)+C1·Vc i (4)

[0073] The first value is the charge on the second capacitor C0, and the second value is the charge on the first capacitor C1.

[0074] In an additional specific case regarding the engagement phase, when the first switch S1 is closed and the second switch S2 is open, the first capacitor C1 and the second capacitor C0 balance their charges to share a common voltage V. f Therefore, the charge on the second capacitor C0 will be added to the charge on the first capacitor C1 (when pre-charging occurs at VH), or vice versa, and the second capacitor C0 will receive the charge from the first capacitor C1 (when pre-charging occurs at VL). Final charge Q f This can be expressed in equation (5) as

[0075] Q f = (C0+C1)·Vf i (5)

[0076] Furthermore, it is assumed that after each transformation, Q s Will equal Q f Equations (6) and (7) can be generated in sequence.

[0077]

[0078]

[0079] consider The steady state, let and Where K is the number of single values ​​output by the ADC314 (and is proportional to the temperature of the diode 213), and N is the number of conversions or clock cycles. Also consider... Equations (8) and (9) can be obtained:

[0080] k·VH+(Nk)·VL-N·Vd=0, then (8)

[0081]

[0082] Equation (9) is the same as the previously mentioned equation (1), and has The resolution.

[0083] As a practical example for illustrative purposes only, assume a voltage Vc of 600mV, which is lower than a hypothetical value of Vd(T) of approximately 1.2V. Based on this information, the output d of voltage comparator 315... iThe voltage comparator 315 will output a "1" (one value) to flip-flop 305 if Vc is higher than Vd(T); otherwise, if Vc is higher than Vd(T), the voltage comparator 315 will output a "0" (zero value) to flip-flop 305. During the ramp-up phase, the voltage comparator output is "1", and the voltage across the second capacitor C0 continues to be applied to C1, which increases the charge and thus increases the voltage at Vci. During the steady-state phase, Vc (from C1) increases to be higher than Vd, and then the output d is switched. i It is "0", thus reducing the voltage at Vc. By making the conversion output d i The voltage Vc is reduced by pre-charging the second capacitor C0 to a lower voltage, and then the voltage is removed from the first capacitor C1 during the engagement phase. The voltage Vc can then begin to fluctuate around Vd throughout the steady-state phase.

[0084] For further reference Figure 3D According to at least some embodiments, counter 218 ( Figure 3D The system includes a first counter 318A coupled to a flip-flop 305, a second counter 318B coupled to an oscillator 302, and a matching circuit 309 coupled to the second counter 318B and used to trigger the value of the first counter 318A to be gated in a latch 322 coupled to the first counter 318A. For example, in these embodiments, the first counter 318A increments in response to detecting a value buffered in the flip-flop 305, and the second counter 318B increments cyclically according to a clock cycle (CLK) generated by the oscillator 302. The latch 322 is coupled to the output of the first counter 318A. The logic gate of the matching circuit 309 activates the latch 322 in response to the second counter 318B reaching a predetermined number (indicated as N) clock cycles, the latch receiving the value of the first counter 318A.

[0085] In at least some embodiments, the extractor 222 is coupled to the latch 322 and is therefore adapted to extract a value retrieved from the latch 322, thereby causing a predetermined number of least significant bits of the value of the first counter 318A stored in the latch 322 to be discarded. The extractor 222 thus outputs a value of the temperature rejecting noise found in the least significant bits. The output temperature value may be in the form of a digital code interpretable by the control logic of the local media controller 135.

[0086] Figure 5A This is a graph illustrating the change in the threshold voltage of the diode relative to temperature according to various embodiments. In these embodiments, this change in the threshold voltage (Vd) of diode 213 can be expressed as equation (10).

[0087]

[0088] The digital code can correspond to the threshold voltage according to this change in temperature, thereby adjusting the resolution of the curve defined by the change in temperature of Vd using the value of j in equation (10). For example, if j is set to zero ("0"), there will be 1 code / degree, while if j is set to one ("1"), there will be 2 codes / degree. For example, increasing the resolution per degree can help increase accuracy. Therefore, as the value of j increases, the least significant bit discarded by the extractor 222 increases to reject more noise. Furthermore, as can be observed, the value of N (the number of conversion cycles used before performing decimation) determines the slope of the curve of Vd relative to temperature (T), and can therefore be adjusted to set the rate of change between Vd and the temperature in the temperature output value from the extractor 222. Figure 5A The specific curve was generated using a value of N of 2200, a clock cycle of 10μs, and a sample period of 22ms, but other possibilities are possible.

[0089] Figure 5B This is a graph illustrating the calibration of the decimation performed by decimator 222 according to at least some embodiments. This graph illustrates curve 501 of the value of K (e.g., the number of ones tracked by the first counter 318A) divided by eight (“8”) and curve 503 of the calibration calculation for (160-K / 8), which will match the temperature value of diode 213. Therefore, calibration can be obtained by adding the number required to achieve the target value, which is chosen in this example as P = 160, but other numbers are contemplated and can be chosen. For example only, assume VH is 0.95V, VL is 0.45V, j is set to 3 (e.g., the three least significant bits are truncated to obtain 1 code / degree), and the Vd slope is -1.82mV / K. For calibration purposes, the control logic can create and store, within a data structure, contents similar to Table 1 that associates temperature values ​​with K / 8 and the calibration value of 160-K / 8. Therefore, in this calibration example, equation (11) can be used to calculate the temperature based on the values ​​of P, K, and j.

[0090]

[0091] Temperature (K) K / 8 (160-K / 8) -40 200 -40 -30 190 -30 -20 180 -20 -10 170 -10 0 160 0 10 150 10 20 140 20 30 130 30 40 120 40 50 110 50 60 100 60 70 90 70 80 80 80 90 70 90 100 60 100 110 50 110 120 40 120

[0092] Table 1

[0093] Figure 6 This is a flowchart of an example method 600 for operating a thermometer 138 on a memory device according to at least some embodiments. Method 600 may be performed by processing logic that may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on a processing device), or a combination thereof. In some embodiments, method 600 is performed by… Figure 1A-1BThe thermometer 138 and the local media controller 135 are combined and executed, and are discussed in more detail herein. Although shown in a particular sequence or order, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0094] In various embodiments, method 600 is to operate a memory device comprising: a memory array; a diode having a temperature-dependent threshold voltage; and an analog-to-digital converter (ADC) coupled to the memory array. In these embodiments, the ADC comprises: a voltage comparator having a positive terminal coupled to the diode; a first capacitor coupled between the negative terminal of the voltage comparator and ground; and a second capacitor selectively coupled between the first capacitor and a voltage reference node, the second capacitor also being coupled to ground and having a capacitance smaller than that of the first capacitor.

[0095] At operation 610, the generated pulse is controlled. More specifically, the processing logic directs the pulse generator to generate pulses that will cause the first capacitor to connect to the second capacitor and equalize the charge between the first and second capacitors.

[0096] At operation 620, an inverted signal of the pulse is generated. More specifically, the processing logic generates an inverted signal from the pulse, which causes the second capacitor to couple to the voltage reference node to precharge the first capacitor before the charge between the first and second capacitors is equalized.

[0097] At operation 630, the comparator output is tracked. More specifically, the processing logic tracks the number of values ​​output by the voltage comparator to determine the diode's temperature value.

[0098] In some embodiments, the oscillator is coupled to the pulse generator of the thermometer 138. In an additional operation of method 600, the processing logic uses a first counter to track the number of values ​​output by the voltage comparator. The processing logic further uses the oscillator to generate a clock from which the pulse generator produces pulses. The processing logic further uses a second counter to track the number of clock cycles. In response to the second counter reaching a predetermined number of clock cycles, the processing logic further decrements the value of the first counter to generate a temperature value.

[0099] Figure 7This describes an example machine of computer system 700, within which a set of instructions for causing the machine to perform any one or more of the methods discussed herein is executable. In some embodiments, computer system 700 may correspond to a host system (e.g., Figure 1A The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1A The memory subsystem 110), or may be used to perform controller operations (e.g., to execute an operating system, thereby executing commands corresponding to...). Figure 1A (Operation of the memory subsystem controller 115). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, or within the capacity of a server or client machine in a client-server network environment.

[0100] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by the machine. Furthermore, while a single machine is described, the term "machine" should also be considered to include any set of machines that individually or collectively execute a set of instructions (or multiple sets of instructions) to perform any or more of the methods discussed herein.

[0101] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), a static memory 710 (e.g., flash memory, static random access memory (SRAM)), and a data storage system 718, which communicate with each other via a bus 730.

[0102] Processing device 702 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 702 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 702 is configured to execute instructions 728 for performing the operations and steps discussed herein. Computer system 700 may further include a network interface device 712 for communication via network 720.

[0103] Data storage system 718 may include machine-readable storage medium 724 (also referred to as computer-readable medium) on which one or more instruction sets 728 or software embodying any one or more of the methods or functions described herein are stored. Data storage system 718 may further include the previously discussed local media controller 135 and thermometer 138. Instructions 728 may also reside wholly or at least partially within main memory 704 and / or processing device 702 during execution by computer system 700, which also constitute machine-readable storage medium. Machine-readable storage medium 724, data storage system 718, and / or main memory 704 may correspond to... Figure 1A The memory subsystem 110.

[0104] In one embodiment, instruction 726 includes instructions for implementing a controller (e.g., Figure 1A The memory subsystem controller 115) provides functional instructions. Although the machine-readable storage medium 724 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0105] Some parts of the foregoing detailed description have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. An algorithm here and generally is considered a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of physical quantities. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0106] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of a computer system, or other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0107] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0108] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may be convenient to construct more specialized devices for performing the methods. The structures of various such systems will be presented as described below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that various programming languages ​​can be used to implement the teachings of this disclosure as described herein.

[0109] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0110] In the foregoing description, embodiments of the present disclosure have been described with reference to specific examples. It will be apparent that various modifications can be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A memory device comprising: Memory cell array; A diode, which has a threshold voltage that changes with temperature; An analog-to-digital converter (ADC) coupled to the array and comprising: A voltage comparator having a positive terminal coupled to the diode; The first capacitor is coupled between the negative terminal of the voltage comparator and ground; A second capacitor is selectively coupled between the first capacitor and the voltage reference node, and the second capacitor is also coupled to the ground and has a capacitance smaller than that of the first capacitor. A first switch, selectively coupled between a high-voltage reference of a resistive voltage divider and the voltage reference node, the resistive voltage divider being driven by a backup bandgap voltage; and A second switch, selectively coupled between the low-voltage reference and the voltage reference node of the resistive voltage divider, wherein the voltage of the low-voltage reference is lower than the voltage of the high-voltage reference; and A pulse generator coupled to the ADC generates pulses, wherein the pulses cause the first capacitor to connect to the second capacitor and equalize the charge between the first and second capacitors, and wherein the inverted signal of the pulses causes the second capacitor to couple to the voltage reference node to precharge the first capacitor.

2. The memory device of claim 1, further comprising an oscillator coupled to the pulse generator, the oscillator being used to provide a clock from which the pulse generator will generate the pulse.

3. The memory device according to claim 1, further comprising: A third switch is selectively coupled to the first capacitor, wherein the pulse will close the third switch; as well as A fourth switch, selectively coupled between the third switch and the voltage reference node, wherein the inverting signal will close the fourth switch.

4. The memory device of claim 1, wherein the voltage of the high voltage reference is selected as a maximum value higher than the threshold voltage, and wherein the voltage of the low voltage reference is selected as a minimum value lower than the threshold voltage.

5. The memory device of claim 1, further comprising a flip-flop coupled to the voltage comparator to store the output of the voltage comparator, wherein the output selectively closes the first switch, and a second inverted signal of the output selectively closes the second switch.

6. The memory device of claim 1, wherein the pulse generator further generates a second pulse, and the memory device further includes a trigger coupled to the voltage comparator, the trigger being configured to store the output of the voltage comparator and to be cleared in the absence of the second pulse.

7. The memory device according to claim 6, further comprising: An oscillator for generating a clock from which the pulse generator will generate the pulses; A first counter, coupled to the trigger, increments in response to the detection of a value buffered in the trigger; A second counter, coupled to the oscillator, is used to cyclically increment according to the clock. A latch, which is coupled to the output of the first counter; as well as A logic gate is used to activate the latch in response to the second counter reaching a predetermined number of clock cycles, the latch receiving the value of the first counter.

8. The memory device of claim 7, further comprising a extractor coupled to the latch, the extractor being configured to: This causes a predetermined number of least significant bits of the value of the first counter stored in the latch to be discarded; and The output temperature rejects the decimation value of noise found in the least significant bit.

9. A system comprising: One or more memory dies; A diode, which has a threshold voltage that changes with temperature; An analog-to-digital converter (ADC) coupled to one or more memory dies, the ADC comprising: A voltage comparator having a positive terminal coupled to the diode; The first capacitor is coupled between the negative terminal of the voltage comparator and ground; A first switch, which is selectively coupled to the first capacitor; A second switch is selectively coupled between the first switch and the voltage reference node; A second capacitor is selectively connected between the first switch and the second switch, and the second capacitor is also coupled to the ground; A third switch, selectively coupled between the high-voltage reference of a resistive voltage divider and the voltage reference node, the resistive voltage divider being driven by a backup bandgap voltage; and A fourth switch is selectively coupled between the low-voltage reference and the voltage reference node of the resistive voltage divider, wherein the voltage of the low-voltage reference is lower than the voltage of the high-voltage reference. A pulse generator, coupled to the ADC, generates pulses that close the first switch, thereby causing the first and second capacitors to equalize their charges; and An inverter, coupled between the pulse generator and the second switch, outputs an inverted signal that closes the second switch, thereby causing the second capacitor to be precharged via the voltage reference node.

10. The system of claim 9, wherein the second capacitor is smaller than the first capacitor.

11. The system of claim 9, further comprising an oscillator coupled to the pulse generator, the oscillator being used to provide a clock from which the pulse generator will generate the pulse.

12. The system of claim 9, wherein the voltage of the high voltage reference is selected as a maximum value higher than the threshold voltage, and wherein the voltage of the low voltage reference is selected as a minimum value lower than the threshold voltage.

13. The system of claim 9, further comprising a trigger coupled to the voltage comparator to store the output of the voltage comparator, wherein the output selectively closes the first switch, and a second inverted signal of the output selectively closes the second switch.

14. The system of claim 9, wherein the pulse generator further generates a second pulse, and the system further includes a trigger coupled to the voltage comparator for storing the output of the voltage comparator and being cleared in the absence of the second pulse.

15. The system of claim 14, further comprising: An oscillator for generating a clock from which the pulse generator will generate the pulses; A first counter, coupled to the trigger, increments in response to the detection of a value buffered in the trigger; A second counter, coupled to the oscillator, is used to cyclically increment according to the clock. A latch, which is coupled to the output of the first counter; as well as A logic gate is used to activate the latch in response to the second counter reaching a predetermined number of clock cycles, the latch receiving the value of the first counter.

16. The system of claim 15, further comprising a withdrawer coupled to the latch, the withdrawer being configured to: This causes a predetermined number of least significant bits of the value of the first counter stored in the latch to be discarded; and The output temperature rejects the decimation value of noise found in the least significant bit.

17. A method of operating a memory device, the memory device comprising: Memory array; A diode, which has a threshold voltage that changes with temperature; and an analog-to-digital converter (ADC) coupled to the memory array, the ADC comprising: a voltage comparator having a positive terminal coupled to the diode; a first capacitor coupled between the negative terminal of the voltage comparator and ground; a second capacitor selectively coupled between the first capacitor and a voltage reference node, the second capacitor also coupled to the ground and having a capacitance smaller than that of the first capacitor; a first switch selectively coupled between a high-voltage reference of a resistor divider and the voltage reference node, the resistor divider being driven by a standby bandgap voltage; and a second switch selectively coupled between a low-voltage reference of the resistor divider and the voltage reference node, wherein the voltage of the low-voltage reference is lower than that of the high-voltage reference, and wherein the method of operating the memory device comprises: A pulse generator is directed to generate pulses, wherein the pulses will cause the first capacitor to connect to the second capacitor and equalize the charge between the first capacitor and the second capacitor; An inverted signal is generated from the pulse, which causes the second capacitor to couple with the voltage reference node to precharge the first capacitor prior to the equalization of the charge between the first and second capacitors; and The number of values ​​output by the voltage comparator is tracked to determine the temperature value of the diode.

18. The method of claim 17, wherein the memory device further comprises an oscillator coupled to the pulse generator, and wherein the method of operating the memory device further comprises: A first counter is used to track the number of values ​​output by the voltage comparator; The oscillator is used to generate a clock from which the pulse generator produces the pulses; A second counter is used to track the number of clock cycles of the clock. as well as In response to the second counter reaching a predetermined number of clock cycles, the value of the first counter is extracted to generate the temperature value.

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