Driving method of pixel array, image sensor, and electronic device

Abstract

The application provides a driving method of a pixel array, an image sensor and an electronic device. In the driving method of the pixel array, a row selection signal is first output row by row for row-by-row quantization, and a first clamping control signal is provided to a row selection transistor corresponding to a preset clamping row in the pixel array when the row selection signal is provided to the row selection transistor of the quantized row. When a light problem causes the signal output transistor to be in a preset state, for example, the output current is too small or the transistor is turned off, each row selection transistor corresponding to the preset clamping row is triggered to be turned on and clamps the connected output line to a first preset voltage, and a current branch is generated. The current branches of the reset readout period and the exposure readout period are the same, so that the current difference can be eliminated by correlated double sampling, the imaging consistency of the pixel array is improved, and the image contrast and the image quality are improved.

Description

Technical Field

[0001] This invention belongs to the field of image sensor technology, and particularly relates to a method for driving a pixel array, an image sensor, and an electronic device. Background Technology

[0002] Image sensors are widely used in many fields such as consumer electronics, security monitoring, automatic control, medical and defense. In particular, with the rise of smart terminals in recent years, the demand for low power consumption has become more important.

[0003] Image sensors typically include pixel arrays and corresponding signal processing circuitry. The pixel array is composed of pixel units, which typically consist of a photosensitive element, a reset transistor, a signal output transistor, and a row selection transistor. The row selection transistor is used to control the output of selected pixel rows.

[0004] In existing designs, there are often imaging problems caused by the ineffective operation of transistors in image sensors due to lighting issues. For example, the ineffective operation of transistors can lead to different current environments around different pixels in the pixel array, which affects the imaging consistency of the entire pixel array.

[0005] The above background information is provided solely for the purpose of clearly and completely explaining the technical solutions of this invention and facilitating understanding by those skilled in the art. It should not be assumed that these solutions are known to those skilled in the art simply because they have been described in the background section of this invention. Summary of the Invention

[0006] The purpose of this invention is to provide a driving method for a pixel array, which aims to solve the problem of inconsistent imaging caused by the ineffective operation of transistors due to illumination issues in traditional pixel arrays.

[0007] A first aspect of this invention provides a driving method for a pixel array, the pixel array comprising pixel units arranged in an array, multiple row selection lines, and multiple output lines. Each row of pixel units is connected to at least one row selection line, and each column of pixel units is connected to at least one output line. Each pixel unit includes a photosensitive element, a reset transistor, a signal output transistor, and a row selection transistor. The photosensitive element, the reset transistor, and the signal output transistor are coupled to a floating diffusion node. The row selection transistor is connected between the signal output transistor and the corresponding output line, and the row selection transistor is also connected to the corresponding row selection line.

[0008] The driving method for the pixel array includes:

[0009] Provide row selection signals to each of the row selection transistors;

[0010] At least when the row selection signal is provided to the row selection transistor of the quantization row, a first clamping control signal is provided to each of the corresponding row selection transistors of a preset clamping row in the pixel array, the preset clamping row and the quantization row being connected to the same output line, the corresponding row selection transistor of the preset clamping row being triggered to conduct when the signal output transistor of the quantization row is in a preset state and clamping the connected output line to a first preset voltage.

[0011] A second aspect of the present invention provides an image sensor, comprising:

[0012] A pixel array includes pixel units arranged in an array, multiple row selection lines, and multiple output lines. Each row of pixel units corresponds to at least one row selection line, and each column of pixel units corresponds to at least one output line. Each pixel unit includes a photosensitive element, a reset transistor, a signal output transistor, and a row selection transistor. The photosensitive element, the reset transistor, and the signal output transistor are coupled to a floating diffusion node. The row selection transistor is connected between the signal output transistor and the corresponding output line, and the row selection transistor is also connected to the corresponding row selection line.

[0013] The control circuit, connected to each of the row selection lines, is used for:

[0014] Provide row selection signals to each of the row selection transistors;

[0015] At least when the row selection signal is provided to the row selection transistor of the quantization row, a first clamping control signal is provided to each of the corresponding row selection transistors of a preset clamping row in the pixel array, the preset clamping row and the quantization row being connected to the same output line, the corresponding row selection transistor of the preset clamping row being triggered to conduct when the signal output transistor of the quantization row is in a preset state and clamping the connected output line to a first preset voltage.

[0016] A third aspect of the present invention provides an electronic device including the image sensor described above.

[0017] The beneficial effects of the present invention embodiments compared with the prior art are as follows: In the above-described pixel array driving method, row selection signals are first output row by row to perform row-by-row quantization. When at least the row selection signal is provided to the row selection transistor of the quantized row, a first clamping control signal is provided to the row selection transistor corresponding to the preset clamping row in the pixel array. When an illumination problem causes the signal output transistor to be in a preset state, such as when the output current is too small or it is turned off, the row selection transistors corresponding to the preset clamping row are triggered to conduct and clamp the connected output line to the first preset voltage, and generate a current branch. The current branches of the reset readout period and the exposure readout period are the same. Therefore, the current difference can be eliminated by correlated double sampling, thereby improving the imaging consistency of the pixel array and improving image contrast and image quality. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of a first structure of a pixel array provided in an embodiment of the present invention;

[0020] Figure 2 This is a schematic diagram of a second structure of a pixel array provided in an embodiment of the present invention;

[0021] Figure 3 This is a schematic diagram of a first type of pixel array provided in an embodiment of the present invention;

[0022] Figure 4 This is a schematic diagram of the first type of circuit for a traditional pixel array;

[0023] Figure 5 This is a schematic diagram of a second type of circuit for a traditional pixel array;

[0024] Figure 6 This is a schematic diagram of a first flowchart of a pixel array driving method provided in an embodiment of the present invention;

[0025] Figure 7 This is a schematic diagram of a second type of pixel array provided in an embodiment of the present invention;

[0026] Figure 8 This is a schematic diagram of a third type of pixel array provided in an embodiment of the present invention;

[0027] Figure 9 This is a schematic diagram of a second process for driving a pixel array according to an embodiment of the present invention;

[0028] Figure 10 This is a schematic diagram of a fourth type of pixel array provided in an embodiment of the present invention;

[0029] Figure 11 This is a schematic diagram of a first structure of an image sensor provided in an embodiment of the present invention;

[0030] Figure 12 This is a schematic diagram of a second structure of an image sensor provided in an embodiment of the present invention;

[0031] Figure 13 This is a schematic diagram of a third structure of an image sensor provided in an embodiment of the present invention;

[0032] Figure 14 This is a schematic diagram of a fourth structure of an image sensor provided in an embodiment of the present invention;

[0033] Figure 15 This is a schematic diagram of a fifth structure of an image sensor provided in an embodiment of the present invention;

[0034] Figure 16 This is a schematic diagram of a sixth structure of an image sensor provided in an embodiment of the present invention;

[0035] Figure 17 This is a schematic diagram of a seventh structure of an image sensor provided in an embodiment of the present invention;

[0036] Figure 18 This is a schematic diagram of a first type of circuit for an image sensor provided in an embodiment of the present invention;

[0037] Figure 19 This is a schematic diagram of the eighth structure of the image sensor provided in an embodiment of the present invention;

[0038] Figure 20 This is a second circuit diagram of an image sensor provided in an embodiment of the present invention;

[0039] Figure 21 This is a schematic diagram of a ninth structure of an image sensor provided in an embodiment of the present invention;

[0040] Figure 22 This is a schematic diagram of the tenth structure of an image sensor provided in an embodiment of the present invention. Detailed Implementation

[0041] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0042] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0043] like Figures 1 to 3 As shown, the pixel array 10 includes pixel units 11 arranged in an array, multiple row selection lines, and multiple output lines, for example... Figure 1 As shown, it includes pixel units 11 arranged in an array, first row selection lines Lrow1 to fourth row selection lines Lrow4, and first output lines BL1 to sixth output lines BL6.

[0044] Each row of pixel units 11 corresponds to at least one row selection line connection, and each column of pixel units 11 corresponds to at least one output line connection, for example... Figure 1 As shown, each pixel unit 11 in the same column is connected to the same output line, or as... Figure 2 As shown, pixel units 11 in the same column are provided with two output lines. In a pixel column sharing these two output lines, each pixel unit 11 is cross-connected to one of the two output lines. For example, pixel units 11 in odd-numbered rows of the first column are connected to the first sub-output line BL11, and pixel units 11 in even-numbered rows of the first column are connected to the second sub-output line BL12. The specific structure and connection method of the pixel array 10 are not limited. Additionally, as... Figure 1 and Figure 2 As shown, each row of pixel units 11 is connected to the same row selection line. The signal readout of the connected pixel units is realized based on the row selection line. Of course, in other implementations, the pixel units in the same row can also correspond to two or more row selection lines to achieve flexible control of the pixel units.

[0045] The pixel array 10 adopts a Bayer array arrangement, in which four pixel units 11 in every two adjacent rows and two columns form a unit group. In the unit group, the two pixel units 11 on one diagonal are red pixel units and blue pixel units, and the two pixel units 11 on the other diagonal are two green pixel units.

[0046] like Figure 3 As shown, each pixel unit 11 includes a photosensitive element 101, a reset transistor RST, a signal output transistor SF, and a row selection transistor RS. The photosensitive element 101, the reset transistor RST, and the signal output transistor SF are coupled to the floating diffusion node FD. The row selection transistor RS is connected between the signal output transistor SF and the corresponding output line. The row selection transistor RS is also connected to the corresponding row selection line.

[0047] The photosensitive element 101 typically includes a photoelectric conversion element and a transmission transistor TX. The photoelectric conversion element includes, but is not limited to, a photodiode PD, such as a pin-type photodiode.

[0048] In this configuration, the cathode of the photodiode PD is connected to the first terminal of the transmission transistor TX. The second terminal of the transmission transistor TX, the first terminal of the reset transistor RST, and the controlled terminal of the signal output transistor SF are all coupled to the floating diffusion node FD. The anode of the photodiode PD is grounded. The second terminal of the reset transistor RST and the first terminal of the signal output transistor SF are both connected to the positive power supply terminal PIXVDD. The second terminal of the signal output transistor SF is connected to the first terminal of the row selection transistor RS. The second terminal of the row selection transistor RS is connected to the corresponding output line to form the output terminal of the pixel unit 11 and outputs the corresponding pixel signal.

[0049] like Figure 4 As shown, existing image sensors typically include a clamping circuit 12 to limit the minimum signal amplitude output from pixel units 11 in the pixel array to the output line. The conventional clamping circuit 12 is located at the top or bottom of the pixel array. During the exposure readout period, when there is excessive charge in the photosensitive element 101, the floating diffusion node (FD) voltage of the pixel unit 11 in the quantization row is low, and the voltage of the output line decreases. When the voltage of the output line decreases to the turn-on voltage of the clamping circuit 12, the clamping circuit 12 turns on and performs clamping operation, clamping the voltage of the output line to a preset voltage. At this time, there are two current branches: one for the pixel unit 11 in the quantization row and one for the clamping circuit 12. During the reset readout period, the image sensor quantizes the reset signal, such as... Figure 1 As shown, the current magnitudes of the quantization rows during the reset readout period are different. Since the current branch during the reset readout period is the same as the current branch during the exposure readout period, the current difference can be eliminated by the correlation double sampling technique.

[0050] Therefore, when the pixel unit 11 is in a preset state where excessive charge causes the voltage of the output line to be too low, an additional clamping circuit is required, which increases the circuit cost.

[0051] Alternatively, during the exposure readout period, when the image sensor is in a preset state of overexposure, the voltage of the floating diffusion node in the quantization row is too low, such as... Figure 5 As shown, this may cause the signal output transistor SF to be directly turned off, the current in the current branch of the pixel unit 11 in the quantization row to be zero, while the exposure current branch during the reset readout period remains unchanged. At this time, the current trend of the entire pixel array 10 changes significantly compared with the quantization process during the reset readout period. The current environment of different rows in the array is different, and the influence of current cannot be eliminated by related double sampling, which in turn causes the ghosting problem, seriously affecting the image contrast and image quality, and reducing image detail information.

[0052] To address the different preset states that occur in the aforementioned signal output transistors, such as Figure 6 As shown, in this embodiment, a driving method for pixel array 10 is proposed, including:

[0053] Step S10: Provide row selection signal rowsel to each row selection transistor RS;

[0054] Step S20: At least when providing the row selection signal rowsel to the row selection transistor RS of the quantization row, a first clamping control signal Cla1 is provided to each corresponding row selection transistor RS of the preset clamping row in the pixel array. The preset clamping row and the quantization row are connected to the same output line. The corresponding row selection transistor RS of the preset clamping row is triggered to conduct when the signal output transistor SF of the quantization row is in a preset state and clamps the connected output line to the first preset voltage.

[0055] In this embodiment, the pixel unit 11 operates cyclically during the reset readout period and the exposure readout period. During the reset readout period, the reset signal is quantized, and during the exposure readout period, the pixel signal is quantized. Taking the example of each row of pixel units connected to the same row selection line, when the row selection signal rowsel is output to each row selection transistor RS, it indicates that the pixel unit corresponding to the row selection transistor RS is subjected to exposure quantization. When one or more rows of pixel units 11 are subjected to exposure quantization, the row of pixel units 11 or the row of pixel units 11 can be defined as a quantized row. When each pixel unit 11 is not quantized, it can be defined as a non-quantized row. One or more rows of pixel units 11 in the non-quantized row can be selected as a preset clamping row.

[0056] When quantizing each row sequentially, row-by-row quantization can be used, or multiple rows can be grouped together and each group of pixel units 11 can be sequentially quantized. For example, two adjacent rows of pixel units 11 can be grouped together as a quantization row and the quantization row can be quantized sequentially.

[0057] When the row selection signal rowsel is output to the row selection transistor RS of each pixel unit 11 in the quantization row, the quantization row may include a row of pixel units 11 or multiple adjacent rows of pixel units 11. The first clamp control signal is synchronously output to the corresponding row selection transistor RS of the preset clamp row. The number of output channels of the first clamp control signal Cla may be the same as or different from the number of output channels of the row selection signal rowsel during each row quantization. That is, during row quantization, each quantization may output one or more first clamp control signals Cla to the selected row or multiple preset clamp rows.

[0058] When there is excessive charge in the photosensitive element 101, the voltage of the floating diffusion node FD in the pixel unit 11 of the quantization row is low, causing the output voltage of the signal output transistor SF to decrease or the signal output transistor SF to be turned off. That is, when the signal output transistor SF is in the corresponding preset state, the voltage of the output line decreases or becomes zero. The row selection transistor RS of the clamping row receives the first clamping control signal Cla1 and forms a corresponding voltage difference with the voltage on the output line. By setting the magnitude of the first clamping control signal Cla1, when a small current or no current branch is generated in the quantization row, the gate and source of the preset clamping row selection transistor RS are clamped. When the voltage difference is greater than the threshold voltage, the row selection transistor RS of the preset clamping row is triggered and turned on. At this time, the clamping row is in the reset readout period state, that is, the gate of the reset transistor RST of the clamping row is at a high level, the floating diffusion node FD of the clamping row is close to the positive voltage, and the signal output transistor SF is turned on. Therefore, the positive power supply terminal PIXVDD, the pixel unit 11 of the corresponding clamping row and the corresponding output line are connected to form a current branch. The pixel unit 11 of the preset clamping row can clamp the output line. The magnitude of the first preset clamping voltage is determined by the threshold voltage and gate voltage of the signal row selection transistor RS of the clamping row.

[0059] The quantization row quantizes the reset signal during the reset readout period, which also generates a current branch. Therefore, for the quantization row, there is always the same number of current branches during the reset readout period and the overexposed exposure readout period. The current difference between the reset readout period and the exposure readout period can be eliminated by the correlated double sampling technique. In particular, the floating diffusion node FD voltage of pixel unit 11 in the quantization row is low, which causes the branch current generated by the reset signal corresponding to the reset readout to remain unchanged when the signal output transistor SF is turned off, while the branch current generated by the image signal corresponding to the exposure readout becomes zero. At this time, the traditional signal acquisition method cannot eliminate this effect through CDS, which degrades the smear effect. However, through the clamping row design of this application, the current difference between the reset and image signals can be eliminated by the correlated double sampling technique.

[0060] By selecting the corresponding pixel unit 11 in the pixel array 10 as the preset clamping row, the original clamping circuit 12 can be replaced for clamping, simplifying the structure of the pixel array 10 and reducing the design cost. At the same time, when facing different preset states, voltage clamping can be realized to form corresponding current branches. Current differences can be eliminated through related double sampling, improving the imaging consistency of the pixel array and improving image contrast and image quality.

[0061] Among them, the pixel unit 11 in the pixel array 10 can be selected as the preset clamping row according to the needs. When quantizing row by row, the pixel unit 11 in the next row can be selected as the quantization row, or two rows of pixel units 11 or multiple rows of pixel units 11 can be quantization rows and clamping rows respectively. The specific setting method is not limited.

[0062] In an optional embodiment, step 20 includes:

[0063] Step 21: At least when providing row selection signal rowsel to row selection transistor RS of the i-th quantized row, at least the (i+n)th and / or (in)th row in pixel array 10 is a preset clamping row, and a first clamping control signal Cla1 is provided to each corresponding row selection transistor RS of the preset clamping row. When the signal output transistor SF of the i-th quantized row is turned off, the row selection transistor RS corresponding to the preset clamping row is triggered to turn on and clamps the connected output line to the first preset voltage, where n is an integer greater than or equal to 1.

[0064] In this embodiment, when the pixel unit 11 in the i-th row is set as the quantization row, the (i+n) and / or (in) rows are set as preset clamping rows. When the row selection signal rowsel is output to the row selection transistor RS of each pixel unit 11 in the quantization row, the first clamping control signal Cla1 is output to the row selection transistor RS corresponding to the (i+n) and / or (in) rows, where n is an integer greater than or equal to 1. Specifically, it can be selected according to actual needs. One or more rows can be selected as the clamping rows of the current quantization row at the same time.

[0065] Optionally, the number of output channels of the first clamp control signal Cla1 is the same as the number of output channels of the row selection signal rowsel during each line quantization.

[0066] Taking a quantized row as an example, when outputting a row selection signal rowsel to the row selection transistor RS of each pixel unit 11 in the i-th row, a first clamping control signal Cla1 is simultaneously output to the row selection transistor RS corresponding to each pixel unit 11 in the adjacent (i+n) or (in)-th row.

[0067] Taking a quantized row consisting of two rows of pixel units 11 as an example, when outputting two row selection signals rowsel to the pixel units 11 of the adjacent i-th row and the pixel units 11 of the (i+1)-th row, a first clamp signal is simultaneously output to the row selection transistor RS corresponding to each pixel unit 11 of the adjacent (in)-th row, and another first clamp signal is output to the row selection transistor RS corresponding to each pixel unit 11 of the adjacent (i+1+n)-th row.

[0068] For example, when n=1, taking a quantization row consisting of two rows of pixel units 11 as an example, this means that the image sensor has a working mode where pixel units 11 of adjacent odd and even rows are selected simultaneously, which requires supporting the simultaneous quantization of rows 2m and 2m+1. At this time, the row selection transistors RS of rows 2m and 2m+1 simultaneously receive the row selection signal rowsel and perform normal quantization. At the same time, a first clamping control signal Cla1 is output to row 2m-1 to set the pixel units 11 of row 2m-1 as the clamping row corresponding to row 2m, and another first clamping control signal Cla1 is output to row 2m+2 to set the pixel units 11 of row 2m+2 as the clamping row corresponding to row 2m+1.

[0069] Each quantization row has a corresponding clamping row. During the exposure readout period, when the row selection signal rowsel is output to the row selection transistors RS of each quantization row, the first clamping control signal Cla1 is output to the row selection transistors RS of each clamping row. The signal output transistor SF of the quantization row is turned off because the voltage of the floating diffusion node FD is too low. At this time, no current branch is generated on the signal output line connected to the quantization row. The row selection transistor RS of the clamping row receives the first clamping control signal Cla1 and is turned on under control. The positive power supply terminal PIXVDD, the pixel unit 11 of the corresponding clamping row and the corresponding output line are connected to form a current branch, and clamp the connected output line to the first preset voltage. The magnitude of the first preset voltage of clamping is determined by the voltage of each terminal of the signal output transistor SF and the row selection transistor RS of the clamping row.

[0070] The quantization line quantizes the reset signal during the reset readout period, which also generates a current branch. Therefore, there is always a current branch for the quantization line during both the reset readout period and the overexposed exposure readout period. The current difference between the reset readout period and the exposure readout period can be eliminated by the relevant double sampling technique.

[0071] The row selection transistor RS of the clamped row can be triggered to turn on based on the magnitude of the first clamp control signal Cla1, or based on the voltage difference between the gate and the source. In an optional embodiment, step 21 includes:

[0072] While providing a row selection signal rowsel to the row selection transistor RS of the i-th quantized row, a first clamping control signal Cla1 is provided to each corresponding row selection transistor RS of the preset clamped row, so as to trigger the output of a first preset voltage based on the voltage value of the output line corresponding to the pixel unit 11 of the i-th quantized row.

[0073] During the exposure readout period, when the row selection signal `rowsel` is output to the row selection transistors `RS` of each quantization row, a first clamping control signal `Cla1` is output to the row selection transistors `RS` of each clamped row. The signal output transistor `SF` of the quantization row is turned off due to the low voltage of the floating diffusion node `FD`. At this time, no current branch is generated on the signal output line connected to that quantization row. The row selection transistors `RS` of the clamped row receive the first clamping control signal `Cla1` and form a corresponding voltage difference with the voltage on the output line. By setting the magnitude of the first clamping control signal `Cla1`, when no current branch is generated in the quantization row, the row selection transistors of the clamped row are clamped. When the voltage difference between the gate and source of the select transistor RS is greater than the threshold voltage, the row select transistor RS of the clamped row is turned on. At this time, the clamped row is in the reset readout period state, that is, the gate of the reset transistor RST of the row is high, the floating diffusion node FD of the clamped row is close to the positive voltage, and the signal output transistor SF is turned on. Therefore, the positive power supply terminal PIXVDD, the pixel unit 11 of the corresponding clamped row and the corresponding output line are connected to form a current branch. The pixel unit 11 of the clamped row can clamp the output line. The magnitude of the first preset voltage of clamping is determined by the threshold voltage and gate voltage of the signal row select transistor RS of the clamped row.

[0074] The quantization line quantizes the reset signal during the reset readout period, which also generates a current branch. Therefore, there is always a current branch for the quantization line during both the reset readout period and the overexposed exposure readout period. The current difference between the reset readout period and the exposure readout period can be eliminated by the relevant double sampling technique.

[0075] by Figure 7 For example, assuming that the pixel unit 11 in the first row and the pixel unit 11 in the second row are the quantization row and the clamping row respectively, when the pixel unit 11 in the first row is exposed and read out, if an overexposure state occurs, the signal output transistor SF of the pixel unit 11 in the first row is turned off. The pixel unit 11 in the second row acts as the clamping row. The row selection transistor RS of the pixel unit 11 in the second row receives the first clamping control signal Cla1, and the corresponding row selection transistor RS of the second row is triggered to turn on. The signal output transistor SF of the corresponding pixel unit 11 in the second row receives a positive voltage, and the signal output transistor SF is triggered to turn on, forming a current branch with the output line and clamping to the first preset voltage.

[0076] Or such as Figure 8As shown, when the second row of pixel units 11 is exposed and read out, if overexposure occurs, the signal output transistor SF of the second row of pixel units 11 is turned off. The first row of pixel units 11 acts as a clamping row. The row selection transistor RS of the first row of pixel units 11 receives the first clamping control signal Cla1, and the corresponding row selection transistor RS of the first row is triggered to turn on. The signal output transistor SF of the corresponding pixel unit 11 of the first row receives a positive voltage, and the signal output transistor SF is triggered to turn on, forming a current branch with the output line and clamping to the first preset voltage.

[0077] The value of n can be set according to requirements, such as 1, 2, 3, etc., and is set to connect two or two groups of pixel units 11 in the same column of the clamping row and quantization row to the same output line.

[0078] As can be seen from the design in this example, during the exposure readout period, when the image sensor is in an overexposed state, the voltage of the floating diffusion node FD in the quantization row is too low, such as... Figure 5 As shown, this may cause the signal output transistor SF to be directly turned off, the current in the current branch of the pixel unit 11 in the quantization row to be zero, while the current branch in the reset readout period remains unchanged. At this time, the current trend of the entire pixel array 10 changes significantly compared with the quantization process in the reset readout period. The current environment of different rows in the array is different, and the current influence cannot be eliminated by related double sampling, which in turn causes the inconsistency problem of the pixel array 10, seriously affecting the image contrast and image quality, and reducing image detail information. In this embodiment, the design based on clamping rows can effectively improve the above problems.

[0079] Furthermore, in order to achieve clamping in a preset state when there is no overexposure, such as Figure 9 and Figure 10 As shown, in an optional embodiment, the pixel array 10 further includes a plurality of clamping circuits 12, each clamping circuit 12 being connected to a corresponding output line, and the driving method of the pixel array 10 further includes:

[0080] Step S30: When providing row selection signal rowsel to row selection transistor RS of each row, a second clamping control signal Cla2 is provided to clamping circuit 12. When the voltage value on the connected output line reaches a preset threshold, clamping the connected output line to the second preset voltage.

[0081] Specifically, the clamping circuit is designed to limit the signal amplitude output from the pixel units in the image sensor pixel array to the column lines. Optionally, the clamping circuit is located at the top or bottom of the pixel array. During the exposure readout period, when there is excessive charge in the photosensitive element, the voltage of the floating diffusion node of the pixel unit in the quantization row is low, and the voltage of the output line decreases. When the voltage of the output line reaches a preset threshold, the clamping circuit is turned on and performs clamping operation, clamping the voltage of the output line to a second preset voltage. At this time, there are two current branches: one for the pixel unit in the quantization row and the other for the clamping circuit. During the reset readout period, the image sensor quantizes the reset signal, such as... Figure 4 As shown, since the current branch during the reset readout period is the same as the current branch during the exposure readout period, the current difference can be eliminated by the correlation double sampling technique.

[0082] In one example, during the exposure readout period, when the row selection signal rowsel is output to the corresponding quantization row, the first clamp control signal Cla1 is simultaneously output to the clamp row, and the second clamp control signal Cla2 is output to the clamp circuit 12.

[0083] When there is no overexposure and the floating diffusion node FD voltage of the pixel unit 11 in the quantization row is small, the row selection transistor RS of the quantization row is turned on and forms the first current branch. The voltage on the output line is small. At this time, when the voltage on the output line drops to the preset threshold, the clamping circuit 12 is triggered to turn on and provides the second current branch. At the same time, the voltage of the output line is clamped to the second preset voltage. At this time, the source voltage of the row selection transistor RS of the clamping row is greater than zero, and the gate-source voltage difference of the row selection transistor RS of the clamping row does not reach the threshold voltage. The pixel unit 11 of the clamping row remains off, and the clamping circuit 12 plays a clamping role.

[0084] When overexposure occurs, the floating diffusion node FD voltage of the pixel unit 11 in the quantization row is too low, causing the row selection transistor RS to turn off, resulting in no current generation and zero voltage on the output line. At this time, the clamping circuit 12 is triggered to conduct and provides a second current branch to clamp the voltage of the output line to a second preset voltage. Furthermore, since the gate-source voltage difference of the row selection transistor RS in the clamping row reaches the threshold voltage, the pixel unit 11 in the clamping row is turned on. Both the pixel unit 11 in the clamping row and the clamping circuit 12 play a clamping role. The final preset voltage of clamping is determined by the specific circuit of the clamping circuit 12 and the pixel unit 11 in the clamping row and the clamping voltage.

[0085] Furthermore, during the exposure readout period, when the output voltage is too low and a small voltage is generated or the signal output transistor SF is turned off during exposure, the clamping circuit 12 provides a current branch. Therefore, during the reset readout period and the overexposed exposure readout period, there are always two current branches for the quantization line and the clamping line. Thus, the current difference generated during the reset readout period and the exposure readout period can be eliminated by the relevant double sampling technique.

[0086] The preset threshold can be set according to requirements. Meanwhile, the magnitudes of the first preset voltage and the second preset voltage can be set according to the exposure clamping requirements. In an optional embodiment, the clamping circuit 12 is triggered to conduct when the voltage value on the connected output line drops to the lower voltage limit and clamps the connected output line to the second preset voltage, where the lower voltage limit is greater than zero; and / or, the voltage value of the first preset voltage is less than the voltage value of the second preset voltage.

[0087] In this embodiment, during the exposure readout period, when the row selection signal rowsel is output to the corresponding quantization row, the first clamp control signal Cla1 is output to the clamp row, and the second clamp control signal Cla2 is output to the clamp circuit 12.

[0088] When there is no overexposure and the floating diffusion node FD voltage of the pixel unit 11 in the quantization row is small, the row selection transistor RS of the quantization row is turned on and forms the first current branch. The voltage on the output line is small. At this time, when the voltage on the output line drops to the lower voltage limit, such as 0.2V, the clamping circuit 12 is triggered to turn on and provides the second current branch. At the same time, the voltage of the output line is clamped to the second preset voltage. At this time, the source voltage of the row selection transistor RS of the clamping row is greater than zero, and the gate-source voltage difference of the row selection transistor RS of the clamping row does not reach the threshold voltage. The pixel unit 11 of the clamping row remains off, and the clamping circuit 12 performs the clamping function.

[0089] When overexposure occurs, the floating diffusion node FD voltage of the pixel unit 11 in the quantization row is too low, causing the row selection transistor RS to turn off, resulting in no current generation and zero voltage on the output line. At this time, the clamping circuit 12 is triggered to conduct and provides a second current branch to clamp the voltage of the output line to a second preset voltage. Furthermore, since the gate-source voltage difference of the row selection transistor RS in the clamping row reaches a threshold voltage, the pixel unit 11 in the clamping row is turned on. Both the pixel unit 11 and the clamping circuit 12 in the clamping row play a clamping role. Specifically, when no overexposure occurs and a preset state is present, the clamping circuit 12 provides the second preset voltage for clamping, and when the preset state of overexposure occurs, the clamping row provides a smaller first preset voltage for clamping.

[0090] The clamping circuit 12 can adopt a corresponding clamping switch or other structure. In an optional embodiment, for example... Figure 10 As shown, the clamping circuit 12 includes a clamping transistor Q1 and a switching transistor Q2 connected in series between the positive power supply terminal PIXVDD and the output line. The control terminal of the clamping transistor Q1 is used to input the first reference voltage VREF1, and the control terminal of the switching transistor Q2 is used to input the second clamping control signal Cla2.

[0091] During the exposure readout period, when the voltage on the output line drops to the lower voltage limit, such as 0.2V, the switching transistor Q2 turns on, the clamping transistor Q1 receives the first reference voltage VREF1 and is triggered to turn on, and provides the current branch. At the same time, the clamping transistor Q1 clamps the voltage of the output line to the second preset voltage, which is determined by the first reference voltage VREF1 and the threshold voltage of the clamping transistor Q1.

[0092] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0093] The beneficial effects of the present invention embodiments compared with the prior art are as follows: In the above-described driving method of pixel array 10, row selection signals rowsel are output line by line to perform line-by-line quantization. When at least row selection signals rowsel are provided to the row selection transistors RS of the quantized rows, a first clamping control signal Cla1 is provided to the row selection transistors RS corresponding to the preset clamping rows in pixel array 10. When an illumination problem causes the signal output transistor SF to be in a preset state, such as when the output current is too small or it is turned off, the row selection transistors RS corresponding to the preset clamping rows are triggered to conduct and clamp the connected output lines to the first preset voltage, and generate a current branch. The current branch is the same during the quantization process of the reset readout period and the exposure readout period. Therefore, the current difference can be eliminated by correlated double sampling, thereby improving the imaging consistency of pixel array 10 and improving image contrast and image quality.

[0094] Corresponding to the driving method of the pixel array 10 described above, a second aspect of the present invention proposes an image sensor, such as... Figures 1 to 3 as well as Figure 11 As shown, the image sensor includes a pixel array 10 and a control circuit 20, and the pixel array 10 adopts the array structure described above.

[0095] Control circuit 20 is connected to each row selection line. To address the different preset states of the aforementioned signal output transistor SF, control circuit 20 is used for:

[0096] Provide row selection signals rowsel to each row selection transistor RS;

[0097] At least when providing a row selection signal rowsel to the row selection transistor RS of the quantization row, a first clamping control signal Cla1 is provided to each corresponding row selection transistor RS of the preset clamping row in the pixel array 10. The preset clamping row and the quantization row are connected to the same output line. The corresponding row selection transistor RS of the preset clamping row is triggered to conduct when the signal output transistor SF of the quantization row is in a preset state and clamps the connected output line to the first preset voltage.

[0098] In this embodiment, the pixel unit 11 operates cyclically during the reset readout period and the exposure readout period. During the reset readout period, the reset signal is quantized, and during the exposure readout period, the pixel signal is quantized. Taking the example of each row of pixel units connected to the same row selection line, when the row selection signal rowsel is output to each row selection transistor RS, it indicates that the pixel unit corresponding to the row selection transistor RS is subjected to exposure quantization. When one or more rows of pixel units 11 are subjected to exposure quantization, the row of pixel units 11 or the row of pixel units 11 can be defined as a quantized row. When each pixel unit 11 is not quantized, it can be defined as a non-quantized row. One or more rows of pixel units 11 in the non-quantized row can be selected as a preset clamping row.

[0099] When quantizing each row sequentially, row-by-row quantization can be used, or multiple rows can be grouped together and each group of pixel units 11 can be sequentially quantized. For example, two adjacent rows of pixel units 11 can be grouped together as a quantization row and the quantization row can be quantized sequentially.

[0100] When the control circuit 20 outputs the row selection signal rowsel to the row selection transistor RS of each pixel unit 11 in the quantization row, the quantization row may include a row of pixel units 11 or multiple adjacent rows of pixel units 11. The output is synchronously sent to the corresponding row selection transistor RS of the preset clamping row. The number of output channels of the first clamping control signal Cla1 may be the same as or different from the number of output channels of the row selection signal rowsel during each row quantization. That is, during row quantization, each quantization may output one or more first clamping control signals Cla1 to the selected row or multiple preset clamping rows.

[0101] When there is excessive charge in the photosensitive element 101, the voltage of the floating diffusion node FD in the pixel unit 11 of the quantization row is low, causing the output voltage of the signal output transistor SF to decrease or the signal output transistor SF to be turned off. That is, when the signal output transistor SF is in the corresponding preset state, the voltage of the output line decreases or becomes zero. The row selection transistor RS of the clamping row receives the first clamping control signal Cla1 and forms a corresponding voltage difference with the voltage on the output line. By setting the magnitude of the first clamping control signal Cla1, when a small current or no current branch is generated in the quantization row, the gate and source of the preset clamping row selection transistor RS are clamped. When the voltage difference is greater than the threshold voltage, the row selection transistor RS of the preset clamping row is triggered and turned on. At this time, the clamping row is in the reset readout period state, that is, the gate of the reset transistor RST of the clamping row is at a high level, the floating diffusion node FD of the clamping row is close to the positive voltage, and the signal output transistor SF is turned on. Therefore, the positive power supply terminal PIXVDD, the pixel unit 11 of the corresponding clamping row and the corresponding output line are connected to form a current branch. The pixel unit 11 of the preset clamping row can clamp the output line. The magnitude of the first preset clamping voltage is determined by the threshold voltage and gate voltage of the signal row selection transistor RS of the clamping row.

[0102] The quantization line quantizes the reset signal during the reset readout period, which also generates a current branch. Therefore, for the quantization line, there is always the same number of current branches during the reset readout period and the overexposed exposure readout period. The current difference generated during the reset readout period and the exposure readout period can be eliminated by the related double sampling technique.

[0103] Therefore, the control circuit 20 can replace the original clamping circuit 12 for clamping by selecting the corresponding pixel unit 11 in the pixel array 10 as the preset clamping row, thereby simplifying the structure of the pixel array 10 and reducing the design cost. At the same time, when facing different preset states, voltage clamping can be realized to form corresponding current branches. Current differences can be eliminated through related double sampling, thereby improving the imaging consistency of the pixel array 10 and improving image contrast and image quality.

[0104] In an optional embodiment, the control circuit 20 is specifically used for:

[0105] At least when providing row selection signal rowsel to row selection transistor RS of the i-th quantized row, the (i+n)th and / or (in)th row in pixel array 10 is a preset clamping row, and a first clamping control signal Cla1 is provided to each corresponding row selection transistor RS of the preset clamping row. When the signal output transistor SF of the i-th quantized row is turned off, the row selection transistor RS corresponding to the preset clamping row is triggered to turn on and clamps the connected output line to the first preset voltage, where n is an integer greater than or equal to 1.

[0106] In this embodiment, when the control circuit 20 sets the pixel unit of the i-th row as the quantization row, it sets the (i+n) and / or (in) rows as preset clamping rows. When outputting the row selection signal rowsel to the row selection transistor RS of each pixel unit 11 of the quantization row, it synchronously outputs the first clamping control signal Cla1 to the row selection transistor RS corresponding to the (i+n) and / or (in) rows, where n is an integer greater than or equal to 1, and can be selected according to actual needs.

[0107] Optionally, the number of output channels of the first clamp control signal Cla1 is the same as the number of output channels of the row selection signal rowsel during each line quantization.

[0108] Taking a quantized row as an example, when outputting a row selection signal rowsel to the row selection transistor RS of each pixel unit 11 in the i-th row, a first clamping control signal Cla1 is simultaneously output to the row selection transistor RS corresponding to each pixel unit 11 in the adjacent (i+n) or (in)-th row.

[0109] Taking a quantized row consisting of two rows of pixel units 11 as an example, when the control circuit 20 outputs two row selection signals rowsel to the pixel units 11 of the adjacent i-th row and the pixel units 11 of the (i+1)-th row, it simultaneously outputs a first clamp signal to the row selection transistor RS corresponding to each pixel unit 11 of the adjacent (in)-th row, and outputs another first clamp signal to the row selection transistor RS corresponding to each pixel unit 11 of the adjacent (i+1+n)-th row.

[0110] For example, when n=1, taking a quantization row consisting of two rows of pixel units 11 as an example, this means that the image sensor has a working mode where pixel units 11 in adjacent odd and even rows are selected simultaneously, i.e., it needs to support the mode where rows 2m and 2m+1 are selected simultaneously. At this time, the row selection transistors RS of rows 2m and 2m+1 simultaneously receive the row selection signal rowsel and perform normal quantization. At the same time, the control circuit 20 outputs a first clamping control signal Cla1 to row 2m-1 to set the pixel units 11 of row 2m-1 as the clamping row corresponding to row 2m, and outputs another first clamping control signal Cla1 to row 2m+2 to set the pixel units 11 of row 2m+2 as the clamping row corresponding to row 2m+1.

[0111] Each quantization row has a corresponding clamping row. During the exposure readout period, when the control circuit 20 outputs the row selection signal rowsel to the row selection transistors RS of each quantization row, it outputs the first clamping control signal Cla1 to the row selection transistors RS of each clamping row. The signal output transistor SF of the quantization row is turned off because the voltage of the floating diffusion node FD is too low. At this time, no current branch is generated on the signal output line connected to that quantization row. The row selection transistor RS of the clamping row receives the first clamping control signal Cla1 and forms a corresponding voltage difference with the voltage on the output line. By setting the magnitude of the corresponding first clamping control signal Cla1, when the quantization row... When no current branch is generated, the voltage difference between the gate and source of the row selection transistor RS of the clamped row is greater than the threshold voltage. At this time, the row selection transistor RS of the clamped row is turned on, and the clamped row is in the reset readout period state. That is, the gate of the RST transistor of the row is high, the floating diffusion node FD of the clamped row is close to the positive voltage, and the signal output transistor SF is turned on. Therefore, the positive power supply terminal PIXVDD, the pixel unit 11 of the corresponding clamped row and the corresponding output line are connected to form a current branch. The pixel unit 11 of the clamped row can clamp the output line. The magnitude of the first preset voltage of clamping is determined by the threshold voltage and gate voltage of the signal row selection transistor RS of the clamped row.

[0112] The quantization line quantizes the reset signal during the reset readout period, which also generates a current branch. Therefore, there is always a current branch for the quantization line during both the reset readout period and the overexposed exposure readout period. The current difference between the reset readout period and the exposure readout period can be eliminated by the relevant double sampling technique.

[0113] by Figure 7 For example, assuming that the pixel unit 11 in the first row and the pixel unit 11 in the second row are the quantization row and the clamping row respectively, when the pixel unit 11 in the first row is exposed and sampled, if overexposure occurs, the signal output transistor SF of the pixel unit 11 in the first row is turned off. The pixel unit 11 in the second row acts as the clamping row. The row selection transistor RS of the pixel unit 11 in the second row receives the first clamping control signal Cla1, and the corresponding row selection transistor RS of the second row is triggered to turn on. The signal output transistor SF of the corresponding pixel unit 11 in the second row receives a positive voltage, and the signal output transistor SF is triggered to turn on, forming a current branch with the output line and clamping to the first preset voltage.

[0114] Or such as Figure 8As shown, when the second row of pixel units 11 is exposed for sampling, if overexposure occurs, the signal output transistor SF of the second row of pixel units 11 is turned off. The first row of pixel units 11 acts as a clamping row. The row selection transistor RS of the first row of pixel units 11 receives the first clamping control signal Cla1, and the corresponding row selection transistor RS of the first row is triggered to turn on. The signal output transistor SF of the corresponding pixel unit 11 of the first row receives a positive voltage, and the signal output transistor SF is triggered to turn on, forming a current branch with the output line and clamping to the first preset voltage.

[0115] The value of n can be set according to requirements, such as 1, 2, 3, etc., and is set to connect two or two groups of pixel units 11 in the same column of the clamping row and quantization row to the same output line.

[0116] Furthermore, in order to achieve clamping without overexposure, such as Figure 9 , Figure 10 and Figure 12 As shown, the pixel array 10 also includes multiple clamping circuits 12, each of which is connected to an output line.

[0117] Control circuit 20 is also used for:

[0118] When providing the row selection signal rowsel to the row selection transistor RS of each row, a second clamping control signal Cla2 is provided to the clamping circuit 12. The clamping circuit 12 is triggered to conduct when the voltage value on the connected output line reaches a preset threshold and clamps the connected output line to the second preset voltage.

[0119] Specifically, the clamping circuit 12 is designed to limit the signal amplitude output from the pixel unit 11 in the image sensor pixel array 10 to the column lines. Optionally, the clamping circuit 12 is located at the top or bottom of the pixel array 10. During the exposure readout period, when there is excessive charge in the photosensitive element 101, the floating diffusion node FD voltage of the pixel unit 11 in the quantization row is low, and the voltage of the output line decreases. When the voltage of the output line reaches a preset threshold, the clamping circuit 12 is turned on and performs clamping operation, clamping the voltage of the output line to a second preset voltage. At this time, there are two current branches: the pixel unit in the quantization row and the clamping circuit 12. During the reset readout period, the image sensor quantizes the reset signal, such as... Figure 4 As shown, since the current branch during the reset readout period is the same as the current branch during the exposure readout period, the current difference can be eliminated by the correlation double sampling technique.

[0120] In one example, during the exposure readout period, when the control circuit 20 outputs the row selection signal rowsel to the corresponding quantization row, it simultaneously outputs the first clamp control signal Cla1 to the clamp row and the second clamp control signal Cla2 to the clamp circuit 12.

[0121] When there is no overexposure and the floating diffusion node FD voltage of the pixel unit 11 in the quantization row is small, the row selection transistor RS of the quantization row is turned on and forms the first current branch. The voltage on the output line is small. At this time, when the voltage on the output line drops to the voltage preset threshold, the clamping circuit 12 is triggered to turn on and provides the second current branch. At the same time, the voltage of the output line is clamped to the second preset voltage. At this time, the source voltage of the row selection transistor RS of the clamping row is greater than zero, and the gate-source voltage difference of the row selection transistor RS of the clamping row does not reach the threshold voltage. The pixel unit 11 of the clamping row remains off, and the clamping circuit 12 plays a clamping role.

[0122] When overexposure occurs, the floating diffusion node FD voltage of pixel unit 11 in the quantization row is too low, the row selection transistor RS is turned off, no current is generated, and the voltage on the output line is zero. At this time, the clamping circuit 12 is triggered to conduct and provides a second current branch to clamp the voltage of the output line to a second preset voltage. At this time, since the gate-source voltage difference of the row selection transistor RS of the clamping row reaches the threshold voltage, the pixel unit 11 of the clamping row is turned on. Both the pixel unit 11 of the clamping row and the clamping circuit 12 play a clamping role. The final preset voltage of clamping is determined by the specific circuit of the clamping circuit 12 and the pixel unit 11 of the clamping row and the clamping voltage.

[0123] Furthermore, during the exposure readout period, when the output voltage is too low and a small voltage is generated or the signal output transistor SF is turned off during exposure, the clamping circuit 12 provides a current branch. Therefore, during the reset readout period and the overexposed exposure readout period, there are always two current branches for the quantization line and the clamping line. Thus, the current difference generated during the reset readout period and the exposure readout period can be eliminated by the relevant double sampling technique.

[0124] The preset threshold can be set according to requirements, and the magnitude of the first preset voltage and the second preset voltage can be set according to the exposure clamping requirements. In an optional embodiment, the clamping circuit 12 is triggered to conduct when the voltage value on the connected output line drops to the lower voltage limit and clamps the connected output line to the second preset voltage, where the lower voltage limit is greater than zero; and / or, the voltage value of the first preset voltage is less than the voltage value of the second preset voltage.

[0125] In this embodiment, during the exposure readout period, when the row selection signal rowsel is output to the corresponding quantization row, the first clamp control signal Cla1 is output to the clamp row, and the second clamp control signal Cla2 is output to the clamp circuit 12.

[0126] When there is no overexposure and the floating diffusion node FD voltage of the pixel unit 11 in the quantization row is small, the row selection transistor RS of the quantization row is turned on and forms the first current branch. The voltage on the output line is small. At this time, when the voltage on the output line drops to the lower voltage limit, such as 0.2V, the clamping circuit 12 is triggered to turn on and provides the second current branch. At the same time, the voltage of the output line is clamped to the second preset voltage. At this time, the source voltage of the row selection transistor RS of the clamping row is greater than zero, and the gate-source voltage difference of the row selection transistor RS of the clamping row does not reach the threshold voltage. The pixel unit 11 of the clamping row remains off, and the clamping circuit 12 performs the clamping function.

[0127] When overexposure occurs, the floating diffusion node FD voltage of pixel unit 11 in the quantization row is too low, causing the row selection transistor RS to turn off, resulting in no current generation and zero voltage on the output line. At this time, the clamping circuit 12 is triggered to conduct and provides a second current branch to clamp the voltage of the output line to a second preset voltage. Furthermore, since the gate-source voltage difference of the row selection transistor RS in the clamping row reaches a threshold voltage, pixel unit 11 in the clamping row is turned on. Both pixel unit 11 and clamping circuit 12 in the clamping row play a clamping role. The final preset voltage of the clamping is determined by pixel unit 11 in the clamping row. That is, when no overexposure occurs and a preset state is present, the clamping circuit 12 provides a second preset voltage for clamping, and when the preset state of overexposure occurs, the clamping row provides a smaller first preset voltage for clamping.

[0128] The clamping circuit 12 can adopt a corresponding clamping switch or other structure. In an optional embodiment, such as... Figure 10 As shown, the clamping circuit 12 includes a clamping transistor Q1 and a switching transistor Q2 connected in series between the positive power supply terminal PIXVDD and the output line. The control terminal of the clamping transistor Q1 is used to input the first reference voltage VREF1, and the control terminal of the switching transistor Q2 is used to input the second clamping control signal Cla2.

[0129] During the exposure readout period, when the voltage on the output line drops to the lower voltage limit, such as 0.2V, the switching transistor Q2 turns on, the clamping transistor Q1 receives the first reference voltage VREF1 and is triggered to turn on, and provides the current branch. At the same time, the clamping transistor Q1 clamps the voltage of the output line to the second preset voltage, which is determined by the first reference voltage VREF1 and the threshold voltage of the clamping transistor Q1.

[0130] The image sensor may also include corresponding readout circuits and processing circuits. The readout circuits are connected to each output line and receive the output signals from each column of output lines during the reset readout period and the exposure readout period. They then process the signals, output corresponding digital code values, and transmit these digital code values ​​to the processing circuits. The processing circuits determine the current image information based on the digital code values. The readout circuits may include corresponding ramp voltage circuits, comparator circuits, counters, and latches, while the processing circuits may employ corresponding controllers or processors.

[0131] The control circuit 20 may include a corresponding memory, processor, signal generator, etc., for example, it includes a timing controller and a signal generator. The timing controller outputs the row selection signal rowsel, the first clamping control signal Cla1, and the second clamping control signal Cla2 based on the output timing control signal generator of the row selection signal rowsel. Alternatively, different signal generators may be used to output different row selection signals rowsel, the first clamping control signal Cla1, and the second clamping control signal Cla2.

[0132] Among them, the pixel unit 11 in the pixel array 10 can be selected as the preset clamping row according to the needs. When quantizing row by row, the pixel unit 11 in the next row can be selected as the quantization row, or two rows of pixel units 11 or multiple rows of pixel units 11 can be quantization rows and clamping rows respectively. The specific setting method is not limited.

[0133] In an optional embodiment, at least two pixel units 11 connected to the same output line form a pixel unit group 13, and the row selection line connected to the pixel units 11 of the pixel unit group 13 forms a row selection line group. When one or more rows in the pixel unit group 13 are quantization rows, the other row or more rows in the pixel unit group 13 are clamping rows.

[0134] Correspondingly, such as Figure 13 and Figure 14 As shown, the control circuit 20 includes:

[0135] The row selection output circuit 21 is connected to each row selection line and is used to output the row selection signal rowsel to each row selection transistor RS.

[0136] The first voltage output circuit 22 is connected to each row selection line and is used to output the first clamping control signal Cla1 to another row selection line in the row selection line group when the row selection output circuit 21 outputs the row selection signal rowsel to the preset row selection line in the row selection line group.

[0137] In this embodiment, it is assumed that the pixel unit group 13 includes three pixel units 11. The three pixel units 11 can be arranged adjacently or not adjacently. It is assumed that the three pixel units are arranged adjacently.

[0138] The row selection output circuit 21 outputs the row selection signal rowsel to the row selection transistor RS of each row pixel unit 11 according to the normal output timing, thereby quantizing each row pixel unit 11.

[0139] The first voltage output circuit 22 is used to output the first clamping control signal Cla1, which is used to clamp the circuit during overexposure.

[0140] The first voltage output circuit 22 is connected to the output line and can select the output of the first clamping control signal Cla1 based on the output signal of the row selection output circuit 21 or the on / off state of the signal output transistor SF of the corresponding quantized row.

[0141] like Figure 13 As shown, assuming that when the row selection output circuit 21 outputs the row selection signal rowsel to the first row selection line Lrow1 and each row selection transistor RS of the first row, the first voltage output circuit 22 detects that the first row selection line Lrow1 is the row selection signal rowsel or detects that the first row signal output transistor SF is turned off, the first voltage output circuit 22 outputs the first clamping control signal Cla1 to the second row selection line Lrow2 and each row selection transistor RS of the second row, and outputs the first clamping control signal Cla1 to the third row selection line Lrow2 and each row selection transistor RS of the third row, so as to control the pixel units 11 of the second and third rows to provide clamping effect when the first row signal output transistor SF is turned off due to overexposure.

[0142] Or such as Figure 14 As shown, assuming that when the row selection output circuit 21 outputs the row selection signal rowsel to the second row selection line Lrow2 and each row selection transistor RS of the second row, the first voltage output circuit 22 detects that the second row selection line Lrow2 is the row selection signal rowsel or detects that the signal output transistor SF of the second row is turned off, the first voltage output circuit 22 outputs the first clamping control signal Cla1 to the first row selection line Lrow1 and each row selection transistor RS of the first row, and outputs the first clamping control signal Cla1 to the third row selection line Lrow2 and each row selection transistor RS of the third row, so as to control the pixel units 11 of the first and third rows to provide clamping effect when the signal output transistor SF of the second row is turned off due to overexposure.

[0143] Similarly, assuming that when the row selection output circuit 21 outputs the row selection signal rowsel to the third row selection line Lrow3 and each row selection transistor RS of the third row, the first voltage output circuit 22 detects that the third row selection line Lrow3 is the row selection signal rowsel or detects that the signal output transistor SF of the third row is turned off, the first voltage output circuit 22 outputs the first clamping control signal Cla1 to the first row selection line Lrow1 and each row selection transistor RS of the first row, and outputs the first clamping control signal Cla1 to the second row selection line Lrow2 and each row selection transistor RS of the second row, so as to control the pixel units 11 of the first and second rows to provide clamping effect when the signal output transistor SF of the third row is turned off due to overexposure.

[0144] Similarly, assuming that each time two row selection signals rowsel are output to two rows of pixel units 11 in pixel unit group 13, the pixel unit 11 of the other row in pixel unit group 13 is used as the clamping row.

[0145] The number and position of pixel units 11 in pixel unit group 13 can be limited according to requirements. In an optional embodiment, n=1, that is, two adjacent pixel units 11 connected to the same output line are pixel unit group 13, and two adjacent row selection lines connected to pixel unit group 13 are row selection line group, that is, the pixel units 11 of two adjacent rows are quantization row and clamping row to each other.

[0146] like Figure 15 or Figure 16 As shown, the control circuit 20 includes:

[0147] The row selection output circuit 21 is connected to each row selection line and is used to output the row selection signal rowsel to each row selection transistor RS;

[0148] The first voltage output circuit 22 is connected to each row selection line and is used to output the first clamping control signal Cla1 to the other row selection line in the row selection line group when the row selection output circuit 21 outputs the row selection signal rowsel to one of the preset row selection lines in the row selection line group.

[0149] In this embodiment, the row selection output circuit 21 outputs the row selection signal rowsel to the row selection transistor RS of each row pixel unit 11 according to the normal output timing, thereby quantizing each row pixel unit 11.

[0150] The first voltage output circuit 22 is used to output the first clamping control signal Cla1, which is used to clamp the circuit during overexposure.

[0151] The first voltage output circuit 22 is connected to the output line and can select the output of the first clamping control signal Cla1 based on the output signal of the row selection output circuit 21 or the on / off state of the signal output transistor SF of the corresponding quantized row.

[0152] like Figure 15 As shown, assuming that when the row selection output circuit 21 outputs the row selection signal rowsel to the first row selection line Lrow1 and each row selection transistor RS of the first row, the first voltage output circuit 22 detects that the first row selection line Lrow1 is the row selection signal rowsel or detects that the first row signal output transistor SF is turned off, the first voltage output circuit 22 outputs the first clamping control signal Cla1 to the second row selection line Lrow2 and each row selection transistor RS of the second row, so as to control the pixel unit 11 of the second row to provide clamping effect when the first row signal output transistor SF is turned off due to overexposure.

[0153] like Figure 16 As shown, assuming that when the row selection output circuit 21 outputs the row selection signal rowsel to the second row selection line Lrow2 and each row selection transistor RS of the second row, the first voltage output circuit 22 detects that the second row selection line Lrow2 is the row selection signal rowsel or detects that the signal output transistor SF of the second row is turned off, the first voltage output circuit 22 outputs the first clamping control signal Cla1 to the first row selection line Lrow1 and each row selection transistor RS of the first row, so as to control the pixel unit 11 of the first row to provide clamping effect when the signal output transistor SF of the second row is turned off due to overexposure.

[0154] The row selection output circuit 21 can adopt the structure of a corresponding signal source, timing controller, etc., the first signal output circuit can adopt the structure of a corresponding detection circuit, signal conversion circuit, etc., and the second signal output circuit can adopt the structure of a corresponding signal source, signal generator, etc.

[0155] like Figures 13 to 16 As shown, based on the clamping circuit structure design, in an optional embodiment, the control circuit further includes:

[0156] The second voltage output circuit 23 is connected to each clamping circuit 12 and is used to output the second clamping control signal Cla2.

[0157] The second voltage output circuit 23 is used to output a second clamping control signal Cla2 when the row selection output circuit 21 outputs the row selection signal rowsel to each row selection transistor RS, so as to achieve clamping when the current and voltage of the quantized row are too low but not overexposed.

[0158] The row selection output circuit 21 can adopt the structure of a corresponding signal source, timing controller, etc., the first signal output circuit can adopt the structure of a corresponding detection circuit, signal conversion circuit, etc., and the second signal output circuit can adopt the structure of a corresponding signal source, signal generator, etc.

[0159] Corresponding to the operating mode of the first signal output circuit, in an optional embodiment, such as Figure 17 As shown, the first voltage output circuit 22 includes:

[0160] Multiple first voltage switching circuits 221 are provided. Each first voltage switching circuit 221 is connected between the output terminals of two signal output transistors SF and the control terminal of the row selection transistor RS in the pixel unit group 13. When the signal output transistor SF of one pixel unit 11 in the pixel unit group 13 is turned off, the first voltage switching circuit 221 switches the output of the first clamping control signal Cla1 to the control terminal of the row selection transistor RS of the other pixel unit 11 in the pixel unit group 13.

[0161] In this embodiment, each pixel unit group 13 corresponds to a first voltage switching circuit 221. The first voltage switching circuit 221 operates during the overexposure readout period. Assuming that the row selection output circuit 21 outputs the row selection signal rowsel to the first row selection line Lrow1 and each row selection transistor RS of the first row, the signal output transistor SF of the first row is turned off due to overexposure, and the voltage at the output terminal of the signal output transistor SF of the first row is zero. When the first voltage switching circuit 221 detects the zero voltage, the first voltage switching circuit 221 outputs the first clamping control signal Cla1 to the row selection transistor RS of the second row. The row selection transistor RS of the second row is triggered to turn on. Furthermore, the gate voltage of the signal output transistor SF of the second row is close to the voltage of the positive power supply terminal PIXVDD. The signal output transistor SF of the second row turns on and realizes the clamping effect.

[0162] Similarly, assuming that when the row selection output circuit 21 outputs the row selection signal rowsel to the second row selection line Lrow2 and each row selection transistor RS of the second row, the signal output transistor SF of the second row is turned off due to overexposure, and the voltage at the output terminal of the signal output transistor SF of the second row is zero. When the first voltage switching circuit 221 detects the zero voltage, the first voltage switching circuit 221 outputs the first clamping control signal Cla1 to the row selection transistor RS of the first row. The row selection transistor RS of the first row is triggered to turn on. Furthermore, the gate voltage of the signal output transistor SF of the first row is close to the voltage of the positive power supply terminal PIXVDD. The signal output transistor SF of the first row turns on and achieves the clamping effect.

[0163] The first voltage switching circuit 221 can be a corresponding switching circuit, signal output circuit, etc. In an optional embodiment, such as... Figure 18 As shown, the first voltage switching circuit 221 includes:

[0164] The first switch K1 has a first terminal for inputting a first clamping control signal Cla1. The control terminal of the first switch K1 is connected to the output terminal of the signal output transistor SF of the first pixel unit 11 in the pixel unit group 13. The second terminal of the first switch K1 is connected to the control terminal of the row selection transistor RS of the second pixel unit 11 in the pixel unit group 13. The first switch K1 is turned on by a low level and turned off by a high level.

[0165] The second switch K2 has a first terminal for inputting the first clamping control signal Cla1. The control terminal of the second switch K2 is connected to the output terminal of the signal output transistor SF of the second pixel unit 11 in the pixel unit group 13. The second terminal of the second switch K2 is connected to the control terminal of the row selection transistor RS of the first pixel unit 11 in the pixel unit group 13. The second switch K2 is turned on by a low level and turned off by a high level.

[0166] In this embodiment, assuming that when the row selection output circuit 21 outputs the row selection signal rowsel to the first row selection line Lrow1 and each row selection transistor RS of the first row, the first row signal output transistor SF is turned off due to overexposure, the voltage at the output terminal of the first row signal output transistor SF is zero, the first switch K1 is triggered to turn on, and the first clamping control signal Cla1 is output to the second row row selection transistor RS. The second row row selection transistor RS is triggered to turn on, and the gate voltage of the second row signal output transistor SF is close to the voltage of the positive power supply terminal PIXVDD. The second row signal output transistor SF turns on and outputs a high level to the second switch K2. The second switch K2 turns off, and the control terminal of the first row row selection transistor RS will not input the first clamping control signal Cla1. The second row signal output transistor SF achieves the clamping function.

[0167] The first switch K1 and the second switch K2 can be switching transistors or transistors with controlled on / off states, such as PMOS transistors or PNP transistors. They can also be a combination circuit of inverters and NMOS transistors, or a combination circuit of inverters and NPN transistors. The specific circuit structure is not limited.

[0168] In another alternative embodiment, such as Figure 19 As shown, the first voltage output circuit 22 includes:

[0169] Multiple second voltage switching circuits 222 are provided. The control terminal and output terminal of each second voltage switching circuit 222 are respectively connected to a group of row selection lines. The second voltage switching circuit 222 is used to trigger the output of the first clamping control signal Cla1 to the other row selection line of the row selection group when it is detected that one of the row selection lines of the row selection line group is the row selection signal rowsel.

[0170] In this embodiment, each pair of row selection lines corresponds to a second voltage switching circuit 222. The second voltage switching circuit 222 detects the output signal of the quantized row in the corresponding pair of row selection lines and switches the output of the first clamping control signal Cla1 to the clamping row accordingly.

[0171] by Figure 19 For example, assuming that when the row selection output circuit 21 outputs the row selection signal rowsel to the first row selection line Lrow1 and each row selection transistor RS of the first row, the first row signal output transistor SF is turned off due to overexposure, and the voltage at the output terminal of the first row signal output transistor SF is zero. When the second voltage switching circuit 222 detects that the first row selection line Lrow1 is the row selection signal rowsel, the second voltage switching circuit 222 outputs the first clamping control signal Cla1 to the second row selection line Lrow2 and the corresponding row selection transistor RS. The second row row selection transistor RS is triggered to turn on, and the gate voltage of the second row signal output transistor SF is close to the voltage of the positive power supply terminal PIXVDD. The second row signal output transistor SF turns on and achieves the clamping effect.

[0172] Similarly, assuming that when the row selection output circuit 21 outputs the row selection signal rowsel to the second row selection line Lrow2 and each row selection transistor RS of the second row, the signal output transistor SF of the second row is turned off due to overexposure, and the voltage at the output terminal of the signal output transistor SF of the second row is zero. When the second voltage switching circuit 222 detects that the second row selection line Lrow2 is the row selection signal rowsel, the second voltage switching circuit 222 outputs the first clamping control signal Cla1 to the first row selection line Lrow1 and the corresponding row selection transistor RS. The row selection transistor RS of the first row is triggered to conduct, and the gate voltage of the signal output transistor SF of the first row is close to the voltage of the positive power supply terminal PIXVDD. The signal output transistor SF of the first row conducts and achieves the clamping effect.

[0173] The second voltage switching circuit 222 can employ a corresponding signal recognition circuit, signal output circuit, etc., as shown in an optional embodiment, such as... Figure 20 As shown, the second voltage switching circuit 222 includes a first comparator U1, a second comparator U2, a third switch K3, and a fourth switch K4;

[0174] The non-inverting input of the first comparator U1 is connected to the first row selection line of the row selection line group, and the non-inverting input of the second comparator U2 is connected to the second row selection line of the row selection line group. The inverting inputs of the first comparator U1 and the second comparator U2 are used to input the second reference voltage VREF2. The output of the first comparator U1 is connected to the control terminal of the third switch K3, and the output of the second comparator U2 is connected to the control terminal of the fourth switch K4. The first terminals of the third switch K3 and the fourth switch K4 are used to input the first clamping control signal Cla1. The second terminal of the third switch K3 is connected to the second row selection line of the row selection line group, and the second terminal of the fourth switch K4 is connected to the first row selection line of the row selection line group.

[0175] In this embodiment, the voltage of the row selection signal rowsel is greater than the first clamping control signal Cla1, and the second reference voltage VREF2 is less than the voltage of the row selection signal rowsel but greater than the voltage of the first clamping control signal Cla1.

[0176] Assuming that the row selection output circuit 21 outputs the row selection signal rowsel to the first row selection line Lrow1 and each row selection transistor RS of the first row, the first row signal output transistor SF is turned off due to overexposure, and the voltage at the output terminal of the first row signal output transistor SF is zero. The first comparator U1 outputs a high level, the third switch K3 is turned on, and the first clamping control signal Cla1 is transmitted to the second row selection line Lrow2 and the corresponding row selection transistor RS. The second row selection transistor RS is triggered and turned on. Furthermore, the gate voltage of the second row signal output transistor SF is close to the voltage of the positive power supply terminal PIXVDD, and the second row signal output transistor SF is turned on and performs the clamping function. At this time, the second row selection line Lrow2 is the first clamping control signal Cla1. The voltage of the first clamping control signal Cla1 is less than the voltage of the second reference voltage VREF2. The second comparator U2 outputs a low level, the fourth switch K4 is turned off, and the first clamping control signal Cla1 is not output to the first row selection line Lrow1, thus not affecting the output of the row selection signal rowsel.

[0177] Similarly, when the row selection output circuit 21 outputs the row selection signal rowsel to the second row selection line Lrow2 and each row selection transistor RS of the second row, the signal output transistor SF of the second row is turned off due to overexposure, and the voltage at the output terminal of the signal output transistor SF of the second row is zero. The second comparator U2 outputs a high level, the fourth switch K4 is turned on, and the first clamping control signal Cla1 is transmitted to the first row selection line Lrow1 and the corresponding row selection transistor RS. The row selection transistor RS of the first row is triggered and turned on. Furthermore, the gate voltage of the signal output transistor SF of the first row is close to the voltage of the positive power supply terminal PIXVDD, and the signal output transistor SF of the first row is turned on and performs the clamping function. At this time, the first row selection line Lrow1 is the first clamping control signal Cla1. The voltage of the first clamping control signal Cla1 is less than the voltage of the second reference voltage VREF2. The first comparator U1 outputs a low level, the third switch K3 is turned off, and the first clamping control signal Cla1 is not output to the second row selection line Lrow2, thus not affecting the output of the row selection signal rowsel.

[0178] Similarly, when the voltage of the row selection signal rowsel is less than the first clamping control signal Cla1, and the second reference voltage VREF2 is greater than the voltage of the row selection signal rowsel but less than the voltage of the first clamping control signal Cla1, the polarity of the input terminals of the first comparator U1 and the second comparator U2 can be switched and adjusted. That is, the inverting input terminal of the first comparator U1 is connected to the first row selection line of the row selection line group, and the inverting input terminal of the second comparator U2 is connected to the second row selection line of the row selection line group. The non-inverting input terminals of the first comparator U1 and the second comparator U2 are used to input the second reference voltage VREF2.

[0179] The third switch K3 and the fourth switch K4 can be switching transistors or other transistors with controlled on / off states, such as NMOS transistors or NPN transistors. They can also be a combination circuit of inverters and PMOS transistors, or a combination circuit of inverters and PNP transistors. The specific circuit structure is not limited.

[0180] The control circuit 20 may also employ one or more signal generators, signal generation circuits 24, etc., for example, multiple shift registers, with the signal generator or signal generation circuit sequentially outputting row selection signal rowsel or switching output of the first clamp control signal Cla1.

[0181] In another alternative embodiment, such as Figure 21 As shown, the control circuit 20 includes:

[0182] Multiple signal generation circuits 24 are provided, each signal generation circuit 24 is connected to a corresponding row selection line, and the multiple signal generation circuits 24 are used to output the row selection signal rowsel to each row selection line in turn.

[0183] The (i+n) and / or (in) signal generation circuit 24 is further configured to output a first clamping control signal Cla1 to the corresponding row selection transistor RS of the preset clamping row when the i-th signal generation circuit 24 outputs the row selection signal rowsel to the row selection transistor RS of the i-th quantized row.

[0184] In this embodiment, each signal generation circuit 24 may output a row selection signal rowsel or a first clamping control signal Cla1 based on a control signal, wherein the control signal may originate from other signal generation circuits 24 or a corresponding controller.

[0185] Correspondingly, multiple signal generation circuits 24 can be interconnected or connected to a controller respectively. For example, the signal generation circuit 24 uses shift registers, which are connected in sequence and output row selection signals in sequence under the control of the control signal. The shift registers also transmit control signals or feedback signals to each other so that when clamping control is performed, the shift register connected to the preset clamping row outputs the first clamping control signal Cla1.

[0186] Alternatively, multiple signal generation circuits 24 can be connected to a corresponding controller, which controls each signal generation circuit 24 to select the output row selection signal rowsel or the first clamping control signal Cla1 according to the timing control logic. The source of the control signal for the signal generation circuit 24 is not limited.

[0187] During the exposure readout period, when the i-th signal generation circuit 24 outputs the row selection signal rowsel to the row selection transistors RS of the i-th quantization row, the (i+n) and / or (in)-th signal generation circuit 24 simultaneously outputs the first clamping control signal Cla1 to the row selection transistors RS of the preset clamped row. Because the voltage of the floating diffusion node FD is too low, the signal output transistor SF of the quantization row is turned off. At this time, no current branch is generated on the signal output line connected to the quantization row, while the row selection transistors RS of the clamped row receive the first clamping control signal. When signal Cla1 is applied, the row selection transistor RS of the clamped row is turned on. At this time, the clamped row is in the reset readout period state, that is, the gate of the RST transistor of the row is high, the floating diffusion node FD of the clamped row is close to the positive voltage, and the signal output transistor SF is turned on. Therefore, the positive power supply terminal PIXVDD, the pixel unit 11 of the corresponding clamped row and the corresponding output line are connected to form a current branch. The pixel unit 11 of the clamped row can clamp the output line. The magnitude of the first preset voltage of clamping is determined by the threshold voltage and gate voltage of the signal row selection transistor RS of the clamped row.

[0188] The quantization line quantizes the reset signal during the reset readout period, which also generates a current branch. Therefore, there is always a current branch for the quantization line during both the reset readout period and the overexposed exposure readout period. The current difference between the reset readout period and the exposure readout period can be eliminated by the relevant double sampling technique.

[0189] For example Figure 21 As shown, assuming n=1, two adjacent pixel units 11 connected to the same output line are pixel unit group 13, and two adjacent row selection lines connected to pixel unit group 13 are row selection line group. That is, the pixel units 11 of two adjacent rows are quantization row and clamping row to each other.

[0190] During the exposure readout period, assuming that the first signal generation circuit 24 outputs the row selection signal rowsel to the first row selection line Lrow1 and the row selection transistors RS of the first row, the second signal generation circuit 24, under the control of the first signal generation circuit 24 or the controller, outputs the first clamping control signal Cla1 to the second row selection line Lrow2 and the row selection transistors RS of the second row, so as to control the pixel unit 11 of the second row to provide clamping when the signal output transistor SF of the first row is turned off due to overexposure.

[0191] The signal generation circuit 24 can adopt a signal generator, shift register, or other structures. In an optional embodiment, to meet the requirements of outputting different voltage signals, such as... Figure 22 As shown, the signal generation circuit 24 includes:

[0192] The first signal generation circuit 241 is connected to a corresponding row selection line and outputs a row selection signal rowsel to the corresponding row selection line. The second signal generation circuit 242 is connected to the output of the first signal generation circuit 241. The second signal generation circuit 242 of the (i+n)th and / or (in)th signal generation circuit is used to output a first clamping control signal Cla1 to the corresponding row selection transistors RS of the preset clamped rows when the first signal generation circuit 241 of the i-th signal generation circuit 24 outputs the row selection signal rowsel to the row selection transistor RS of the i-th quantized row. Of course, the signal generation circuit 24 can correspond one-to-one with the rows of the pixel array, and the signal generation circuit 24 can be implemented using other existing circuits that satisfy the functions of this example.

[0193] In this embodiment, the output terminals of the first signal generating circuit 241 and the second signal generating circuit 242 are connected together, and under the control of the control signal, the row selection signal rowsel or the first clamping control signal Cla1 is output.

[0194] The first signal generating circuit 241 and the second signal generating circuit 242 can be composed of corresponding voltage sources and switching circuits. When the switching circuits inside the first signal generating circuit 241 and the second signal generating circuit 242 are turned on or off respectively, the output row selection signal rowsel or the first clamping control signal Cla1 is selected.

[0195] like Figure 22 As shown, assuming n=1, two adjacent pixel units 11 connected to the same output line are pixel unit group 13, and two adjacent row selection lines connected to pixel unit group 13 are row selection line group. That is, the pixel units 11 of two adjacent rows are quantization row and clamping row to each other.

[0196] During the exposure readout period, assuming that when the first signal generation circuit 241 of the first signal generation circuit 24 outputs the row selection signal rowsel to the first row selection line Lrow1 and the row selection transistors RS of the first row, the second signal generation circuit 242 of the second signal generation circuit 24 outputs the first clamping control signal Cla1 to the second row selection line Lrow2 and the row selection transistors RS of the second row, so as to control the pixel unit 11 of the second row to provide clamping when the signal output transistor SF of the first row is turned off due to overexposure.

[0197] Correspondingly, during the exposure readout period, assuming that when the first signal generation circuit 241 of the second signal generation circuit 24 outputs the row selection signal rowsel to the second row selection line Lrow2 and the row selection transistors RS of the second row, the second signal generation circuit 242 of the first signal generation circuit 24 outputs the first clamping control signal Cla1 to the first row selection line Lrow1 and the row selection transistors RS of the first row, so as to control the pixel unit 11 of the first row to provide clamping effect when the signal output transistor SF of the second row is turned off due to overexposure.

[0198] The present invention also proposes an electronic device, which includes an image sensor. The specific structure of the image sensor is as described in the above embodiments. Since the electronic device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0199] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A method for driving a pixel array, characterized in that, The pixel array includes pixel units arranged in an array, multiple row selection lines, and multiple output lines. Each row of pixel units is connected to at least one row selection line, and each column of pixel units is connected to at least one output line. Each pixel unit includes a photosensitive element, a reset transistor, a signal output transistor, and a row selection transistor. The photosensitive element, the reset transistor, and the signal output transistor are coupled to a floating diffusion node. The row selection transistor is connected between the signal output transistor and the corresponding output line, and the row selection transistor is also connected to the corresponding row selection line. The driving method for the pixel array includes: Provide row selection signals to each of the row selection transistors; At least when the row selection signal is provided to the row selection transistor of the quantization row, a first clamping control signal is provided to each of the corresponding row selection transistors of a preset clamping row in the pixel array, the preset clamping row and the quantization row being connected to the same output line, the corresponding row selection transistor of the preset clamping row being triggered to conduct when the signal output transistor of the quantization row is in a preset state and clamping the connected output line to a first preset voltage.

2. The pixel array driving method as described in claim 1, characterized in that, At least when the row selection signal is provided to the row selection transistor of the quantization row, a first clamping control signal is provided to each corresponding row selection transistor of a preset clamping row in the pixel array, the preset clamping row and the quantization row being connected to the same output line, the row selection transistor corresponding to the preset clamping row being triggered to conduct when the signal output transistor of the quantization row is in a preset state and clamping the connected output line to a first preset voltage, including: At least when the row selection signal is provided to the row selection transistor of the i-th quantized row, the preset clamping row is at least the (i+n)-th and / or (in)-th row in the pixel array, and a first clamping control signal is provided to each of the corresponding row selection transistors of the preset clamping row. When the signal output transistor of the i-th quantized row is turned off, the row selection transistor corresponding to the preset clamping row is triggered to turn on and clamps the connected output line to a first preset voltage, where n is an integer greater than or equal to 1.

3. The pixel array driving method as described in claim 2, characterized in that, The pixel array further includes multiple clamping circuits, each of which is connected to a corresponding output line. The driving method for the pixel array further includes: When the row selection signal is provided to the row selection transistor of each row, a second clamping control signal is provided to the clamping circuit. The clamping circuit is triggered to conduct when the voltage value on the connected output line reaches a preset threshold and clamps the connected output line to a second preset voltage.

4. The pixel array driving method as described in claim 3, characterized in that, The clamping circuit is triggered to conduct when the voltage value on the connected output line drops to the lower voltage limit and clamps the connected output line to a second preset voltage, wherein the lower voltage limit is greater than zero. And / or, the voltage value of the first preset voltage is less than the voltage value of the second preset voltage.

5. The pixel array driving method as described in claim 2, characterized in that, The provision of a first clamping control signal to each of the corresponding row selection transistors in the (i+n) and / or (in) rows when at least the row selection signal is provided to the row selection transistor in the i-th row includes: While providing the row selection signal to the row selection transistor of the i-th quantized row, the first clamp control signal is also provided to each of the corresponding row selection transistors of the preset clamped row, so as to trigger the output of the first preset voltage based on the voltage value of the output line corresponding to the pixel unit of the i-th quantized row.

6. An image sensor, characterized in that, include: A pixel array includes pixel units arranged in an array, multiple row selection lines, and multiple output lines. Each row of pixel units corresponds to at least one row selection line, and each column of pixel units corresponds to at least one output line. Each pixel unit includes a photosensitive element, a reset transistor, a signal output transistor, and a row selection transistor. The photosensitive element, the reset transistor, and the signal output transistor are coupled to a floating diffusion node. The row selection transistor is connected between the signal output transistor and the corresponding output line, and the row selection transistor is also connected to the corresponding row selection line. The control circuit, connected to each of the row selection lines, is used for: Provide row selection signals to each of the row selection transistors; At least when the row selection signal is provided to the row selection transistor of the quantization row, a first clamping control signal is provided to each of the corresponding row selection transistors of a preset clamping row in the pixel array, the preset clamping row and the quantization row being connected to the same output line, the corresponding row selection transistor of the preset clamping row being triggered to conduct when the signal output transistor of the quantization row is in a preset state and clamping the connected output line to a first preset voltage.

7. The image sensor as described in claim 6, characterized in that, The control circuit is specifically used for: At least when the row selection signal is provided to the row selection transistor of the i-th quantized row, the preset clamping row is at least the (i+n)-th and / or (in)-th row in the pixel array, and a first clamping control signal is provided to each of the corresponding row selection transistors of the preset clamping row. When the signal output transistor of the i-th quantized row is turned off, the row selection transistor corresponding to the preset clamping row is triggered to turn on and clamps the connected output line to a first preset voltage, where n is an integer greater than or equal to 1.

8. The image sensor as claimed in claim 7, characterized in that, The pixel array further includes multiple clamping circuits, each of which is connected to a corresponding output line. The control circuit is also used for: When the row selection signal is provided to the row selection transistor of each row, a second clamping control signal is provided to the clamping circuit. The clamping circuit is triggered to conduct when the voltage value on the connected output line reaches a preset threshold and clamps the connected output line to a second preset voltage.

9. The image sensor as claimed in claim 8, characterized in that, The clamping circuit includes a clamping transistor and a switching transistor connected in series between the positive power supply terminal and the output line. The control terminal of the clamping transistor is used to input the first reference voltage, and the control terminal of the switching transistor is used to input the second clamping control signal.

10. The image sensor as claimed in claim 7, characterized in that, At least two pixel units connected to the same output line constitute a pixel unit group, and a row selection line connected to the pixel units of the pixel unit group constitutes a row selection line group. The control circuit includes: A row selection output circuit, connected to each row selection line, is used to output row selection signals to each row selection transistor. A first voltage output circuit, connected to each of the row selection lines, is used to output a first clamping control signal to another row selection line in the row selection line group when the row selection output circuit outputs a row selection signal to a preset row selection line in the row selection line group.

11. The image sensor as claimed in claim 10, characterized in that, Two adjacent pixel units connected to the same output line constitute a pixel unit group, and two adjacent row selection lines of the pixel unit group constitute a row selection line group; wherein, the control circuit includes: A row selection output circuit, connected to each row selection line, is used to output row selection signals to each row selection transistor; A first voltage output circuit, connected to each of the row selection lines, is used to output a first clamping control signal to the other row selection line in the row selection line group when the row selection output circuit outputs a row selection signal to one of the row selection lines in the row selection line group.

12. The image sensor as claimed in claim 10, characterized in that, The control circuit further includes a second voltage output circuit, which is connected to each clamping circuit and is used to output a second clamping control signal.

13. The image sensor as claimed in claim 11, characterized in that, In the control circuit The first voltage output circuit includes: Multiple first voltage switching circuits are provided, each first voltage switching circuit being connected between the output terminal of a different signal output transistor and the control terminal of a row selection transistor in the pixel unit group. When the signal output transistor of a preset pixel unit in the pixel unit group is turned off, the first voltage switching circuit switches and outputs the first clamping control signal to the control terminal of the row selection transistor of another pixel unit in the pixel unit group. Alternatively, the first voltage output circuit includes: Multiple second voltage switching circuits are provided, with the control terminal and output terminal of each second voltage switching circuit respectively connected to a group of the row selection lines. The second voltage switching circuit is used to trigger the output of the first clamping control signal to another row selection line of the row selection line group when it detects that a preset row selection line of the row selection line group is the row selection signal.

14. The image sensor as claimed in claim 13, characterized in that, The first voltage switching circuit includes: A first switch, the first end of the first switch is used to input the first clamping control signal, the control end of the first switch is connected to the output end of the signal output transistor of the first pixel unit in the pixel unit group, the second end of the first switch is connected to the control end of the row selection transistor of the second pixel unit in the pixel unit group, the first switch is turned on by a low level and turned off by a high level. The second switch has a first terminal for inputting the first clamping control signal, a control terminal for being connected to the output terminal of the signal output transistor of the second pixel unit in the pixel unit group, and a second terminal for being connected to the control terminal of the row selection transistor of the first pixel unit in the pixel unit group. The second switch is turned on by a low level and turned off by a high level. Alternatively, the second voltage switching circuit includes a first comparator, a second comparator, a third switch, and a fourth switch: The non-inverting input of the first comparator is connected to the first row selection line of the row selection line group, and the non-inverting input of the second comparator is connected to the second row selection line of the row selection line group. The inverting inputs of the first and second comparators are used to input a second reference voltage. The output of the first comparator is connected to the control terminal of the third switch, and the output of the second comparator is connected to the control terminal of the fourth switch. The first terminals of the third and fourth switches are used to input the first clamping control signal. The second terminal of the third switch is connected to the second row selection line of the row selection line group, and the second terminal of the fourth switch is connected to the first row selection line of the row selection line group.

15. The image sensor as claimed in claim 7, characterized in that, The control circuit includes: Multiple signal generation circuits are provided, each signal generation circuit being connected to a corresponding row selection line, and the multiple signal generation circuits are used to output row selection signals to each row of the row selection line in turn. The (i+n)th and / or (in)th signal generation circuit is further configured to output the first clamping control signal to each corresponding row selection transistor of the preset clamping row when the i-th signal generation circuit outputs the row selection signal to the row selection transistor of the i-th quantized row.

16. The image sensor as claimed in claim 15, characterized in that, The signal generation circuit includes: A first signal generating circuit is connected to a corresponding row selection line and is used to output the row selection signal to the corresponding row selection line. The second signal generating circuit is connected to the output terminal of the first signal generating circuit; The second signal generation circuit of the (i+n)th and / or (in)th signal generation circuit is used to output the first clamping control signal to each corresponding row selection transistor of the preset clamping row when the first signal generation circuit of the ith signal generation circuit outputs the row selection signal to the row selection transistor of the ith quantized row.

17. An electronic device, characterized in that, Including the image sensor as described in any one of claims 6 to 16.

Images