Memory device

Abstract

A memory device according to an embodiment of the disclosure can include: word lines buried in a substrate and extending in a first direction; bit line contacts disposed between the word lines, in contact with an active region of the substrate, and having at least a portion of a side surface recessed toward a center in a second direction perpendicular to the first direction; a gate cover layer including a first cover portion in contact with an upper surface of the word lines and a second cover portion on the first cover portion, the second cover portion overlapping at least a portion of the side surface of the bit line contact in the second direction and having a width different from a width of the first cover portion.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0177281, filed on December 3, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments of this disclosure generally relate to a storage device. Background Technology

[0004] Memory devices, with their miniaturization, multifunctionality, and / or low manufacturing cost, are becoming increasingly important components in the electronics industry. As the electronics industry develops, the integration level of memory devices is also increasing. For highly integrated memory devices, the width of the lines included in the memory device is gradually decreasing, and the size of the memory cell is also decreasing accordingly. This increases the difficulty of the manufacturing process for forming the memory cell. Summary of the Invention

[0005] Embodiments of this disclosure provide a storage device that can prevent process defects during the manufacturing process of the storage device.

[0006] The purposes of the embodiments disclosed herein are not limited to those set forth herein, and other purposes not mentioned herein will become apparent to those skilled in the art from the following description.

[0007] Embodiments of this disclosure may provide a memory device comprising: word lines embedded in a substrate and extending along a first direction; bit line contacts disposed between the word lines, contacting an active region of the substrate, and having at least a portion of a side surface recessed toward a center in a second direction perpendicular to the first direction; and a gate capping layer comprising a first capping portion contacting an upper surface of the word lines and a second capping portion located on the first capping portion, the second capping portion overlapping at least a portion of the side surface of the bit line contacts in the second direction, and having a width different from the width of the first capping portion.

[0008] Embodiments of this disclosure may provide a memory device comprising: word lines embedded in a substrate and extending along a first direction; bit line contacts disposed between the word lines, contacting an active region of the substrate, and having at least a portion of their side surfaces recessed toward a center in a second direction perpendicular to the first direction; a gate capping layer overlapping the word lines, and having at least a portion thereof overlapping at least a portion of the side surfaces of the bit line contacts in the second direction; and a buffer layer disposed on the gate capping layer and surrounding the bit line contacts.

[0009] Embodiments of this disclosure may provide a memory device, including: word lines embedded in a substrate and extending along a first direction; bit line contacts disposed between word lines and in contact with an active region of the substrate; a gate capping layer including a first capping portion in contact with an upper surface of the word lines and a second capping portion located on the first capping portion, the lower surface of the second capping portion being located above the upper surface of the substrate; and a buffer layer covering the second capping portion of the gate capping layer and surrounding the bit line contacts.

[0010] According to embodiments of this disclosure, process defects can be prevented during the manufacturing process of storage devices.

[0011] The effects of the embodiments disclosed herein are not limited to the foregoing objectives, and other effects will be apparent to those skilled in the art from the following detailed description. Attached Figure Description

[0012] The embodiments of this disclosure can be more fully understood through the following detailed description and accompanying drawings. These detailed descriptions and drawings are provided for illustrative purposes only and are not intended to limit the embodiments.

[0013] Figure 1 This is a diagram illustrating the planar structure of a storage device according to an embodiment of the present disclosure;

[0014] Figure 2 It is shown Figure 1 A diagram of the cross-sectional structure of section I-I';

[0015] Figure 3 It is shown Figure 1 A diagram of the cross-sectional structure of section II-II';

[0016] Figure 4 It is shown Figure 1 A diagram of the cross-sectional structure of section III-III';

[0017] Figures 5 to 7 yes Figure 2 Middle part 10 and Figure 3 Enlarged view of section 20 in the middle;

[0018] Figure 8 It is shown Figure 1 A diagram of another cross-sectional structure of the I-I' section;

[0019] Figure 9 It is shown Figure 1 A diagram of another cross-sectional structure of section II-II';

[0020] Figure 10 and Figure 11 yes Figure 8 Part 30 and Figure 9Enlarged view of part 40;

[0021] Figures 12 to 21 A diagram illustrating a method of manufacturing a storage device according to an embodiment of the present disclosure;

[0022] Figure 22 A diagram illustrating another method of manufacturing a storage device according to an embodiment of the present disclosure. Detailed Implementation

[0023] Embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. Throughout the specification and drawings, the same or substantially the same reference numerals are used to refer to the same or substantially the same elements. Details of prior art or functionality may be omitted where the subject matter of this disclosure may be unclear. As used herein, when a component “comprises,” “has,” or “is composed of” another component, the component may include additional components unless the component “only” includes, has, or is composed of another component. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are also intended to include the plural forms.

[0024] Labels such as “first,” “second,” “A,” “B,” “(a),” and “(b)” can be used to describe components of embodiments of this disclosure. These labels are used only to distinguish the components from other components, and the nature, order, or number of the components is not limited by the order or sequence of the labels.

[0025] When describing the positional relationship between components, if two or more components are described as “connected,” “coupled,” or “linked,” these two or more components may be directly “connected,” “coupled,” or “linked,” or another component may be involved. Here, the other component may be included in one or more of the two or more components that are “connected,” “coupled,” or “linked” to each other.

[0026] When using terms such as “after,” “immediately following,” and “before” to describe time-flow relationships related to components, operating methods, and manufacturing methods, it can include discontinuous relationships unless the terms “immediately following” or “directly” are used.

[0027] When a value or its corresponding information (e.g., grade) of a component is mentioned, it can be interpreted, even if not explicitly stated, as including an error margin that can be caused by various factors (e.g., process factors, internal or external shocks, noise, etc.).

[0028] Various embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0029] In the accompanying drawings, the three directions parallel to the upper surface of the substrate are defined as the first direction FD, the second direction SD, and the third direction TD, respectively, while the direction protruding perpendicular to the upper surface of the substrate is defined as the fourth direction VD. The first direction FD and the second direction SD can be substantially perpendicular to each other. The fourth direction VD is perpendicular to the first direction FD, the second direction SD, and the third direction TD. In the following description, "perpendicular" or "perpendicular direction" will be used to have substantially the same meaning as the fourth direction VD. The directions indicated by the arrows in the figures and their opposite directions represent the same direction.

[0030] Figure 1 This is a diagram illustrating the planar structure of a storage device according to an embodiment of the present disclosure.

[0031] refer to Figure 1 The memory device according to embodiments of the present disclosure includes an active region 110, word lines 120, and bit line structures 130. Word lines 120 extend along a first direction FD and intersect the active region 110. Multiple word lines 120 may be arranged parallel to each other in a second direction SD. In one embodiment, two corresponding word lines 120 may intersect one active region 110.

[0032] Bit line structure 130 extends along the second direction SD and intersects with active region 110. Multiple bit line structures 130 may be arranged parallel to each other in the first direction FD. Bit line structure 130 intersects word line 120. Bit line structure 130 may be orthogonal to word line 120. In one embodiment, a corresponding bit line structure 130 may intersect with an active region 110.

[0033] Bit line contact holes (CNTs) can be configured to overlap with each active region 110. Each bit line contact hole (CNT) can correspond to one active region 110. The bit line contact hole (CNT) can be located near the center of the active region 110. The bit line contact hole (CNT) is located between word lines 120. In one embodiment, at least a portion of the bit line contact hole (CNT) can overlap with a word line 120 in the second direction SD. The bit line contact hole (CNT) overlaps with each bit line structure 130. Figure 1 In the plan view, the bit line contact hole (CNT) is shown as an ellipse, but the shape of the bit line contact hole (CNT) is not limited to this.

[0034] Figure 2 To show Figure 1 A diagram of the cross-sectional structure of the I-I' section. Figure 3 To show Figure 1 A diagram of the cross-sectional structure of section II-II'. Figure 4 To show Figure 1 A diagram of the cross-sectional structure of section III-III'. Figures 5 to 7 for Figure 2 Middle part 10 and Figure 3 Enlarged view of section 20 in the middle.

[0035] refer to Figure 2 and Figure 5 The memory device according to an embodiment of the present disclosure includes a substrate 200, an element isolation layer 203, a gate structure 210, a first insulating layer 202, a gate cover layer 221, a buffer layer 222, a first spacer 231, a bit line contact 230, a bit line structure 130, and a bit line spacer 251.

[0036] Substrate 200 may include a semiconductor substrate, such as a silicon wafer or a silicon-on-insulator (SOI) wafer. Substrate 200 may include a III-V group semiconductor substrate, such as a compound semiconductor substrate such as gallium arsenide (GaAs). Substrate 200 may include monocrystalline silicon, polycrystalline silicon, amorphous silicon, monocrystalline silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, or combinations thereof.

[0037] A device isolation layer 203 restricting the active region 110 may be disposed in the substrate 200. The active region 110 may be spaced apart from each other in a first direction FD, a second direction SD, and a third direction TD by the device isolation layer 203. The active region 110 and the device isolation layer 203 may be formed using trench device isolation technology (such as shallow trench isolation (STI)). In one embodiment, the active region 110 may comprise single-crystal silicon having a P-type impurity. The P-type impurity may include boron (B), boron trifluoride (BF3), boron difluoride (BF2), or combinations thereof. The device isolation layer 203 may be a single layer or multiple layers. The device isolation layer 203 may contain at least two elements selected from the group consisting of silicon (Si), oxygen (O), nitrogen (N), carbon (C), and hydrogen (H). The device isolation layer 203 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric, or combinations thereof.

[0038] Gate structure 210 is buried in substrate 200. Gate structure 210 may include gate insulating layer 211 and word line 120. Gate insulating layer 211 may surround the side surface and bottom surface of word line 120. The upper surface of gate insulating layer 211 may be located at a position higher than the upper surface of word line 120. However, embodiments are not limited to this; the upper surface of gate insulating layer 211 may be located at the same height as the upper surface of word line 120, or at a height lower than the upper surface of word line 120. Word line 120 may include upper word line 213 and lower word line 212. Word line 120 may be located in the vertical direction at a position lower than the upper surface of active region 110.

[0039] The gate insulating layer 211 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric, or a combination thereof. The word line 120 may include a conductive material, such as a metal, metal oxide, metal nitride, metal silicide, polysilicon, conductive carbon, or a combination thereof. The upper word line 213 may include a material different from the material forming the lower word line 212. In one embodiment, the upper word line 213 may include a low work function material, while the lower word line 212 may include a high work function material. For example, the upper word line 213 may include doped polysilicon, while the lower word line 212 may include titanium nitride.

[0040] The first insulating layer 202 may be disposed on the active region 110. In one embodiment, the first insulating layer 202 may comprise a material such as ultra-low temperature oxide (ULTO).

[0041] A gate cover layer 221 may be disposed on a word line 120. The gate cover layer 221 may overlap with the word line 120. In one embodiment, each gate cover layer 221 may correspond to one word line 120. The gate cover layer 221 may include a first cover portion 221a and a second cover portion 221b.

[0042] The first covering portion 221a contacts the upper surface of the word line 213. In one embodiment, the first covering portion 221a may fill the space between the inner surfaces of the gate insulating layer 211.

[0043] In another embodiment, the first covering portion 221a may be disposed on the gate insulating layer 211. For example, when the upper surface of the gate insulating layer 211 and the upper surface of the upper word line 213 are at the same height, the first covering portion 221a may be disposed on the gate insulating layer 211 and the upper word line 213. In this case, the first covering portion 221a may fill the space between the active regions 110 and the space between the inner surfaces of the first insulating layer 202.

[0044] In one embodiment, the lower surface of the first covering portion 221a may be located at a position higher than the upper surface of the substrate 200.

[0045] The second covering portion 221b may be disposed on the first covering portion 221a. The second covering portion 221b is continuous with the first covering portion 221a. The width of the second covering portion 221b may be different from the width of the first covering portion 221a. (Refer to the following text.) Figure 3 The width of the second cover portion 221b is described. In one embodiment, the lower surface of the second cover portion 221b may contact the upper surface of the gate insulating layer 211. In one embodiment, the lower surface of the second cover portion 221b may contact the upper surface of the first insulating layer 202.

[0046] The gate capping layer 221 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or a combination thereof. In one embodiment, the gate capping layer 221 may include, for example, silicon nitride.

[0047] A buffer layer 222 may be disposed on the first insulating layer 202, the element isolation layer 203, the gate insulating layer 211, and the gate cover layer 221. The buffer layer 222 fills the space between the gate cover layers 221 corresponding to different word lines 120. The buffer layer 222 may contact the upper surface of the first insulating layer 202. The buffer layer 222 covers the second cover portion 221b of the gate cover layer 221. The buffer layer 222 contacts the upper surface and side surface of the second cover portion 221b of the gate cover layer 221.

[0048] Buffer layer 222 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or combinations thereof. For example, buffer layer 222 may include SiCOH, SiCO, SiO2, SiCN, or combinations thereof. Alternatively, buffer layer 222 may include materials such as ultra-low temperature oxide (ULTO) or spin-on dielectric (SOD), depending on how they are deposited. In one embodiment, buffer layer 222 may include a material with etch selectivity relative to gate cap layer 221 and first bit line 241.

[0049] refer to Figure 1 , Figure 2 and Figure 5 Bit line contact holes (CNTs) can be provided between word lines 120. The bit line contact holes (CNTs) can be spaces formed by etching a buffer layer 222, a first insulating layer 202, and a gate insulating layer 211. In one embodiment, the bit line contact holes (CNTs) can overlap with the gate capping layer 221 and the word lines 120. The bit line contact holes (CNTs) expose the active region 110 of the substrate 200 between the word lines 120.

[0050] The first spacer 231 may be disposed along the side surface of the bit line contact hole CNT. In one embodiment, the first spacer 231 may conformally cover the side surface of the bit line contact hole CNT. The first spacer 231 surrounds the side surface of the bit line contact 230. The first spacer 231 may include, for example, silicon nitride.

[0051] Bit line contact 230 penetrates buffer layer 222 and first insulating layer 202 to contact active region 110 of substrate 200. In one embodiment, the side surface of bit line contact 230 facing word line 120 may have a concave shape toward the center of bit line contact 230. The side surface of bit line contact 230 may be recessed in a direction facing the second cover portion 221b of gate cover layer 221. In one embodiment, the width of bit line contact 230 may be minimized in a region adjacent to the lower surface of the second cover portion 221b. Bit line contact 230 may comprise a conductive material such as metal, metal oxide, metal nitride, metal silicide, polysilicon, conductive carbon, or combinations thereof. Reference will be made below. Figure 3 Describe the detailed structure of the bit line contact 230.

[0052] Bit line structure 130 may be disposed on bit line contact 230. Bit line structure 130 may include a first bit line 241, a second bit line 242, a third bit line 243, and a bit line capping layer 244. The first bit line 241, the second bit line 242, the third bit line 243, and the bit line capping layer 244 are stacked sequentially in a vertical direction. The first bit line 241, the second bit line 242, and the third bit line 243 may constitute a single bit line. The first bit line 241, the second bit line 242, and the third bit line 243 may include conductive materials such as metals, metal oxides, metal nitrides, metal silicides, polysilicon, conductive carbon, or combinations thereof. The bit line capping layer 244 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, high-k dielectrics, or combinations thereof. In one embodiment, the first bit line 241 may be polysilicon, the second bit line 242 may be a metal silicide, and the third bit line 243 may be a metal. In one embodiment, the bit line capping layer 244 may be silicon nitride.

[0053] Bit line spacer 251 may be disposed on the side surface of bit line contact 230 and the side surface of bit line structure 130. Bit line spacer 251 may include, for example, silicon nitride. Insulating material may fill the space BSA1 between bit line spacer 251 and first spacer 231.

[0054] refer to Figure 1 , Figure 3 and Figure 5 The gate capping layer 221 may extend along the first direction FD. The gate capping layers 221 may be disposed spaced apart from each other on the second direction SD.

[0055] In one embodiment, the width W2 of the second cover portion 221b of the gate cover layer 221 in the second direction SD can decrease in the vertical direction as it moves away from the upper surface of the substrate 200. For example, the cross-section of the second cover portion 221b can be trapezoidal, wherein the width of the lower surface is greater than the width of the upper surface. However, the cross-section of the second cover portion 221b is not limited to this, and the cross-section of the second cover portion 221b can have various shapes, such as rectangular and semi-circular.

[0056] In one embodiment, the second covering portion 221b may have a maximum width W2 on its lower surface. max In one embodiment, the maximum width W2 of the second covering portion 221b max The width W1 of the first covering portion 221a in the second direction SD may be greater than that of the first covering portion 221a in the second direction SD. The second covering portion 221b may protrude further than the first covering portion 221a in the second direction SD. The second covering portion 221b may extend in the second direction SD toward the recessed side surface of the bit line contact 230.

[0057] refer to Figure 3 and Figure 5 The bit line contact 230 may include a first contact portion 230a, a second contact portion 230b and a third contact portion 230c.

[0058] The first contact portion 230a contacts the active region of the substrate 200. The first contact portion 230a may overlap with the first cover portion 221a of the gate cover layer 221 in the second direction SD. The width W3 of the first contact portion 230a in the second direction SD may be constant. For example, the width of the lower surface of the first contact portion 230a may be the same as the width of the upper surface.

[0059] The second contact portion 230b may be disposed on the first contact portion 230a. The second contact portion 230b is continuous with the first contact portion 230a. The second contact portion 230b may overlap with the second cover portion 221b of the gate cover layer 221 in the second direction SD. In one embodiment, the width W4 of the lower surface of the second contact portion 230b may be smaller than the width W3 of the upper surface of the first contact portion 230a. In one embodiment, the width of the second contact portion 230b may be thinnest on the lower surface. In one embodiment, the shape of the second contact portion 230b may vary according to the shape of the second cover portion 221b of the gate cover layer 221.

[0060] The third contact portion 230c may be disposed on the second contact portion 230b. The third contact portion 230c is continuous with the second contact portion 230b. The third contact portion 230c may be located at a position higher than the second cover portion 221b of the gate cover layer 221. In one embodiment, the lower surface of the third contact portion 230c may be located at a position higher than the upper surface of the second cover portion 221b. In one embodiment, the width W6 of the lower surface of the third contact portion 230c in the second direction SD may be greater than the width W5 of the upper surface of the second contact portion 230b in the second direction SD.

[0061] In one embodiment, the second cover portion 221b of the gate cover layer 221 may overlap with the first contact portion 230a and the third contact portion 230c of the bit line contact 230 in the vertical direction.

[0062] refer to Figure 4 The storage device according to embodiments of the present disclosure further includes a second spacer 532, a third spacer 533, and a contact plug 540. The contact plug 540 includes a lower contact plug 541 and an upper contact plug 542 disposed on the lower contact plug. The lower contact plug 541 and the upper contact plug 542 may include conductive materials, such as metals, metal oxides, metal nitrides, metal silicides, polycrystalline silicon, conductive carbon, or combinations thereof.

[0063] Contact plugs 540 contact the active region 110. In one embodiment, two contact plugs 540 may be located between bit line contacts 230 along a first direction FD. Between the contact plugs 540, a first insulating layer 202 and a buffer layer 222 are disposed below the bit line structure 130. In one embodiment, the buffer layer 222 may be located between the bit line contacts 230 in the first direction FD. The second insulating layer 202 and the buffer layer 222 may overlap with a component isolation layer 203 in the vertical direction. The lower surface of the first bit line 241 may contact the upper surface of the buffer layer 222. The bit line structure 130 and the contact plugs 540 may be alternately arranged in the first direction FD. A bit line spacer 251 may be disposed between the bit line structure 130 and the contact plugs 540.

[0064] The second spacer 532 may be disposed on the side surface of the lower contact plug 541. The third spacer 533 may be disposed in the space surrounded by the first spacer 231, the second spacer 532, and the bit line spacer 251. The first spacer 231 may extend between the element isolation layer 203 and the third spacer 533. The bit line spacer 251 may extend between the buffer layer 222 and the third spacer 533.

[0065] The second spacer 532 and the third spacer 533 may include dielectrics, such as silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, high-k dielectrics, or combinations thereof.

[0066] according to Figure 2 and Figure 6 In the embodiment shown, at least a portion of the side surface of the second contact portion 230b of the bit line contact 230 may be spaced apart from the inner surface of the first spacer 231. The bit line spacer 251 may be disposed on the side surfaces of the second contact portion 230b and the third contact portion 230c.

[0067] In a direction other than the second direction SD (e.g., the third direction TD, or a direction extending parallel to the upper surface of the substrate 200 between the first direction FD and the third direction TD), the width of the third contact portion 230c of the bit line contact 230 can be less than [the width of the third contact portion 230c]. Figure 5 The width of the third contact portion 230c of the bit line contact 230. In a direction other than the second direction SD (e.g., the third direction TD, or a direction extending parallel to the upper surface of the substrate 200 between the first direction FD and the third direction TD), the width of the upper surface of the second contact portion 230b of the bit line contact 230 can be substantially the same as the width of the lower surface of the third contact portion 230c. Insulating material can fill the gap BSA2 between the bit line spacer 251 and the first spacer 231.

[0068] refer to Figure 3 and Figure 6 The width of the third contact portion 230c of the bit line contact 230 in the second direction SD can be the same as that of the bit line contact 230. Figure 5 The widths of the third contact portions 230c of the bit line contact 230 shown are substantially the same. In the second direction SD, the width of the upper surface of the second contact portion 230b of the bit line contact 230 may be smaller than the width of the lower surface of the third contact portion 230c.

[0069] refer to Figure 2 and Figure 7 In one embodiment, the side surfaces of the second contact portion 230b and the first contact portion 230a of the bit line contact 230 may be spaced apart from the inner surface of the first spacer 231. In one embodiment, the bit line spacer 251 may be disposed on the side surfaces of the first contact portion 230a, the second contact portion 230b, and the third contact portion 230c.

[0070] In a direction other than the second direction SD (e.g., the third direction TD, or a direction extending parallel to the upper surface of the substrate 200 between the first direction FD and the third direction TD), the widths of the first contact portion 230a, the second contact portion 230b, and the third contact portion 230c of the bit line contact 230 can be substantially the same. An insulating material can fill the space BSA3 between the bit line spacer 251 and the first spacer 231.

[0071] refer to Figure 3 and Figure 7 The widths of the first contact portion 230a, the second contact portion 230b, and the third contact portion 230c of the bit line contact 230 in the second direction SD can be respectively compared with the reference. Figure 5 The widths of the first contact portion 230a, the second contact portion 230b, and the third contact portion 230c are substantially the same.

[0072] Figure 8 To show Figure 1 A diagram of another cross-sectional structure of the I-I' section. Figure 9 To show Figure 1 A diagram of another cross-sectional structure of section II-II'. Figure 10 and Figure 11 for Figure 8 Middle part 30 and Figure 9 Enlarged view of section 40 in the middle.

[0073] refer to Figure 8 and Figure 10 The memory device according to an embodiment of the present disclosure includes a substrate 200, an element isolation layer 203, a gate structure 210, a first insulating layer 202, a gate cover layer 221, a buffer layer 222, a first spacer 231, a bit line contact 230, a bit line structure 130, and a bit line spacer 251.

[0074] A gate cover layer 221 may be disposed on a word line 120. The gate cover layer 221 may overlap with the word line 120. In one embodiment, each gate cover layer 221 may correspond to one word line 120. The gate cover layer 221 may include a first cover portion 221a and a second cover portion 221b.

[0075] The first covering portion 221a can be compared with the reference. Figure 2 The first coverage portion 221a described is substantially the same and can be set on word line 120.

[0076] The second covering portion 221b may be disposed on the first covering portion 221a. The second covering portion 221b is continuous with the first covering portion 221a. The width of the second covering portion 221b may be different from the width of the first covering portion 221a. The width of the second covering portion 221b may decrease in the direction away from the first covering portion. (Refer to the following text.) Figure 9 The width of the second cover portion 221b is described. In one embodiment, the lower surface of the second cover portion 221b may be at the same level as the upper surface of the gate insulating layer 211. In one embodiment, the lower surface of the second cover portion 221b may contact the upper surface of the gate insulating layer 211. In one embodiment, the lower surface of the second cover portion 221b may be at the same level as the upper surface of the first insulating layer 202. (Reference) Figure 1 , Figure 8 and Figure 10 Bit line contact holes (CNTs) can be disposed between word lines 120. In one embodiment, the bit line contact holes (CNTs) can overlap with the gate cap 221 and the word lines 120. The bit line contact holes (CNTs) expose the active regions 110 of the substrate 200 between the word lines 120.

[0077] The first spacer 231 may be disposed along the side surface of the bit line contact hole CNT. In one embodiment, the first spacer 231 may conformally cover the side surface of the bit line contact hole CNT. The first spacer 231 surrounds the side surface of the bit line contact 230. The first spacer 231 may include, for example, silicon nitride.

[0078] Bit line contact 230 penetrates buffer layer 222 and first insulating layer 202 to contact active region 110 of substrate 200. In one embodiment, the side surface of bit line contact 230 facing word line 120 may have a concave shape toward the center of bit line contact 230. The side surface of bit line contact 230 may be recessed in the direction facing the second cover portion 221b of gate cover layer 221. In one embodiment, the width of bit line contact 230 may be thinnest on the lower surface of bit line contact 230.

[0079] refer to Figure 1 , Figure 9 and Figure 10 The gate capping layer 221 may extend along the first direction FD. The gate capping layers 221 may be disposed spaced apart from each other on the second direction SD.

[0080] In one embodiment, the width W3 of the second cover portion 221b of the gate cover layer 221 in the second direction SD can decrease in the vertical direction as it moves away from the upper surface of the substrate 200. For example, the cross-section of the second cover portion 221b can have a shape in which the width of the lower surface is greater than the width of the upper surface. However, the cross-sectional shape of the second cover portion 221b is not limited to this.

[0081] In one embodiment, the second covering portion 221b may have a maximum width W3 along the second direction SD on its lower surface. max In one embodiment, the second covering portion 221b has a maximum width W3 in the second direction SD. max The width W1 of the first cover portion 221a in the second direction SD may be substantially the same. The second cover portion 221b may not protrude further than the first cover portion 221a in the second direction SD. The second cover portion 221b may extend along the second direction SD toward the recessed side surface of the bit line contact 230. Insulating material may fill the space BSA4 between the bit line spacer 251 and the first spacer 231.

[0082] refer to Figure 8 and Figure 11 In one embodiment, the side surface of the bit line contact 230 may be spaced apart from the inner surface of the first spacer 231. In one embodiment, the bit line spacer 251 may be disposed on the entire side surface of the bit line contact 230.

[0083] In a direction other than the second direction SD (e.g., the third direction TD, or a direction extending parallel to the upper surface of the substrate 200 between the first direction FD and the third direction TD), the width of the bit line contact 230 may be less than [the width of the bit line contact 230]. Figure 10 The width of the bit line contact 230 is shown. The width of the bit line contact 230 can be constant in a direction other than the second direction SD (e.g., the third direction TD, or a direction extending parallel to the upper surface of the substrate 200 between the first direction FD and the third direction TD). For example, the widths of the upper and lower surfaces of the bit line contact 230 can be substantially the same. An insulating material can fill the space BSA5 between the bit line spacer 251 and the first spacer 231.

[0084] refer to Figure 9 and Figure 11 The width of the bit line contact 230 in the second direction SD can be the same as Figure 10 The bit line contacts 230 shown have substantially the same width. For example, the width of the upper surface of the bit line contact 230 in the second direction SD can be greater than the width of the lower surface.

[0085] Figures 12 to 21A diagram illustrating a method of manufacturing a storage device according to an embodiment of the present disclosure.

[0086] refer to Figure 12 A substrate 200 is provided, the substrate 200 having an element isolation layer 203 that confines an active region 110 of the substrate 200, a gate structure 210 buried in the substrate 200, and a first insulating layer 202.

[0087] The first insulating layer 202 may be formed before the gate structure 210. For example, when the first insulating layer 202 can be formed on the substrate 200, the upper portion of the first insulating layer 202 and the upper portion of the substrate 200 may be removed to form a trench on which the gate structure 210 may be disposed. In one embodiment, the thickness of the first insulating layer 202 may be more than 100 angstroms and less than 300 angstroms.

[0088] Subsequently, gate structures 210 can be formed on the side and bottom surfaces of the trench. Gate structures 210 can be formed in the device isolation layer 203 or in the active region 110 of the substrate 200. Figure 12 In this embodiment, the gate insulating layer 211 is shown to be formed on the side surface of the first insulating layer 202 and the side surface of the element isolation layer 203, but this embodiment is not necessarily limited to this. For example, the upper surface of the gate insulating layer 211 may be formed below the upper surface of the upper word line 213.

[0089] refer to Figure 13 A first gate cover material 1300 can be formed on the word line 120. The first gate cover material 1300 can be formed to correspond to each word line 120. The process of forming the first gate cover material 1300 may include an etch-back process. Figure 13 In the illustrated embodiment, the upper surface of the first gate cover material 1300 may be located lower than the upper surface of the first insulating layer 202. Furthermore, the upper surface of the first gate cover material 1300 may be located higher than the upper surface of the substrate 200. The first gate cover material 1300 may include, for example, silicon nitride.

[0090] refer to Figure 14 A portion of the first insulating layer 202, a portion of the element isolation layer 203, and a portion of the gate insulating layer 211 can be removed to expose the upper part of the side surface of the first gate cover material 1300. The process of removing a portion of the first insulating layer 202, a portion of the element isolation layer 203, and a portion of the gate insulating layer 211 may include an etching process.

[0091] In one embodiment, the thickness of the etched first insulating layer 202 can be 50 angstroms or more and 100 angstroms or less. The upper surface of the first insulating layer 202 can be located at a position lower than the upper surface of the first gate cover material 1300.

[0092] refer to Figure 15 The second gate cover material 1500 can be formed on the first insulating layer 202 and the first gate cover material 1300. The second gate cover material 1500 can be formed along a step of the lower layer. For example, the position of the upper surface of the second gate cover material 1500 in the region where the first gate cover material 1300 is disposed can be higher than the position of the upper surface of the second gate cover material 1500 in the region where the first gate cover material 1300 is not disposed.

[0093] refer to Figure 16 At least a portion of the first gate cover material 1300 and the second gate cover material 1500 is removed to form a gate cover layer 221. The process of forming the gate cover layer 221 may include an etching process. At least a portion of the first gate cover material 1300 and the second gate cover material 1500 may be removed to expose the upper surface of the first insulating layer 202.

[0094] In one embodiment, the maximum width of the second cover portion 221b of the gate cover layer 221 may be greater than the width of the first cover portion 221a. The side surface of the second cover portion 221b may be tapered, wherein the width of the second cover portion 221b is greater at the interface with the first cover portion 221a.

[0095] refer to Figure 17 A buffer layer 222 can be formed on the gate capping layer 221. The buffer layer 222 can contact the upper surface of the first insulating layer 202. The buffer layer 222 can contact the upper surface and side surface of the second covering portion 221b of the gate capping layer 221.

[0096] refer to Figure 18 The buffer layer 222, the first insulating layer 202, and the upper portion of the substrate 200 in the region between the gate capping layer 221 are removed to form bit line contact vias (CNTs). Each bit line contact via (CNT) exposes the active region 110 of the substrate 200. The process of forming the bit line contact via (CNT) includes an etching process. In one embodiment of this disclosure, the process of forming the bit line contact via (CNT) may include a self-aligned contact etching process that utilizes etching selectivity between the buffer layer 222 and the gate capping layer 221.

[0097] The gas used in the etching process may contain materials capable of improving the etching selectivity between the gate capping layer 221 and the buffer layer 222. In one embodiment, the gas used in the etching process may contain a CxFy-based material, where x and y are natural numbers. Here, the value obtained by dividing y by x may be greater than or equal to 1.5. In one embodiment, the gas used in the dry etching process may be C4F6 (hexafluorobutadiene).

[0098] In the process of forming the bit line contact hole (CNT), the gate capping layer 221 can remain in an unetched state. For example, after forming the bit line contact hole (CNT), the second cover portion 221b of the gate capping layer 221 can protrude further outward than the buffer layer 222. The width of the upper surface of the second cover portion 221b of the gate capping layer 221 can be substantially the same as the width of the upper surface of the second cover portion 221b before forming the bit line contact hole (CNT).

[0099] refer to Figure 19 A first spacer 231 can be formed on the side and bottom surfaces of the bit line contact hole CNT. In one embodiment, the first spacer 231 can be conformally formed on the side and bottom surfaces of the bit line contact hole CNT. Subsequently, the first spacer 231 located on the bottom surface of the bit line contact hole CNT can be removed to expose the active region 110 of the substrate 200.

[0100] refer to Figure 20 Bit line contacts 230 can be formed in the bit line contact holes (CNTs). The process for forming bit line contacts 230 may include a process of depositing conductive material and a process of etching back. The upper surface of the bit line contact 230 may be formed into a plane substantially the same as the upper surface of the buffer layer 222. The lower surface of the bit line contact 230 may contact the active region 110 of the substrate 200.

[0101] refer to Figure 21 A first bit line 241, a second bit line 242, a third bit line 243, and a bit line cover layer 244 can be sequentially formed on the bit line contact 230 and the buffer layer 222. The process for forming the first bit line 241, the second bit line 242, the third bit line 243, and the bit line cover layer 244 may include an etching process. In one embodiment, at least a portion of the bit line contact 230 may be etched together using an etching process. (Return to Reference) Figure 5 In one embodiment, at least a portion of the side surface of the third contact portion 230c of the bit line contact 230 may be spaced apart from the first spacer 231.

[0102] Bit line spacers 251 may be formed on the side surfaces of the first bit line 241, the second bit line 242, the third bit line 243, and the bit line cover layer 244. In one embodiment, bit line spacers 251 may extend below the upper surface of the buffer layer 222.

[0103] Figure 22 A diagram illustrating another method of manufacturing a storage device according to an embodiment of the present disclosure.

[0104] Figure 22The storage device shown can be used with reference Figures 12 to 15 The method described for manufacturing storage devices is the same as the method used to form them.

[0105] refer to Figure 15 and Figure 22 At least a portion of the first gate cover material 1300 and the second gate cover material 1500 is removed to form a gate cover layer 221. The process of forming the gate cover layer 221 may include an etching process. At least a portion of the first gate cover material 1300 and the second gate cover material 1500 may be removed to expose the upper surface of the first insulating layer 202.

[0106] exist Figure 22 In the embodiment shown, the maximum width of the second covering portion 221b of the gate cover layer 221 can be the same as the width of the first covering portion 221a.

[0107] Return to reference Figure 8 A buffer layer 222, a first spacer 231, a bit line contact 230, a bit line structure 130, and a bit line spacer 251 can be formed on the gate capping layer 221. The process and reference for forming the buffer layer 222, the first spacer 231, the bit line contact 230, the bit line structure 130, and the bit line spacer 251 are provided. Figures 17 to 21 The processes for forming the buffer layer 222, the first spacer 231, the bit line contact 230, the bit line structure 130, and the bit line spacer 251 are basically the same.

[0108] Refer again Figure 2 , Figure 3 and Figure 5 The gate capping layer 221 may include a first capping portion 221a disposed on the word line 120 and a second capping portion 221b disposed on the first capping portion 221a, the second capping portion 221b extending toward the concave side of the bit line contact 230 and having a width different from that of the first capping portion 221a. The side surface of the bit line contact 230 facing the word line 120 may be recessed toward the center of the bit line contact 230. In one embodiment, the process of forming the bit line contact hole CNT may include a self-aligned contact etching process utilizing the etching selectivity between the buffer layer 222 and the gate capping layer 221. In one embodiment, the gate capping layer 221 may include a nitride, while the buffer layer 222 may include an oxide.

[0109] According to embodiments of this disclosure, during the formation of the bit line contact hole CNT, since an etching process is used to improve the etching selectivity between the gate capping layer 221 and the buffer layer 222, the buffer layer 222 can be selectively etched only. The gate capping layer 221 is not etched around the bit line contact hole CNT. Therefore, during the formation of the bit line contact hole CNT, the bit line contact 230 and the word line 120 can be prevented from becoming short-circuited due to the etching of the gate capping layer 221.

[0110] Return to reference Figure 4 The buffer layer 222 may be disposed beneath the bit line structure 130. The buffer layer 222 may comprise SiCOH, SiCO, SiO2, SiCN, or combinations thereof. Alternatively, the buffer layer 222 may comprise a material such as ultra-low temperature oxide (ULTO) or spin-on dielectric (SOD), depending on how it is deposited. The buffer layer 222 may comprise a material with etch selectivity relative to the first bit line 241, the second bit line 242, and the third bit line 243.

[0111] According to embodiments of this disclosure, since the buffer layer 222 contains a material that is etch-selective relative to the first bit line 241, the second bit line 242, and the third bit line 243, the buffer layer 222 is not etched along with the first bit line 241, the second bit line 242, and the third bit line 243 during their formation. Therefore, defects resulting from etching residue preventing the landing area of ​​the contact plug 540 from opening can be prevented during the formation of the first bit line 241, the second bit line 242, and the third bit line 243.

[0112] In addition, the buffer layer 222 has higher insulation performance than the gate capping layer 221. Since the buffer layer 222 is disposed around the bit line contact 230, short circuits between the bit line contact 230 and the surrounding structures (e.g., contact plug 540) can be prevented during ion implantation processes that improve the conductivity of the bit line contact 230.

[0113] The above embodiments are merely examples, and those skilled in the art should understand that various modifications can be made to them without departing from the scope of this disclosure. Therefore, the embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this disclosure, and it should be understood that the scope of this disclosure is not limited to these embodiments. Furthermore, these embodiments can be combined to form additional embodiments.

Claims

1. A storage device, comprising: Word lines, It is embedded in the substrate, and the word lines extend along a first direction; Bit line contacts are disposed between the word lines, the bit line contacts contact the active region of the substrate, and the bit line contacts have at least a portion of a side surface recessed toward the center in a second direction perpendicular to the first direction. as well as A gate cover layer includes a first cover portion that contacts the upper surface of the word line and a second cover portion located on the first cover portion, the second cover portion overlapping at least a portion of the side surface of the bit line contact in the second direction and having a width different from the width of the first cover portion.

2. The storage device according to claim 1, wherein, The maximum width of the second covering portion of the gate cover layer is greater than the width of the first covering portion.

3. The storage device according to claim 2, wherein, The bit line contact includes: The first contact portion contacts the active region of the substrate; A second contact portion, located on the first contact portion and overlapping the second covering portion of the gate cover layer in the second direction; and A third contact portion is located on the second contact portion, and the width of the upper surface of the first contact portion is greater than the width of the lower surface of the second contact portion.

4. The storage device according to claim 3, wherein, The width of the upper surface of the second contact portion of the bit line contact is smaller than the width of the lower surface of the third contact portion.

5. The storage device according to claim 3, wherein, The second covering portion of the gate cover layer overlaps with the first contact portion and the third contact portion of the bit line contact.

6. The storage device according to claim 1, wherein, The maximum width of the second covering portion of the gate cover layer is substantially the same as the width of the first covering portion.

7. The memory device of claim 1, further comprising a bit line spacer surrounding the bit line contact, wherein the bit line spacer contacts the upper surface of the second covered portion of the gate cover layer.

8. The storage device according to claim 1, wherein, The lower surface of the second covering portion of the gate capping layer is located at a position higher than the upper surface of the substrate.

9. The memory device of claim 1, further comprising a buffer layer disposed on the gate capping layer, wherein the buffer layer surrounds the bit line contact.

10. The storage device according to claim 9, wherein, The buffer layer comprises an oxide, and the gate capping layer comprises a nitride.

11. A storage device comprising: Word lines, which are embedded in a substrate, extend along a first direction; Bit line contacts are disposed between the word lines, the bit line contacts contact the active region of the substrate, and the bit line contacts have at least a portion of a side surface recessed toward the center in a second direction perpendicular to the first direction. A gate capping layer that overlaps with the word line, and at least a portion thereof overlaps with at least a portion of the side surface of the bit line contact in a second direction; as well as A buffer layer is disposed on the gate cover layer and surrounds the bit line contact.

12. The storage device according to claim 11, wherein, The bit line contact includes: The first contact portion contacts the active region of the substrate; A second contact portion, located on the first contact portion, and overlapping at least a portion of the gate capping layer in the second direction; and A third contact portion is located on the second contact portion, and the width of the upper surface of the first contact portion is greater than the width of the lower surface of the second contact portion.

13. The storage device according to claim 12, wherein, The width of the upper surface of the second contact portion of the bit line contact is smaller than the width of the lower surface of the third contact portion.

14. The storage device according to claim 11, wherein, The gate cover layer includes a first cover portion that contacts the upper surface of the word line and a second cover portion located on the first cover portion, the second cover portion overlapping at least a portion of the side surface of the bit line contact in the second direction and having a width different from the width of the first cover portion.

15. The storage device according to claim 14, wherein, The maximum width of the second covering portion of the gate cover layer is greater than the width of the first covering portion.

16. The storage device according to claim 14, wherein, The maximum width of the second covering portion of the gate cover layer is substantially the same as the width of the first covering portion.

17. The storage device according to claim 14, wherein, The lower surface of the second covering portion of the gate capping layer is located at a position higher than the upper surface of the substrate.

18. The memory device of claim 11, further comprising a bit line spacer surrounding the bit line contact, wherein the bit line spacer contacts a side surface of the buffer layer and an upper surface of the gate capping layer.

19. The storage device according to claim 11, wherein, The buffer layer comprises an oxide, and the gate capping layer comprises a nitride.

20. A storage device comprising: The character line is embedded in the substrate and extends along a first direction; Bit line contacts are disposed between the word lines and in contact with the active region of the substrate; A gate capping layer includes a first capping portion that contacts the upper surface of the word line and a second capping portion located on the first capping portion, wherein the lower surface of the second capping portion is located at a position higher than the upper surface of the substrate; as well as A buffer layer that covers the second cover portion of the gate cover layer and surrounds the bit line contact.

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