Semiconductor device including vertical active pattern

Abstract

A semiconductor device can include a memory region and a peripheral region. The memory region can include cell vertical active patterns, cell gate electrodes, cell upper source / drain patterns, cell contact plugs, cell separation patterns, and data storage structures on the cell contact plugs and the cell separation patterns. The peripheral region can include peripheral vertical active patterns, peripheral gate electrodes having side surfaces facing side surfaces of the peripheral vertical active patterns, and peripheral upper source / drain patterns and peripheral upper interconnects on the peripheral vertical active patterns. Each of the cell upper source / drain patterns can contact a corresponding one of the cell vertical active patterns. The peripheral upper source / drain patterns can include a first peripheral upper source / drain pattern, and the first peripheral upper source / drain pattern can contact a first peripheral vertical active pattern and a second peripheral vertical active pattern among the peripheral vertical active patterns.

Description

Cross-references to related applications

[0001] This application claims the benefit of Korean Patent Application No. 10-2024-0178429, filed on December 4, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes. Technical Field

[0002] Some embodiments of this disclosure relate to semiconductor devices including vertically active patterns. Background Technology

[0003] With increasing demands for high performance, high speed, and / or versatility in semiconductor devices, the integration level of semiconductor devices is constantly increasing. When manufacturing semiconductor devices with fine patterns corresponding to this trend of high integration, it is necessary to implement patterns with fine widths or fine pitches. Summary of the Invention

[0004] According to some example embodiments of this disclosure, a semiconductor device may be provided, and the semiconductor device may include a peripheral transistor having a vertical active pattern disposed in a peripheral region.

[0005] According to some example embodiments of this disclosure, a semiconductor device may be provided, and the semiconductor device may include: a memory region; and a peripheral region, wherein the memory region includes: a cell vertical active pattern; a cell gate electrode, wherein the side surface of the cell gate electrode faces the side surface of the cell vertical active pattern; a cell on-source / drain pattern located on the cell vertical active pattern; at least one cell contact plug located on the cell on-source / drain pattern; a cell separation pattern located on the side surface of the cell on-source / drain pattern and the side surface of at least one cell contact plug; and a data storage structure located on at least one cell contact plug and the cell separation pattern. The peripheral region includes: a peripheral vertical active pattern; a peripheral gate electrode, wherein the side surface of the peripheral gate electrode faces the side surface of the peripheral vertical active pattern; a peripheral upper source / drain pattern located on the peripheral vertical active pattern; at least one peripheral upper interconnect located on the peripheral upper source / drain pattern, wherein each of the cell upper source / drain patterns contacts a corresponding cell vertical active pattern in the cell vertical active pattern, wherein the peripheral upper source / drain pattern includes a first peripheral upper source / drain pattern, and wherein the first peripheral upper source / drain pattern contacts a first peripheral vertical active pattern and a second peripheral vertical active pattern in the peripheral vertical active pattern.

[0006] According to some example embodiments of this disclosure, a semiconductor device may be provided, and the semiconductor device may include: a memory region; and a peripheral region, wherein the memory region includes: a cell vertical active pattern; a cell gate electrode, wherein the side surface of the cell gate electrode faces the side surface of the cell vertical active pattern; a cell on-source / drain pattern located on the cell vertical active pattern; at least one cell contact plug located on the cell on-source / drain pattern; a cell separation pattern located on the side surface of the cell on-source / drain pattern and the side surface of at least one cell contact plug; and a data storage structure located on at least On a cell contact plug and cell separation pattern, wherein the peripheral region includes: a peripheral vertical active pattern; a peripheral gate electrode, wherein the side surface of the peripheral gate electrode faces the side surface of the peripheral vertical active pattern; a peripheral upper source / drain pattern located on the peripheral vertical active pattern; at least one peripheral upper interconnect located on the peripheral upper source / drain pattern, wherein the cell upper source / drain pattern respectively contacts a corresponding cell vertical active pattern in the cell vertical active pattern, and wherein the horizontal width of each of the peripheral upper source / drain patterns is greater than the horizontal width of each of the cell upper source / drain patterns.

[0007] According to some example embodiments of the present disclosure, a semiconductor device may be provided, and the semiconductor device may include: a memory region; and a peripheral region, wherein the memory region includes: a cell vertical active pattern; a cell gate electrode, wherein a side surface of the cell gate electrode faces a side surface of the cell vertical active pattern; a contact structure located on the cell vertical active pattern; a cell separation pattern located on a side surface of the contact structure; a data storage structure located on the contact structure and the cell separation pattern; an insulating layer located on the data storage structure and extending to the peripheral region; and an upper contact plug passing through the insulating layer and connected to the data storage structure, wherein the peripheral region includes: a peripheral vertical active pattern; a peripheral gate electrode, wherein a side surface of the peripheral gate electrode faces a side surface of the peripheral vertical active pattern; a peripheral interconnect structure located on the peripheral vertical active pattern; and a peripheral upper contact plug penetrating the insulating layer and connected to the peripheral interconnect structure, wherein the peripheral interconnect structure contacts a plurality of peripheral vertical active patterns among the peripheral vertical active patterns, and the peripheral interconnect structure is lower than the lower surface of the data storage structure.

[0008] According to some exemplary embodiments of this disclosure, a method for manufacturing a semiconductor device can be provided, and the method includes: forming a cell vertical active pattern and a peripheral vertical active pattern; forming a cell gate electrode and a peripheral gate electrode, wherein a side surface of the cell gate electrode faces a side surface of the cell vertical active pattern, and a side surface of the peripheral gate electrode faces a side surface of the peripheral vertical active pattern; forming a cell upper source / drain pattern and a peripheral upper source / drain pattern, wherein the cell upper source / drain pattern is located on the cell vertical active pattern, and the peripheral upper source / drain pattern is located on the peripheral vertical active pattern; and forming at least one cell contact plug on the cell upper source / drain pattern. The method comprises: forming a cell separation pattern on the side surface of the cell source / drain pattern and on the side surface of at least one cell contact plug; forming a data storage structure on at least one cell contact plug and the cell separation pattern; and forming at least one peripheral interconnect on the peripheral source / drain pattern, wherein each of the cell source / drain patterns contacts a corresponding cell vertical active pattern in the cell vertical active pattern, wherein the peripheral source / drain pattern includes a first peripheral source / drain pattern, and wherein the first peripheral source / drain pattern contacts a first peripheral vertical active pattern and a second peripheral vertical active pattern in the peripheral vertical active pattern.

[0009] According to some example embodiments of this disclosure, the peripheral source / drain pattern is located at the same level as the cell source / drain pattern.

[0010] According to some example embodiments of this disclosure, at least one peripheral interconnect is located at the same level as at least one cell contact plug.

[0011] According to some example embodiments of this disclosure, the peripheral vertical active pattern is located at the same level as the unit vertical active pattern. Attached Figure Description

[0012] The above and other aspects, features, and advantages of embodiments of the present disclosure will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a conceptual perspective view of a semiconductor device according to an example embodiment; Figure 2 This is a circuit diagram illustrating a memory region of a semiconductor device according to an example embodiment; Figure 3 This is a plan view of a semiconductor device according to an example embodiment; Figure 4 yes Figure 3 The diagram shows a vertical cross-sectional view of the semiconductor device taken along line I-I'. Figure 5A and Figure 5B yes Figure 4 An enlarged view of a portion of the semiconductor device shown in the image; Figure 6 This is a conceptual perspective view illustrating a bitline shielding structure according to an example embodiment; Figures 7 to 11 This is a vertical cross-sectional view of a semiconductor device according to an example embodiment; Figures 12 to 27 This is a vertical cross-sectional view shown according to the process sequence used to describe the method of manufacturing a semiconductor device according to an example embodiment. Detailed Implementation

[0013] In the following text, terms such as "upper," "middle," "in the middle," and "lower" may be replaced by other terms such as "first," "second," and "third" to describe components in the specification. Although terms such as "first," "second," and "third" may be used to describe various components, these components are not limited by these terms, and "first component" may be referred to as "second component." In the specification, terms such as "lower," "upper," "top," and "bottom" may be terms used based on the accompanying drawings.

[0014] It will be understood that when a component or layer is referred to as being "on" another component or layer, "connected to", or "coupled to" another component or layer, the component or layer may be directly on, directly connected to, or directly coupled to the other component or layer, or there may be intermediate components or layers. Conversely, when a component or layer is referred to as being "directly on" another component or layer, "directly connected to", or "directly coupled to" another component or layer, there are no intermediate components or layers.

[0015] Reference Figure 1 The following describes a semiconductor device according to an example embodiment. Figure 1 This is a conceptual perspective view of a semiconductor device according to an example embodiment.

[0016] Reference Figure 1 The semiconductor device 1 according to the example embodiment may include a first structure ST1 and a second structure ST2 that vertically overlaps the first structure ST1. The second structure ST2 may be disposed below the first structure ST1.

[0017] In an example embodiment, the first structure ST1 may be a first chip structure including a memory region and a peripheral region, and the second structure ST2 may be a second chip structure including a second peripheral circuit. The first structure ST1 and the second structure ST2 can be formed by bonding via a bonding process such as a wafer bonding process. Therefore, the first structure ST1 can contact and bond with the second structure ST2.

[0018] Semiconductor device 1 may include multiple memory banks BA and an outer peripheral region PERI.

[0019] The outer peripheral area PERI may include a first peripheral area PERI1 within the first structure ST1 and a second peripheral area PERI2 within the second structure ST2. The outer peripheral area PERI may be a peripheral area in which peripheral circuitry for data or command input / output or power / ground input is provided.

[0020] Each of the multiple memory banks BA may include a first memory bank region BA1 within a first structure ST1 and a second memory bank region BA2 within a second structure ST2.

[0021] The first memory bank region BA1 within the first structure ST1 may include memory cells. The second memory bank region BA2 within the second structure ST2 may include peripheral circuitry such as a sense amplifier and a sub-word line driver.

[0022] Next, refer to Figure 2 This will describe the circuitry of the memory region of the first structure ST1. Figure 2 This is a circuit diagram illustrating the memory region of a semiconductor device according to an example embodiment.

[0023] Reference Figure 2 The memory region CR may include memory cells MC. The memory region CR may include memory cells MC arranged in a first horizontal direction X and a second horizontal direction Y, word lines WL connected to the memory cells MC and extending in the first horizontal direction X, and bit lines BL connected to the memory cells MC and extending in the second horizontal direction Y. The first horizontal direction X and the second horizontal direction Y may be perpendicular to each other.

[0024] The word line WL can cross the memory region CR in the first horizontal direction X. The bit line BL can cross the memory region CR in the second horizontal direction Y.

[0025] Each of the memory cells MC may include a data storage structure DS that can be used as a data storage unit, and a cell transistor cTR electrically connected to the data storage structure DS. In a memory such as dynamic random access memory (DRAM), the data storage structure DS may be a cell capacitor capable of storing data.

[0026] The memory region CR may also include a back gate line BG. The corresponding back gate line BG may be disposed between a pair of adjacent word lines WL in the second horizontal direction Y. The corresponding back gate line BG may be disposed between the vertical channel regions of the cell transistor cTR.

[0027] In the following text, refer to Figures 3 to 6as well as Figure 1 and Figure 2 This section will describe an illustrative example of the first portion ST1_A of the first structure ST1 of a semiconductor device according to an example embodiment. Figure 3 This is a plan view of a semiconductor device according to an example embodiment. Figure 4 yes Figure 3 The diagram shows a vertical cross-sectional view of the semiconductor device along line I-I'. Figure 5A and Figure 5B yes Figure 4 An enlarged view of a portion of the semiconductor device shown in the image. Figure 6 This is a conceptual perspective view illustrating a bitline shielding structure according to an example embodiment.

[0028] Reference Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5A , Figure 5B and Figure 6 The first structure ST1 of the semiconductor device 1 may include a memory region CR and a peripheral region PR. Hereinafter, the memory region CR and the peripheral region PR within the first portion ST1_A of the first structure ST1 of the semiconductor device 1 will be described.

[0029] The memory region CR may include a cell vertical active pattern 21c, a cell gate electrode 27c, a cell source / drain pattern 35c, a cell contact plug 57c, and a cell separation pattern 52a. The peripheral region PR may include a first peripheral vertical active pattern 21n, a first peripheral gate electrode 27n, a first peripheral source / drain pattern 35n, and a first peripheral interconnect 57n. The peripheral region PR may also include a second peripheral vertical active pattern 21p, a second peripheral gate electrode 27p, a second peripheral source / drain pattern 35p, and a second peripheral interconnect 57p.

[0030] Each of the cell vertical active patterns 21c may include a cell lower source / drain region 21c_L, a cell vertical channel region 21c_CH on the cell lower source / drain region 21c_L, and a cell upper source / drain region 21c_U on the cell vertical channel region 21c_CH. Each of the first peripheral vertical active patterns 21n may include a first peripheral lower source / drain region 21n_L, a first peripheral vertical channel region 21n_CH on the first peripheral lower source / drain region 21n_L, and a first peripheral upper source / drain region 21n_U on the first peripheral vertical channel region 21n_CH. Each of the second peripheral vertical active patterns 21p may include a second peripheral lower source / drain region 21p_L, a second peripheral vertical channel region 21p_CH on the second peripheral lower source / drain region 21p_L, and a second peripheral upper source / drain region 21p_U on the second peripheral vertical channel region 21p_CH.

[0031] The unit gate electrode 27c can be Figure 2 The word line WL described in the text. The cell gate electrode 27c may have a side surface facing the side surface of the cell vertical active pattern 21c. The first peripheral gate electrode 27n may have a side surface facing the side surface of the first peripheral vertical active pattern 21n. The second peripheral gate electrode 27p may have a side surface facing the side surface of the second peripheral vertical active pattern 21p.

[0032] Each of the source / drain patterns 35c on the cell may include a first source / drain pattern 36c and a second source / drain pattern 42c stacked sequentially. The side surfaces of the first source / drain pattern 36c and the second source / drain pattern 42c may be aligned with each other and are coplanar. Each of the first peripheral source / drain patterns 35n may include a first peripheral source / drain layer 36n and a second peripheral source / drain layer 42n stacked sequentially. The side surfaces of the first peripheral source / drain layer 36n and the second peripheral source / drain layer 42n may be aligned with each other and are coplanar. Each of the second peripheral source / drain patterns 35p may include a third peripheral source / drain layer 36p and a fourth peripheral source / drain layer 48p stacked sequentially. The side surfaces of the third peripheral source / drain layer 36p and the fourth peripheral source / drain layer 48p may be aligned with each other and are coplanar.

[0033] The source / drain pattern 35c on the unit cell can have N-type conductivity. The source / drain pattern 35n on the first periphery can have N-type conductivity. The source / drain pattern 35p on the second periphery can have P-type conductivity.

[0034] The second cell source / drain pattern 42c can have a higher impurity concentration than the first cell source / drain pattern 36c. The impurity concentration of the first cell source / drain pattern 36c can be higher than the impurity concentration of the first cell source / drain region 21c_U. The second peripheral source / drain layer 42n can have a higher impurity concentration than the first peripheral source / drain layer 36n. The impurity concentration of the first peripheral source / drain layer 36n can be higher than the impurity concentration of the first peripheral source / drain region 21n_U. The fourth peripheral source / drain layer 48p can have a higher impurity concentration than the third peripheral source / drain layer 36p. The impurity concentration of the third peripheral source / drain layer 36p can be higher than the impurity concentration of the second-first peripheral source / drain region 21p_U.

[0035] The upper source / drain patterns (e.g., cell upper source / drain pattern 35c, first peripheral upper source / drain pattern 35n, and second peripheral upper source / drain pattern 35p) may vertically overlap with and contact the vertical active patterns (e.g., cell vertical active pattern 21c, first peripheral vertical active pattern 21n, and second peripheral vertical active pattern 21p). The width of each of the upper source / drain patterns (e.g., cell upper source / drain pattern 35c, first peripheral upper source / drain pattern 35n, and second peripheral upper source / drain pattern 35p) in the first horizontal direction X may be greater than the width of each of the vertical active patterns (e.g., cell vertical active pattern 21c, first peripheral vertical active pattern 21n, and second peripheral vertical active pattern 21p) in the first horizontal direction X. The memory region CR and the peripheral region PR may further include pseudo-source / drain patterns 35D, which are disposed at the same level as the upper source / drain patterns (e.g., cell upper source / drain pattern 35c, first peripheral upper source / drain pattern 35n, and second peripheral upper source / drain pattern 35p) and formed of the same material and structure as the upper source / drain patterns (e.g., cell upper source / drain pattern 35c, first peripheral upper source / drain pattern 35n, and second peripheral upper source / drain pattern 35p). The pseudo-source / drain patterns 35D may be spaced apart from the vertical active patterns (e.g., cell vertical active pattern 21c, first peripheral vertical active pattern 21n, and second peripheral vertical active pattern 21p).

[0036] Cell contact plugs 57c may be disposed on the cell source / drain pattern 35c. Each of the cell contact plugs 57c may include a metal-semiconductor compound layer 53c that contacts the upper surface of the second cell source / drain pattern 42c, and a plug pattern 56c on the metal-semiconductor compound layer 53c. The sequentially stacked cell source / drain patterns 35c and cell contact plugs 57c may have side surfaces that are aligned with each other and can form coplanar surfaces. The cell source / drain patterns 35c and cell contact plugs 57c may form a contact structure CS. The side surfaces of the contact structure CS may be defined by a cell separation pattern 52a.

[0037] First peripheral interconnects 57n can be disposed on first peripheral source / drain patterns 35n. Each of the first peripheral interconnects 57n may include a metal semiconductor compound layer 53n contacting the upper surface of the second peripheral source / drain layer 42n, and a conductive layer 56n on the metal semiconductor compound layer 53n. The first peripheral source / drain patterns 35n and first peripheral interconnects 57n, which are stacked sequentially, may have side surfaces aligned with each other. The side surfaces of the first peripheral interconnects 57n may be aligned with the side surfaces of the first peripheral source / drain patterns 35n and may form coplanar surfaces. The metal semiconductor compound layer 53n and the conductive layer 56n may each comprise the same material as the metal semiconductor compound layer 53c and the plug pattern 56c, and may be disposed at the same level as the metal semiconductor compound layer 53c and the plug pattern 56c. The first peripheral source / drain patterns 35n and the first peripheral interconnects 57n may form a first peripheral interconnect structure LSN. The source / drain pattern 35p on the second periphery and the interconnect 57p on the second periphery can form a second periphery interconnect structure LSp. The contact structure CS, the first periphery interconnect structure LSn, and the second periphery interconnect structure LSp can be positioned at the same level as each other.

[0038] like Figure 3 and Figure 4 As shown, the horizontal width of the interconnect 57n on the first periphery can be greater than the horizontal width of the cell contact plug 57c. Furthermore, the horizontal width of the source / drain pattern 35n on the first periphery can be greater than the horizontal width of the cell contact plug 57c.

[0039] Second peripheral interconnects 57p can be disposed on second peripheral source / drain patterns 35p. Each of the second peripheral interconnects 57p may include a metal semiconductor compound layer 53p in contact with the upper surface of the fourth peripheral source / drain layer 48p, and a conductive layer 56p on the metal semiconductor compound layer 53p. The sequentially stacked second peripheral source / drain patterns 35p and second peripheral interconnects 57p may have side surfaces aligned with each other. The side surfaces of the second peripheral interconnects 57p may be aligned with the side surfaces of the second peripheral source / drain patterns 35p and may form coplanar surfaces. The metal semiconductor compound layer 53p and the conductive layer 56p may each comprise the same material as the metal semiconductor compound layer 53c and the plug pattern 56c, and may be disposed at the same level as the metal semiconductor compound layer 53c and the plug pattern 56c.

[0040] like Figure 3 and Figure 4 As shown, the horizontal width of the interconnect 57p on the second periphery can be greater than the horizontal width of the cell contact plug 57c. Furthermore, the horizontal width of the source / drain pattern 35p on the second periphery can be greater than the horizontal width of the cell contact plug 57c.

[0041] Cell contact plugs 57c, first peripheral interconnects 57n, and second peripheral interconnects 57p can be aligned and contacted with upper source / drain patterns (e.g., cell upper source / drain pattern 35c, first peripheral upper source / drain pattern 35n, and second peripheral upper source / drain pattern 35p). Memory regions CR and PR can also include pseudo-contact plugs 57D aligned and contacted with pseudo-source / drain patterns 35D. Pseudo-contact plugs 57D can be positioned at the same level as cell contact plugs 57c, first peripheral interconnects 57n, and second peripheral interconnects 57p, and can be formed of the same material and structure as cell contact plugs 57c, first peripheral interconnects 57n, and second peripheral interconnects 57p.

[0042] Cell separation pattern 52a may define the side surfaces of the sequentially stacked cell source / drain patterns 35c and cell contact plugs 57c. Cell separation pattern 52a may surround the side surfaces of the sequentially stacked cell source / drain patterns 35c and cell contact plugs 57c. Cell separation pattern 52a may include insulating material.

[0043] The peripheral region PR may also include a pad pattern 63a. The memory region CR and the peripheral region PR may also include an insulating liner 66.

[0044] The pad pattern 63a may not vertically overlap with the first peripheral interconnect 57n and the second peripheral interconnect 57p. An insulating liner 66 may be disposed on the cell contact plug 57c, the cell separation pattern 52a, and the pad pattern 63a. The insulating liner 66 may cover the upper surfaces of the cell contact plug 57c and the cell separation pattern 52a in the memory region CR, and may cover the upper and side surfaces of the pad pattern 63a in the peripheral region PR. The insulating liner 66 may include an insulating material such as SiN, SiBN, SiCN, or a high-k dielectric.

[0045] The insulating liner 66 includes a first portion disposed on the upper surface of the cell separation pattern 52a and a second portion disposed on the upper surface of the pad pattern 63a, and the second portion of the insulating liner 66 may be disposed at a level higher than that of the first portion of the insulating liner 66.

[0046] The memory region CR and the peripheral region PR may also include the data storage structure DS and the insulating layer 70.

[0047] The data storage structure DS may include: a first electrode 68a connected within a memory region CR to a cell contact plug 57c (e.g., a cell plug pattern), penetrating an insulating liner 66 and extending in the vertical direction Z; a second electrode 68c located on the side and top surfaces of the first electrode 68a; and a dielectric layer 68b located between the first electrode 68a and the second electrode 68c. The data storage structure DS may be a cell capacitor of a memory such as DRAM.

[0048] The insulating layer 70 may cover the data storage structure DS within the memory region CR and the insulating liner 66 within the peripheral region PR. The insulating layer 70 may include at least one of silicon oxide and a low-k dielectric.

[0049] The memory region CR and the peripheral region PR may further include: a lower source / drain pattern (e.g., cell lower source / drain pattern 78c, first peripheral lower source / drain pattern 78n, and second peripheral lower source / drain pattern 79p), which is connected below the vertical active pattern (e.g., cell vertical active pattern 21c, first peripheral vertical active pattern 21n, and second peripheral vertical active pattern 21p) to the vertical active pattern (e.g., cell vertical active pattern 21c, first peripheral vertical active pattern 21n, and second peripheral vertical active pattern 21p). The vertical active pattern 21p); and the conductive pattern (e.g., bit line 83c, first peripheral lower interconnect 83n and second peripheral lower interconnect 83p) are aligned below the lower source / drain pattern (e.g., cell lower source / drain pattern 78c, first peripheral lower source / drain pattern 78n and second peripheral lower source / drain pattern 79p) with the lower source / drain pattern (e.g., cell lower source / drain pattern 78c, first peripheral lower source / drain pattern 78n and second peripheral lower source / drain pattern 79p).

[0050] The lower source / drain pattern may include a lower source / drain pattern 78c connected to the cell vertical active pattern 21c, a first peripheral lower source / drain pattern 78n connected to the first peripheral vertical active pattern 21n, and a second peripheral lower source / drain pattern 79p connected to the second peripheral vertical active pattern 21p.

[0051] The conductive pattern may include a bit line 83c that contacts and is aligned with the cell lower source / drain pattern 78c, a first peripheral lower interconnect 83n that contacts and is aligned with the first peripheral lower source / drain pattern 78n, and a second peripheral lower interconnect 83p that contacts and is aligned with the second peripheral lower source / drain pattern 79p. Each of the conductive patterns (e.g., bit line 83c, first peripheral lower interconnect 83n, and second peripheral lower interconnect 83p) may include a first conductive layer 81 and a second conductive layer 82 disposed below the first conductive layer 81. The bit line 83c may be... Figure 2 The bit line BL described herein. The conductive patterns (e.g., bit line 83c, first peripheral lower interconnect 83n, and second peripheral lower interconnect 83p) may comprise the same material as each other and may be positioned at the same level as each other.

[0052] The memory region CR may further include a cell gate dielectric layer 24c, a cell back gate electrode 16c, a cell back gate dielectric layer 14c, and an insulating layer (e.g., a back gate cap insulating layer 18, an insulating layer 22, a gate cap insulating layer 33, a separation insulating layer 30, and an insulating layer 75). The peripheral region PR may further include a first peripheral gate dielectric layer 24n, a first peripheral back gate electrode 16n, a first peripheral back gate dielectric layer 14n, a second peripheral gate dielectric layer 24p, a second peripheral back gate electrode 16p, a second peripheral back gate dielectric layer 14p, an insulating layer (e.g., a back gate cap insulating layer 18, an insulating layer 22, a gate cap insulating layer 33, a separation insulating layer 30, and an insulating layer 75), and an insulating structure (e.g., an insulating liner 54 and an insulating pattern 56).

[0053] The unit back gate electrode 16c can be a reference Figure 2 The back gate line BG is described. The unit gate electrodes 27c can each extend in the second horizontal direction Y. The unit gate electrodes 27c can be spaced apart from each other in a first horizontal direction X perpendicular to the second horizontal direction Y. Each of the unit back gate electrodes 16c can have a linear shape extending in the second horizontal direction Y.

[0054] In the unit back gate electrode 16c, a pair of unit back gate electrodes 16c adjacent to each other in the first horizontal direction X can be disposed between unit gate electrodes 27c. In the plane, each of the unit vertical active patterns 21c can have a stripe extending in the second horizontal direction Y. Each of the unit vertical active patterns 21c can be disposed between adjacent unit back gate electrodes 16c and unit gate electrodes 27c.

[0055] Each of the first peripheral gate electrodes 27n may extend in the second horizontal direction Y. Each of the first peripheral back gate electrodes 16n may have a linear shape extending in the second horizontal direction Y. Among the first peripheral gate electrodes 27n, a pair of first peripheral gate electrodes 27n adjacent to each other in the first horizontal direction X may be disposed between a pair of first peripheral back gate electrodes 16n adjacent to each other in the first horizontal direction X. In the plane, each of the first peripheral vertical active patterns 21n may have a strip shape extending in the second horizontal direction Y. Each of the first peripheral vertical active patterns 21n may be disposed between adjacent first peripheral back gate electrodes 16n and first peripheral gate electrodes 27n.

[0056] Each of the second peripheral gate electrodes 27p may extend in the second horizontal direction Y. Each of the second peripheral back gate electrodes 16p may have a linear shape extending in the second horizontal direction Y. Among the second peripheral gate electrodes 27p, a pair of second peripheral gate electrodes 27p adjacent to each other in the first horizontal direction X may be disposed between a pair of second peripheral back gate electrodes 16p adjacent to each other in the first horizontal direction X. In the plane, each of the second peripheral vertical active patterns 21p may have a strip shape extending in the second horizontal direction Y. Each of the second peripheral vertical active patterns 21p may be disposed between adjacent second peripheral back gate electrodes 16p and second peripheral gate electrodes 27p.

[0057] A cell gate dielectric layer 24c can be disposed between the side surface of the cell vertical active pattern 21c and the side surface of the cell gate electrode 27c. The cell gate dielectric layer 24c can extend to cover the lower surface of the cell vertical active pattern 21c. A first peripheral gate dielectric layer 24n can be disposed between the side surface of the first peripheral vertical active pattern 21n and the side surface of the first peripheral gate electrode 27n. The first peripheral gate dielectric layer 24n can extend to cover the lower surface of the first peripheral vertical active pattern 21n. A second peripheral gate dielectric layer 24p can be disposed between the side surface of the second peripheral vertical active pattern 21p and the side surface of the second peripheral gate electrode 27p. The second peripheral gate dielectric layer 24p can extend to cover the lower surface of the second peripheral vertical active pattern 21p.

[0058] The cell back gate dielectric layer 14c can be disposed between the cell vertical active pattern 21c and the cell back gate electrode 16c. The first peripheral back gate dielectric layer 14n can be disposed between the first peripheral vertical active pattern 21n and the first peripheral back gate electrode 16n. The second peripheral back gate dielectric layer 14p can be disposed between the second peripheral vertical active pattern 21p and the second peripheral back gate electrode 16p.

[0059] A back gate capping insulating layer 18 may be disposed below the lower surface of the back gate electrode (e.g., the unit back gate electrode 16c, the first peripheral back gate electrode 16n, and the second peripheral back gate electrode 16p). An insulating layer 75 may be disposed on the upper surface of the back gate electrode (e.g., the unit back gate electrode 16c, the first peripheral back gate electrode 16n, and the second peripheral back gate electrode 16p). A gate capping insulating layer 33 may be disposed on the upper surface of the gate electrode (e.g., the unit gate electrode 27c, the first peripheral gate electrode 27n, and the second peripheral gate electrode 27p). Each of the separating insulating layers 30 may be disposed between adjacent gate electrodes in the gate electrode (e.g., the unit gate electrode 27c, the first peripheral gate electrode 27n, and the second peripheral gate electrode 27p) and between adjacent gate capping insulating layers in the gate capping insulating layer 33. The insulating layer 22 may be disposed between the lower surface of the gate dielectric layer (e.g., the cell gate dielectric layer 24c, the first peripheral gate dielectric layer 24n, and the second peripheral gate dielectric layer 24p) and the lower source / drain pattern (e.g., the cell lower source / drain pattern 78c, the first peripheral lower source / drain pattern 78n, and the second peripheral lower source / drain pattern 79p).

[0060] Each of the insulating structures (e.g., insulating liner 54 and insulating pattern 56) may be positioned at the same level as the upper source / drain patterns (e.g., cell upper source / drain pattern 35c, first peripheral upper source / drain pattern 35n and second peripheral upper source / drain pattern 35p), and the cell contact plug 57c, the first peripheral upper interconnect 57n and the second peripheral upper interconnect 57p. For example, the lower surface of the insulating structure (e.g., insulating liner 54 and insulating pattern 56) may be positioned at the same level as the lower surface of the upper source / drain pattern (e.g., cell upper source / drain pattern 35c, first peripheral upper source / drain pattern 35n and second peripheral upper source / drain pattern 35p), and the upper surface of the insulating structure (e.g., insulating liner 54 and insulating pattern 56) may be positioned at the same level as the upper surface of the cell contact plug 57c, the first peripheral upper interconnect 57n and the second peripheral upper interconnect 57p. The insulating structure may include an insulating pattern 56 and an insulating liner 54 covering the side and bottom surfaces of the insulating pattern 56, respectively. The insulating pattern 56 may include an oxide, and the insulating liner 54 may include a nitride. A pad pattern 63a may be disposed on the upper surface of the insulating structure (e.g., the insulating liner 54 and the insulating pattern 56).

[0061] The memory region CR may also include a bit line shielding structure 88, and the memory region CR and the peripheral region PR may also include insulating structures (e.g., insulating liner 85 and insulating pattern 86) and an insulating layer 90.

[0062] The insulating structure may include an insulating pattern 86 and an insulating liner 85. The insulating liner 85 may cover the upper surface of the insulating pattern 86 and may cover the side surfaces of the lower source / drain patterns (e.g., cell lower source / drain pattern 78c, first peripheral lower source / drain pattern 78n and second peripheral lower source / drain pattern 79p), as well as the side and lower surfaces of the conductive patterns (e.g., bit line 83c, first peripheral lower interconnect 83n and second peripheral lower interconnect 83p).

[0063] Reference Figure 6 The bit line shielding structure 88 may include a vertical portion 88V disposed between bit lines 83c, and a plate portion 88P extending from the vertical portion 88V and vertically overlapping the bit lines 83c. The bit line shielding structure 88 may be spaced apart from the bit lines 83c by an insulating liner 85. An insulating layer 90 may be disposed beneath the insulating structure (e.g., the insulating liner 85 and the insulating pattern 86) and the bit line shielding structure 88.

[0064] Vertical active patterns (e.g., cell vertical active pattern 21c, first peripheral vertical active pattern 21n, and second peripheral vertical active pattern 21p) may include monocrystalline silicon.

[0065] The source / drain pattern 35c on the cell and the first peripheral source / drain pattern 35n may include a first polysilicon, such as a polysilicon having N-type conductivity. The second peripheral source / drain pattern 35p may include a second polysilicon, such as a polysilicon having P-type conductivity.

[0066] The lower source / drain pattern 78c and the first peripheral lower source / drain pattern 78n may include a third polysilicon, such as N-type conductive polysilicon. The second peripheral lower source / drain pattern 79p may include a fourth polysilicon, such as P-type conductive polysilicon.

[0067] The upper source / drain SDcU of the cell may include an upper source / drain pattern 35c and an upper source / drain region 21c_U. The lower source / drain SDcL of the cell may include a lower source / drain pattern 78c and a lower source / drain region 21c_L. The upper source / drain SDcU and the lower source / drain SDcL of the cell may have N-type conductivity. The cell transistor TRc may include an upper source / drain SDcU, a lower source / drain SDcL, a vertical channel region 21c_CH, a gate dielectric layer 24c, and a gate electrode 27c.

[0068] The first peripheral upper source / drain SDnU may include a first peripheral upper source / drain pattern 35n and a first peripheral upper source / drain region 21n_U. The first peripheral lower source / drain SDnL may include a first peripheral lower source / drain pattern 78n and a first peripheral lower source / drain region 21n_L. The first peripheral upper source / drain SDnU and the first peripheral lower source / drain SDnL may have N-type conductivity. The first peripheral transistor TRn may include a first peripheral upper source / drain SDnU, a first peripheral lower source / drain SDnL, a first peripheral vertical channel region 21n_CH, a first peripheral gate dielectric layer 24n, and a first peripheral gate electrode 27n. The first peripheral transistor TRn may be an N-channel metal-oxide-semiconductor (NMOS) transistor. Multiple first peripheral transistors TRn may be configured, and may be as follows: Figure 3 They are positioned as shown in the NMOS transistor regions NMOS1 and NMOS2. Figure 4 In the diagram, the first peripheral transistor TRn is shown sharing the first peripheral upper source / drain pattern 35n, the first peripheral upper interconnect 57n, the first peripheral lower source / drain pattern 78n, and the first peripheral lower interconnect 83n, but the embodiments of this disclosure are not limited thereto.

[0069] The second peripheral upper source / drain SDpU may include a second peripheral upper source / drain pattern 35p and a second peripheral upper source / drain region 21p_U. The second peripheral lower source / drain SDpL may include a second peripheral lower source / drain pattern 79p and a second peripheral lower source / drain region 21p_L. The second peripheral upper source / drain SDpU and the second peripheral lower source / drain SDpL may have P-type conductivity. The second peripheral transistor TRp may include a second peripheral upper source / drain SDpU, a second peripheral lower source / drain SDpL, a second peripheral vertical channel region 21p_CH, a second peripheral gate dielectric layer 24p, and a second peripheral gate electrode 27p. The second peripheral transistor TRp may be a PMOS transistor. Multiple second peripheral transistors TRp may be provided, and the multiple second peripheral transistors TRp may be configured as follows: Figure 3 The PMOS transistor regions PMOS1 and PMOS2 are configured as shown in the diagram. Figure 4 In the diagram, the second peripheral transistor TRp is shown sharing the second peripheral upper source / drain pattern 35p, the second peripheral upper interconnect 57p, the second peripheral lower source / drain pattern 79p, and the second peripheral lower interconnect 83p, but the embodiments of this disclosure are not limited thereto.

[0070] Figures 7 to 13 This is a vertical cross-sectional view of a semiconductor device according to an example embodiment.

[0071] Reference Figure 7 , Figure 4 The first part of the first structure ST1, ST1_A, can be used Figure 7 The first part ST1_B of the first structure ST1 is replaced. In an example embodiment, the first peripheral vertical active pattern 21n may include first peripheral vertical active patterns 21n1 and 21n2 that are respectively connected to the first peripheral lower source / drain pattern 78n and the first peripheral lower interconnect 83n. For example, the first peripheral vertical active pattern 21n1 may be connected to the lower source / drain pattern 78n1 and the first peripheral lower interconnect 83n1, and the first peripheral vertical active pattern 21n2 may be connected to the lower source / drain pattern 78n2 and the first peripheral lower interconnect 83n2. The first peripheral vertical active patterns 21n1 and 21n2 may be connected to the same first peripheral upper source / drain pattern 35n and the first peripheral upper interconnect 57n.

[0072] The first peripheral vertical active pattern 21n1 and the first peripheral vertical active pattern 21n2 can respectively constitute the first peripheral transistor TRn, and the first peripheral transistor TRn composed of the first peripheral vertical active pattern 21n1 and the first peripheral transistor TRn composed of the first peripheral vertical active pattern 21n2 can share the first peripheral source / drain pattern 35n and the first peripheral interconnect 57n.

[0073] In an example embodiment, the second peripheral vertical active pattern 21p may include second peripheral vertical active patterns 21p1 and 21p2, respectively connected to different second peripheral upper source / drain patterns 35p and second peripheral upper interconnects 57p. For example, second peripheral vertical active pattern 21p1 may be connected to second peripheral upper source / drain pattern 35p1 and second peripheral upper interconnect 57p1, and second peripheral vertical active pattern 21p2 may be connected to second peripheral upper source / drain pattern 35p2 and second peripheral upper interconnect 57p2. Second peripheral vertical active patterns 21p1 and 21p2 may be connected to the same second peripheral lower source / drain pattern 79p and the same second peripheral lower interconnect 83p.

[0074] The second peripheral vertical active pattern 21p1 and the second peripheral vertical active pattern 21p2 can respectively form the second peripheral transistor TRp, and the second peripheral transistor TRp formed by the second peripheral vertical active pattern 21p1 and the second peripheral transistor TRp formed by the second peripheral vertical active pattern 21p2 can share the same second peripheral lower source / drain pattern 79p and the same second peripheral lower interconnect 83p.

[0075] Reference Figure 8 , Figure 4 The first part of the first structure ST1, ST1_A, can be used Figure 8The first structure ST1 is replaced by a portion of ST1_C. In an example embodiment, the peripheral region PR may further include a first peripheral interconnect 57n, a second peripheral interconnect 57p, and an upper interconnect structure on the insulating liner 66 (e.g., interlayer insulating layer 205 and conductive pattern 225). The upper interconnect structure may include interlayer insulating layer 205 and conductive pattern 225. Interlayer insulating layer 205 may be disposed on the insulating liner 66.

[0076] The conductive pattern 225 may include: a first via 215n that penetrates the interlayer insulating layer 205 and the insulating liner 66 and is connected to the first peripheral interconnect 57n; a second via 215p that penetrates the interlayer insulating layer 205 and the insulating liner 66 and is connected to the second peripheral interconnect 57p; and an interconnect portion 220pn that is connected to the first via 215n and the second via 215p and is disposed on the interlayer insulating layer 205.

[0077] The interconnect portion 220pn can vertically overlap with the first peripheral interconnect 57n and the second peripheral interconnect 57p. A first via 215n and a second via 215p can extend from the interconnect portion 220pn. The first via 215n and the second via 215p can be disposed between the interconnect portion 220pn, the first peripheral interconnect 57n, and the second peripheral interconnect 57p, and can electrically connect the interconnect portion 220pn, the first peripheral interconnect 57n, and the second peripheral interconnect 57p.

[0078] The conductive pattern 225pn may include a first conductive material layer 210 and a second conductive material layer 212 on the first conductive material layer 210.

[0079] The memory region CR and the peripheral region PR may further include an upper insulating liner 230 disposed on the insulating liner 66 and the upper interconnect structure (e.g., interlayer insulating layer 205 and conductive pattern 225). The upper insulating liner 230 may be disposed on the insulating liner 66 and may cover the side and top surfaces of the upper interconnect structure (e.g., interlayer insulating layer 205 and conductive pattern 225). Figure 8 In this embodiment, the upper interconnect structure (e.g., interlayer insulating layer 205 and conductive pattern 225) can be configured to connect adjacent first peripheral upper interconnects 57n and second peripheral upper interconnects 57p, but is not limited thereto. In an example embodiment, the upper interconnect structure (e.g., interlayer insulating layer 205 and conductive pattern 225) can connect adjacent first peripheral upper interconnects 57n or connect adjacent second peripheral upper interconnects 57p.

[0080] The first electrode 68a of the data storage structure DS can penetrate the insulating liner 66 and the upper insulating liner 230 and is connected to the cell contact plug 57c.

[0081] Reference Figure 9 , Figure 4 The first part of the first structure ST1, ST1_A, can be used Figure 9 The first part of the first structure ST1, ST1_D, is replaced. (This is in contrast to the previous sentence.) Figure 4 , Figure 5A and Figure 5B As shown, the cell gate dielectric layer 24c' can be disposed between the side surface of the cell vertical active pattern 21c and the side surface of the cell gate electrode 27c, and can extend to cover the upper surface of the cell gate electrode 27c. The first peripheral gate dielectric layer 24n' can be disposed between the side surface of the first peripheral vertical active pattern 21n and the side surface of the first peripheral gate electrode 27n, and can extend to cover the upper surface of the first peripheral gate electrode 27n. The second peripheral gate dielectric layer 24p' can be disposed between the side surface of the second peripheral vertical active pattern 21p and the side surface of the second peripheral gate electrode 27p, and can extend to cover the upper surface of the second peripheral gate electrode 27p.

[0082] The back gate capping insulating layer 18 may be disposed on the upper surface of the back gate electrode (e.g., the unit back gate electrode 16c, the first peripheral back gate electrode 16n, and the second peripheral back gate electrode 16p). The insulating layer 75 may be disposed below the lower surface of the back gate electrode (e.g., the unit back gate electrode 16c, the first peripheral back gate electrode 16n, and the second peripheral back gate electrode 16p). The gate capping insulating layer 33 may be disposed below the lower surface of the gate electrode (e.g., the unit gate electrode 27c, the first peripheral gate electrode 27n, and the second peripheral gate electrode 27p). The insulating layer 22 may be disposed on the upper surface of the gate dielectric layer (e.g., the unit gate dielectric layer 24c', the first peripheral gate dielectric layer 24n', and the second peripheral gate dielectric layer 24p').

[0083] Reference Figure 1 and Figure 10A Semiconductor device 1a may include and Figure 1 The first structure ST1 in the first structure ST1 corresponds to the first structure ST1a and is related to Figure 1 The second structure ST2 corresponds to the second structure ST2a. The second structure ST2a can be located below the first structure ST1a, and can be in contact with the first structure ST1a while being connected to it.

[0084] The first structure ST1a may include references Figures 4 to 9 The first part ST1_1 is identical to one of the first parts ST1_A, ST1_B, ST1_C, and ST1_D. For example, the first part ST1_1 can be the same as... Figure 4 The first part ST1_A is the same.

[0085] The first structure ST1a may also include an insulating layer 74 on the first part ST1_1 and an insulating layer 95 below the first part ST1_1.

[0086] The first structure ST1a may also include an upper contact plug (e.g., connecting contact plug 70a and unit contact plug 70c) and an upper interconnect 72. Each of the contact plugs 70a may include a conductive plug pattern 69b and a conductive liner 69a covering the side and lower surfaces of the conductive plug pattern 69b.

[0087] The upper contact plug may include: a unit contact plug 70c that penetrates the insulating layer 70 and is connected to the second electrode 68c; and a connection contact plug 70a that penetrates the insulating layer 70 and the insulating liner 66 and is connected to the pad pattern 63a.

[0088] The upper interconnect 72 may be connected to the contact plug (e.g., connecting contact plug 70a and unit contact plug 70c) and the insulating layer 70. The insulating layer 74 may be disposed on the insulating layer 70 and the upper interconnect 72.

[0089] The first structure ST1a may further include a first peripheral contact plug 70n and a second peripheral contact plug 70p, and an upper interconnect 72 connected to the first peripheral contact plug 70n and the second peripheral contact plug 70. The first peripheral contact plug 70n can penetrate the insulating layer 70 and is connected to the first peripheral interconnect 77n. The second peripheral contact plug 70p can penetrate the insulating layer 70 and is connected to the second peripheral interconnect 57p.

[0090] The first structure ST1a may also include a lower contact plug (e.g., contact plugs 93b, 93a, 93n and 93p) extending upward through the insulating layer 90.

[0091] Each of the lower contact plugs (e.g., contact plugs 93b, 93a, 93n, and 93p) may include a conductive plug pattern 92 and a conductive liner 91 covering the lower and side surfaces of the conductive plug pattern 92.

[0092] The lower contact plug may include a contact plug 93a connected to and in contact with bit line 83c, a contact plug 93b connected to and in contact with pad pattern 63a, a contact plug 93n connected to and in contact with first peripheral lower interconnect 83n, and a contact plug 93p connected to and in contact with second peripheral lower interconnect 83p.

[0093] The first structure ST1a may include an insulating layer 95 disposed below the first portion ST_1, a wiring interconnect structure 97 disposed within the insulating layer 95 and electrically connected to lower contact plugs (e.g., contact plugs 93b, 93a, 93n, and 93p), and a first bonding pad 99 connected to the wiring interconnect structure 97. The lower surface of the insulating layer 95 and the lower surface of the first bonding pad 99 may form coplanar surfaces (e.g., they may be coplanar with each other).

[0094] The second structure ST2a may include a substrate 403 and a device isolation region 406 defining an active region 409 in the substrate 403. The substrate 403 may be a semiconductor substrate.

[0095] The first peripheral circuit pTRa and the second peripheral circuit pTRb can be disposed on the substrate 403.

[0096] Each of the first peripheral circuit pTRa and the second peripheral circuit pTRb may include: a peripheral gate structure (e.g., a peripheral gate dielectric layer pGO and a peripheral gate electrode pGE) disposed on the active region 409; a peripheral source / drain region pSD disposed on both sides of the peripheral gate structure (e.g., the peripheral gate dielectric layer pGO and the peripheral gate electrode pGE) within the active region 409; and a peripheral channel region pCH located between the peripheral source / drain regions pSD. The peripheral gate structure may include a peripheral gate dielectric layer pGO and a peripheral gate electrode pGE stacked sequentially.

[0097] The second structure ST2a may further include: a lower wiring interconnect structure 420 disposed on the substrate 403 and electrically connected to the first peripheral circuit pTRa and the second peripheral circuit pTRb; a second bonding pad 425 disposed on the lower wiring interconnect structure 420; and a lower insulating structure 415. The lower insulating structure 415 may be disposed on the substrate 403 and may have an upper surface coplanar with the upper surface of the second bonding pad 425. The upper surface of the second bonding pad 425 may be bonded to the lower surface of the first bonding pad 99, and the upper surface of the lower insulating structure 415 may be bonded to the lower surface of the insulating layer 95.

[0098] The bottom wiring interconnect structure 420 may include a first bottom wiring interconnect structure 420a electrically connected to the second bonding pad 425, and a second bottom wiring interconnect structure 420b not directly connected to the second bonding pad 425.

[0099] The second structure ST2a may further include: an insulating layer 430 disposed below the substrate 403; a conductive via 440 penetrating the insulating layer 430 and the substrate 403 and connected to the second lower wiring interconnect structure 420b; an insulating spacer 435 disposed on the side surface of the conductive via 440; and an input / output pad 450 connected to the conductive via 440 below the insulating layer 430.

[0100] In the example embodiment, the insulating layer 95, the lower contact plugs (e.g., contact plugs 93b, 93a, 93n and 93p), the wiring interconnect structure 97 and the first bonding pad 99 may be omitted, and the second structure ST2a may be disposed on the first structure ST1a.

[0101] Reference Figure 10B Semiconductor device 1b may include and Figure 1 The first structure ST1 in the first structure ST1 corresponds to the first structure ST1a and is related to Figure 1 The second structure ST2 corresponds to the second structure ST2a in the example embodiment. In this embodiment, the first peripheral contact plug 70n and the second peripheral contact plug 70p of the first structure ST1a can be omitted, and the first structure ST1a can include contact plugs 93n1, 93n2, 93p1, and 93p2. Contact plugs 93n1 and 93p1 can have the same characteristics as the referenced... Figure 10A The described contact plugs 93n and 93p have the same structure. Contact plugs 93n2 and 93p2 can extend upward while penetrating the insulating layer 90. For example, contact plug 93n2 can be connected to the first peripheral interconnect 57n by penetrating the first peripheral source / drain pattern 35n, and contact plug 93p2 can be connected to the second peripheral interconnect 57p by penetrating the second peripheral source / drain pattern 35p.

[0102] Reference Figure 11 The semiconductor device 1c may include a first structure ST1a and a second structure ST2b below the first structure ST1a. It can be... Figure 10A The first bonding pad 99 is omitted in the first structure ST1a. Figure 10A The second structure ST2a in the middle can be used Figure 11 The second structure ST2b is replaced.

[0103] The second structure ST2b may include a first peripheral circuit pTRa vertically overlapping the memory region CR, and a second peripheral circuit pTRb vertically overlapping the peripheral region PR. The second structure ST2b may include a substrate 503 and a component isolation region 506 defining an active region 509 within the substrate 503. The substrate 503 may be a semiconductor substrate.

[0104] The first peripheral circuit pTRa and the second peripheral circuit pTRb can be disposed below the substrate 503.

[0105] Each of the first peripheral circuit pTRa and the second peripheral circuit pTRb may include: a peripheral gate structure (e.g., a peripheral gate dielectric layer pGO and a peripheral gate electrode pGE) disposed below the active region 509; a peripheral source / drain region pSD disposed on both sides of the peripheral gate structure (e.g., the peripheral gate dielectric layer pGO and the peripheral gate electrode pGE) within the active region 509; and a peripheral channel region pCH located between the peripheral source / drain regions pSD. The peripheral gate structure may include the peripheral gate dielectric layer pGO and the peripheral gate electrode pGE sequentially stacked in a downward direction.

[0106] The second structure ST2b may further include: a lower wiring interconnect structure 520 disposed below the substrate 503 and electrically connected to the first peripheral circuit pTRa and the second peripheral circuit pTRb; and a lower insulating structure 515 covering the lower wiring interconnect structure 520 below it.

[0107] The bottom wiring interconnect structure 520 may include a first bottom wiring interconnect structure 520a and a second bottom wiring interconnect structure 520b.

[0108] The second structure ST2b may further include: an input / output pad 550 disposed below the lower insulating structure 515 and electrically connected to the second lower wiring interconnect structure 520b; and an insulating layer 530 disposed between the substrate 503 and the first structure ST1a. The insulating layers 530 and 95 may be interconnected.

[0109] The first structure ST1a and the second structure ST2b may further include: a conductive via 535 electrically connected to the first lower wiring interconnect structure 520a and extending in the vertical direction Z, penetrating the substrate 503 and the insulating layer 530, and contacting and connecting with the wiring interconnect structure 97; and an insulating spacer 534 located on the side surface of the conductive via 535. The conductive via 535 may include a conductive post 535a and a conductive liner layer 535b covering the side and top surfaces of the conductive post 535a.

[0110] Therefore, a semiconductor device 1c comprising a first structure ST1a and a second structure ST2b can be provided.

[0111] In the example embodiment, the insulating layer 95, the lower contact plugs (e.g., contact plugs 93b, 93a, 93n and 93p) and the wiring interconnect structure 97 may be omitted, and the second structure ST2b may be disposed on the first structure ST1a.

[0112] Figures 12 to 27This is a vertical cross-sectional view showing a method for manufacturing a semiconductor device according to an example embodiment, arranged in the process sequence. Figures 12 to 27 It shows along Figure 3 A cross-sectional view of the region intercepted by line I-I', illustrating an example of a method for forming a semiconductor device according to an exemplary embodiment.

[0113] Reference Figure 3 and Figure 12 The sacrificial substrate 3, the sacrificial insulating layer 6, and the semiconductor layer 9 can be formed sequentially. The semiconductor layer 9 can be formed from a semiconductor material such as single-crystal silicon.

[0114] Trench 12 can be formed that penetrates the semiconductor layer 9 and the sacrificial insulating layer 6. Trench 12 can be formed in the memory region CR and the peripheral region PR. Each of the trenches 12 can have a linear shape extending in the second horizontal direction Y. Portions of the semiconductor layer 9 can be spaced apart from each other in the first horizontal direction X via the trenches 12.

[0115] The method may include: forming a back gate dielectric layer 14 conformally covering the inner wall of the trench 12; forming a back gate conductive layer on the back gate dielectric layer 14; partially etching the back gate conductive layer by an etch-back process to form an initial back gate electrode 16 that partially fills the trench 12; and forming a back gate capping insulating layer 18 on the initial back gate electrode 16 that fills the remaining portion of the trench 12. The back gate capping insulating layer 18 may be formed of an insulating material.

[0116] Reference Figure 3 and Figure 13 Semiconductor layer 9 (see Figure 12 Patterning is used to form vertical active patterns while exposing the sacrificial insulating layer 6.

[0117] The vertical active pattern may include a cell vertical active pattern 21c formed in the memory region CR, and a first peripheral vertical active pattern 21n and a second peripheral vertical active pattern 21p formed in the peripheral region PR.

[0118] In the vertical active pattern (e.g., the cell vertical active pattern 21c, the first peripheral vertical active pattern 21n, and the second peripheral vertical active pattern 21p), a pair of vertical active patterns adjacent to each other can be formed on the corresponding side of one of the initial back gate electrodes 16.

[0119] An insulating layer 22 can be formed on the exposed sacrificial insulating layer 6. The upper surface of the insulating layer 22 can be positioned at a level lower than the level of the upper surface of the initial back gate electrode 16.

[0120] The formation of dielectric layers (e.g., cell gate dielectric layer 24c, dielectric layer 24, first peripheral gate dielectric layer 24n, and second peripheral gate dielectric layer 24p) and gate electrodes (e.g., cell gate electrode 27c, first peripheral gate electrode 27n, and second peripheral gate electrode 27p) may include: forming dielectric layers (e.g., cell gate dielectric layer 24c, dielectric layer 24, first peripheral gate dielectric layer 24n, and second peripheral gate dielectric layer 24p) that conformally cover the upper surface of the insulating layer 22 and the exposed side surfaces of vertical active patterns (e.g., cell vertical active pattern 21c, first peripheral vertical active pattern 21n, and second peripheral vertical active pattern 21p) that conformally cover the upper surface of the insulating layer 22 and the exposed side surfaces of the vertical active patterns (e.g., cell vertical active pattern 21c, first peripheral vertical active pattern 21n, and second peripheral vertical active pattern 21p). The process includes: forming an initial gate conductive layer that conformally covers the dielectric layer (e.g., unit gate dielectric layer 24c, dielectric layer 24, first peripheral gate dielectric layer 24n, and second peripheral gate dielectric layer 24p); anisotropically etching the initial gate conductive layer to form the gate conductive layer; forming a separate insulating layer 30 on the gate conductive layer; partially etching the gate conductive layer to form gate electrodes (e.g., unit gate electrode 27c, first peripheral gate electrode 27n, and second peripheral gate electrode 27p); and forming a gate capping insulating layer 33 on the gate electrodes (e.g., unit gate electrode 27c, first peripheral gate electrode 27n, and second peripheral gate electrode 27p).

[0121] The dielectric layer may include a cell gate dielectric layer 24c, a first peripheral gate dielectric layer 24n, a second peripheral gate dielectric layer 24p, and a dielectric layer 24. The cell gate dielectric layer 24c may be in contact with the side surface of the cell vertical active pattern 21c. The first peripheral gate dielectric layer 24n may be in contact with the side surface of the first peripheral vertical active pattern 21n. The second peripheral gate dielectric layer 24p may be in contact with the side surface of the second peripheral vertical active pattern 21p. The dielectric layer 24 may be disposed between adjacent groups of a group of cell vertical active patterns 21c, a group of first peripheral vertical active patterns 21n, and a group of second peripheral vertical active patterns 21p.

[0122] The separation insulating layer 30 can be disposed between adjacent unit gate electrodes 27c, between adjacent first peripheral gate electrodes 27n, between adjacent second peripheral gate electrodes 27p, and on the dielectric layer 24.

[0123] The upper surfaces of the vertical active patterns (e.g., cell vertical active pattern 21c, first peripheral vertical active pattern 21n, and second peripheral vertical active pattern 21p), the separation insulating layer 30, and the gate cap insulating layer 33 can be coplanar with each other.

[0124] Subsequently, a first semiconductor layer 36 and a protective layer 39 on the first semiconductor layer 36 can be formed. The lower surface of the first semiconductor layer 36 can contact the upper surface of the vertical active pattern (e.g., cell vertical active pattern 21c, first peripheral vertical active pattern 21n and second peripheral vertical active pattern 21p).

[0125] The vertical active patterns (e.g., unit vertical active pattern 21c, first peripheral vertical active pattern 21n, and second peripheral vertical active pattern 21p) can be formed from monocrystalline silicon. For example, the vertical active patterns (e.g., unit vertical active pattern 21c, first peripheral vertical active pattern 21n, and second peripheral vertical active pattern 21p) can be formed from undoped monocrystalline silicon.

[0126] In this example, the first semiconductor layer 36 may be formed of polysilicon. For instance, the first semiconductor layer 36 may be formed of undoped polysilicon.

[0127] In the example, the first semiconductor layer 36 can be formed from epitaxial silicon.

[0128] Reference Figure 3 and Figure 14 The protective layer 39 (see Figure 13 Patterning is used to expose portions of the vertical active pattern 21c of the contact cells and the first peripheral vertical active pattern 21n of the first semiconductor layer 36, and to form a lower protective pattern 39a retained on portions of the second peripheral vertical active pattern 21p of the contact cells of the first semiconductor layer 36.

[0129] Reference Figure 3 and Figure 15 A second semiconductor layer 42 and an upper protective pattern 44 can be sequentially formed on a first semiconductor layer 36 exposed by a lower protective pattern 39a. The second semiconductor layer 42 can be formed of polycrystalline silicon having N-type conductivity.

[0130] Reference Figure 3 and Figure 16 This can remove the lower protective pattern 39a (see Figure 15 Therefore, a portion of the first semiconductor layer 36 that contacts the second peripheral vertical active pattern 21p can be exposed.

[0131] A third semiconductor layer may be formed. The third semiconductor layer may include: a first portion 48_1, which contacts the upper surface of a portion of the first semiconductor layer 36 that contacts the second peripheral vertical active pattern 21p; and a second portion 48_2, which contacts the upper surface of the upper protective pattern 44. The second portion 48_2 may be formed at a higher level than the first portion 48_1. The third semiconductor layer (e.g., the first portion 48_1 and the second portion 48_2) may be formed of polysilicon having P-type conductivity. An insulating layer may be formed on the third semiconductor layer (e.g., the first portion 48_1 and the second portion 48_2), and the insulating layer may be planarized until the upper surface of the second portion 48_2 is exposed, thereby forming a buffer insulating pattern 50 retained on the first portion 48_1.

[0132] Reference Figure 3 and Figure 17 The second portion 48_2 of the third semiconductor layer can be etched and removed. Therefore, the first portion 48_1 of the third semiconductor layer can be retained.

[0133] Reference Figure 3 and Figure 18 The thickness of the first portion 48_1 of the third semiconductor layer and the second semiconductor layer 42 can be planarized to form the third semiconductor pattern 48a and the second semiconductor pattern 42a. During planarization, the upper protective pattern 44 and the buffer insulating pattern 50 can be removed.

[0134] The third semiconductor pattern 48a and the second semiconductor pattern 42a can have substantially the same thickness.

[0135] The first impurity in the second semiconductor pattern 42a can diffuse into the upper regions of the first semiconductor layer 36, the unit vertical active pattern 21c, and the first peripheral vertical active pattern 21n. Therefore, the concentration of the first impurity in the second semiconductor pattern 42a can be higher than the concentration of the first impurity in the first semiconductor layer 36, and the concentration of the first impurity in the first semiconductor layer 36 can be higher than the concentration of the first impurity in the upper regions of the unit vertical active pattern 21c and the first peripheral vertical active pattern 21n. The first impurity can be a Group V element from the periodic table, such as P or As.

[0136] The second impurity in the third semiconductor pattern 48a can diffuse into the upper region of the first semiconductor layer 36 and the second peripheral vertical active pattern 21p. Therefore, the concentration of the second impurity in the third semiconductor pattern 48a can be higher than the concentration of the second impurity in the first semiconductor layer 36, and the concentration of the second impurity in the first semiconductor layer 36 can be higher than the concentration of the second impurity in the upper region of the second peripheral vertical active pattern 21p. The second impurity can be a Group III element from the periodic table, such as B or Al. The first semiconductor layer 36 can be formed of polycrystalline silicon doped with Group V and Group III elements.

[0137] Reference Figure 3 and Figure 19 An initial conductive layer 57 can be formed on the second semiconductor pattern 42a and the third semiconductor pattern 48a. The initial conductive layer 57 may include a first conductive layer 53 and a second conductive layer 55 on the first conductive layer 53. The first conductive layer 53 may include a metal semiconductor compound, and the second conductive layer 55 may include at least one of a metal and a metal nitride.

[0138] Reference Figure 3 and Figure 20 An insulating structure (e.g., insulating liner 54 and insulating pattern 56) can be formed. An insulating structure (e.g., insulating liner 54 and insulating pattern 56) can be formed within the peripheral region PR.

[0139] The insulating structures (e.g., insulating liner 54 and insulating pattern 56) may penetrate the first semiconductor layer 36, the second semiconductor pattern 42a, the third semiconductor pattern 48a, and the initial conductive layer 57. Each of the insulating structures may include the insulating pattern 56 and the insulating liner 54 covering the side and bottom surfaces of the insulating pattern 56. The insulating pattern 56 may include an oxide, and the insulating liner 54 may include a nitride.

[0140] Within the peripheral region PR, the first semiconductor layer 36, the second semiconductor pattern 42a, the third semiconductor pattern 48a, and the initial conductive layer 57 can be patterned using insulating structures (e.g., insulating liner 54 and insulating pattern 56). The first semiconductor layer 36, defined by the insulating structures (e.g., insulating liner 54 and insulating pattern 56), can be referred to as the first peripheral source / drain layer 36n and the third peripheral source / drain layer 36p. The second semiconductor pattern 42a, defined by the insulating structures (e.g., insulating liner 54 and insulating pattern 56), can be referred to as the second peripheral source / drain layer 42n. The third semiconductor pattern 48a, defined by the insulating structures (e.g., insulating liner 54 and insulating pattern 56), can be referred to as the fourth peripheral source / drain layer 48p. The first peripheral source / drain layer 36n and the second peripheral source / drain layer 42n can form the first peripheral source / drain pattern 35n. The third peripheral upper source / drain layer 36p and the fourth peripheral upper source / drain layer 48p can form the second peripheral upper source / drain pattern 35p.

[0141] The initial conductive layer 57 separated by the insulating structure (e.g., insulating liner 54 and insulating pattern 56) may be referred to as a first peripheral interconnect 57n and a second peripheral interconnect 57p. For example, the first conductive layer 53 and the second conductive layer 55 separated by the insulating structure (e.g., insulating liner 54 and insulating pattern 56) may be referred to as metal semiconductor compound layers 53n and 53p and conductive layers 56n and 56p.

[0142] The first peripheral interconnect 57n and the second peripheral interconnect 57p can be as follows: Figure 3 The pattern shown extends horizontally and can be used as an interconnect to electrically connect the corresponding first peripheral vertical active pattern 21n and the second peripheral vertical active pattern 21p, respectively.

[0143] Reference Figure 3 and Figure 21 This can form a unit separation pattern 52a. The unit separation pattern 52a can be formed from an insulating nitride, such as silicon nitride.

[0144] Cell separation pattern 52a is shown as spaced apart from cell vertical active pattern 21c, but according to an example embodiment, at least one of the cell separation patterns 52a may contact at least one of the cell vertical active patterns 21c. Cell separation pattern 52a may be formed within memory region CR and may penetrate the first semiconductor layer 36, the second semiconductor pattern 42a, and the initial conductive layer 57. The first semiconductor layer 36, the second semiconductor pattern 42a, and the initial conductive layer 57 may be patterned within memory region CR to form cell separation pattern 52a. The first semiconductor layer 36 and the second semiconductor pattern 42a, separated by cell separation pattern 52a, may be referred to as first cell upper source / drain pattern 36c and second cell upper source / drain pattern 42c. The first cell upper source / drain pattern 36c and the second cell upper source / drain pattern 42c may form cell upper source / drain pattern 35c.

[0145] The initial conductive layer 57 divided by the cell separation pattern 52a can be referred to as cell contact plug 57c. For example, the first conductive layer 53 and the second conductive layer 55 of the initial conductive layer 57 can be divided by the cell separation pattern 52a and can be referred to as metal semiconductor compound layer 53c and plug pattern 56c.

[0146] like Figure 20 and Figure 21 As shown, according to an example embodiment of this disclosure, since the peripheral interconnects 57n and 57p are formed by patterning the initial conductive layer 57, the process can be simplified compared to forming a separation pattern such as cell separation pattern 52a in the peripheral region PR and forming the interconnects on the separation pattern. Furthermore, the shape and structure of the peripheral interconnects 57n and 57p can be implemented in a more diverse manner. For example, as... Figure 3 As shown, since a structure such as the cell contact plug 57c is not formed on the peripheral region PR, the peripheral interconnects 57n and 57p can be formed with a structure larger than that of the cell contact plug 57c.

[0147] Reference Figure 3 and Figure 22 Pad patterns 63a can be formed on the insulating structure (e.g., insulating liner 54 and insulating pattern 56) within the peripheral region PR. An insulating liner 66 can be formed that covers the upper surfaces of the cell contact plug 57c and cell separation pattern 52a in the memory region CR, and covers the upper surfaces of the insulating structure (e.g., insulating liner 54 and insulating pattern 56), pad patterns 63a, first peripheral interconnect 57n, and second peripheral interconnect 57p in the peripheral region PR.

[0148] A data storage structure DS can be formed in the memory region CR. The data storage structure DS may include: a first electrode 68a connected to a cell contact plug 57c, penetrating an insulating liner 66 and extending in the vertical direction Z; a second electrode 68c located on the side and top surfaces of the first electrode 68a; and a dielectric layer 68b located between the first electrode 68a and the second electrode 68c.

[0149] An insulating layer 70 may be formed, which covers the data storage structure DS within the memory region CR and the insulating liner 66 within the peripheral region PR. The insulating liner 66 may include a material different from that of the insulating layer 70.

[0150] Reference Figure 3 and Figure 23 It can form contact plugs (e.g., connecting contact plug 70a and unit contact plug 70c) and peripheral contact plugs (e.g., first peripheral contact plug 70n and second peripheral contact plug 70p). Each of the contact plugs (e.g., connecting contact plug 70a and unit contact plug 70c) and peripheral contact plugs (e.g., first peripheral contact plug 70n and second peripheral contact plug 70p) can include a conductive plug pattern 69b and a conductive liner 69a covering the side and bottom surfaces of the conductive plug pattern 69b.

[0151] The contact plugs may include: a unit contact plug 70c that penetrates the insulating layer 70 and is connected to the second electrode 68c; and a connecting contact plug 70a that penetrates the insulating layer 70 and the insulating liner 66 and is connected to the pad pattern 63a. Peripheral contact plugs may include: a first peripheral contact plug 70n that penetrates the insulating layer 70 and is connected to the first peripheral interconnect 57n; and a second peripheral contact plug 70p that penetrates the insulating layer 70 and is connected to the second peripheral interconnect 57p.

[0152] Upper interconnects 72 may be formed on the contact plugs (e.g., connecting contact plug 70a and unit contact plug 70c), peripheral contact plugs (e.g., first peripheral contact plug 70n and second peripheral contact plug 70p), and insulating layer 70, connecting to the contact plugs (e.g., connecting contact plug 70a and unit contact plug 70c) and peripheral contact plugs (e.g., first peripheral contact plug 70n and second peripheral contact plug 70p). An insulating layer 74 may be formed on insulating layer 70 and upper interconnects 72.

[0153] Reference Figure 3 and Figure 24After the insulating layer 74 is positioned downwards, the sacrificial substrate 3 and the sacrificial insulating layer 6 can be removed. The initial back gate electrode 16 can be partially etched to form back gate electrodes (e.g., unit back gate electrode 16c, first peripheral back gate electrode 16n, and second peripheral back gate electrode 16p), and the insulating layer 75 can be formed on the back gate electrodes (e.g., unit back gate electrode 16c, first peripheral back gate electrode 16n, and second peripheral back gate electrode 16p). The insulating layer 22 and vertical active patterns (e.g., unit vertical active pattern 21c, first peripheral vertical active pattern 21n, and second peripheral vertical active pattern 21p) can be exposed.

[0154] Reference Figure 3 and Figure 25 The second semiconductor pattern 42a (see [reference]) can be formed on the exposed insulating layer 22 and the vertical active pattern (e.g., cell vertical active pattern 21c, first peripheral vertical active pattern 21n, and second peripheral vertical active pattern 21p). Figure 18 ) and third semiconductor pattern 48a (see Figure 18 The corresponding fifth semiconductor pattern 78 and sixth semiconductor pattern 79. These can be used in conjunction with the formation of the second semiconductor pattern 42a (see...). Figure 18 ) and third semiconductor pattern 48a (see Figure 18 The fifth semiconductor pattern 78 and the sixth semiconductor pattern 79 are formed in the same manner as the second semiconductor pattern 42a (see...). Figure 18 The fifth semiconductor pattern 78 and the third semiconductor pattern 48a (see [reference]) can be formed from the same material as each other, and the third semiconductor pattern 48a (see [reference]) can also be formed from the same material as each other. Figure 18 The sixth semiconductor pattern 79 and the sixth semiconductor pattern 79 can be formed from the same material as each other.

[0155] Reference Figure 3 and Figure 26 Conductive structures (e.g., a first conductive layer 81 and a second conductive layer 82) can be formed on the fifth semiconductor pattern 78 and the sixth semiconductor pattern 79. The conductive structures may include a first conductive layer 81 and a second conductive layer 82 stacked sequentially.

[0156] The conductive structures (e.g., the first conductive layer 81 and the second conductive layer 82), the fifth semiconductor pattern 78 and the sixth semiconductor pattern 79 can be patterned to form conductive patterns (e.g., bit line 83c, the first peripheral lower interconnect 83n and the second peripheral lower interconnect 83p) and lower source / drain patterns (e.g., cell lower source / drain pattern 78c, the first peripheral lower source / drain pattern 78n and the second peripheral lower source / drain pattern 79p).

[0157] The lower source / drain pattern may include a lower source / drain pattern 78c connected to the cell vertical active pattern 21c, a first peripheral lower source / drain pattern 78n connected to the first peripheral vertical active pattern 21n, and a second peripheral lower source / drain pattern 79p connected to the second peripheral vertical active pattern 21p.

[0158] Impurities in the lower source / drain pattern 78c of the cell can diffuse into the vertical active pattern 21c of the cell, thereby forming a source / drain region in the vertical active pattern 21c. Impurities in the first peripheral lower source / drain pattern 78n can diffuse into the first peripheral vertical active pattern 21n, thereby forming a source / drain region in the first peripheral vertical active pattern 21n. Impurities in the second peripheral lower source / drain pattern 79p can diffuse into the second peripheral vertical active pattern 21p, thereby forming a source / drain region in the second peripheral vertical active pattern 21p.

[0159] The conductive patterns (e.g., bit line 83c, first peripheral lower interconnect 83n, and second peripheral lower interconnect 83p) may include: bit line 83c, which contacts and is self-aligned to cell lower source / drain pattern 78c; first peripheral lower interconnect 83n, which contacts and is self-aligned to first peripheral lower source / drain pattern 78n; and second peripheral lower interconnect 83p, which contacts and is self-aligned to second peripheral lower source / drain pattern 79p.

[0160] Reference Figure 3 and Figure 27 An insulating structure (e.g., an insulating liner 85 and an insulating pattern 86) and a bit line shielding structure 88 can be formed. The insulating structure may include the insulating pattern 86 and the insulating liner 85, the insulating liner 85 covering the lower surface of the insulating pattern 86, the side surfaces of the lower source / drain patterns (e.g., cell lower source / drain pattern 78c, first peripheral lower source / drain pattern 78n, and second peripheral lower source / drain pattern 79p), and the side and upper surfaces of the conductive patterns (e.g., bit lines 83c, first peripheral lower interconnects 83n, and second peripheral lower interconnects 83p). The bit line shielding structure 88 may be disposed between and above the bit lines 83c. The bit line shielding structure 88 may be spaced apart from the bit lines 83c by the insulating liner 85.

[0161] An insulating layer 90 may be formed on an insulating structure (e.g., an insulating liner 85 and an insulating pattern 86) and a bit line shielding structure 88.

[0162] Contact plugs (e.g., contact plugs 93b, 93a, 93n and 93p) may be formed that extend downward through the insulating layer 90.

[0163] Each of the contact plugs (e.g., contact plugs 93b, 93a, 93n, and 93p) may include a conductive plug pattern 92 and a conductive liner 91 covering the lower and side surfaces of the conductive plug pattern 92. The contact plugs may include a contact plug 93a connected to and in contact with a bit line 83c, a contact plug 93b connected to and in contact with a pad pattern 63a, a contact plug 93n connected to and in contact with a first peripheral lower interconnect 83n, and a contact plug 93p connected to and in contact with a second peripheral lower interconnect 83p.

[0164] An insulating layer 95 can be formed on the contact plugs (e.g., contact plugs 93b, 93a, 93n, and 93p) and the insulating layer 90; a wiring interconnect structure 97 disposed within the insulating layer 95 and electrically connected to the contact plugs (e.g., contact plugs 93b, 93a, 93n, and 93p); and a first bonding pad 99 connected to the wiring interconnect structure 97. The upper surface of the insulating layer 95 and the upper surface of the first bonding pad 99 can form a common surface (e.g., they can be coplanar with each other). Therefore, a structure such as... Figure 10A The first structure ST1a in the text.

[0165] As described above, according to some embodiments, peripheral interconnects with various sizes and structures can be implemented.

[0166] Although non-limiting exemplary embodiments have been described above with reference to the accompanying drawings, it will be apparent to those skilled in the art that modifications and changes can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, comprising: Memory area; as well as Outer area The memory region includes: Vertical active pattern in the unit; A unit gate electrode, wherein the side surface of the unit gate electrode faces the side surface of the unit vertical active pattern; The source / drain pattern on the cell is located on the vertical active pattern of the cell; At least one cell contact plug is located on the source / drain pattern of the cell; Cell separation patterns are located on the side surfaces of the source / drain patterns on the cells and on the side surfaces of the at least one cell contact plug; and A data storage structure is located on the at least one unit contact plug and the unit separation pattern. The peripheral area includes: The outer edge features a vertical active pattern; A peripheral gate electrode, wherein the side surface of the peripheral gate electrode faces the side surface of the peripheral vertical active pattern; The peripheral source / drain pattern is located on the peripheral vertical active pattern; and At least one peripheral interconnect located on the peripheral source / drain pattern, Each of the source / drain patterns on the unit contacts a corresponding vertical active pattern in the unit's vertical active pattern. Wherein, the peripheral source / drain pattern includes a first peripheral source / drain pattern, and Wherein, the first peripheral source / drain pattern contacts the first peripheral vertical active pattern and the second peripheral vertical active pattern among the peripheral vertical active patterns.

2. The semiconductor device according to claim 1, wherein, The peripheral source / drain pattern is located at the same level as the source / drain pattern of the cell.

3. The semiconductor device according to claim 1, wherein, The at least one peripheral interconnect is located at the same level as the at least one unit contact plug.

4. The semiconductor device according to claim 1, wherein, The peripheral vertical active pattern is located at the same horizontal level as the unit vertical active pattern.

5. The semiconductor device according to claim 1, wherein, The at least one peripheral interconnect includes a first peripheral interconnect located on the first peripheral source / drain pattern, and Wherein, the side surface of the interconnect on the first periphery is coplanar with the side surface of the source / drain pattern on the first periphery.

6. The semiconductor device according to claim 5, wherein, The horizontal width of the interconnect on the first periphery is the same as the horizontal width of the source / drain pattern on the first periphery.

7. The semiconductor device according to claim 1, wherein, The memory region also includes: The source / drain pattern of the cell is located below the vertical active pattern of the cell; and Bit lines, which are located below the source / drain pattern of the cell, and The peripheral area also includes: At least one peripheral lower source / drain pattern is located below the peripheral vertical active pattern; and At least one peripheral lower interconnect is located below the at least one peripheral lower source / drain pattern.

8. The semiconductor device according to claim 7, wherein, The at least one peripheral lower source / drain pattern includes a first peripheral lower source / drain pattern that contacts the first peripheral vertical active pattern and the second peripheral vertical active pattern.

9. The semiconductor device according to claim 7, wherein, The side surface of the at least one peripheral lower interconnect is coplanar with the side surface of the at least one peripheral lower source / drain pattern.

10. The semiconductor device according to claim 7, wherein, The at least one peripheral lower source / drain pattern includes a first peripheral lower source / drain pattern and a second peripheral lower source / drain pattern spaced apart in the horizontal direction. Wherein, the first peripheral lower source / drain pattern contacts the first peripheral vertical active pattern, and The second peripheral lower source / drain pattern contacts the second peripheral vertical active pattern.

11. The semiconductor device according to claim 7, wherein, The peripheral source / drain pattern also includes: The second peripheral source / drain pattern contacts the third peripheral vertical active pattern within the aforementioned peripheral vertical active patterns; and The third peripheral source / drain pattern contacts the fourth peripheral vertical active pattern among the peripheral vertical active patterns, and One of the at least one peripheral lower source / drain patterns contacts the third peripheral vertical active pattern and the fourth peripheral vertical active pattern.

12. The semiconductor device according to claim 7, wherein, The vertical distance from the peripheral vertical active pattern to the at least one peripheral upper interconnect is greater than the vertical distance from the peripheral vertical active pattern to the at least one peripheral lower interconnect.

13. The semiconductor device according to claim 7, wherein, The at least one peripheral lower interconnect is located at the same level as the bit line.

14. The semiconductor device according to claim 1, wherein, The peripheral region also includes an upper connection structure, which is located on the at least one peripheral upper interconnect and connects the at least one peripheral upper interconnect.

15. A semiconductor device, comprising: Memory area; as well as Outer area The memory region includes: Vertical active pattern in the unit; A unit gate electrode, wherein the side surface of the unit gate electrode faces the side surface of the unit vertical active pattern; The source / drain pattern on the cell is located on the vertical active pattern of the cell; At least one cell contact plug is located on the source / drain pattern of the cell; Cell separation patterns are located on the side surfaces of the source / drain patterns on the cells and on the side surfaces of the at least one cell contact plug; and A data storage structure is located on the at least one unit contact plug and the unit separation pattern. The peripheral area includes: The outer edge features a vertical active pattern; A peripheral gate electrode, wherein the side surface of the peripheral gate electrode faces the side surface of the peripheral vertical active pattern; The peripheral source / drain pattern is located on the peripheral vertical active pattern; and At least one peripheral interconnect located on the peripheral source / drain pattern, Wherein, the source / drain patterns on the unit respectively contact one of the corresponding vertical active patterns in the unit's vertical active patterns, and Wherein, the horizontal width of each of the peripheral source / drain patterns is greater than the horizontal width of each of the cell source / drain patterns.

16. The semiconductor device according to claim 15, wherein, The horizontal width of each of the at least one peripheral interconnect is greater than the horizontal width of the corresponding unit contact plug among the at least one unit contact plug.

17. The semiconductor device according to claim 15, wherein, At least one of the peripheral source / drain patterns vertically overlaps with multiple of the unit vertical active patterns.

18. The semiconductor device according to claim 15, wherein, The unit vertical active pattern and the peripheral vertical active pattern comprise monocrystalline silicon, and The source / drain pattern on the unit and the source / drain pattern on the periphery include polysilicon.

19. The semiconductor device according to claim 15, wherein, The at least one unit contact plug comprises the same material as the at least one peripheral interconnect.

20. A semiconductor device, comprising: Memory area; as well as Outer area The memory region includes: Vertical active pattern in the unit; A unit gate electrode, wherein the side surface of the unit gate electrode faces the side surface of the unit vertical active pattern; A contact structure located on the vertical active pattern of the unit; Unit separation pattern, which is located on the side surface of the contact structure; A data storage structure is located on the contact structure and the unit separation pattern; An insulating layer, which is located on the data storage structure and extends onto the peripheral area; and The upper contact plug passes through the insulating layer and connects to the data storage structure. The peripheral area includes: The outer edge features a vertical active pattern; A peripheral gate electrode, wherein the side surface of the peripheral gate electrode faces the side surface of the peripheral vertical active pattern; Peripheral interconnect structure, which is located on the peripheral vertical active pattern; and The peripheral contact plug penetrates the insulating layer and connects to the peripheral interconnect structure, and The peripheral interconnect structure contacts multiple peripheral vertical active patterns in the peripheral vertical active pattern, and the peripheral interconnect structure is lower than the lower surface of the data storage structure.

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