A memory device and a method of fabricating the same

Abstract

The application discloses a memory device and a manufacturing method thereof. The memory device comprises a first electrical connection structure protruding on a horizontal surface of a substrate; and a phase change memory unit suspended on the surface of the substrate, the phase change memory unit comprising a first electrode, a phase change unit and a second electrode connected in sequence, two ends of the first electrode spanning between a top end of the first electrical connection structure and the phase change unit, a planar bottom surface of one end of the first electrode connected with the top end of the first electrical connection structure, an end surface of the other end of the first electrode connected with a side surface of the phase change unit, the phase change unit arranged on one side of a horizontal plane where the first electrode is located, and the second electrode located on a top surface of the phase change unit. The application can reduce the vertical occupation height of the memory device, and make the chip area after embedding the memory device consistent with the normal chip when not embedded, so as to minimize the influence of the embedding process on the chip, and make the device further miniaturized and densified.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit technology, and in particular to a memory device and its manufacturing method. Background Technology

[0002] Traditional embedded memories typically employ a structure where a bottom electrode, a functional layer, and a top electrode are sequentially connected vertically on a substrate, forming a bottom-up conductive operating mode. The thickness of the functional layer and the height of the conductive electrode directly limit the versatility of integrating embedded memories into integrated circuit processes.

[0003] The best manufacturing process for embedded memory is to add some steps to the normal standard manufacturing process without changing the shape and structure of other devices outside the embedded area, thereby obtaining some new storage functions.

[0004] As a type of embedded memory, traditional phase-change memory (PCM) typically requires blade electrodes with very small contact areas as bottom electrodes. This generates a large amount of heat when current passes through, altering the resistive characteristics of the phase-change material in the phase-change functional layer. Therefore, PCM requires more vertical space to manufacture these blade electrodes, making it occupy more vertical space on the chip compared to other types of memory. This increases the difficulty of embedding PCM and makes it difficult to meet the requirements of process platforms. Summary of the Invention

[0005] The purpose of this invention is to overcome the above-mentioned defects in the prior art and to provide a storage device and a method for manufacturing the same.

[0006] To achieve the above objectives, the technical solution of the present invention is as follows: This invention provides a storage device, comprising: The first electrical connection structure is protruding and disposed on the horizontal surface of the substrate; A phase-change memory cell is suspended on the surface of the substrate. The phase-change memory cell includes a first electrode, a phase-change unit, and a second electrode connected in sequence. The two ends of the first electrode span between the top end of the first electrical connection structure and the phase-change unit. The bottom plane of one end of the first electrode is connected to the top end of the first electrical connection structure, and the end face of the other end of the first electrode is connected to the side of the phase-change unit. The phase-change unit is located on one side of the horizontal plane where the first electrode is located, and the second electrode is located on the top surface of the phase-change unit.

[0007] Furthermore, it also includes a second electrical connection structure, which is disposed on the top surface of the second electrode.

[0008] Further, the first electrical connection structure includes a contact hole; and / or, the second electrical connection structure includes a metal interconnect and is directly connected to the top surface of the second electrode; and / or, a dielectric layer is provided on the surface of the substrate, and the first electrical connection structure, the phase change memory cell, and the second electrical connection structure are disposed in the dielectric layer.

[0009] Furthermore, the second electrode material includes tantalum nitride.

[0010] Furthermore, the first electrode forms a blade electrode for laterally heating the phase change unit.

[0011] Furthermore, the distance between the bottom surface of the phase change unit and the substrate surface is less than the distance between the top end of the first electrical connection structure and the substrate surface; and / or, the first electrode is arranged in a direction parallel to the substrate surface, and after the first electrode extends laterally from the top end of the first electrical connection structure, it first turns towards the substrate along the side of the first electrical connection structure, and then extends to the side connected to the phase change unit in a direction parallel to the substrate surface; and / or, a protective layer is provided on the first electrode.

[0012] The present invention also provides a method for manufacturing a storage device, comprising: A first electrical connection structure is formed protruding from the horizontal surface of the substrate; A phase change memory cell is formed suspended on the surface of the substrate. The phase change memory cell includes a first electrode, a phase change unit, and a second electrode connected in sequence. The two ends of the first electrode span between the top end of the first electrical connection structure and the phase change unit. The bottom plane of one end of the first electrode is connected to the top end of the first electrical connection structure, and the end face of the other end of the first electrode is connected to the side of the phase change unit. The phase change unit is located on one side of the horizontal plane where the first electrode is located, and the second electrode is located on the top surface of the phase change unit.

[0013] Furthermore, it also includes: forming a second electrical connection structure, the second electrical connection structure being disposed on the top surface of the second electrode.

[0014] Furthermore, the formation of the first electrical connection structure, the phase-change memory unit, and the second electrical connection structure specifically includes: A first dielectric layer is formed on the surface of the substrate; A contact hole is formed on the surface of the first dielectric layer, with its bottom end connected to the substrate, as a first electrical connection structure; A first isolation layer is formed on the surface of the first dielectric layer to cover the contact hole; A first groove is formed on the surface of the first isolation layer, such that one sidewall of the first groove is connected to the top side of the contact hole, and the bottom surface of the first groove is lower than the top of the contact hole, exposing the top of the contact hole and the surface of the first dielectric layer located on the bottom surface of the first groove. A first electrode material layer is formed on the surface of the first isolation layer, such that the first electrode material layer covers the top of the contact hole and the sidewalls and bottom surface of the first trench; A second isolation layer is formed on the surface of the first electrode material layer, and the first trench within the first electrode material layer is filled; The second isolation layer and the first electrode material layer are patterned to form a first electrode intermediate pattern connected to the top of the contact hole through a first end in the first trench, and a second isolation layer intermediate pattern located on the first electrode intermediate pattern, exposing the surface of the first isolation layer outside the first trench, and exposing the second end of the first electrode intermediate pattern and the surface of the first dielectric layer inside the first trench. A third isolation layer is formed on the surface of the first isolation layer, covering the middle pattern of the second isolation layer, the middle pattern of the first electrode, and the exposed surface of the first dielectric layer; A second dielectric layer with a planarized surface is formed on the surface of the third isolation layer; A second trench with its bottom located in the first dielectric layer is formed on the surface of the second dielectric layer within the first trench, and the second end of the middle pattern of the first electrode is exposed on the sidewall of the second trench, thereby forming a first electrode; wherein, the middle pattern of the second isolation layer located within the first trench and the third isolation layer form a protective layer, and the first isolation layer and the third isolation layer located outside the first trench form an interlayer isolation layer; A phase change material layer is formed on the surface of the second dielectric layer to fill the second trench. The excess phase change material layer outside the second trench is removed by planarization to expose the surface of the protective layer and the phase change material layer, and a phase change unit is formed in the second trench. A second electrode material layer is formed on the surface of the second dielectric layer to cover the protective layer and the phase change unit body; The second electrode material layer and the phase change unit body are patterned, and a phase change unit connected to the first electrode by a side is formed in the second trench, and a second electrode is located on the top surface of the phase change unit, thereby forming a phase change memory unit; A third dielectric layer with a planarized surface is formed on the surface of the second dielectric layer to cover the phase change memory cell; A metal interconnect is formed on the surface of the third dielectric layer, with its bottom end connected to the top surface of the second electrode.

[0015] Furthermore, the thickness of the first electrode material layer is greater than zero and less than or equal to 50 angstroms; and / or, the second electrode material comprises tantalum nitride.

[0016] As can be seen from the above technical solution, the present invention, by protruding a first electrical connection structure (contact hole) on the surface of the substrate, allows the two ends of the first electrode of the phase-change memory cell suspended on the substrate surface to be connected transversely between the top of the first electrical connection structure and the side of the phase-change cell. This allows the phase-change cell to be located on one side of the horizontal plane where the first electrode is located, enabling the first electrode to be formed as a blade electrode laterally distributed on the substrate for lateral heating of the phase-change cell. This utilizes the lateral space of the chip, transforming the traditional interlayer vertical device into a planar device operating laterally within the layer. Therefore, it reduces the vertical occupancy height of the memory device and ensures that the chip area after embedding the memory device is consistent with the normal chip without embedding, thus minimizing the impact of the embedding process on the chip. Furthermore, directly connecting the second electrode of the phase-change memory cell to the metal interconnect (second electrical connection structure) eliminates the need for redundant intermediate layers, saving process steps, reducing the difficulty of connecting memory devices, and making it easier to be compatible with circuits. It also allows for further miniaturization and densification of the device, providing new technical support for embedding memory devices in process platforms, enabling the memory device to be expanded and extended in the process. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a storage device according to a preferred embodiment of the present invention.

[0018] Figures 2-13 This is a schematic diagram of the manufacturing process steps of a preferred embodiment of the present invention for a storage device.

[0019] Figure 14 This is a schematic diagram comparing the structure of the phase-change memory cell of the present invention with that of a conventional phase-change memory cell. In the figure, (a) is the same as... Figure 1 The corresponding phase change memory cell of the present invention, (b) is a conventional phase change memory cell. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, but does not exclude other elements or objects.

[0021] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0022] refer to Figure 1 A memory device according to the present invention includes a first electrical connection structure 11 and a phase change memory cell 12 disposed on a substrate 10.

[0023] The first electrical connection structure 11 protrudes from the horizontal surface of the substrate 10 in a direction away from the substrate 10. The phase-change memory cell 12 is suspended on the surface of the substrate 10. The phase-change memory cell 12 includes a first electrode 13, a phase-change cell 14, and a second electrode 15 connected in sequence. The first electrode 13 spans between the top of the first electrical connection structure 11 and the phase-change cell 14. The bottom plane of one end of the first electrode 13 is connected to the top of the first electrical connection structure 11, and the end face of the other end of the first electrode 13 is connected to the side of the phase-change cell 14. The phase-change cell 14 is located on one side of the horizontal plane where the first electrode 13 is located. The second electrode 15 is located on the top surface of the phase-change cell 14. This forms a planar device operating laterally on the substrate 10, reducing the vertical occupancy of the memory device and providing new technical support for embedding memory devices in the process platform. This allows the memory device to be expanded and extended in the process, while also facilitating further miniaturization and densification of the device.

[0024] In some embodiments, the first electrical connection structure 11 includes a contact hole. The contact hole may be, for example, a tungsten contact hole, and the filling material in the contact hole includes a Ti / TiN material disposed on the inner wall of the contact hole and a tungsten material filling the contact hole within the Ti / TiN material. However, it is not limited to this.

[0025] In some embodiments, the first electrode 13 is a heating electrode.

[0026] Furthermore, the first electrode 13 forms a blade electrode for lateral heating of the phase change unit 14.

[0027] In some embodiments, the thickness of the first electrode 13 in the vertical direction is greater than zero and less than or equal to 50 angstroms.

[0028] In some embodiments, the material of the first electrode 13 includes TiN. However, it is not limited to this.

[0029] In some embodiments, the phase change material of the phase change unit 14 includes GST (Ge2Sb2Te5). However, it is not limited to this.

[0030] In some embodiments, the distance between the bottom surface of the phase change unit 14 and the surface of the substrate 10 is less than the distance between the top surface of the first electrical connection structure 11 and the surface of the substrate 10. By utilizing the lateral space of the chip itself, memory devices are embedded in the gaps, ensuring consistency between the chip region with embedded memory devices and the chip region without embedded memory devices, thereby minimizing the impact of the embedding process on the chip. Furthermore, this structure allows for the application of small-scale embedding processes within a process platform.

[0031] In some embodiments, the first electrode 13 is disposed in a direction parallel to the surface of the substrate 10. A first end (shown as the left end in the figure) of the first electrode 13 is connected to the top end of the first electrical connection structure 11, and a second end of the first electrode 13 extends outward from the top end of the first electrical connection structure 11 until it connects to the side surface of the phase change unit 14. Furthermore, after extending laterally from the top end of the first electrical connection structure 11, the first electrode 13 first bends along the side surface of the first electrical connection structure 11 towards the substrate 10, and then extends in a direction parallel to the surface of the substrate 10 to connect to the side surface of the phase change unit 14. In this way, the first electrode 13 is horizontally connected to the side surface of the phase change unit 14 in a horizontal direction parallel to the surface of the substrate 10, and is perpendicular to the side surface of the phase change unit 14. The structure of the first electrode 13 described above can, on the one hand, adapt well to the recessed design of the phase change unit 14, ensuring that the second end of the first electrode 13 is perpendicularly connected to the side of the phase change unit 14 to ensure the heating effect; on the other hand, it can enhance the firmness of the connection between the first end of the first electrode 13 and the top of the first electrical connection structure 11, reduce the contact resistance, and thus improve the electrical connection performance.

[0032] In some embodiments, a protective layer 17 is provided on the first electrode 13. The protective layer 17 effectively insulates and isolates the second electrode 15 located on the top surface of the phase change unit 14 from the first electrode 13 connected to the side surface of the phase change unit 14.

[0033] In some embodiments, the protective layer 17 is made of SiN. However, it is not limited to this.

[0034] It should be noted that the present invention does not limit the number of phase change memory units 12. In application, the number of phase change memory units 12 can be determined according to design requirements.

[0035] Figure 1 The diagram exemplarily illustrates a structure in which two phase-change memory cells 12 are provided on a substrate 10 along the X-direction. Furthermore, when the number of phase-change memory cells 12 is greater, each phase-change memory cell 12 can be arranged sequentially behind any one of the phase-change memory cells 12 in the diagram along the Y-direction (perpendicular to the plane of the diagram). Additionally, the phase-change memory cells 12 can be arranged in rows and columns on the substrate 10 to form an array.

[0036] refer to Figure 1 In some embodiments, the second electrode 15 is provided with a second electrical connection structure 16. The second electrical connection structure 16 is connected to the top surface of the second electrode 15 via its bottom end.

[0037] In some embodiments, the second electrical connection structure 16 includes metal interconnects. The metal interconnects may be, for example, the bottommost metal interconnect (M1) in a metal interconnect layer. This differs from conventional phase-change memory cells which require additional top contact vias (see reference). Figure 14 The structure that allows the metal interconnects of the metal interconnect layer to connect to the metal interconnect layer eliminates the need for an extra intermediate layer, thereby saving process steps, reducing the process difficulty of connecting memory devices, and making it easier to be compatible with circuits.

[0038] In some embodiments, the metal interconnects include copper metal interconnects.

[0039] In some embodiments, the second electrode 15 is made of TaN. The phase-change memory cell 12 is brought out by directly connecting the TaN second electrode 15 via copper metal interconnects.

[0040] refer to Figure 1 In some embodiments, a third electrical connection structure 20 is provided on the side of the first electrical connection structure 11 away from the phase change unit 14. The third electrical connection structure 20 may be arranged in the same direction as the first electrical connection structure 11, each third electrical connection structure 20 corresponds to one first electrical connection structure 11, and is respectively connected to a gate tube (not shown) disposed on the substrate 10.

[0041] In some embodiments, a fourth electrical connection structure 19 is connected to the top of the third electrical connection structure 20.

[0042] In some embodiments, the third electrical connection structure 20 includes a contact hole; the fourth electrical connection structure 19 includes a metal interconnect. For ease of distinction, the contact hole serving as the first electrical connection structure 11 will be referred to as the first contact hole 111, the contact hole serving as the third electrical connection structure 20 will be referred to as the second contact hole 201; the metal interconnect serving as the second electrical connection structure 16 will be referred to as the first metal interconnect 161, and the metal interconnect serving as the fourth electrical connection structure 19 will be referred to as the second metal interconnect 191. The first contact hole 111 and the second contact hole 201 are located at a contact hole layer on the substrate 10. The second contact hole 201 is directly connected to the metal interconnect layer through the lowest layer, the second metal interconnect 191.

[0043] The space between the second contact holes 201 on both sides serves as a storage area, and the storage device is embedded in the storage area between the contact hole layer and the metal interconnect layer to form an embedded storage device.

[0044] In some embodiments, a dielectric layer 21 is provided on the surface of the substrate 10, and a first electrical connection structure 11, a phase change storage unit 12, a second electrical connection structure 16, a third electrical connection structure 20 and a fourth electrical connection structure 19 are disposed in the dielectric layer 21.

[0045] In some embodiments, an interlayer isolation layer 18 is provided in the dielectric layer 21. The interlayer isolation layer 18 is located above the contact hole layer and is disconnected in the storage area. That is, the interlayer isolation layer 18 is provided on the second contact hole 201, but not on the first contact hole 111. The second contact hole 201 is directly connected to the upper metal interconnect layer through a second metal interconnect 191 passing through the interlayer isolation layer 18.

[0046] In some embodiments, the interlayer isolation layer 18 and the protective layer 17 are connected at the outer side of the top of the first electrical connection structure 11 (on the side near the third electrical connection structure 20), surrounding the first end of the first electrode 13.

[0047] In some embodiments, an extension 131 is provided on the first end of the first electrode 13. The extension 131 is located in the protective layer 17 and extends upward along the interface between the protective layer 17 and the interlayer isolation layer 18, that is, in a direction perpendicular to the surface of the substrate 10. Since the first electrode 13 is extremely thin, by providing the extension 131, the first end of the first electrode 13 can be simultaneously connected to the first electrical connection structure 11, the protective layer 17 and the interlayer isolation layer 18, which can further improve the structural stability of the first electrode 13.

[0048] In some embodiments, the interlayer isolation layer 18 is made of SiN or NDC. However, it is not limited to this.

[0049] refer to Figure 14 .like Figure 14As shown in (b), a conventional phase-change memory includes a bottom contact hole 102, a bottom electrode (blade electrode) 103, a phase-change unit (including a phase-change material layer 104 and a protective layer 105) disposed longitudinally on the surface of a substrate 101, and a top electrode (top contact hole) 106. The top electrode 106 is then connected to the metal interconnects of the metal interconnect layer. Because the conventional blade electrode 103 is disposed longitudinally, it occupies a large longitudinal space, which increases the difficulty of device embedding.

[0050] like Figure 14 As shown in (a), the memory device of the present invention uses a first electrode 13 laterally disposed on the first contact hole 111 to form a laterally disposed blade electrode. This allows the memory device to be embedded in the gap between the second contact holes 201 using the lateral space of the chip itself, thus significantly saving space occupied in the vertical direction. Furthermore, the present invention uses TaN material as the material for the second electrode 15 on the top surface of the phase change unit 14, and directly connects it through a copper metal interconnect (first metal interconnect 161) to form a path. Compared with conventional methods, this avoids the technological difficulties associated with using top contact holes for connection, and also makes it easier to achieve circuit compatibility.

[0051] The following detailed description, in conjunction with specific embodiments and accompanying drawings, provides a further detailed explanation of a method for manufacturing a storage device according to the present invention.

[0052] A method for manufacturing a storage device according to the present invention includes: A first electrical connection structure is formed protruding from the horizontal surface of the substrate; A phase change memory cell is formed suspended on the surface of a substrate. The phase change memory cell includes a first electrode, a phase change unit, and a second electrode connected in sequence. The two ends of the first electrode span between the top of the first electrical connection structure and the phase change unit. The bottom plane of one end of the first electrode is connected to the top of the first electrical connection structure, and the end face of the other end of the first electrode is connected to the side of the phase change unit. The phase change unit is located on one side of the horizontal plane where the first electrode is located, and the second electrode is located on the top surface of the phase change unit.

[0053] Furthermore, it also includes: forming a second electrical connection structure, the second electrical connection structure being disposed on the top surface of the second electrode.

[0054] refer to Figures 2-13 To make, for example Figure 1 Taking a storage device as an example, the method for manufacturing the storage device of the present invention specifically includes the following steps: Step S1: Form a first dielectric layer 211 on the surface of substrate 10.

[0055] This invention can embed a storage device between the contact hole layer and the bottom metal interconnect layer (M1) based on the design rules of the contact hole layer and the bottom metal interconnect layer under standard process.

[0056] First, the front-end process and contact hole process on substrate 10 need to be completed.

[0057] like Figure 2 As shown, a first dielectric layer 211 with a flat surface is formed on the surface of the substrate 10 using a deposition process.

[0058] The substrate 10 may be, for example, a silicon substrate. The material of the first dielectric layer 211 may be, for example, silicon dioxide (the same applies to the dielectric layer materials below).

[0059] Step S2: A first contact hole 111 with its bottom end connected to the substrate 10 is formed on the surface of the first dielectric layer 211 as a first electrical connection structure 11.

[0060] like Figure 2 As shown, a contact hole process, including photolithography, etching and metal deposition processes, is used to form four contact holes with their bottom ends connected to the substrate 10 along the X direction on the surface of the first dielectric layer 211 (behind these four contact holes, i.e. along the Y direction, more contact holes can be formed and formed into an array). Figures 3-13 The X and Y directions in Figure 2 The X and Y directions are consistent (the X and Y direction markings are omitted in subsequent figures), including two second contact holes 201 located on the outermost sides as the third electrical connection structure 20, and a first contact hole 111 located between the two second contact holes 201 as the first electrical connection structure 11. The space between the two second contact holes 201 serves as a storage area for the embedding of storage devices. The first contact hole 111 is used to place the phase-change memory cell 12.

[0061] In this embodiment, a tungsten first contact hole 111 and a tungsten second contact hole 201 are formed.

[0062] Step S3: Form a first isolation layer on the surface of the first dielectric layer 211 to cover the first contact hole 111.

[0063] like Figure 2 As shown, a first isolation layer 181 is formed on the surface of the first dielectric layer 211 using a deposition process, covering the first contact hole 111 and the second contact hole 201.

[0064] The first isolation layer 181 can be made of standard contact hole interlayer isolation material. The first isolation layer 181 material can be SiN or NDC. In this embodiment, the first isolation layer 181 material is SiN, and the thickness of the SiN first isolation layer 181 is, for example, 300 angstroms.

[0065] Step S4: A first groove is formed on the surface of the first isolation layer 181, such that one side wall of the first groove is connected to the top side of the first contact hole 111, and the bottom surface of the first groove is lower than the top surface of the first contact hole 111, exposing the top surface of the first contact hole 111 and the surface of the first dielectric layer 211 located on the bottom surface of the first groove.

[0066] like Figure 3 As shown, a first trench 22 is formed on the surface of the first isolation layer 181 used for the storage area using photolithography and etching processes. In this embodiment, photolithography and etching are performed between the outer sides of the two first contact holes 111 where the phase change memory cell 12 is placed, opening the first isolation layer 181 and etching away about 100-300 angstroms of the material of the underlying first dielectric layer 211, so that the two sidewalls of the formed first trench 22 are connected to the outer sides of the top of the two first contact holes 111, and the bottom surface of the first trench 22 is lower than the top of the two first contact holes 111, exposing the top of the two first contact holes 111 and the surface of the first dielectric layer 211 located on the bottom surface of the first trench 22.

[0067] In the X-axis direction, the size of the first trench 22 formed by photolithography can be the sum of the sizes of two phase change units 14, the sizes of two first electrodes 13, and the spacing between the two phase change units 14. In this embodiment, a first trench 22 with a relatively easy-to-implement size of 560nm is described. Each phase change unit 14 has a size of 130nm, each first electrode 13 has a size of 120nm, and the spacing between the two phase change units 14 is 60nm. Of course, if the space allowed for the first trench 22 is too small, the two phase change units 14 can be arranged in a staggered manner in the Y-axis direction to reduce the size occupied by the two phase change units 14 in the X-axis direction, but the two phase change units 14 still need to have a necessary spacing distance in the Y-axis direction.

[0068] Step S5: A first electrode material layer is formed on the surface of the first isolation layer 181, so that the first electrode material layer covers the top of the first contact hole 111 and the sidewalls and bottom surface of the first trench 22.

[0069] like Figure 4 As shown, a deposition process is used to deposit a TiN first electrode material layer 132 on the surface of the first isolation layer 181, and the first electrode material layer 132 covers the top of the first contact hole 111 and the sidewalls and bottom of the first trench 22. Since the phase change material changes resistance due to the heat generated by the electrical pulse signal on the high-resistivity first electrode 13 material, the contact area between the first electrode 13 material and the phase change material is an important performance factor of the memory device. Therefore, the film thickness of the TiN first electrode material layer 132 should not exceed 50 angstroms.

[0070] Step S6: A second isolation layer is formed on the surface of the first electrode material layer 132, and the first trench 22 inside the first electrode material layer 132 is filled.

[0071] like Figure 4 As shown, a deposition process is used to deposit, for example, a second isolation layer 182 of SiN on the surface of the first electrode material layer 132 to fill the first trench 22 within the first electrode material layer 132.

[0072] The thickness of the second isolation layer 182 not only needs to ensure the insulation performance of the first electrode material layer 132, but also needs to act as a hard mask for subsequent etching and planarization (e.g., chemical mechanical polishing, CMP) steps.

[0073] In some embodiments, the thickness of the second isolation layer 182 is 200 to 600 angstroms.

[0074] Step S7: Pattern the second isolation layer 182 and the first electrode material layer 132, forming a first electrode intermediate pattern connected to the top of the first contact hole 111 through the first end in the first trench 22, and a second isolation layer intermediate pattern located on the first electrode intermediate pattern, exposing the surface of the first isolation layer 181 outside the first trench 22, and exposing the second end of the first electrode intermediate pattern and the surface of the first dielectric layer 211 inside the first trench 22.

[0075] like Figure 5 As shown, photolithography and etching processes are used to pattern the SiN second isolation layer 182 and the TiN first electrode material layer 132. The second isolation layer 182 and the first electrode material layer 132 located outside the first trench 22 are removed, and a first electrode intermediate pattern 133 and a second isolation layer intermediate pattern 183 are formed within the first trench 22. The formed first electrode intermediate pattern 133 is connected to the top of the first contact hole 111 at its first end, and its second end is suspended. The second isolation layer intermediate pattern 183 is located on the first electrode intermediate pattern 133, protecting it. During etching, the first electrode material layer 132 needs to be etched through, exposing the surface of the first isolation layer 181 outside the first trench 22, as well as the side surface of the first electrode intermediate pattern 133 (including its second end) and the surface of the first dielectric layer 211 within the first trench 22.

[0076] The resulting intermediate pattern 133 of the two first electrodes is a strip horizontally arranged along the X direction. Its length in the X direction is slightly longer than the final length of the first electrode 13 to be formed in the X direction. Other features, such as its width in the Y direction, its bend shape, and the structural features of the extension 131 at the first end, are consistent with... Figure 1The final shape of the first electrode 13 shown is consistent.

[0077] In some embodiments, the length of the middle pattern 133 of the first electrode in the X direction is 90~150nm, and the width in the Y direction is 60~120nm.

[0078] Step S8: A third isolation layer is formed on the surface of the first isolation layer 181, covering the intermediate pattern 183 of the second isolation layer, the intermediate pattern 133 of the first electrode, and the surface of the exposed first dielectric layer 211.

[0079] like Figure 6 As shown, a deposition process is used to form, for example, a third SiN isolation layer 184 on the surface of the first isolation layer 181, which covers and wraps the exposed surfaces of the intermediate pattern 183 of the second isolation layer and the intermediate pattern 133 of the first electrode, and also covers the surface of the first dielectric layer 211 exposed on the bottom surface of the first trench 22.

[0080] Since the thickness of the first SiN isolation layer 181 will be thinner after the previous etching step, this step requires depositing a third SiN isolation layer 184 on the first isolation layer 181 to ensure that the total thickness of the first isolation layer 181 and the third isolation layer 184 outside the first trench 22 is not less than the thickness of the standard interlayer isolation layer between the contact hole layer and the bottommost metal interconnect layer (M1). At the same time, the exposed side surface of the middle pattern 133 of the first electrode is covered to form protection.

[0081] In some embodiments, the thickness of the third isolation layer 184 is 100 to 300 angstroms.

[0082] Step S9: Form a second dielectric layer with a planarized surface on the surface of the third isolation layer 184.

[0083] like Figure 6 As shown, a deposition process is then used to deposit a second dielectric layer 212 on the surface of the third isolation layer 184. The second dielectric layer 212 serves as a buffer layer, and its deposition thickness is 500-800 angstroms.

[0084] Then, the surface of the second dielectric layer 212 is planarized by, for example, CMP, to eliminate the step difference caused by the previous etching and deposition process, forming a flat second dielectric layer 212, thereby preparing for subsequent processes.

[0085] The remaining thickness of the second dielectric layer 212 after CMP can be, for example, around 400 angstroms, and it can be used as a buffer layer.

[0086] Step S10: A second trench with its bottom located in the first dielectric layer 211 is formed on the surface of the second dielectric layer 212 within the first trench 22, and the second end of the first electrode intermediate pattern 133 is exposed on the sidewall of the second trench, thereby forming the first electrode 13; wherein, the second isolation layer intermediate pattern 183 and the third isolation layer 184 located within the first trench 22 form a protective layer 17, and the first isolation layer 181 and the third isolation layer 184 located outside the first trench 22 form an interlayer isolation layer 18.

[0087] like Figure 7 As shown, a second trench 23 with its bottom located in the first dielectric layer 211 is formed on the surface of the second dielectric layer 212 within the first trench 22 using photolithography and etching processes. The second trench 23 is located between the two intermediate patterns 133 of the first electrodes, but the width of the second trench 23 in the X-direction is greater than the distance between the second ends of the two intermediate patterns 133 of the first electrodes, thereby creating a longitudinal cut at the second ends of the two intermediate patterns 133 of the first electrodes, appropriately shortening the length of each intermediate pattern 133 to meet the length design requirements of the blade electrode.

[0088] After the second groove 23 is formed, the second end of the middle pattern 133 of the first electrode is exposed on the side wall of the second groove 23, thereby forming two first electrodes 13 on the left and right.

[0089] For example, this step etches a second trench 23 with a width of approximately 320 nm, controlling the length of the first electrode 13, which serves as the blade electrode, to be approximately 80-120 nm. Compared to the length of the central pattern 133 of the first electrode, the width of the first electrode 13 formed in this step remains unchanged along the Y direction, only its length along the X direction is reduced slightly. This ensures that the first electrode 13 is completely surrounded by dielectric isolation material. The subsequently deposited phase change material is also completely isolated from electrode materials in other directions and from the underlying tungsten contact hole material due to the isolation effect of the second dielectric layer 212, which acts as a buffer layer. Simultaneously, the depth of the second trench 23 determines the space between the phase change material embedded in the contact hole layer and the bottommost metal interconnect layer, thus affecting the device height.

[0090] In some embodiments, the depth of the second trench 23 is controlled within the range of 500 to 1000 angstroms.

[0091] At this time, the intermediate pattern 183 of the second isolation layer and the third isolation layer 184 located in the first trench 22 together form the protective layer 17; the first isolation layer 181 and the third isolation layer 184 located outside the first trench 22 together form the interlayer isolation layer 18.

[0092] Step S11: A phase change material layer is formed on the surface of the second dielectric layer 212 to fill the second trench 23. The excess phase change material layer outside the second trench 23 is removed by planarization to expose the protective layer 17 and the surface of the phase change material layer, and a phase change unit is formed in the second trench 23.

[0093] like Figure 8 As shown, a phase change material layer 141 is formed on the surface of the second dielectric layer 212 using a deposition process, and the second trench 23 is filled. The deposition thickness of the second dielectric layer 212 can be, for example, 500 to 1000 angstroms.

[0094] Subsequently, CMP planarization is performed to remove excess phase change material layer 141 outside the second trench 23, exposing the surface of the protective layer 17 and phase change material layer 141 located in the region of the first trench 22, and a phase change unit cell 142 is formed in the second trench 23, as shown below. Figure 9 As shown. The thickness of the remaining second dielectric layer 212 after CMP is approximately 100~200 angstroms.

[0095] Step S12: A second electrode material layer is formed on the surface of the second dielectric layer 212, covering the protective layer 17 and the phase change unit 142.

[0096] like Figure 10 As shown, a TaN second electrode material layer 151 is formed on the surface of the second dielectric layer 212 using a deposition process, covering the protective layer 17 and the phase change unit 142. The deposition thickness of the second electrode material layer 151 is 100~200 angstroms.

[0097] Step S13: Pattern the second electrode material layer 151 and the phase change unit body 142, and form a phase change unit 14 connected to the first electrode 13 by its side in the second trench 23, and a second electrode 15 located on the top surface of the phase change unit 14, thereby forming a phase change storage unit 12.

[0098] like Figure 11 As shown, a two-step photolithography and etching process is used to form the second electrode 15 and the phase change unit 14. In the first step of the photolithography and etching process, the second electrode material layer 151 outside the second trench 23 is removed, leaving only the second electrode material layer 151 located on the top surface of the phase change unit body 142.

[0099] Then, through a second photolithography and etching process, the phase change unit 142 and the second electrode material layer 151 on its top surface are patterned. The phase change unit 142 and the second electrode material layer 151 on its top surface are separated from the middle in the X-direction, forming two independent phase change units 14 and their TaN second electrodes 15 on their top surfaces in the second trench 23. The spacing between the two phase change units 14 is approximately 40-60 nm. The phase change units 14 are connected to the second end of the first electrode 13 via their side surfaces. This forms two phase change memory units 12 with a horizontally arranged first electrode 13 and phase change units 14. If the space of the first groove 22 is too small, causing the width of the second groove 23 in the X direction to decrease accordingly, so that the phase change unit body 142 is insufficient to form two parallel phase change units 14 in the X direction, then the two phase change units 14 on the left and right can be arranged in a staggered manner (interdigitated) in the Y direction to reduce the size occupied by the two phase change units 14 in the X direction. However, the two phase change units 14 on the left and right still need to have a necessary spacing distance in the Y direction.

[0100] Step S14: A third dielectric layer with a planarized surface is formed on the surface of the second dielectric layer 212 to cover the phase change memory cell 12.

[0101] like Figure 12 As shown, a third dielectric layer 213 (IMD film) is formed on the surface of the second dielectric layer 212 using a deposition process and following the standard operating procedure for the bottommost metal interconnect layer, covering the phase change memory cell 12. The surface of the third dielectric layer 213 is then planarized using CMP.

[0102] Step S15: A first metal interconnect 161 is formed on the surface of the third dielectric layer 213, with its bottom end connected to the top surface of the second electrode 15, as the second electrical connection structure 16.

[0103] like Figure 13 As shown, using the standard manufacturing process for the bottom layer of metal interconnects, a first metal interconnect 161 is formed on the surface of the third dielectric layer 213, with its bottom end connected to the top surface of the second electrode 15. The first metal interconnect 161 serves as the second electrical connection structure 16. A second metal interconnect 191 is also formed at the top of the second contact hole 201, serving as the fourth electrical connection structure 19. This ultimately forms the conductive lead for the embedded memory device.

[0104] In some embodiments, the first metal interconnect 161 and the second metal interconnect 191 are made of copper.

[0105] The first dielectric layer 211, the second dielectric layer 212, and the third dielectric layer 213 described above together form dielectric layer 21. This completes the process of... Figure 1The manufacturing process of the storage device shown.

[0106] As can be seen, the present invention only adds some steps to the normal standard manufacturing process without changing the morphology and structure of the device without embedded memory device regions, achieving a solution with the lowest design cost and simple process, enabling the device to be further miniaturized and densified, and enabling small-scale embedding processes to be applied in process platforms.

[0107] In summary, this invention, by protruding a first electrical connection structure (contact hole) on the surface of the substrate, allows the two ends of the first electrode of the phase-change memory cell suspended on the substrate surface to be connected transversely between the top of the first electrical connection structure and the side of the phase-change cell. This places the phase-change cell on one side of the horizontal plane where the first electrode is located, enabling the first electrode to be formed as a blade electrode laterally distributed on the substrate for lateral heating of the phase-change cell. This utilizes the lateral space of the chip, transforming traditional interlayer vertical devices into planar devices operating laterally within a layer. Therefore, it reduces the vertical occupancy of the memory device and ensures that the chip area after embedding the memory device is consistent with the normal chip without embedding, thus minimizing the impact of the embedding process on the chip. Furthermore, directly connecting the second electrode of the phase-change memory cell to the metal interconnect (second electrical connection structure) eliminates the need for redundant intermediate layers, saving process steps, reducing the difficulty of interconnecting the memory device, facilitating circuit compatibility, and enabling further miniaturization and densification of the device. This provides new technical support for embedding memory devices in process platforms, allowing the memory device to be expanded and extended in the process.

[0108] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as set forth in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.

Claims

1. A memory device, comprising: include: The first electrical connection structure is protruding and disposed on the horizontal surface of the substrate; A phase-change memory cell is suspended on the surface of the substrate. The phase-change memory cell includes a first electrode, a phase-change unit, and a second electrode connected in sequence. The two ends of the first electrode span between the top end of the first electrical connection structure and the phase-change unit. The bottom plane of one end of the first electrode is connected to the top end of the first electrical connection structure, and the end face of the other end of the first electrode is connected to the side of the phase-change unit. The phase-change unit is located on one side of the horizontal plane where the first electrode is located, and the second electrode is located on the top surface of the phase-change unit.

2. The storage device according to claim 1, characterized in that, It also includes a second electrical connection structure, which is disposed on the top surface of the second electrode.

3. The storage device according to claim 2, characterized in that, The first electrical connection structure includes a contact hole; and / or, the second electrical connection structure includes a metal interconnect and is directly connected to the top surface of the second electrode; and / or, a dielectric layer is provided on the surface of the substrate, and the first electrical connection structure, the phase change memory cell, and the second electrical connection structure are disposed in the dielectric layer.

4. The storage device according to claim 3, characterized in that, The second electrode material includes tantalum nitride.

5. The storage device according to claim 1, characterized in that, The first electrode forms a blade electrode for lateral heating of the phase change unit.

6. The storage device according to claim 1, characterized in that, The distance between the bottom surface of the phase change unit and the surface of the substrate is less than the distance between the top end of the first electrical connection structure and the surface of the substrate; and / or, the first electrode is arranged in a direction parallel to the surface of the substrate, and after the first electrode extends laterally from the top end of the first electrical connection structure, it first turns towards the substrate along the side of the first electrical connection structure, and then extends to the side of the phase change unit in a direction parallel to the surface of the substrate; and / or, the first electrode is provided with a protective layer.

7. A method for manufacturing a storage device, characterized in that, include: A first electrical connection structure is formed protruding from the horizontal surface of the substrate; A phase change memory cell is formed suspended on the surface of the substrate. The phase change memory cell includes a first electrode, a phase change unit, and a second electrode connected in sequence. The two ends of the first electrode span between the top end of the first electrical connection structure and the phase change unit. The bottom plane of one end of the first electrode is connected to the top end of the first electrical connection structure, and the end face of the other end of the first electrode is connected to the side of the phase change unit. The phase change unit is located on one side of the horizontal plane where the first electrode is located, and the second electrode is located on the top surface of the phase change unit.

8. The method for manufacturing a storage device according to claim 7, characterized in that, Also includes: A second electrical connection structure is formed, which is disposed on the top surface of the second electrode.

9. The method for manufacturing a storage device according to claim 8, characterized in that, Forming the first electrical connection structure, the phase-change memory unit, and the second electrical connection structure specifically includes: A first dielectric layer is formed on the surface of the substrate; A contact hole is formed on the surface of the first dielectric layer, with its bottom end connected to the substrate, as a first electrical connection structure; A first isolation layer is formed on the surface of the first dielectric layer to cover the contact hole; A first groove is formed on the surface of the first isolation layer, such that one sidewall of the first groove is connected to the top side of the contact hole, and the bottom surface of the first groove is lower than the top of the contact hole, exposing the top of the contact hole and the surface of the first dielectric layer located on the bottom surface of the first groove. A first electrode material layer is formed on the surface of the first isolation layer, such that the first electrode material layer covers the top of the contact hole and the sidewalls and bottom surface of the first trench; A second isolation layer is formed on the surface of the first electrode material layer, and the first trench within the first electrode material layer is filled; The second isolation layer and the first electrode material layer are patterned to form a first electrode intermediate pattern connected to the top of the contact hole through a first end in the first trench, and a second isolation layer intermediate pattern located on the first electrode intermediate pattern, exposing the surface of the first isolation layer outside the first trench, and exposing the second end of the first electrode intermediate pattern and the surface of the first dielectric layer inside the first trench. A third isolation layer is formed on the surface of the first isolation layer, covering the middle pattern of the second isolation layer, the middle pattern of the first electrode, and the exposed surface of the first dielectric layer; A second dielectric layer with a planarized surface is formed on the surface of the third isolation layer; A second trench with its bottom located in the first dielectric layer is formed on the surface of the second dielectric layer within the first trench, and the second end of the middle pattern of the first electrode is exposed on the sidewall of the second trench, thereby forming a first electrode; wherein, the middle pattern of the second isolation layer located within the first trench and the third isolation layer form a protective layer, and the first isolation layer and the third isolation layer located outside the first trench form an interlayer isolation layer; A phase change material layer is formed on the surface of the second dielectric layer to fill the second trench. The excess phase change material layer outside the second trench is removed by planarization to expose the surface of the protective layer and the phase change material layer, and a phase change unit is formed in the second trench. A second electrode material layer is formed on the surface of the second dielectric layer to cover the protective layer and the phase change unit body; The second electrode material layer and the phase change unit body are patterned, and a phase change unit connected to the first electrode by a side is formed in the second trench, and a second electrode is located on the top surface of the phase change unit, thereby forming a phase change memory unit; A third dielectric layer with a planarized surface is formed on the surface of the second dielectric layer to cover the phase change memory cell; A metal interconnect is formed on the surface of the third dielectric layer, with its bottom end connected to the top surface of the second electrode.

10. The method for manufacturing a storage device according to claim 9, characterized in that, The thickness of the first electrode material layer is greater than zero and less than or equal to 50 angstroms; and / or, the second electrode material comprises tantalum nitride.

Images