Semiconductor device

Abstract

Embodiments of the present application relate to a semiconductor device. The semiconductor device of the embodiments includes a transistor region and a diode region. Further, the semiconductor device includes a semiconductor layer including a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type between the first semiconductor region and a first surface, a third semiconductor region of the second conductivity type having a lower impurity concentration than the second semiconductor region between the second semiconductor region and the first surface, and a sixth semiconductor region of the second conductivity type having a higher impurity concentration than the second semiconductor region between the second semiconductor region and a second surface. The second semiconductor region includes a first region between the sixth semiconductor region and the third semiconductor region and a second region between the first semiconductor region and the third semiconductor region. The impurity concentration of the first region is 80% or more and 120% or less of the second region. The carrier concentration of the first region is lower than that of the second region.

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2024-209871 (filed on December 3, 2024). This application incorporates all the contents of the basic application by reference to that basic application. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device. Background Technology

[0004] An example of a semiconductor device used in power applications is the Insulated Gate Bipolar Transistor (IGBT). An IGBT, for example, has a p-type collector region, an n-type drift region, and a p-type base region on its collector electrode. Furthermore, a gate electrode is formed by sandwiching a gate insulating film within a trench that extends through the p-type base region and reaches the n-type drift region. Finally, an n-type emitter region, connected to the emitter electrode, is formed on the surface of the p-type base region adjacent to the trench.

[0005] In recent years, reverse-conducting IGBTs (RC-IGBTs), which integrate IGBTs and freewheeling diodes onto the same semiconductor chip, have been widely developed and commercialized. RC-IGBTs are used, for example, as switching elements in inverter circuits. The freewheeling diode allows current to flow in the opposite direction to the IGBT's on-state current. Integrating the IGBT and freewheeling diode onto the same semiconductor chip offers many advantages, including simplified assembly and dispersion of heat-generating components. Summary of the Invention

[0006] A semiconductor device embodiment includes a transistor region and a diode region. The transistor region comprises: a semiconductor layer having a first surface and a second surface opposite to the first surface; the semiconductor layer comprising: a first semiconductor region of a first conductivity type, disposed between the first semiconductor region and the first surface; a third semiconductor region of a second conductivity type, disposed between the second semiconductor region and the first surface, the third semiconductor region having a lower second conductivity type impurity concentration than the second semiconductor region; a fourth semiconductor region of a first conductivity type, disposed between the third semiconductor region and the first surface; and a fifth semiconductor region of a second conductivity type, disposed between the fourth semiconductor region and the first surface, and disposed between the fourth semiconductor region and the first surface; a gate electrode opposite to the fourth semiconductor region; a gate insulating film disposed between the gate electrode and the fourth semiconductor region; a first electrode disposed between the fifth semiconductor region; and a second electrode disposed between the first semiconductor region. The diode... The region includes: the semiconductor layer, which includes: the second semiconductor region; the third semiconductor region; the sixth semiconductor region of the second conductivity type, disposed between the second semiconductor region and the second surface, and connected to the second surface, wherein the second conductivity type impurity concentration of the sixth semiconductor region is higher than that of the second semiconductor region; and the seventh semiconductor region of the first conductivity type, disposed between the third semiconductor region and the first surface, and connected to the first surface; the first electrode connected to the seventh semiconductor region; and the second electrode connected to the sixth semiconductor region. The second semiconductor region includes a first region and a second region, wherein the first region is disposed between the sixth semiconductor region and the third semiconductor region, and the second region is disposed between the first semiconductor region and the third semiconductor region, wherein the second conductivity type impurity concentration of the first region is 80% or more and 120% or less of the second conductivity type impurity concentration of the second region, and the carrier concentration of the first region is lower than that of the second region.

[0007] According to this embodiment, it is possible to provide a semiconductor device that includes an RC-IGBT having an IGBT and a diode and can improve its characteristics. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of the semiconductor device according to the first embodiment.

[0009] Figure 2 This is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment.

[0010] Figure 3This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0011] Figure 4 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0012] Figure 5 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0013] Figure 6 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0014] Figure 7 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0015] Figure 8 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0016] Figure 9 This is a schematic cross-sectional view of a part of the semiconductor device according to the second embodiment.

[0017] Figure 10 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment.

[0018] Figure 11 This is an explanatory diagram illustrating the function and effects of the semiconductor device according to the second embodiment.

[0019] Figure 12 This is an explanatory diagram illustrating the function and effects of the semiconductor device according to the second embodiment.

[0020] Figure 13 This is a schematic cross-sectional view of a semiconductor device in a second variation of the second embodiment.

[0021] Figure 14 This is a schematic cross-sectional view of a part of the semiconductor device according to the third embodiment.

[0022] Figure 15 This is a schematic cross-sectional view of a portion of a semiconductor device according to a variation of the third embodiment.

[0023] Explanation of reference numerals in the attached figures

[0024] 10 semiconductor layers

[0025] 12. Upper electrode (first electrode)

[0026] 14. Lower electrode (second electrode)

[0027] The collector region (first semiconductor region) of the 26p type.

[0028] The first buffer region (second semiconductor region) of the 28n type.

[0029] 28a First Region

[0030] 28b Second Region

[0031] 28c Third Region

[0032] 28c1 Part 1

[0033] 28c2 Part 2

[0034] The second buffer region (eighth semiconductor region) of the 29n type.

[0035] 30n - Type of drift region (third semiconductor region)

[0036] 32p base region (fourth semiconductor region)

[0037] 34n + Emitter region of type (fifth semiconductor region)

[0038] 36n + Type of contact area (sixth semiconductor region)

[0039] The anode region (seventh semiconductor region) of the 38p type.

[0040] 41 Gate insulating film

[0041] 51 gate electrode

[0042] 100RC-IGBT (Semiconductor Device)

[0043] 101 transistor region

[0044] 102 diode region

[0045] 200RC-IGBT (Semiconductor Device)

[0046] 210RC-IGBT (Semiconductor Device)

[0047] 300RC-IGBT (Semiconductor Device)

[0048] 310RC-IGBT (Semiconductor Device)

[0049] F1 First Side

[0050] F2 Second Side Detailed Implementation

[0051] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Furthermore, in the following description, the same or similar components will be labeled with the same reference numerals, and descriptions of components that have been described once will be appropriately omitted.

[0052] In this specification, when there is n + Type, n-type, n - In the case of the type expression, it means that the concentration of n-type impurities is according to n + Type, n-type, n - The order of the type decreases. Furthermore, in the presence of p... + Type, p type, p - In the case of p-type marking, it means that the concentration of p-type impurities is according to p + Type, p type, p - The order of the types decreases.

[0053] In this specification, the n-type impurity concentration does not represent the actual n-type impurity concentration, but rather the compensated effective n-type impurity concentration. Similarly, the p-type impurity concentration does not represent the actual p-type impurity concentration, but rather the compensated effective p-type impurity concentration. For example, if the actual n-type impurity concentration is greater than the actual p-type impurity concentration, the concentration obtained by subtracting the p-type impurity concentration from the actual n-type impurity concentration is set as the n-type impurity concentration. The same applies to the p-type impurity concentration.

[0054] In this specification, the concentrations of n-type and p-type impurities are not the concentrations of activated impurities, but rather the atomic concentrations of physically existing impurity atoms.

[0055] In this specification, carrier concentration refers to the concentration of activated impurities.

[0056] The distribution and absolute value of impurity concentration in semiconductor regions can be determined, for example, using secondary ion mass spectrometry (SIMS) or energy dispersive X-ray spectroscopy (EDX).

[0057] The relative magnitudes and absolute values ​​of carrier concentrations in semiconductor regions can be determined using methods such as Scanning Capacitance Microscopy (SCM) or Spreading Resistance Analysis (SRA).

[0058] For example, SCM can be used to evaluate the planar distribution of semiconductor regions. For example, SCM can be used to determine the depth of semiconductor regions and the distance between semiconductor regions.

[0059] Unless otherwise specified in the specification, the impurity concentration or carrier concentration of the semiconductor region shall be represented by the concentration near the center of the semiconductor region.

[0060] The relative magnitudes of crystal defect densities in semiconductor regions can be determined, for example, using transmission electron microscopy (TEM) or photoluminescence (PL).

[0061] (First Implementation)

[0062] The semiconductor device of the first embodiment includes a transistor region and a diode region. The transistor region includes: a semiconductor layer having a first surface and a second surface opposite to the first surface; the semiconductor layer including: a first semiconductor region of a first conductivity type, disposed between the first semiconductor region and the first surface; a second semiconductor region of a second conductivity type, disposed between the second semiconductor region and the first surface; a third semiconductor region of a second conductivity type, disposed between the second semiconductor region and the first surface, the second conductivity type impurity concentration of the third semiconductor region being lower than that of the second semiconductor region; a fourth semiconductor region of a first conductivity type, disposed between the third semiconductor region and the first surface; and a fifth semiconductor region of a second conductivity type, disposed between the fourth semiconductor region and the first surface, and disposed between the fourth semiconductor region and the first surface; a gate electrode opposite to the fourth semiconductor region; a gate insulating film disposed between the gate electrode and the fourth semiconductor region; a first electrode disposed between the fifth semiconductor region; and a second electrode disposed between the first semiconductor region. The diode region includes: a half-wave diode... A conductor layer, the semiconductor layer comprising: a second semiconductor region; a third semiconductor region; a sixth semiconductor region of a second conductivity type disposed between the second semiconductor region and a second surface, and connected to the second surface, wherein the impurity concentration of the second conductivity type in the sixth semiconductor region is higher than the impurity concentration of the second conductivity type in the second semiconductor region; and a seventh semiconductor region of a first conductivity type disposed between the third semiconductor region and a first surface, and connected to the first surface; a first electrode connected to the seventh semiconductor region; and a second electrode connected to the sixth semiconductor region, wherein the second semiconductor region comprises a first region and a second region, the first region being disposed between the sixth semiconductor region and the third semiconductor region, the second region being disposed between the first semiconductor region and the third semiconductor region, the impurity concentration of the second conductivity type in the first region being 80% or more and 120% or less of the impurity concentration of the second conductivity type in the second region, and the carrier concentration of the first region being lower than the carrier concentration of the second region.

[0063] The semiconductor device of the first embodiment is an RC-IGBT 100 in which an IGBT and a freewheeling diode are formed on the same semiconductor chip. The RC-IGBT 100 has a trench-gate type IGBT with a gate electrode formed in a trench in a semiconductor layer. Hereinafter, the case where the first conductivity type is p-type and the second conductivity type is n-type will be described as an example.

[0064] Figure 1 This is a schematic diagram of the semiconductor device according to the first embodiment.

[0065] like Figure 1 As shown, the RC-IGBT 100 has a transistor region 101, a diode region 102, and a terminal region 103. The transistor region 101 and the diode region 102 are alternately arranged in a first direction. The transistor region 101 and the diode region 102 extend in a second direction perpendicular to the first direction. The terminal region 103 surrounds the transistor region 101 and the diode region 102.

[0066] Transistor region 101 operates as an IGBT. Diode region 102 operates as a freewheeling diode. The freewheeling diode is, for example, a Fast Recovery Diode (FRD).

[0067] When the RC-IGBT 100 is in the off state, the end region 103 reduces the intensity of the electric field applied to the ends of the pn junctions in the transistor region 101 and the diode region 102. The end region 103 also improves the breakdown voltage characteristics of the RC-IGBT 100.

[0068] A gate electrode pad 104 is provided in the end region 103.

[0069] The RC-IGBT 100 of the first embodiment includes a semiconductor layer 10, an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a gate insulating film 41, a dummy gate insulating film 42, a gate electrode 51, a dummy gate electrode 52, an interlayer insulating layer 60, and a gate electrode pad 104. The dummy gate electrode 52 is connected to the emitter electrode, and no inversion layer is formed in the anode region 38 of the p-type.

[0070] Semiconductor layer 10 includes a gate trench 21, a dummy trench 22, a p-type collector region 26 (first semiconductor region), an n-type first buffer region 28 (second semiconductor region), and an n-type collector region 26 (first semiconductor region). - The drift region 30 of the p-type (third semiconductor region), the base region 32 of the p-type (fourth semiconductor region), and the n-type... + Emitter region 34 (fifth semiconductor region), n +The first buffer region 28 includes a first region 28a and a second region 28b. The first buffer region 28 comprises a contact region 36 (sixth semiconductor region) of type A and a contact region 38 (seventh semiconductor region) of type B.

[0071] The semiconductor layer 10 has a first surface F1 and a second surface F2 opposite to the first surface F1. The semiconductor layer 10 is, for example, monocrystalline silicon. The film thickness of the semiconductor layer 10 is, for example, 40 μm or more and 700 μm or less.

[0072] In this specification, a direction parallel to the first surface F1 is referred to as the first direction. Furthermore, a direction parallel to the first surface F1 and perpendicular to the first direction is referred to as the second direction. Additionally, the direction connecting the first surface F1 and the second surface F2 is referred to as the third direction.

[0073] Figure 2 This is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment. Figure 2 This is a schematic cross-sectional view of the boundary between diode region 102 and transistor region 101. Figure 2 yes Figure 1 AA' section.

[0074] The transistor region 101 includes a semiconductor layer 10, an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a gate insulating film 41, a gate electrode 51, and an interlayer insulating layer 60.

[0075] The semiconductor layer 10 of transistor region 101 includes a gate trench 21, a p-type collector region 26 (first semiconductor region), and an n-type collector region 26. - The drift region 30 of the p-type (third semiconductor region), the base region 32 of the p-type (fourth semiconductor region), and the n-type... + Emitter region 34 (fifth semiconductor region) of type.

[0076] The upper electrode 12 is disposed on the first surface F1 side of the semiconductor layer 10. At least a portion of the upper electrode 12 is in contact with the first surface F1 of the semiconductor layer 10.

[0077] The upper electrode 12 functions as the emitter electrode of the IGBT within the transistor region 101. The upper electrode 12 is, for example, metal.

[0078] The upper electrode 12 is connected to the emitter region 34. The upper electrode 12 is electrically connected to the emitter region 34.

[0079] The lower electrode 14 is disposed on the second surface F2 side of the semiconductor layer 10. The lower electrode 14 is in contact with the second surface F2 of the semiconductor layer 10.

[0080] The lower electrode 14 functions as the collector electrode of the IGBT in the transistor region 101. The lower electrode 14 is, for example, metal.

[0081] The lower electrode 14 is connected to the collector region 26 in the transistor region 101. The lower electrode 14 is electrically connected to the collector region 26 in the transistor region 101.

[0082] Collector region 26 is a p-type semiconductor region. Collector region 26 is connected to the second surface F2. Collector region 26 is electrically connected to the lower electrode 14. Collector region 26 is connected to the lower electrode 14. When the IGBT is in the on state, collector region 26 becomes a hole supply source.

[0083] The first buffer region 28 is an n-type semiconductor region. The first buffer region 28 is disposed between the collector region 26 and the first surface F1. The second region 28b of the first buffer region 28 is disposed between the collector region 26 and the first surface F1.

[0084] The first buffer region 28 has the function of suppressing the extension of the depletion layer extending from the first surface F1 side when the IGBT is in the off state, and maintaining the withstand voltage of the IGBT.

[0085] Drift region 30 is n - The first buffer region 28 is a type of semiconductor region. The drift region 30 is disposed between the first buffer region 28 and the first surface F1. The n-type impurity concentration of the drift region 30 is lower than that of the first buffer region 28.

[0086] The drift region 30 becomes the path for the conducting current when the IGBT is in the on state. The drift region 30 also has the function of depleting itself when the IGBT is in the off state, thus maintaining the IGBT's withstand voltage.

[0087] The base region 32 is a p-type semiconductor region. The base region 32 is disposed between the drift region 30 and the first surface F1.

[0088] In the base region 32 opposite to the gate electrode 51, an n-type inversion layer is formed when the IGBT is in the on state. The base region 32 functions as the channel region of the transistor.

[0089] Emitter region 34 is n + A semiconductor region of type 32. The emitter region 34 is disposed between the base region 32 and the first surface F1. The emitter region 34 is connected to the first surface F1.

[0090] The concentration of n-type impurities in emitter region 34 is higher than that in drift region 30.

[0091] The emitter region 34 is connected to the upper electrode 12. The emitter region 34 is electrically connected to the upper electrode 12. When the transistor is in the on state, the emitter region 34 becomes the source of electrons.

[0092] A gate trench 21 is disposed on the first surface F1 side of the semiconductor layer 10. The gate trench 21 is a trench disposed in the semiconductor layer 10. The gate trench 21 is a part of the semiconductor layer 10.

[0093] The gate electrode 51 is disposed in the gate trench 21. The gate electrode 51 is, for example, a semiconductor or a metal. The gate electrode 51 is, for example, amorphous silicon or polycrystalline silicon containing n-type impurities or p-type impurities.

[0094] The gate electrode 51 is electrically connected to the gate electrode pad 104.

[0095] A gate insulating film 41 is disposed between the gate electrode 51 and the semiconductor layer 10. The gate insulating film 41 is also disposed between the gate electrode 51 and the base region 32. The gate insulating film 41 is, for example, silicon oxide.

[0096] An interlayer insulating layer 60 is disposed between the gate electrode 51 and the upper electrode 12. The interlayer insulating layer 60 electrically separates the gate electrode 51 from the upper electrode 12. The interlayer insulating layer 60 is, for example, silicon oxide.

[0097] The diode region 102 includes a semiconductor layer 10, an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a virtual gate insulating film 42, a virtual gate electrode 52, and an interlayer insulating layer 60.

[0098] The semiconductor layer 10 of diode region 102 includes virtual trenches 22 and n + Contact region 36 (sixth semiconductor region) of type n, first buffer region 28 (second semiconductor region) of type n, n - The drift region 30 (third semiconductor region) of the p-type and the anode region 38 (seventh semiconductor region) of the p-type.

[0099] The upper electrode 12 functions as the anode electrode of the diode in the diode region 102. The upper electrode 12 is connected to the anode region 38.

[0100] The lower electrode 14 functions as the cathode electrode of the diode in the diode region 102. The lower electrode 14 is connected to the contact region 36.

[0101] Contact area 36 is n + A semiconductor region of type 36. Contact region 36 is in contact with the second surface F2. Contact region 36 becomes an electron supply source when the diode is in the conducting state. Contact region 36 is in contact with the lower electrode 14.

[0102] The first buffer region 28 is an n-type semiconductor region. The first buffer region 28 is disposed between the contact region 36 and the first surface F1. The first region 28a of the first buffer region 28 is disposed between the contact region 36 and the first surface F1.

[0103] Drift region 30 is n - A type of semiconductor region. The drift region 30 is disposed between the first buffer region 28 and the first surface F1.

[0104] The drift region 30 becomes the path for the conduction current when the diode is in the conducting state.

[0105] The anode region 38 is a p-type semiconductor region. The anode region 38 is disposed between the drift region 30 and the first surface F1.

[0106] The anode region 38 becomes a source of holes when the diode is in the on state.

[0107] The anode region 38 is connected to the upper electrode 12. The anode region 38 is electrically connected to the upper electrode 12.

[0108] A virtual trench 22 is disposed on the first surface F1 side of the semiconductor layer 10. The virtual trench 22 is a trench disposed in the semiconductor layer 10. The virtual trench 22 is a part of the semiconductor layer 10.

[0109] A virtual gate electrode 52 is disposed in a virtual trench 22. The virtual gate electrode 52 is, for example, a semiconductor or a metal. The virtual gate electrode 52 is, for example, amorphous silicon or polycrystalline silicon containing n-type or p-type impurities.

[0110] The virtual gate electrode 52 is electrically connected to the upper electrode 12, for example.

[0111] A virtual gate insulating film 42 is disposed between the virtual gate electrode 52 and the semiconductor layer 10.

[0112] The first buffer area 28 includes a first area 28a and a second area 28b.

[0113] The first region 28a is disposed between the contact region 36 and the drift region 30. The first region 28a is in contact with both the contact region 36 and the drift region 30. The first region 28a is disposed directly above the contact region 36. The first region 28a is disposed to the third direction above the contact region 36.

[0114] The second region 28b is disposed between the collector region 26 and the drift region 30. The second region 28b is connected to both the collector region 26 and the drift region 30. The second region 28b is disposed directly above the collector region 26. The second region 28b is disposed to a third direction from the collector region 26.

[0115] The concentration of n-type impurities in the first region 28a is 80% or more and 120% or less of the concentration of n-type impurities in the second region 28b. For example, the concentration of n-type impurities in the first region 28a is 90% or more and 110% or less of the concentration of n-type impurities in the second region 28b. For example, the concentration of n-type impurities in the first region 28a is substantially the same as the concentration of n-type impurities in the second region 28b.

[0116] The carrier concentration in the first region 28a is lower than that in the second region 28b. For example, the carrier concentration in the first region 28a is more than 1 / 1000 and less than 1 / 2 of the carrier concentration in the second region 28b.

[0117] The n-type impurity concentration and carrier concentration in the first region 28a are, for example, in... Figure 2 The position of the first point P1 in the diagram was determined. Additionally, the n-type impurity concentration and carrier concentration in the second region 28b, for example, are... Figure 2 The position of the second point P2 is determined. The distance from the second face F2 to the first point P1 in a third direction is equal to the distance from the second face F2 to the second point P2 in a third direction.

[0118] The first region 28a contains crystal defects. These crystal defects function as a lifetime killer. By enabling the crystal defects in the first region 28a to function as a lifetime killer, the switching characteristics of a freewheeling diode can be improved, for example.

[0119] The second region 28b may or may not contain crystal defects. The crystal defect density of the second region 28b is, for example, lower than that of the first region 28a. The crystal defect density of the first region 28a is, for example, higher than that of the second region 28b.

[0120] Next, an example of the method for manufacturing the semiconductor device according to the first embodiment will be described.

[0121] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. Figures 3-8 Is with Figure 2 The corresponding diagram.

[0122] First, in the case of n - On the first surface F1 side of the semiconductor layer 10 of the p-type drift region 30, a gate trench 21, a dummy trench 22, a p-type base region 32, and an n-type base region 32 are formed using known process techniques. +The structure includes a p-type emitter region 34, a p-type anode region 38, a gate insulating film 41, a dummy gate insulating film 42, a gate electrode 51, a dummy gate electrode 52, an interlayer insulating layer 60, and an upper electrode 12. Figure 3 ).

[0123] Next, the first ion implantation is performed. The first ion implantation uses ion implantation to implant n-type impurities into the semiconductor layer 10 from the second surface F2 side. Figure 4 The n-type impurity is, for example, phosphorus (P). The implantation of the n-type impurity forms a first n-type region 71. A portion of the first n-type region 71 eventually becomes a first buffer region 28. Crystal defects 71x, formed in conjunction with ion implantation, are formed in the first n-type region 71.

[0124] Next, a second ion implantation is performed. The second ion implantation uses ion implantation to implant p-type impurities into the semiconductor layer 10 from the second surface F2 side. Figure 5 The p-type impurity is, for example, boron (B). Through the implantation of the p-type impurity, a p-type region 72 is formed between the first n-type region 71 and the second surface F2. A portion of the p-type region 72 eventually becomes the collector region 26.

[0125] Next, a resist layer 61 is formed on a portion of the second surface F2. Then, a third ion implantation is performed. Using the resist layer 61 as a mask, the third ion implantation uses ion implantation to implant n-type impurities (n-type impurities) from the second surface F2 side into the semiconductor layer 10. Figure 6 The dose of the n-type impurity implanted in the third ion implantation is higher than the dose of the n-type impurity implanted in the first ion implantation. The n-type impurity is, for example, phosphorus (P). Through the implantation of the n-type impurity, a second n-type region 73 is formed. A portion of the second n-type region 73 eventually becomes the contact region 36. The second n-type region 73 becomes amorphous through high-dose ion implantation.

[0126] Next, the resist layer 61 is stripped. Then, infrared laser IR is irradiated onto the semiconductor layer 10 from the second surface F2 side. Figure 7 By using a longer wavelength infrared laser (IR), the laser can reach a position far from the second surface F2.

[0127] Irradiation with infrared laser IR activates the n-type impurities in the first n-type region 71 directly above the p-type region 72. Furthermore, crystal defects formed in the first n-type region 71 directly above the p-type region 72 during ion implantation are restored and disappear.

[0128] On the other hand, the activation of n-type impurities in the first n-type region 71 directly above the second n-type region 73 is suppressed. This suppresses the recovery and disappearance of crystal defects formed in the first n-type region 71 directly above the second n-type region 73. This is because infrared laser IR irradiating the second n-type region 73 is absorbed by the amorphous second n-type region 73, suppressing its reach to the first n-type region 71.

[0129] Next, green laser GR is irradiated into semiconductor layer 10 from the second surface F2 side. Figure 8 By using a green laser GR with a wavelength longer than that of infrared laser IR, the laser can be effectively directed to the vicinity of the second surface F2. The short wavelength of the green laser GR makes it difficult to reach locations far from the second surface F2.

[0130] Irradiation with green laser GR activates the p-type impurities in p-type region 72 and the n-type impurities in the second n-type region 73.

[0131] The above manufacturing methods can be used to manufacture... Figure 2 The RC-IGBT 100 of the first embodiment shown.

[0132] Next, the function and effects of the semiconductor device in the first embodiment will be explained.

[0133] In RC-IGBTs, lifetime control is sometimes implemented by introducing lifetime control factors to improve the switching characteristics of the freewheeling diode. On the other hand, if lifetime control is implemented, the leakage current increases at high temperatures, leading to thermal runaway of the RC-IGBT and potential damage.

[0134] In the RC-IGBT 100 of the first embodiment, a lifetime control factor is introduced only into the first buffer region 28 of the diode region 102. That is, the lifetime control factor is introduced only into the first buffer region 28, i.e., the first region 28a, of the diode region 102.

[0135] No lifetime control factor is introduced in the first buffer region 28 of transistor region 101. That is, no lifetime control factor is introduced in the first buffer region 28, i.e., the second region 28b, of transistor region 101.

[0136] Therefore, in transistor region 101, defects are significantly reduced compared to the first region 28a, so leakage current at high temperatures is not a problem. Thus, according to the RC-IGBT 100 of the first embodiment, thermal runaway at high temperatures is suppressed compared to a construction that introduces lifetime control factors into both the transistor region and the diode region.

[0137] In particular, as described above, the RC-IGBT 100 of the first embodiment uses infrared laser IR and green laser GR for impurity activation, enabling a lifetime control factor to be self-aligned only directly above the contact region 36 of the diode region 102. In other words, a lifetime control factor can be self-aligned at the boundary between the diode region 102 and the transistor region 101. According to the RC-IGBT 100 of the first embodiment, an RC-IGBT with suppressed thermal runaway at high temperatures can be manufactured using a simple process.

[0138] From the viewpoint of increasing crystal defect density and effectively controlling lifetime, the carrier concentration of the first region 28a is preferably less than 1 / 2 of the carrier concentration of the second region 28b, more preferably less than 1 / 5, and even more preferably less than 1 / 10.

[0139] According to the first embodiment, a semiconductor device comprising an RC-IGBT having an IGBT and a diode can be realized, and its characteristics can be improved by suppressing thermal runaway at high temperatures.

[0140] (Second Implementation)

[0141] The semiconductor device of the second embodiment differs from that of the semiconductor device of the first embodiment in that the second semiconductor region further includes a third region, which is connected to the second surface and is disposed between the sixth semiconductor region and the first semiconductor region. The carrier concentration in the first region is lower than that in the third region. Hereinafter, some descriptions that are repeated in the first embodiment will be omitted.

[0142] The semiconductor device in the second embodiment is an RC-IGBT 200 in which the IGBT and the freewheeling diode are formed on the same semiconductor chip.

[0143] Figure 9 This is a schematic cross-sectional view of a part of the semiconductor device according to the second embodiment. Figure 9 It is the same as the first embodiment. Figure 2 The corresponding diagram.

[0144] In addition to the first region 28a and the second region 28b, the first buffer region 28 of the RC-IGBT 200 also includes a third region 28c.

[0145] The third region 28c is located between the contact region 36 and the collector region 26. The third region 28c is connected to the second surface F2.

[0146] The concentration of n-type impurities in the first region 28a is 80% or more and 120% or less of the concentration of n-type impurities in the third region 28c. For example, the concentration of n-type impurities in the first region 28a is 90% or more and 110% or less of the concentration of n-type impurities in the third region 28c. For example, the concentration of n-type impurities in the first region 28a is substantially the same as the concentration of n-type impurities in the third region 28c.

[0147] The carrier concentration in the first region 28a is lower than that in the third region 28c. For example, the carrier concentration in the first region 28a is more than 1 / 1000 and less than 1 / 2 of the carrier concentration in the third region 28c. The carrier concentration in the third region 28c is higher than that in the first region 28a.

[0148] The n-type impurity concentration and carrier concentration in the third region 28c are, for example, in... Figure 9 The position of the third point P3 is determined. The distances from the second face F2 to the first point P1 in a third direction and from the second face F2 to the second point P2 in a third direction are equal to the distances from the second face F2 to the third point P3 in a third direction.

[0149] The third region 28c may or may not contain crystal defects. The crystal defect density of the third region 28c is, for example, lower than that of the first region 28a. The crystal defect density of the first region 28a is, for example, higher than that of the third region 28c.

[0150] The contact region 36 and the collector region 26 sandwich the third region 28c and are separated in the first direction. The distance in the first direction between the contact region 36 and the collector region 26 ( Figure 9 d1 in the figure is, for example, the third-direction distance between the collector region 26 and the drift region 30. Figure 9 The distance d1 between the contact region 36 and the collector region 26 in the first direction is, for example, less than 5 times the distance d2 between the collector region 26 and the drift region 30 in the third direction.

[0151] Figure 10 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment. Figure 10 The manufacturing method of the semiconductor device according to the first embodiment and Figure 5 The corresponding diagram.

[0152] For example, before the second ion implantation, a resist layer 61 is formed on a portion of the second surface F2. Using the resist layer 61 as a mask, the second ion implantation implants a p-type impurity into the semiconductor layer 10 from the second surface F2 side. The p-type impurity is, for example, boron (B). Through the implantation of the p-type impurity, a p-type region 72 is formed in a portion between the first n-type region 71 and the second surface F2. The p-type region 72 ultimately becomes the collector region 26.

[0153] Then, by performing the same manufacturing method as the semiconductor device manufacturing method of the first embodiment, it is possible to manufacture... Figure 9 The RC-IGBT 200 of the second embodiment shown.

[0154] Next, the function and effects of the semiconductor device in the second embodiment will be explained.

[0155] Figure 11 This is an explanatory diagram illustrating the function and effects of the semiconductor device according to the second embodiment. Figure 11 This is a diagram illustrating the subject matter of the semiconductor device according to the first embodiment. Figure 11 It is the same as the first embodiment. Figure 2 The corresponding diagram.

[0156] Figure 11 This indicates that the RC-IGBT 100 is in a cutoff state and the depletion layer extends into the drift region 30. Figure 11 In the diagram, the end of the depletion layer is indicated by a dashed line.

[0157] The carrier concentration in the first region 28a of the first buffer region 28 of the diode region 102 is lower than the carrier concentration in the second region 28b of the first buffer region 28 of the transistor region 101. Therefore, the depletion layer tends to extend more easily in the first region 28a compared to the second region 28b.

[0158] In this case, the distance between the end of the depletion layer in the first region 28a and the collector region 26 is close, making it easier for holes to be injected from the collector region 26 into the depletion layer. Therefore, the leakage current increases at high temperatures, potentially leading to thermal runaway at high temperatures.

[0159] Figure 12 This is an explanatory diagram illustrating the function and effects of the semiconductor device according to the second embodiment. Figure 12 It is the same as the second embodiment. Figure 9 The corresponding diagram.

[0160] Figure 12 This indicates that the RC-IGBT 200 is in a cutoff state and the depletion layer extends into the drift region 30. Figure 12 In the diagram, the end of the depletion layer is indicated by a dashed line.

[0161] In the RC-IGBT 200, the contact region 36 and the collector region 26 sandwich the third region 28c, separating them in the first direction. The carrier concentration in the third region 28c is higher than that in the first region 28a.

[0162] Therefore, compared to the RC-IGBT 100, the distance between the depletion layer end and the collector region 26 in the first region 28a is greater. This suppresses the injection of holes from the collector region 26 into the depletion layer. Consequently, leakage current at high temperatures is further suppressed, and thermal runaway at high temperatures is further suppressed.

[0163] From the viewpoint of suppressing the injection of holes from the collector region 26 into the depletion layer, the distance d1 in the first direction between the contact region 36 and the collector region 26 is preferably less than or equal to the distance d2 in the third direction between the collector region 26 and the drift region 30.

[0164] (Modified Example)

[0165] The semiconductor device of the modified example of the second embodiment differs from the semiconductor device of the second embodiment in that the third region has a first portion that is in contact with the second surface and a second portion between the first portion and the third semiconductor region, and the second conductivity type impurity concentration of the first portion is higher than that of the second conductivity type impurity concentration of the second portion.

[0166] The semiconductor device in a modified embodiment of the second embodiment is an RC-IGBT 210 in which the IGBT and the freewheeling diode are formed on the same semiconductor chip.

[0167] Figure 13 This is a schematic cross-sectional view of a portion of a semiconductor device in a variation of the second embodiment. Figure 13 It is the same as the second embodiment. Figure 9 The corresponding diagram.

[0168] The third region 28c in the first buffer region 28 of the RC-IGBT 210 includes a first part 28c1 and a second part 28c2.

[0169] The first part 28c1 is connected to the second surface F2. The second part 28c2 is located between the first part 28c1 and the drift region 30.

[0170] The concentration of n-type impurities in the first region 28c1 is higher than that in the second region 28c2. The concentration of n-type impurities in the first region 28c1 is higher than that in the second region 28b.

[0171] In the RC-IGBT 210, due to the high concentration of n-type impurities in the first portion 28c1, the distance between the depletion layer end in the first region 28a and the collector region 26 becomes greater. Therefore, leakage current at high temperatures is further suppressed, and thermal runaway at high temperatures is further suppressed.

[0172] Based on the second embodiment and its variations, a semiconductor device comprising an RC-IGBT having an IGBT and a diode can be realized, and its characteristics can be improved by suppressing thermal runaway at high temperatures.

[0173] (Third Implementation)

[0174] The semiconductor device of the third embodiment differs from that of the semiconductor device of the second embodiment in that the semiconductor layer further includes an eighth semiconductor region of a second conductivity type, which is disposed between the second semiconductor region and the third semiconductor region. The second conductivity type impurity concentration is lower than that of the sixth semiconductor region and higher than that of the third semiconductor region. Hereinafter, descriptions that are repeated in the second embodiment will sometimes be omitted.

[0175] The semiconductor device in the third embodiment is an RC-IGBT 300 in which the IGBT and the freewheeling diode are formed on the same semiconductor chip.

[0176] Figure 14 This is a schematic cross-sectional view of a part of the semiconductor device according to the third embodiment. Figure 14 It is the same as the second embodiment. Figure 9 The corresponding diagram.

[0177] The semiconductor layer 10 in the RC-IGBT 300 also includes an n-type second buffer region 29 (eighth semiconductor region).

[0178] The second buffer region 29 is an n-type semiconductor region. The second buffer region 29 is disposed between the first buffer region 28 and the drift region 30.

[0179] The n-type impurity concentration in the second buffer region 29 is lower than that in the contact region 36. The n-type impurity concentration in the second buffer region 29 is higher than that in the drift region 30.

[0180] The carrier concentration in the second buffer region 29 is higher than that in the first region 28a of the first buffer region 28. The crystal defect density in the second buffer region 29 is lower than that in the first region 28a of the first buffer region 28.

[0181] Regarding the formation of the second buffer region 29, for example, in the manufacturing method of the first embodiment, before performing the first ion implantation to form the first n-type region 71, ion implantation is performed to form an n-type region of n-type impurities in a region closer to the first surface F1 than the first n-type region 71. Then, infrared laser IR is irradiated into the semiconductor layer 10 from the second surface F2 side to activate the n-type impurities in the n-type region and restore crystal defects.

[0182] The RC-IGBT 300, by providing a second buffer region 29 with a high carrier concentration, can suppress defects in the first region 28a caused by the depletion layer extending from the F1 side of the first surface. Since an electric field is not applied to the defects, current generation can be suppressed. On the other hand, when the diode operates, the first region 28a helps to eliminate residual carriers, thus improving the trade-off between the diode's switching characteristics and leakage current.

[0183] (Modified Example)

[0184] The semiconductor device of the modified example of the third embodiment differs from the semiconductor device of the third embodiment in that the second semiconductor region does not include the third region.

[0185] The semiconductor device in a variation of the third embodiment is an RC-IGBT 310 in which the IGBT and the freewheeling diode are formed on the same semiconductor chip.

[0186] Figure 15 This is a schematic cross-sectional view of a portion of a semiconductor device according to a variation of the third embodiment. Figure 15 It is the same as the third embodiment. Figure 14 The corresponding diagram.

[0187] The first buffer region 28 of the RC-IGBT 310 does not include the third region 28c. The contact region 36 is connected to the collector region 26.

[0188] Based on the third embodiment and its variations, a semiconductor device comprising an RC-IGBT having an IGBT and a diode can be realized, and its characteristics can be improved by suppressing thermal runaway at high temperatures.

[0189] In the first to third embodiments, the case where the semiconductor layer is monocrystalline silicon was described as an example, but the semiconductor layer is not limited to monocrystalline silicon. For example, it could also be other monocrystalline semiconductors such as monocrystalline silicon carbide.

[0190] In the first to third embodiments, the case where the first conductivity type is p-type and the second conductivity type is n-type was described as an example, but the first conductivity type can also be set to n-type and the second conductivity type to p-type.

[0191] In the first to third embodiments, an RC-IGBT with a trench gate IGBT was described as an example, but it could also be an RC-IGBT with a planar gate IGBT.

[0192] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, the constituent elements of one embodiment may be substituted or modified with the constituent elements of other embodiments. These embodiments and their variations are included within the scope or spirit of the invention, and also within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor device, characterized in that, have: transistor region; and diode region, The transistor region includes: A semiconductor layer having a first surface and a second surface opposite to the first surface, the semiconductor layer comprising: A first semiconductor region of a first conductivity type is connected to the second surface; A second semiconductor region of a second conductivity type is disposed between the first semiconductor region and the first surface; A third semiconductor region of a second conductivity type is disposed between the second semiconductor region and the first surface, wherein the impurity concentration of the second conductivity type in the third semiconductor region is lower than that in the second semiconductor region. A fourth semiconductor region of a first conductivity type is disposed between the third semiconductor region and the first surface; as well as The fifth semiconductor region of the second conductivity type is disposed between the fourth semiconductor region and the first surface and is in contact with the first surface; The gate electrode is opposite to the fourth semiconductor region; A gate insulating film is disposed between the gate electrode and the fourth semiconductor region; The first electrode connected to the fifth semiconductor region; as well as The second electrode is connected to the first semiconductor region. The diode region includes: The semiconductor layer comprises: The second semiconductor region; The third semiconductor region; A sixth semiconductor region of the second conductivity type is disposed between the second semiconductor region and the second surface, and is in contact with the second surface, and the second conductivity type impurity concentration of the sixth semiconductor region is higher than that of the second conductivity type impurity concentration of the second semiconductor region; as well as The seventh semiconductor region of the first conductivity type is disposed between the third semiconductor region and the first surface and is in contact with the first surface; The first electrode connected to the seventh semiconductor region; as well as The second electrode connected to the sixth semiconductor region, The second semiconductor region includes a first region and a second region. The first region is disposed between the sixth semiconductor region and the third semiconductor region. The second region is disposed between the first semiconductor region and the third semiconductor region. The concentration of the second conductivity type impurity in the first region is more than 80% and less than 120% of the concentration of the second conductivity type impurity in the second region, and the carrier concentration in the first region is lower than the carrier concentration in the second region.

2. The semiconductor device according to claim 1, characterized in that, The crystal defect density in the first region is higher than that in the second region.

3. The semiconductor device according to claim 1, characterized in that, The second semiconductor region also includes a third region. The third region is connected to the second surface and is disposed between the sixth semiconductor region and the first semiconductor region. The carrier concentration of the first region is lower than that of the third region.

4. The semiconductor device according to claim 3, characterized in that, The third region has a first portion that is in contact with the second surface and a second portion between the first portion and the third semiconductor region, wherein the second conductivity type impurity concentration of the first portion is higher than that of the second conductivity type impurity concentration of the second portion.

5. The semiconductor device according to claim 3, characterized in that, The semiconductor layer further includes an eighth semiconductor region of a second conductivity type, which is disposed between the second semiconductor region and the third semiconductor region. The second conductivity type impurity concentration of the eighth semiconductor region is lower than that of the sixth semiconductor region, and the second conductivity type impurity concentration of the eighth semiconductor region is higher than that of the third semiconductor region.

6. The semiconductor device according to claim 1, characterized in that, The semiconductor layer further includes an eighth semiconductor region of a second conductivity type, which is disposed between the second semiconductor region and the third semiconductor region. The second conductivity type impurity concentration of the eighth semiconductor region is lower than that of the sixth semiconductor region, and the second conductivity type impurity concentration of the eighth semiconductor region is higher than that of the third semiconductor region.

7. The semiconductor device according to claim 1, characterized in that, The carrier concentration in the first region is less than half of the carrier concentration in the second region.

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