Semiconductor device and manufacturing method, power module, power conversion circuit, and vehicle

Abstract

The application discloses a semiconductor device and a manufacturing method, a power module, a power conversion circuit and a vehicle. The manufacturing method comprises the following steps: providing a semiconductor body; comprising a first surface; forming a barrier portion on the side of the first surface away from the semiconductor body; performing a preset number of operations of forming a side wall structure and a JFET region on the semiconductor body; wherein the side wall structure is located on both sides of the barrier portion; the JFET region is of a first conductivity type; removing the barrier portion and forming a central JFET region in the semiconductor body; wherein the central JFET region is coincident with the orthogonal projection of the barrier portion on the first surface; the ion concentration of the central JFET region is less than that of the JFET region; forming an insulating layer on the first surface; forming a gate electrode on the side of the insulating layer away from the first surface. The embodiment of the application can improve the voltage resistance of the gate oxide layer and reduce the resistance of the JFET region.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a semiconductor device and manufacturing method, a power module, a power conversion circuit, and a vehicle. Background Technology

[0002] Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) made of third-generation wide-bandgap semiconductors such as silicon carbide (SiC) or gallium nitride (GaN) possess characteristics such as large critical breakdown electric field strength, high thermal conductivity, large bandgap width, and high electron saturation drift velocity. These characteristics have made SiC or GaN a research hotspot for power semiconductor devices. In high-power applications such as high-speed rail, hybrid electric vehicles, and intelligent high-voltage direct current transmission, SiC devices are highly anticipated.

[0003] However, the ion concentration at the junction field-effect transistor (JFET) site in existing MOS devices is too high. Although this can reduce the resistance of the JFET region, it has a significant impact on the reliability of the gate oxide layer. Summary of the Invention

[0004] This application provides a semiconductor device and manufacturing method, a power module, a power conversion circuit, and a vehicle, which improve the breakdown voltage of the gate oxide layer and enhance the reliability of the gate oxide layer while reducing the region resistance of the JFET.

[0005] In a first aspect, a method for manufacturing a semiconductor device is provided, comprising: A semiconductor body is provided; the semiconductor body is configured with a first conductivity type and includes a first surface; A blocking portion is formed on the side of the first surface away from the semiconductor body; The semiconductor body is subjected to a predetermined number of operations to form a sidewall structure and a JFET region; wherein the sidewall structure is disposed on the side of the first surface away from the semiconductor body and is located on both sides of the blocking portion; the JFET region is located within the semiconductor body and is configured as a first conductivity type; The blocking portion is removed, and a central JFET region is formed within the semiconductor body; wherein the orthographic projection of the central JFET region onto the first surface coincides with the orthographic projection of the blocking portion onto the first surface; the central JFET region is configured with a first conductivity type, and the ion concentration of the central JFET region is less than the ion concentration of the JFET region; A well region and a first region are formed in the semiconductor body; the first region is configured with a first conductivity type and is located on the first surface, and the well region is configured with a second conductivity type and is located on the side of the first region away from the first surface; An insulating layer is formed on the first surface; A gate is formed on the side of the insulating layer away from the first surface.

[0006] Optionally, forming a blocking portion on the side of the first surface away from the semiconductor body includes: An oxide layer and a barrier layer are sequentially stacked on the first surface; the oxide layer and the barrier layer are disposed over the entire surface. The barrier layer and the oxide layer are photolithographically and etched to form the barrier portion.

[0007] Optionally, the operation of forming the sidewall structure and JFET region on the semiconductor body a predetermined number of times includes: A polycrystalline silicon layer is deposited on the first surface, and the sidewall structure is formed by etching. Ion implantation is performed on the semiconductor body using implanted ions of a first conductivity type to form the JFET region and remove the sidewall structure; wherein, the orthographic projection of the JFET region on the first surface is located on both sides of the orthographic projection of the sidewall structure on the first surface; The operations of depositing a polycrystalline silicon layer and ion implanting the semiconductor body are repeated a preset number of times. During each operation, the corresponding sidewall structure and the corresponding JFET region are formed. In the same operation, the orthographic projection of the JFET region on the first surface is located on both sides of the orthographic projection of the corresponding sidewall structure on the first surface.

[0008] Optionally, the preset number of times includes at least one; In the direction perpendicular to the thickness of the semiconductor body, the ion concentration in the JFET region includes at least two different gradients; The ion concentration in the JFET region gradually decreases from the edge to the center of the semiconductor body.

[0009] Optionally, in the order of the preset number of repeated operations, in the direction perpendicular to the thickness of the semiconductor body, the width of the sidewall structure formed in the later operation is smaller than the width of the sidewall structure formed in the previous operation.

[0010] Optionally, before forming the insulating layer on the first surface, the method further includes: A second region is formed in the semiconductor body; the second region is configured with a second conductivity type and is located on the first surface; the second region is in contact with the first region, and the ion concentration of the second region is greater than the ion concentration of the well region.

[0011] In a second aspect, a semiconductor device is provided, comprising: A semiconductor body includes a first surface; the semiconductor body further includes a well region and a first region, the first region being configured with a first conductivity type and located on the first surface, and the well region being configured with a second conductivity type and located on the side of the first region away from the first surface; the semiconductor body further includes a JFET region and a central JFET region, the JFET region being located on both sides of the central JFET region in a direction perpendicular to the thickness of the semiconductor body; the JFET region and the central JFET region are configured with the first conductivity type, and the ion concentration of the central JFET region is lower than the ion concentration of the JFET region; An insulating layer is located on the first surface; A gate is located on the side of the insulating layer away from the first surface; wherein the insulating layer is used to insulate the gate from the semiconductor body.

[0012] Optionally, the ion concentration in the JFET region includes at least two different gradients in a direction perpendicular to the thickness of the semiconductor body; The ion concentration in the JFET region gradually decreases from the edge to the center of the semiconductor body.

[0013] Optionally, the semiconductor body further includes a second region configured with a second conductivity type and located on the first surface; the second region is in contact with the first region, and the ion concentration of the second region is greater than the ion concentration of the well region.

[0014] Thirdly, a power module is provided, including a substrate and a semiconductor device as described in any embodiment of the second aspect, wherein the substrate is used to support the semiconductor device.

[0015] Fourthly, a power conversion circuit is provided, which is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of the second aspect, the semiconductor device being electrically connected to the circuit board.

[0016] Fifthly, a vehicle is provided, including a load and a power conversion circuit as described in the fourth aspect embodiment, the power conversion circuit being used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input the converted direct current to the load.

[0017] The semiconductor device manufacturing method provided in this application involves forming a barrier portion on a first surface of a semiconductor body, the barrier portion covering a portion of the first surface. A predetermined number of operations are performed on the semiconductor body to form sidewall structures and JFET regions, thereby forming a predetermined number of JFET partitions within the semiconductor body. The ion concentration of each JFET region formation can be different to achieve the formation of JFET regions with different ion concentrations in the lateral direction (i.e., perpendicular to the thickness direction of the semiconductor body). After removing the barrier portion, ion implantation is performed at that location to form a central JFET region. Subsequently, an insulating layer and a gate are formed on the first surface. The central JFET region corresponds to the center position below the gate. Since the electric field strength of the gate oxide layer is larger at the center position below the gate and smaller further away from the center position, and the ion concentration of the central JFET region is smaller than that of other JFET regions, the electric field distribution below the gate oxide layer can be adjusted. This improves the breakdown voltage of the gate oxide layer at the location with a larger electric field strength at the center, and simultaneously achieves lower resistance in the JFET regions through higher ion concentrations in other JFET regions, which is beneficial for improving the electrical performance of the semiconductor device.

[0018] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of this application; Figures 2 to 7 yes Figure 1 A structural diagram corresponding to each relevant step in the process; Figure 8 This is a schematic flowchart of step S120 in a semiconductor device manufacturing method according to an embodiment of this application; Figures 9 to 10 yes Figure 8 A structural diagram corresponding to the relevant steps in the process; Figure 11 This is a schematic diagram of the specific process of step S130 in a semiconductor device manufacturing method according to an embodiment of this application; Figures 12 to 17 yes Figure 11 A structural diagram corresponding to each relevant step in the process; Figure 18 This is a comparison curve of the electric field intensity distribution in a JFET region according to an embodiment of this application. Detailed Implementation

[0021] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0022] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0023] This application provides a method for manufacturing a semiconductor device. Figure 1 This is a schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application. Figures 2 to 7 yes Figure 1 A structural diagram corresponding to each relevant step. See also... Figures 1 to 7 The manufacturing method of this semiconductor device specifically includes the following steps: S110, Provide a semiconductor body; the semiconductor body is configured with a first conductivity type and includes a first surface.

[0024] Specifically, see Figure 2The semiconductor body 100 is configured with a first conductivity type and includes a first surface 101 on which other films will be subsequently fabricated. Exemplarily, the semiconductor body 100 may include a substrate 10 and an epitaxial layer 20; in some embodiments of this application, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of this application, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the substrate 10 by a single epitaxial process, including chemical vapor deposition (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE). Exemplarily, the semiconductor body 100 may be a silicon carbide semiconductor body or a gallium nitride semiconductor body, without limitation.

[0025] S120, a blocking portion is formed on the side of the first surface away from the semiconductor body.

[0026] Specifically, see Figure 3 A barrier portion 102 is formed on the side of the first surface 101 away from the semiconductor body 100. By providing the barrier portion 102 on the first surface 101, the portion of the semiconductor body 100 corresponding to the barrier portion 102 can be protected from ion implantation during subsequent ion implantation of the semiconductor body 100, thereby reserving a position for setting the central JFET region, so that the ion concentration of the central JFET region is different from the ion concentration of JFET regions at other locations. For example, the barrier portion 102 can be located at the center of the first surface 101 of the semiconductor body 100, corresponding to the center of the gate, thereby making the ion concentration of the JFET region below the center of the gate different from the ion concentration of JFET regions at other locations. By adjusting the ion concentration of the JFET regions at different locations, the breakdown voltage capability of the gate oxide layer can be improved.

[0027] S130, Perform an operation to form a sidewall structure and a JFET region on the semiconductor body a preset number of times; wherein the sidewall structure is disposed on the side of the first surface away from the semiconductor body and is located on both sides of the blocking portion; the JFET region is located within the semiconductor body and is configured as a first conductivity type.

[0028] Specifically, see Figure 4The semiconductor body 100 is subjected to a predetermined number of operations to form the sidewall structure 103 and the JFET region 104. The sidewall structure 103 is disposed on the side of the first surface 101 away from the semiconductor body 100 and located on both sides of the blocking portion 102. The JFET region 104 is located within the semiconductor body 100 and is configured with a first conductivity type. Exemplarily, the MOSFET semiconductor device may include an N-type MOSFET semiconductor device or a P-type MOSFET semiconductor device. In this embodiment, an N-type MOSFET semiconductor device is used as an example. If the semiconductor body 100 is an N-type semiconductor body, then the JFET region 104 is an N-type JFET region, and the ion concentration of the JFET region 104 is greater than the ion concentration of the semiconductor body 100.

[0029] A sidewall structure 103 is formed on the first surface 101 of the semiconductor body 100. The exposed portion of the first surface 101 is used to form the JFET region 104 for this operation, and the portion of the first surface 101 covered by the sidewall structure 103 is used to form the corresponding JFET region 104 multiple times thereafter. Ion implantation is performed on the portion of the semiconductor body 100 exposed by the sidewall structure 103 to form the JFET region 104. The above-mentioned formation of the sidewall structure 103 and the corresponding implantation to form the corresponding JFET region 104 constitutes one operation. By sequentially performing the operation of forming the sidewall structure 103 and the corresponding JFET region 104 a preset number of times, the complete JFET region can be divided into a preset number of JFET partitions, and the ion concentration between each JFET partition can be different. This allows for adjustment of the ion concentration distribution of the JFET region in the lateral direction (i.e., perpendicular to the thickness direction of the semiconductor body 100), which is beneficial for adjusting the relationship between reducing the resistance of the JFET region and improving the breakdown voltage capability of the gate oxide layer.

[0030] S140. Remove the blocking portion and form a central JFET region within the semiconductor body; wherein the orthographic projection of the central JFET region on the first surface coincides with the orthographic projection of the blocking portion on the first surface; the central JFET region is configured as a first conductivity type, and the ion concentration of the central JFET region is less than the ion concentration of the JFET region.

[0031] Specifically, see Figure 5The blocking portion is removed, and a central JFET region 105 is formed within the semiconductor body 100. The orthographic projection of the central JFET region 105 onto the first surface 101 coincides with the orthographic projection of the blocking portion onto the first surface 101. The central JFET region 105 is configured with a first conductivity type, and the ion concentration of the central JFET region 105 is less than the ion concentration of the JFET region 104. For example, still using an N-type MOSFET semiconductor device as an example, if the semiconductor body 100 is an N-type semiconductor body, then the central JFET region 105 is an N-type JFET region.

[0032] After etching to remove the blocking portion, an ion implantation is performed to form the central JFET region 105. The central JFET region 105 is located at the center of the semiconductor body 100, corresponding to the center position below the gate. Since the central JFET region 105 is formed by only one ion implantation process, the ion concentration of the central JFET region 105 is lower than the ion concentration of any other JFET region 104, thus achieving the effect of having the minimum ion concentration in the central JFET region 105 located at the center position below the gate. The electric field intensity distribution under the gate oxide layer is that the electric field intensity is high at the center position, and gradually decreases from the center position away from the center position. By setting the central JFET region 105 with the minimum ion concentration to correspond to the center position under the gate oxide layer with the higher electric field intensity, the electric field distribution under the gate oxide layer can be adjusted, effectively improving the breakdown voltage capability of the gate oxide layer at the position with the higher electric field intensity. At the same time, it can achieve a lower resistance in the overall JFET region, which is beneficial to improving the electrical performance of the semiconductor device.

[0033] S150, A well region and a first region are formed in the semiconductor body; the first region is configured with a first conductivity type and is located on the first surface, and the well region is configured with a second conductivity type and is located on the side of the first region away from the first surface.

[0034] Specifically, see Figure 6 A well region 106 and a first region 107 are formed in the semiconductor body 100. The first region 107 is configured with a first conductivity type and is located on the first surface 101, while the well region 106 is configured with a second conductivity type and is located on the side of the first region 107 away from the first surface 101. For example, still using an N-type MOSFET semiconductor device as an example, the semiconductor body 100 is an N-type semiconductor body, the well region 106 is a P-type well region, and the first region 107 is an N+ doped region.

[0035] S160, An insulating layer is formed on the first surface.

[0036] Specifically, see Figure 7An insulating layer 108 is formed on the first surface 101. For example, an insulating material layer can be formed by depositing silicon dioxide material over the entire first surface 101, and then etching the insulating material layer by photolithography and etching processes to form the insulating layer 108.

[0037] S170, A gate is formed on the side of the insulating layer away from the first surface.

[0038] Specifically, see [link to relevant documentation] Figure 7 A gate 109 is formed on the side of the insulating layer 108 away from the first surface 101. A polysilicon material layer is deposited on the surface of the insulating layer 108, and then the polysilicon material layer is etched by photolithography and etching processes to form the gate 109. The gate 109 is insulated from the semiconductor body 100 through the insulating layer 108, and the center position below the gate 109 corresponds to the central JFET region 105, which is the region with the lowest ion concentration in the complete JFET region, thereby effectively improving the breakdown voltage capability of the central position of the gate oxide layer with a large electric field strength.

[0039] The semiconductor device manufacturing method provided in this application involves forming a barrier portion 102 on a first surface 101 of a semiconductor body 100, the barrier portion 102 covering a portion of the first surface 101. The semiconductor body 100 is subjected to a predetermined number of operations to form sidewall structures 103 and JFET regions 104, thereby forming a predetermined number of JFET partitions in the semiconductor body 100. The ion concentration of the JFET regions 104 formed each time can be different, to achieve the formation of JFET regions 104 with different ion concentrations in the lateral direction (i.e., perpendicular to the thickness direction of the semiconductor body 100). After removing the barrier portion, ion implantation is performed at that location to form a central JFET region 105, followed by the formation of an insulating layer 108 and a gate 109 on the first surface 101. The central JFET region 105 corresponds to the center position below the gate 109. Since the electric field strength of the gate oxide layer is larger at the center position below and smaller further away from the center position, and the ion concentration of the central JFET region 105 is smaller than that of other JFET regions 104, the electric field distribution below the gate oxide layer can be adjusted to improve the breakdown voltage of the gate oxide layer at the position with a larger electric field strength at the center. Furthermore, the higher ion concentration of other JFET regions 104 can simultaneously achieve a lower resistance in the JFET region, which is beneficial to improving the electrical performance of the semiconductor device.

[0040] Based on the above embodiments, Figure 8 This is a schematic flowchart of step S120 in a semiconductor device manufacturing method provided in an embodiment of this application. Figures 9 to 10 yes Figure 8 A structural diagram corresponding to the relevant steps. See also... Figure 3 , Figures 8 to 10 Optionally, forming a blocking portion on the side of the first surface away from the semiconductor body in step S120 specifically includes the following steps: S121. An oxide layer and a barrier layer are sequentially stacked on the first surface; the oxide layer and the barrier layer are disposed over the entire surface.

[0041] Specifically, see Figure 9 An oxide layer 110 and a barrier layer 111 are sequentially stacked on the first surface 101; the oxide layer 110 and the barrier layer 111 are disposed across the entire surface. Exemplarily, the oxide layer 110 can be made of silicon dioxide, and the barrier layer 111 can be made of silicon nitride. A relatively thin oxide layer 110 is grown on the first surface 101 using a thermal oxidation method with silicon dioxide, and a relatively thick barrier layer 111 is grown on the side of the oxide layer 110 away from the first surface 101 using silicon nitride. The purpose of growing an oxide layer 110 before growing the silicon nitride barrier layer 111 is to reduce the stress generated during the growth of the silicon nitride.

[0042] S122. Photolithography and etching are performed on the barrier layer and oxide layer to form the barrier portion.

[0043] Specifically, see Figure 10 and Figure 3 The barrier layer 111 and the oxide layer 110 are photolithographically and etched to form the barrier portion 102. A photoresist layer 112 is coated on the side of the barrier layer 111 away from the oxide layer 110 and exposed. Then, the portion of the barrier layer 111 and the oxide layer 110 exposed by the photoresist layer 112 is etched, thereby retaining the portion of the barrier layer 111 and the oxide layer covered and protected by the photoresist layer 112, so as to form the barrier portion 102 on the first surface 101.

[0044] Based on the above embodiments, Figure 11 This is a schematic flowchart of step S130 in a semiconductor device manufacturing method provided in an embodiment of this application. Figures 12 to 17 yes Figure 11 A structural diagram corresponding to each relevant step. See also... Figure 5 , Figures 11 to 17 Optionally, the operation of forming the sidewall structure and JFET region on the semiconductor body a preset number of times in step S130 includes: S131. A polysilicon layer is deposited on the first surface and etched to form a sidewall structure.

[0045] Specifically, see Figure 12 and Figure 13A polysilicon layer 113 is deposited on the first surface 101, and then etched to form a sidewall structure 103. Polysilicon material is deposited over the entire surface of the first surface 101, and the deposited polysilicon layer 113 is etched using a dry etching method. Due to the anisotropy of the continuous polysilicon layer 113 covering the first surface 101 and the barrier portion 102, the polysilicon layer on both sides of the barrier portion 102 can be retained during the dry etching process, thus allowing the sidewall structure 103 to be directly etched without photolithography.

[0046] S132. Using implanted ions of the first conductivity type, ion implantation is performed on the semiconductor body to form a JFET region and remove the sidewall structure; wherein, the orthographic projection of the JFET region on the first surface is located on both sides of the orthographic projection of the sidewall structure on the first surface.

[0047] Specifically, see Figure 14 and Figure 15 Ion implantation of the semiconductor body 100 is performed using implanted ions of the first conductivity type to form a JFET region 104 and remove the sidewall structure 103. The orthographic projection of the JFET region 104 onto the first surface 101 is located on both sides of the orthographic projection of the sidewall structure 103 onto the first surface 101. Ion implantation of the first surface 101 forms an ion-doped region in the semiconductor body 100 at a position corresponding to the sidewall structure 103 away from the barrier portion 102. Figure 14 The JFET region 104 is then removed using a wet etching method to remove the sidewall structure 103 from the first operation.

[0048] S133. Repeat the operations of depositing a polysilicon layer and ion implanting the semiconductor body a preset number of times, and form a corresponding sidewall structure and a corresponding JFET region during each operation; wherein, during the same operation, the orthographic projection of the JFET region on the first surface is located on both sides of the orthographic projection of the corresponding sidewall structure on the first surface.

[0049] Specifically, see Figure 4 , Figure 16 and Figure 17The process of depositing a polysilicon layer and performing ion implantation on the semiconductor body is repeated a preset number of times. During each operation, a corresponding sidewall structure 103 and a corresponding JFET region 104 are formed. In the same operation, the orthographic projection of the JFET region 104 onto the first surface 101 is located on both sides of the orthographic projection of the corresponding sidewall structure 103 onto the first surface 101. Depositing a polysilicon layer 113 on the first surface 101 and forming the sidewall structure 103 through dry etching, as well as performing ion implantation on the first surface 101 to form the JFET region 104 in the semiconductor body 100, constitutes one operation. Therefore, each operation forms a JFET region 104 with a corresponding ion concentration in the semiconductor body 100. The preset number of operations can be set according to the user's actual needs and is not limited here.

[0050] For example, Figure 4 , Figure 16 and Figure 17 A schematic diagram shows a structural process in which the operations of depositing a polycrystalline silicon layer 113 and ion implanting the semiconductor body 100 are repeated twice, with a preset number of times of deposition. Figure 4 and Figure 16 This diagram illustrates the structure of repeating the first operation. Figure 17 A schematic diagram of the structure for repeating the second operation is shown. It should be noted that in the last operation, there is no need to deposit the polysilicon layer 113 again to form the sidewall structure 103. Ion implantation can be performed directly on the first surface 101. As a result, the JFET region 104 in this operation can be formed in the semiconductor body 100 in the region between the JFET region 104 and the blocking portion 102 and the orthogonal projection of the first surface 101.

[0051] Based on the above embodiments, see below. Figure 5 Optionally, the preset number of times includes at least one; In the direction perpendicular to the thickness of the semiconductor body 100, the ion concentration of the JFET region 104 includes at least two different gradients. From the edge to the center of the semiconductor body 100, the ion concentration in the JFET region 104 gradually decreases.

[0052] Specifically, by repeatedly performing the above-mentioned related operations a preset number of times, JFET partitions can be formed in the semiconductor body 100 with the same number of preset operations. Furthermore, each time the above-mentioned related operations are repeated, ion implantation forms the JFET region 104 in this operation. Ion implantation is performed on the entire exposed first surface 101. Therefore, while forming the JFET region 104 in this operation, ion implantation is also performed on the JFET regions 104 already formed in previous operations, resulting in an increase in the ion concentration of the already formed JFET regions 104 in each operation. This results in a relatively low ion concentration in the JFET regions 104 near the center and a relatively high ion concentration in the JFET regions 104 far from the center, i.e., the overall ion concentration distribution of the JFET regions 104 is bowl-shaped. For example, Figure 18 This is a comparative curve showing the electric field intensity distribution in a JFET region according to an embodiment of this application. See also... Figure 18 The horizontal axis of the graph represents the location of the electric field intensity test point in the JFET region, and the vertical axis represents the electric field intensity, in V / cm. Curve 01 represents the electric field intensity distribution in a JFET region with the same and relatively high ion concentration in the lateral direction, as provided in related technologies. Curve 02 represents the electric field intensity distribution in a JFET region with different ion concentration gradients in the lateral direction, as provided in the embodiments of this application. Figure 18 As can be seen, curve 02 is bowl-shaped, and at the center position corresponding to the gate oxide layer below the gate, the electric field strength of curve 02 is significantly lower than that of curve 01. This indicates that the semiconductor device provided in this application embodiment can effectively improve the breakdown voltage at the center position of the gate oxide layer and improve the reliability of the gate oxide layer; and the JFET region 104 far from the center position has a higher ion concentration, which can also effectively reduce the resistance of the JFET region.

[0053] Based on the above embodiments, see below. Figure 4 and Figure 13 Optionally, in the order of a preset number of repeated operations, the width of the sidewall structure 103 formed in the later operation is smaller than the width of the sidewall structure 103 formed in the previous operation in the direction perpendicular to the thickness of the semiconductor body 100.

[0054] Specifically, since the distance between the outer edge of the sidewall structure 103 and the previously formed JFET region 104 is equal to the width of the JFET region 104 formed in the current operation, the width of the sidewall structure 103 formed each time an operation is performed should gradually decrease. This allows multiple JFET regions 104 with different ion concentration gradients to be formed in the lateral direction of the semiconductor body 100, thereby improving the breakdown voltage at the center position below the gate oxide layer while achieving a lower resistance in the JFET region.

[0055] Based on the above embodiments, optionally, before forming an insulating layer on the first surface in step S160, the following step is further included: A second region is formed in the semiconductor body; the second region is configured with a second conductivity type and is located on the first surface; the second region is in contact with the first region, and the ion concentration of the second region is greater than the ion concentration of the well region.

[0056] Specifically, see [link to relevant documentation] Figure 6 A second region 114 is formed in the semiconductor body 100. The second region 114 is configured with a second conductivity type and is located on the first surface 101. The second region 114 is in contact with the first region 107, and the ion concentration of the second region 114 is greater than the ion concentration of the well region 106. The conductivity type of the second region 114 is opposite to that of the first region 107. For example, taking an N-type MOSFET semiconductor device as an example, if the first conductivity type is N-type, then the second conductivity type is P-type, and the second region 114 includes a P+ doped region. The ion concentration of the second region 114 is greater than that of the well region 106. The second region 114 is provided to form a better ohmic contact with the source.

[0057] This application also provides a semiconductor device. See [link to relevant documentation]. Figure 7 The semiconductor device includes: The semiconductor body 100 includes a first surface 101; the semiconductor body 100 also includes a well region 106 and a first region 107, the first region 107 being configured with a first conductivity type and located on the first surface 101, and the well region 106 being configured with a second conductivity type and located on the side of the first region 107 away from the first surface 101; the semiconductor body 100 also includes a JFET region 104 and a central JFET region 105, the JFET region 104 being located on both sides of the central JFET region 105 in a direction perpendicular to the thickness of the semiconductor body 100; the JFET region 104 and the central JFET region 105 are configured with the first conductivity type, and the ion concentration of the central JFET region 105 is less than the ion concentration of the JFET region 104; Insulating layer 108 is located on the first surface 101; The gate 109 is located on the side of the insulating layer 108 away from the first surface 101; wherein the insulating layer 108 is used to insulate the gate 109 from the semiconductor body 100.

[0058] Specifically, a JFET region 104 and a central JFET region 105 are disposed in the region between two adjacent well regions 106 in the semiconductor body 100. The ion concentration in the central JFET region 105 is lower than that in the JFET region 104 located further from the center. An insulating layer 108 and a gate 109 are stacked on the first surface 101, with the center of the gate 109 corresponding to the central JFET region 105 in the semiconductor body 100. The electric field strength is stronger at the center position below the gate 109 in the semiconductor body 100 and weaker further away from the center; that is, the electric field strength gradually decreases from the center to the position further away from the center. Therefore, the central JFET region 105 with a lower ion concentration can effectively improve the breakdown voltage at the center position of the gate oxide layer, thereby improving the reliability of the semiconductor device. Simultaneously, by disposing of the JFET region 104 with a higher ion concentration located further from the center, a lower JFET region resistance can be achieved, improving the electrical performance of the semiconductor device.

[0059] The semiconductor device provided in this application embodiment has a central JFET region 105 and a predetermined number of JFET regions 104 in the semiconductor body 100, and the ion concentration of the central JFET region 105 is lower than that of the JFET regions 104. The central JFET region 105 is located at the center position below the gate 109 disposed on the surface of the insulating layer 108. Since the electric field strength below the gate 109 gradually decreases from the center position to the position away from the center, by setting JFET regions 104 and the central JFET region 105 with different ion concentrations, the breakdown voltage at the center position of the gate oxide layer can be effectively improved, thereby improving the reliability of the semiconductor device. Furthermore, by setting JFET regions 104 with higher ion concentrations further away from the center, a lower JFET region resistance can be achieved, improving the electrical performance of the semiconductor device.

[0060] Based on the above embodiments, see below. Figure 7 Optionally, in the direction perpendicular to the thickness of the semiconductor body 100, the ion concentration of the JFET region 104 includes at least two different gradients. From the edge to the center of the semiconductor body 100, the ion concentration in the JFET region 104 gradually decreases.

[0061] Specifically, in the direction perpendicular to the thickness of the semiconductor body 100, i.e., in the lateral direction, the JFET region includes multiple JFET regions 104 and a central JFET region 105. The multiple JFET regions 104 are formed through multiple processes of forming sidewall structures and implanting JFET regions. Each formation of a JFET region 104 involves ion implantation onto the entire exposed first surface 101, thus the ion concentration of each formed JFET region 104 can be different. Furthermore, according to the formation sequence of each JFET region 104 and the central JFET region 105, the ion concentration of the JFET regions 104 gradually decreases from the center to the location furthest from the center, with the central JFET region 105 having the lowest ion concentration. This effectively improves the breakdown voltage at the center of the gate oxide layer while ensuring that the semiconductor device has a low JFET region resistance.

[0062] Based on the above embodiments, see below. Figure 7 Optionally, the semiconductor body 100 further includes a second region 114, which is configured as a second conductivity type and located on the first surface 101; the second region 114 is in contact with the first region 107, and the ion concentration of the second region 114 is greater than the ion concentration of the well region 106.

[0063] Specifically, the conductivity type of the second region 114 is opposite to that of the first region 107. For example, taking an N-type MOSFET semiconductor device as an example, if the first conductivity type is N-type, then the second conductivity type is P-type. The second region 114 includes a P+ doped region. The ion concentration in the second region 114 is greater than that in the well region 106. The second region 114 is configured to form a better ohmic contact with the source.

[0064] This application provides a power module including a substrate and at least one semiconductor device provided in any of the embodiments of this application, wherein the substrate is used to support the semiconductor device. Therefore, the beneficial effects of this power module including the semiconductor device provided in any of the embodiments of this application will not be elaborated further here.

[0065] This application provides a power conversion circuit for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and at least one semiconductor device provided in any of the embodiments of this application, and the semiconductor device is electrically connected to the circuit board.

[0066] Therefore, the beneficial effects of this power conversion circuit, which includes any of the semiconductor devices provided in the embodiments of this application, will not be elaborated further here.

[0067] This application also provides a vehicle, including a load and a power conversion circuit as provided in any embodiment of this application. The power conversion circuit is used to convert AC power to DC power, AC power to AC power, DC power to DC power, or DC power to AC power and then input it to the load. Therefore, the beneficial effects of this vehicle including the power conversion circuit provided in any embodiment of this application will not be elaborated further here.

[0068] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A semiconductor body is provided; the semiconductor body is configured with a first conductivity type and includes a first surface; A blocking portion is formed on the side of the first surface away from the semiconductor body; The semiconductor body is subjected to a predetermined number of operations to form a sidewall structure and a JFET region; wherein the sidewall structure is disposed on the side of the first surface away from the semiconductor body and located on both sides of the blocking portion; the JFET region is located within the semiconductor body and is configured as a first conductivity type; The blocking portion is removed, and a central JFET region is formed within the semiconductor body; wherein the orthographic projection of the central JFET region onto the first surface coincides with the orthographic projection of the blocking portion onto the first surface; the central JFET region is configured with a first conductivity type, and the ion concentration of the central JFET region is less than the ion concentration of the JFET region; A well region and a first region are formed in the semiconductor body; the first region is configured with a first conductivity type and is located on the first surface, and the well region is configured with a second conductivity type and is located on the side of the first region away from the first surface; An insulating layer is formed on the first surface; A gate is formed on the side of the insulating layer away from the first surface.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The method of forming a barrier portion on the side of the first surface away from the semiconductor body includes: An oxide layer and a barrier layer are sequentially stacked on the first surface; the oxide layer and the barrier layer are disposed over the entire surface. The barrier layer and the oxide layer are photolithographically and etched to form the barrier portion.

3. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The operation of forming the sidewall structure and JFET region on the semiconductor body a predetermined number of times includes: A polycrystalline silicon layer is deposited on the first surface, and the sidewall structure is formed by etching. Ion implantation is performed on the semiconductor body using implanted ions of a first conductivity type to form the JFET region and remove the sidewall structure; wherein, the orthographic projection of the JFET region on the first surface is located on both sides of the orthographic projection of the sidewall structure on the first surface; The operations of depositing a polycrystalline silicon layer and ion implanting the semiconductor body are repeated a preset number of times. During each operation, the corresponding sidewall structure and the corresponding JFET region are formed. In the same operation, the orthographic projection of the JFET region on the first surface is located on both sides of the orthographic projection of the corresponding sidewall structure on the first surface.

4. The method for manufacturing a semiconductor device according to claim 3, characterized in that, The preset number of times includes at least one; In the direction perpendicular to the thickness of the semiconductor body, the ion concentration in the JFET region includes at least two different gradients; The ion concentration in the JFET region gradually decreases from the edge to the center of the semiconductor body.

5. The method for manufacturing a semiconductor device according to claim 3, characterized in that, In accordance with the predetermined number of repeated operations, in the direction perpendicular to the thickness of the semiconductor body, the width of the sidewall structure formed in the later operation is smaller than the width of the sidewall structure formed in the previous operation.

6. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Before forming the insulating layer on the first surface, the method further includes: A second region is formed in the semiconductor body; the second region is configured with a second conductivity type and is located on the first surface; the second region is in contact with the first region, and the ion concentration of the second region is greater than the ion concentration of the well region.

7. A semiconductor device, characterized in that, include: A semiconductor body includes a first surface; the semiconductor body further includes a well region and a first region, the first region being configured with a first conductivity type and located on the first surface, and the well region being configured with a second conductivity type and located on the side of the first region away from the first surface; the semiconductor body further includes a JFET region and a central JFET region, the JFET region being located on both sides of the central JFET region in a direction perpendicular to the thickness of the semiconductor body; the JFET region and the central JFET region are configured with the first conductivity type, and the ion concentration of the central JFET region is lower than the ion concentration of the JFET region; An insulating layer is located on the first surface; A gate is located on the side of the insulating layer away from the first surface; wherein the insulating layer is used to insulate the gate from the semiconductor body.

8. The semiconductor device according to claim 7, characterized in that, In the direction perpendicular to the thickness of the semiconductor body, the ion concentration in the JFET region includes at least two different gradients; The ion concentration in the JFET region gradually decreases from the edge to the center of the semiconductor body.

9. The semiconductor device according to claim 8, characterized in that, The semiconductor body further includes a second region, which is configured with a second conductivity type and located on the first surface; the second region is in contact with the first region, and the ion concentration of the second region is greater than the ion concentration of the well region.

10. A power module, characterized in that, The invention includes a substrate and the semiconductor device according to any one of claims 7-9, wherein the substrate is used to support the semiconductor device.

11. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any one of claims 7-9, wherein the semiconductor device is electrically connected to the circuit board.

12. A vehicle, characterized in that, The device includes a load and a power conversion circuit as described in claim 11, the power conversion circuit being used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

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