Trench gate semiconductor device and method of manufacturing the same
By directly epitaxially forming the bulk region and using in-situ doping, the defect problem at the semiconductor-gate oxide interface of trench MOSFETs was solved, improving channel mobility and threshold voltage stability, reducing on-resistance and increasing breakdown voltage.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HUNAN SANAN SEMICON CO LTD
- Filing Date
- 2024-11-28
- Publication Date
- 2026-06-05
AI Technical Summary
Trench MOSFETs have a high density of traps or defects at the semiconductor-gate oxide interface, which affects the threshold voltage stability and channel mobility of the device.
By adopting direct epitaxial formation of the bulk region, lattice damage within the bulk region is reduced, and in-situ doping of the region improves the interface defects between the channel and the gate oxide layer, avoiding the tailing effect caused by ion implantation.
It improves channel mobility and threshold voltage stability, reduces device on-resistance, and increases breakdown voltage.
Smart Images
Figure CN122161132A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor devices, and more particularly to a trench gate semiconductor device and its fabrication method. Background Technology
[0002] A trench MOSFET (or trench gate MOSFET) is a specially designed MOSFET (metal-oxide-semiconductor field-effect transistor). Compared to planar MOSFETs, trench MOSFETs offer better channel utilization and eliminate the resistance inherent in the JFET (junction field-effect transistor) region.
[0003] However, trench MOSFETs have a high density of traps or defects at the semiconductor-gate oxide interface, which can affect the overall performance of the device, such as the threshold voltage stability, channel mobility and leakage current amplitude. Summary of the Invention
[0004] The main technical problem addressed by this disclosure is how to improve the performance of devices.
[0005] To solve the above-mentioned technical problems, the first technical solution adopted in this disclosure is: to provide a trench gate semiconductor device, wherein, it includes:
[0006] Substrate;
[0007] The drift region is disposed on the substrate surface, and both the drift region and the substrate are of the first conductivity type.
[0008] The body region is epitaxially formed on the surface of the drift region away from the substrate and is an in-situ doped region of the second conductivity type.
[0009] To solve the above-mentioned technical problems, the second technical solution adopted in this disclosure is: providing a method for fabricating a trench gate semiconductor device, comprising:
[0010] A drift region and a bulk region are epitaxially grown sequentially on a substrate; both the substrate and the drift region are of the first conductivity type; the bulk region is an in-situ doped region of the second conductivity type.
[0011] The beneficial effects of this disclosure are as follows: Unlike the prior art, this disclosure provides a trench gate semiconductor device and its fabrication method. The trench gate semiconductor device includes a substrate, a drift region, and a body region. The drift region is disposed on the surface of the substrate and is of a first conductivity type, as is the substrate. The body region is epitaxially formed on the surface of the drift region away from the substrate and is an in-situ doped region of a second conductivity type. The direct epitaxial formation of the body region in this disclosure reduces lattice damage within the body region, thereby reducing interface defects between the body region and the gate oxide layer, and thus improving channel mobility; secondly, it avoids the tailing effect of ion implantation in the channel, thereby improving threshold voltage stability. Attached Figure Description
[0012] Figure 1 This is a schematic diagram of the structure of the first embodiment of the trench gate semiconductor device provided in this disclosure;
[0013] Figure 2 This is a schematic diagram of the structure of a second embodiment of the trench gate semiconductor device provided in this disclosure;
[0014] Figure 3 This is a schematic diagram of the structure of a third embodiment of the trench gate semiconductor device provided in this disclosure;
[0015] Figure 4 This is a schematic flowchart of the first embodiment of the method for fabricating a trench gate semiconductor device provided in this disclosure;
[0016] Figure 5 yes Figure 4 A schematic diagram of the structure corresponding to step S1 in the middle section;
[0017] Figure 6 yes Figure 4 A flowchart illustrating the implementation method of step S2;
[0018] Figure 7 yes Figure 6 Structural diagrams corresponding to one embodiment of steps S211 to S214;
[0019] Figure 8 This is a schematic diagram of the structure of a contact area of a body provided in this disclosure.
[0020] Figure 9 This is a flowchart illustrating a second embodiment of the trench gate semiconductor device provided in this disclosure.
[0021] Figure 10 yes Figure 9 A flowchart illustrating the implementation method of step S2;
[0022] Figure 11 yes Figure 10Schematic diagrams of the structures corresponding to one embodiment of steps S221 to S225;
[0023] Figure 12 This is a flowchart illustrating a third embodiment of the trench gate semiconductor device provided in this disclosure.
[0024] Figure 13 yes Figure 12 A flowchart illustrating the implementation method of step S2;
[0025] Figure 14 yes Figure 13 Structural diagrams corresponding to one embodiment of steps S231 to S235;
[0026] Figure 15 This is a schematic diagram of a structure corresponding to an embodiment of the present disclosure that forms a gate electrode layer, an interlayer dielectric layer, an ohmic contact layer, and a source electrode layer.
[0027] Explanation of reference numerals in the attached figures:
[0028] 1. Trench gate semiconductor device; 10. Substrate; 20. Drift region; 30. Body region; 40. Cell; 41. Source region; 42. First doped region; 43. Third doped region; 44. Fourth doped region; 45. Body contact region; 50. Trench; 51. Corner; 60. Gate oxide layer; 61. First gate oxide layer; 62. Second gate oxide layer; 70. Second doped region; 80. Fifth doped region; 90. Gate electrode layer; 100. Interlayer dielectric layer; 110. Ohmic contact layer; 120. Source electrode layer; 101. First trench; 102. Second trench; 103. Third trench; 104. Fourth trench; 105. First pre-fabricated epitaxial layer; 106. Second pre-fabricated epitaxial layer. Detailed Implementation
[0029] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the embodiments of this disclosure.
[0030] The terms "first," "second," and "third" in this disclosure are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in this disclosure are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.
[0031] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the embodiments disclosed herein. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0032] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings and examples.
[0033] Please see Figures 1 to 3 , Figure 1 This is a schematic diagram of the structure of the first embodiment of the trench gate semiconductor device provided in this disclosure. Figure 2 This is a schematic diagram of the structure of a second embodiment of the trench gate semiconductor device provided in this disclosure. Figure 3 This is a schematic diagram of the structure of a third embodiment of the trench gate semiconductor device provided in this disclosure.
[0034] This disclosure provides a trench gate semiconductor device 1. The trench gate semiconductor device 1 includes a substrate 10, a drift region 20, and a body region 30. The drift region 20 is disposed on the surface of the substrate 10 and is of a first conductivity type, as is the substrate 10. The body region 30 is epitaxially formed on the surface of the drift region 20 away from the substrate 10 and is an in-situ doped region of a second conductivity type.
[0035] In related technologies, the body region 30 is formed by ion implantation. Ion implantation introduces a lattice damage layer, which increases the interface defects between the body region 30 and the gate oxide layer 60, reducing the channel mobility. Secondly, the ion-implanted channel has a tailing effect, and the channel length is greatly affected by the ion implantation process, resulting in poor stability of the WIW (Within-Wafer / Run-to-Run) / RTR (Run-to-Run) threshold voltage.
[0036] Compared with related technologies, the direct epitaxial formation of the body region 30 in this embodiment can reduce lattice damage within the body region 30, thereby reducing interface defects between the body region 30 and the gate oxide layer 60, and thus improving channel mobility; secondly, it can avoid the tailing effect of the channel due to ion implantation, thereby improving threshold voltage stability.
[0037] For example, the substrate 10 may be silicon carbide.
[0038] For example, the first conductivity type is N-type and the second conductivity type is P-type.
[0039] In other embodiments, the first conductivity type can be P-type and the second conductivity type can be N-type. The substrate 10 can be other materials, which are not limited here and can be selected according to actual needs.
[0040] For example, the drift region 20 is silicon carbide.
[0041] For example, body region 30 is silicon carbide.
[0042] In-situ doped regions refer to doped regions formed by directly incorporating impurity atoms during material growth.
[0043] It can be understood that the body region 30 in this embodiment is not formed by doping after the epitaxial layer is grown, but by doping during the growth of the epitaxial layer.
[0044] In some embodiments, the trench gate semiconductor device 1 further includes a plurality of cells 40, a trench 50, and a gate oxide layer 60, wherein the cells 40 are located at least in the body region 30. The cells 40 have a source region 41.
[0045] The trench 50 is located between the cells 40 and extends from the surface of the source region 41 away from the substrate 10 into the drift region 20.
[0046] The gate oxide layer 60 includes a first gate oxide layer 61 and a second gate oxide layer 62 connected to each other. The first gate oxide layer 61 is at least partially located on the outer sidewall of the trench 50, and the second gate oxide layer 62 is located on the outer bottom wall of the trench 50.
[0047] Source region 41 is used to provide charge carriers (such as electrons or holes).
[0048] In some embodiments, the sidewalls of the groove 50 and the bottom wall of the groove 50 can be arranged vertically or inclined, and the angle between the sidewalls of the groove 50 and the bottom wall of the groove 50 is adjustable.
[0049] For example, the sidewalls of the trench 50 are perpendicular to the bottom wall of the trench 50.
[0050] The corners 51 within the trench 50 are either right angles or rounded corners. The corners 51 within the trench 50 include a top corner and a bottom corner. The top corner is located at the opening of the trench 50 and is the corner 51 formed by the sidewall of the trench 50 and the adjacent surface of the source region 41 away from the substrate 10. The bottom corner is the corner 51 formed by the sidewall of the trench 50 and the bottom wall of the trench 50. The top corner is either a rounded corner or a right angle, and / or, the bottom corner is either a rounded corner or a right angle.
[0051] For example, the bottom corner is rounded and the top corner is right angled. Designing the bottom corner as rounded can distribute the electric field more evenly and reduce the concentration of the electric field at the bottom corner, thereby improving the breakdown voltage of the device.
[0052] In some embodiments, the source region 41 is located at least in the body region 30 and is of a first conductivity type.
[0053] In some embodiments, such as Figure 1 As shown, cell 40 also includes a first doped region 42, which is epitaxially formed on the surface of body region 30 near trench 50 and located on the surface of drift region 20 away from substrate 10, and is in contact with the first gate oxide layer 61. The first doped region 42 is an in-situ doped region of the second conductivity type. Exemplarily, the first doped region 42 is formed by epitaxial growth of 3C-type SiC, thereby further reducing on-resistance.
[0054] For example, the source region 41 extends toward the substrate 10 from the side surface of the body region 30 away from the substrate 10, and extends from the surface of the first doped region 42 near the trench 50 into the body region 30.
[0055] The first doped region 42 forms a channel in the portion between the drift region 20 and the source region 41. Epitaxial formation of the channel reduces lattice damage within the channel, thereby reducing interface defects between the channel and the gate oxide layer 60 and improving channel mobility. Secondly, it avoids the tailing effect of ion implantation in the channel, thereby improving threshold voltage stability.
[0056] For example, in the arrangement direction of the cells 40, the width of the first doped region 42 is smaller than the width of the source region 41.
[0057] In other embodiments, such as Figure 2As shown, cell 40 also includes a first doped region 42, the doping of which is described above and will not be repeated here. The trench gate semiconductor device 1 also includes a second doped region 70 and a fifth doped region 80. Cell 40 also includes a third doped region 43, located on the side of body region 30 away from substrate 10. The second doped region 70 is located between the second gate oxide layer 62 and the drift region 20. The fifth doped region 80 is located within the first doped region 42, on the side of body region 30 closest to substrate 10, and is in contact with the second doped region 70. The source region 41 extends from the side of third doped region 43 away from substrate 10 into body region 30, and also extends from the surface of first doped region 42 near trench 50 into body region 30. The first doped region 42, second doped region 70, and third doped region 43 are formed from the same pre-fabricated epitaxial layer. The second doped region 70 and third doped region 43 are both in-situ doped regions of the second conductivity type, and the fifth doped region 80 is of the first conductivity type.
[0058] The pre-fabricated epitaxial layer is located on the outer wall of the trench 50 and also on the surface of the body region 30 away from the substrate 10. The gate oxide layer 60 is obtained by oxidizing the pre-fabricated epitaxial layer, and the second doped region 70 is formed from the unoxidized portion of the pre-fabricated epitaxial layer.
[0059] The second doped region 70 is located at the bottom of the trench 50 and is equipotentially connected to the source region 41.
[0060] Compared to the design of forming an implantation region at the bottom of the trench 50 by ion implantation in related technologies, the present invention uses a secondary epitaxial method to form a second doped region 70 at the bottom of the trench 50. The second doped region 70 has fewer ion defects and a better PN junction morphology, which can reduce the accumulation of electric field lines at the bottom corner of the trench 50, thereby reducing the peak electric field at the bottom corner and improving the breakdown voltage.
[0061] The fifth doped region 80 is used to space the first doped region 42 and the second doped region 70, serving as a current spread layer to prevent the first doped region 42 from being forward-biased. Since the doping concentration at the fifth doped region 80 is greater than the doping concentration at the drift region 20, the on-resistance can be reduced.
[0062] It is understood that the lateral width of the fifth doped region 80 may not be exactly the same as the width of the first doped region 42. In some embodiments, the lateral width of the fifth doped region 80 may be equal to the width of the first doped region 42; in other embodiments, the lateral width of the fifth doped region 80 may be greater than the width of the first doped region 42. Here, the width of the first doped region 42 can be set according to the device's on-resistance requirements and the doping concentration of the fifth doped region 80, thereby meeting the device's on-resistance requirements. It is known that, for a given on-resistance, the higher the doping concentration, the narrower the lateral width of the fifth doped region 80 can be; conversely, the lower the doping concentration, the wider the lateral width of the fifth doped region 80 can be.
[0063] For example, the source region 41 is located in the body region 30, the first doped region 42, and the second doped region 70. The portion of the first doped region 42 located between the source region 41 and the drift region 20 forms a channel.
[0064] In this embodiment, the pre-fabricated epitaxial layer is located on the outer wall of the trench 50, and the gate oxide layer 60 is formed by oxidizing the pre-fabricated epitaxial layer. This can repair the problem of large roughness of the sidewall of the trench 50 caused by etching during the etching process of forming the trench 50 on the body region 30, thereby reducing the influence of surface roughness scattering of the trench 50 on the channel mobility.
[0065] In some embodiments, the thickness of the second doped region 70 is 100 nm to 600 nm. The ion doping concentration of the second doped region 70 is greater than 1E16 cm⁻³.
[0066] In some embodiments, cell 40 further includes a body contact region 45 located between source regions 41 and extending from the side of source region 41 away from substrate 10 into drift region 20. The surface of body contact region 45 near substrate 10 is higher than the surface of trench 50 near substrate 10.
[0067] In some other embodiments, such as Figure 3 As shown, the source region 41 is epitaxially formed on the surface of the body region 30 away from the substrate 10, and is an in-situ doped region of the first conductivity type.
[0068] In some embodiments, cell 40 further includes a fourth doped region 44 located between source regions 41. The fourth doped region 44 extends from the side of source region 41 away from substrate 10 into drift region 20 and is of a second conductivity type. The surface of the fourth doped region 44 near substrate 10 is lower than the surface of trench 50 near substrate 10.
[0069] The fourth doped region 44 serves to shield the electric field at the corner 51 of the trench 50.
[0070] In some embodiments, the thickness of the body region 30 is 0.25 μm to 1 μm, and the ion doping concentration of the body region 30 is 1E16 cm⁻³ to 1E18 cm⁻³.
[0071] The thickness of the drift region 20 and the source region 41, as well as the ion doping concentration, are adjusted according to the device voltage.
[0072] In some embodiments, the end of the second gate oxide layer 62 away from the substrate 10 is at least 0.1 μm higher than the surface of the source region 41 near the substrate 10.
[0073] In some embodiments, the trench gate semiconductor device 1 further includes a gate electrode layer 90, an interlayer dielectric layer 100, an ohmic contact layer 110, and a source electrode layer 120.
[0074] Exemplarily, the gate electrode layer 90 is located within the trench 50, and the interlayer dielectric layer 100 covers the gate electrode layer 90 and is partially inserted within the trench 50. An ohmic contact layer 110 is located on the surface of the body region 30 away from the substrate 10 and is in contact with the source region 41. A source electrode layer 120 is located on the surface of the ohmic contact layer 110 away from the substrate 10. The interlayer dielectric layer 100 serves to insulate the gate electrode layer 90 and the source electrode layer 120.
[0075] There are no restrictions on the structure and materials of the gate electrode layer 90, the interlayer dielectric layer 100, the ohmic contact layer 110 and the source electrode layer 120; they can be selected according to actual needs.
[0076] Please see Figures 1 to 5 , Figure 4 This is a schematic flowchart of the first embodiment of the method for fabricating a trench gate semiconductor device provided in this disclosure. Figure 5 yes Figure 4 A schematic diagram of the structure corresponding to step S1.
[0077] This disclosure provides a method for fabricating a trench gate semiconductor device, used to fabricate the trench gate semiconductor device 1 described above. The steps of the method for fabricating the trench gate semiconductor device are as follows:
[0078] S1: Drift region 20 and body region 30 are epitaxially grown sequentially on substrate 10; both substrate 10 and drift region 20 are of the first conductivity type; body region 30 is an in-situ doped region of the second conductivity type.
[0079] Specifically, a drift region 20 and a bulk region 30 are epitaxially grown sequentially on a substrate 10.
[0080] For example, the first conductivity type is N-type and the second conductivity type is P-type.
[0081] In some implementations, step S1 is followed by:
[0082] S2: Multiple cells 40 and grooves 50 located between cells 40 are provided in the body region 30.
[0083] Specifically, a plurality of cells 40 and trenches 50 located between the cells 40 are provided in the body region 30. The cells 40 are located at least in the body region 30. The cells 40 include source regions 41. The trenches 50 are located between the source regions 41 and extend from the surface of the source regions 41 away from the substrate 10 into the drift region 20.
[0084] The structures of source region 41 and trench 50 are as described above and will not be repeated here.
[0085] Please see Figures 1 to 8 , Figure 6 yes Figure 4 A flowchart illustrating the implementation method of step S2. Figure 7 yes Figure 6 S211 to S214 are schematic diagrams of the structures corresponding to one embodiment. Figure 8 This is a schematic diagram of the structure of one embodiment of the contact area of the body provided in this disclosure.
[0086] In some embodiments, step S2: setting a plurality of cells 40 and grooves 50 located between cells 40 in the body region 30 specifically includes:
[0087] S211: A first groove 101 is formed on the body region 30, and a first doped region 42 is epitaxially grown on the inner sidewall of the first groove 101; the surface of the first groove 101 away from the substrate 10 of the body region 30 extends to the surface of the drift region 20 close to the substrate 10; the first doped region 42 is an in-situ doped region of the second conductivity type.
[0088] Specifically, a first groove 101 is formed on the body region 30. The first groove 101 is located on the side of the drift region 20 away from the substrate 10 and passes through the body region 30.
[0089] An epitaxial layer is grown in the first groove 101 and on the surface of the body region 30 away from the substrate 10. The epitaxial layer located at the bottom of the first groove 101 and on the surface of the body region 30 away from the substrate 10 is etched away, while the epitaxial layer located on the inner sidewall of the trench 50 is retained to form the first doped region 42.
[0090] The structure of the first doped region 42 is as described above and will not be repeated here.
[0091] S212: A second groove 102 is formed on the surface of the drift area 20 exposed to the first groove 101; the second groove 102 is located at the bottom of the first groove 101 and communicates with the bottom wall of the first groove 101.
[0092] Specifically, a second groove 102 is formed on the surface of the drift region 20 exposed by the first groove 101 through the first groove 101. The second groove 102 is located on the side of the first groove 101 close to the substrate 10 and is connected to the bottom wall of the first groove 101.
[0093] The width of the second groove 102 is smaller than the width of the first groove 101.
[0094] In some implementations, steps 211 and 212 can be performed simultaneously.
[0095] For example, during the process of etching the epitaxial layer to form the first doped region 42, the second groove 102 can be formed simultaneously when etching the epitaxial layer at the bottom of the first groove 101, which can simplify the process steps.
[0096] S213: Doping the body region 30 and the first doped region 42 to form a source region 41; the source region 41 extends from the side surface of the body region 30 away from the substrate 10 toward the substrate 10, and extends from the surface of the first doped region 42 away from the body region 30 into the body region 30.
[0097] Specifically, the body region 30 and the first doped region 42 are doped to form the source region 41. The source region 41 is located at the top corner of the first groove 101. The first doped region 42 is partially doped to form the source region 41. The source region 41 extends from the surface of the body region 30 away from the substrate 10 toward the substrate 10, and extends from the surface of the first doped region 42 away from the body region 30 into the body region 30.
[0098] S214: The surface of the first doped region 42 away from the body region 30 and the surface of the drift region 20 exposed in the second groove 102 are oxidized to obtain the gate oxide layer 60, and the gate oxide layer 60 surrounds the trench 50.
[0099] Specifically, the surface of the first doped region 42 away from the body region 30 and the surface of the drift region 20 exposed in the second groove 102 are oxidized to obtain the gate oxide layer 60.
[0100] The surface of the first doped region 42 away from the body region 30 and the portion of the drift region 20 along the sidewall of the second groove 102 are oxidized to form a first gate oxide layer 61, and the portion of the drift region 20 along the bottom wall of the second groove 102 is oxidized to form a second gate oxide layer 62. The first gate oxide layer 61 and the second gate oxide layer 62 together form a trench 50.
[0101] In some embodiments, the trench gate semiconductor device 1 further includes a body contact region 45. The step S1 is followed by forming the body contact region 45.
[0102] Specifically, the body region 30 and the drift region are doped to form a body contact region 45, which extends from the side of the body region 30 away from the substrate 10 into the drift region 20.
[0103] The structure of the body contact area 45 is as described above and will not be repeated here.
[0104] For example, the body contact area 45 is prepared after step S213 and before step S214.
[0105] In other embodiments, the body contact area 45 may be prepared prior to any of steps S211 to S214.
[0106] Please see Figures 1 to 11 , Figure 9 This is a flowchart illustrating a second embodiment of the trench gate semiconductor device provided in this disclosure. Figure 10 yes Figure 9 A flowchart illustrating the implementation method of step S2. Figure 11 yes Figure 10 Schematic diagrams of the structures corresponding to one embodiment of steps S221 to S225.
[0107] In another embodiment, step S1 is followed by:
[0108] Step S2: A plurality of cells 40 and trenches 50 located between the cells 40 are provided on the side of the drift region 20 away from the substrate 10; the cells 40 are located at least in the body region 30.
[0109] In some embodiments, step S2: setting a plurality of cells 40 and grooves 50 located between cells 40 in the body region 30 specifically includes:
[0110] S221: A third groove 103 is formed on the body region 30; the third groove 103 extends from the surface of the body region 30 away from the substrate 10 into the drift region 20.
[0111] Specifically, a third groove 103 is formed on the body region 30. The third groove 103 extends from the surface of the body region 30 away from the substrate 10 into the drift region 20.
[0112] S222: A first pre-epitaxial layer 105 is grown in the third groove 103 and on the surface of the body region 30 away from the substrate 10; the first pre-epitaxial layer 105 is of the second conductivity type; the portion of the first pre-epitaxial layer 105 along the surface of the body region 30 away from the substrate 10 is configured as a third doped region 43, and the portion along the sidewall of the third groove 103 is configured as a first doped region 42.
[0113] Specifically, a first pre-fabricated epitaxial layer 105 is grown within the third groove 103 and on the surface of the body region 30 away from the substrate 10. The first pre-fabricated epitaxial layer 105 is of a second conductivity type. The portion of the first pre-fabricated epitaxial layer 105 along the surface of the body region 30 away from the substrate 10 is configured as a third doped region 43, and the portion along the sidewall of the third groove 103 is configured as a first doped region 42.
[0114] In some embodiments, step S222 specifically includes: growing a first pre-fabricated epitaxial layer 105 in the third groove 103 and on the surface of the body region 30 away from the substrate 10, and making the growth rate of the first pre-fabricated epitaxial layer 105 on the bottom wall of the third groove 103 greater than the growth rate of the first pre-fabricated epitaxial layer 105 on the side wall of the third groove 103.
[0115] By controlling the growth rate of the first pre-fabricated epitaxial layer 105 on the bottom wall of the third groove 103 to be greater than the growth rate of the first pre-fabricated epitaxial layer 105 on the side wall of the third groove 103, the thickness of the first pre-fabricated epitaxial layer 105 on the bottom wall of the third groove 103 is made greater than the thickness of the first pre-fabricated epitaxial layer 105 on the side wall of the third groove 103. This facilitates the formation of a second doped region 70 of a certain thickness in subsequent steps, avoiding the second doped region 70 being too thin to effectively shield the electric field at the corner 51 of the trench 50.
[0116] In other embodiments, the growth rate of the first pre-epitaxial layer 105 on the bottom wall of the third trench 103 can be equal to the growth rate of the first pre-epitaxial layer 105 on the side wall of the third trench 103, that is, the trench gate semiconductor device 1 finally formed does not include the second doped region 70.
[0117] S223: The portion of the first pre-epitaxial layer 105 along the inner sidewall of the third groove 103, the portion of the first pre-epitaxial layer 105 along the surface of the body region 30 away from the substrate 10, and the body region 30 are doped to form the source region 41.
[0118] Specifically, the portion of the first pre-epitaxial layer 105 along the inner sidewall of the third groove 103, the portion of the first pre-epitaxial layer 105 along the surface of the body region 30 away from the substrate 10, and the body region 30 are doped to form the source region 41.
[0119] The source region 41 is located at the top corner of the third groove 103. The source region 41 extends from the surface of the third doped region 43 away from the substrate 10 into the body region 30, and also extends from the surface of the first doped region 42 away from the body region 30 into the body region 30.
[0120] S224: The portion of the first doped region 42 located in the body region 30 near the substrate 10 is inverted to form a fifth doped region 80; the fifth doped region 80 is of the first conductivity type.
[0121] Specifically, the portion of the first doped region 42 located in the body region 30 near the substrate 10 is inverted to form the fifth doped region 80.
[0122] The structure of the fifth doped region 80 is as described above and will not be repeated here.
[0123] It should be noted that when the trench gate semiconductor device 1 does not include the second doped region 70, there is no need to form the fifth doped region 80.
[0124] In other embodiments, the fifth doped region 80 may be formed before the source region 41, that is, step S224 may be formed before step 223.
[0125] S225: The first pre-fabricated epitaxial layer 105 is oxidized to obtain a gate oxide layer 60; the portion of the first pre-fabricated epitaxial layer 105 along the inner sidewall of the third groove 103 is oxidized to form a first gate oxide layer 61, the portion along the inner bottom wall of the third groove 103 is oxidized to form a second gate oxide layer 62, and the unoxidized portion along the inner bottom wall of the third groove 103 forms a second doped region 70; the first gate oxide layer 61 and the second gate oxide layer 62 form a trench 50; the third doped region 43 is located between the second gate oxide layer 62 and the body region 30; the fifth doped region 80 is disposed in contact with the second doped region 70.
[0126] Specifically, the first pre-fabricated epitaxial layer 105 is oxidized to obtain a gate oxide layer 60. A portion of the first pre-fabricated epitaxial layer 105 along the inner sidewall of the third groove 103 is oxidized to form a first gate oxide layer 61, a portion along the inner bottom wall of the third groove 103 is oxidized to form a second gate oxide layer 62, and the unoxidized portion along the inner bottom wall of the third groove 103 forms a second doped region 70. The first gate oxide layer 61 and the second gate oxide layer 62 together form a trench 50. A third doped region 43 is located between the second gate oxide layer 62 and the body region 30. A fifth doped region 80 is disposed in contact with the second doped region 70.
[0127] In other embodiments, after step S1, the method further includes forming a body contact region 45. The doping order of the body contact region 45 and the source region 41 is not limited here and can be selected according to actual needs.
[0128] Please see Figures 1 to 14 , Figure 12 This is a flowchart illustrating a third embodiment of the trench gate semiconductor device provided in this disclosure. Figure 13 yes Figure 12 A flowchart illustrating the implementation method of step S2. Figure 14 yes Figure 13 Schematic diagrams of the structures corresponding to one of the embodiments of steps S231 to S235.
[0129] In yet another embodiment, step S1 is followed by:
[0130] S2: A plurality of cells 40 and trenches 50 located between cells 40 are provided on the side of the drift region 20 away from the substrate 10; the cells 40 are located at least in the body region 30.
[0131] In some embodiments, step S2: the specific steps of forming a plurality of cells 40 and trenches 50 located between the cells 40 on the side of the drift region 20 away from the substrate 10 include:
[0132] S231: A second pre-epitaxial layer 106 is epitaxially grown on the surface of the bulk region 30 away from the substrate 10; the second pre-epitaxial layer 106 is of the first conductivity type.
[0133] Specifically, a second pre-epitaxial layer 106 is epitaxially grown on the surface of the body region 30 away from the substrate 10. The second pre-epitaxial layer 106 is of a first conductivity type.
[0134] S232: A fourth groove 104 is formed on the second pre-epitaxial layer 106; the fourth groove 104 extends from the surface of the second pre-epitaxial layer 106 away from the substrate 10 into the drift region 20.
[0135] Specifically, a fourth groove 104 is formed on the second pre-epitaxial layer 106, and the fourth groove 104 extends from the surface of the second pre-epitaxial layer 106 away from the substrate 10 to the drift region 20.
[0136] S233: A fourth doped region 44 of a cell 40 is formed on the surface of the second pre-epitaxial layer 106 away from the substrate 10; the fourth doped region 44 extends from the surface of the second pre-epitaxial layer 106 away from the substrate 10 into the drift region 20 and is of the second conductivity type.
[0137] Specifically, the second pre-fabricated epitaxial layer 106, the body region 30, and the drift region 20 are doped to form a fourth doped region 44.
[0138] In some embodiments, the fourth doped region 44 may be prepared before the fourth groove 104, that is, before step S233 and step S232.
[0139] S234: The portion of the second pre-fabricated epitaxial layer 106 located between the fourth doped region 44 and the trench 50 is configured as the source region 41 of the cell 40, and the source region 41 is an in-situ doped region of the first conductivity type.
[0140] Specifically, the portion of the second pre-fabricated epitaxial layer 106 located between the fourth doped region 44 and the trench 50 is configured as the source region 41 of the cell 40, and the source region 41 is an in-situ doped region of the first conductivity type.
[0141] S235: The surface of the fourth groove 104 is oxidized to obtain a gate oxide layer 60; the side wall of the fourth groove 104 is oxidized to form a first gate oxide layer 61, the bottom wall of the fourth groove 104 is oxidized to form a second gate oxide layer 62, and the first gate oxide layer 61 and the second gate oxide layer 62 form a trench 50.
[0142] Specifically, the surface of the fourth groove 104 is oxidized to obtain a gate oxide layer 60; the sidewall of the fourth groove 104 is oxidized to form a first gate oxide layer 61, the bottom wall of the fourth groove 104 is oxidized to form a second gate oxide layer 62, and the first gate oxide layer 61 and the second gate oxide layer 62 form a trench 50.
[0143] Please see Figures 1 to 15 , Figure 15 This is a schematic diagram of a structure corresponding to an embodiment of the present disclosure that forms a gate electrode layer, an interlayer dielectric layer, an ohmic contact layer, and a source electrode layer.
[0144] In some embodiments, step S2 is followed by: sequentially forming a gate electrode layer 90, an interlayer dielectric layer 100, an ohmic contact layer 110, and a source electrode layer 120.
[0145] Exemplarily, the gate electrode layer 90 is located within the trench 50, and the interlayer dielectric layer 100 covers the gate electrode layer 90 and is partially inserted within the trench 50. An ohmic contact layer 110 is located on the surface of the body region 30 away from the substrate 10 and is in contact with the source region 41. A source electrode layer 120 is located on the surface of the ohmic contact layer 110 away from the substrate 10. The interlayer dielectric layer 100 serves to insulate the gate electrode layer 90 and the source electrode layer 120.
[0146] The structure of the gate electrode layer 90, the interlayer dielectric layer 100, the ohmic contact layer 110 and the source electrode layer 120 can also be other structures. There are no major restrictions here, and the selection can be made according to actual needs.
[0147] For example, the interlayer dielectric layer 100 may be one or more of SIO2, SION, BPSG, and SIN.
[0148] For example, the ohmic contact layer 110 may be formed by high-temperature nickel tempering, high-temperature titanium tempering, or an alloy of the two tempering.
[0149] There are no restrictions on the fabrication methods and materials of the gate electrode layer 90, interlayer dielectric layer 100, ohmic contact layer 110 and source electrode layer 120; they can be selected according to actual needs.
[0150] The above description is merely an implementation method of the present disclosure and does not limit the patent scope of the present disclosure. Any equivalent structural or procedural transformations made based on the description and drawings of the present disclosure, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present disclosure.
Claims
1. A trench gate semiconductor device, characterized in that, include: Substrate; A drift region is disposed on the surface of the substrate, and both the drift region and the drift region are of the first conductivity type. The body region is epitaxially formed on the surface of the drift region away from the substrate and is an in-situ doped region of the second conductivity type.
2. The trench gate semiconductor device according to claim 1, characterized in that, The trench gate semiconductor device further includes multiple cells, trenches, and a gate oxide layer, wherein the cells are located at least in the body region; the cells have source regions; The trench is located between the cells and extends from the surface of the source region away from the substrate into the drift region; The gate oxide layer includes a first gate oxide layer and a second gate oxide layer connected to each other, wherein the first gate oxide layer is at least partially located on the outer wall of the trench, and the second gate oxide layer is located on the outer bottom wall of the trench.
3. The trench gate semiconductor device according to claim 2, characterized in that, The source region is located at least within the body region and is of the first conductivity type.
4. The trench gate semiconductor device according to claim 3, characterized in that, The cell further includes a first doped region, which is epitaxially formed on the surface of the body region near the trench and located on the surface of the drift region away from the substrate, and is in contact with the first gate oxide layer; the first doped region is an in-situ doped region of the second conductivity type.
5. The trench gate semiconductor device according to claim 4, characterized in that, The source region extends from the side of the body region away from the substrate toward the substrate, and extends from the surface of the first doped region near the trench into the body region.
6. The trench gate semiconductor device according to claim 4, characterized in that, The trench gate semiconductor device further includes a second doped region and a fifth doped region. The cell also includes a third doped region, which is located on the side of the body region away from the substrate. The second doped region is located between the second gate oxide layer and the drift region. The fifth doped region is located within the first doped region and on the side of the body region near the substrate, and is in contact with the second doped region. The source region extends from the side of the third doped region away from the substrate into the body region, and extends from the surface of the first doped region near the trench into the body region. The first doped region, the second doped region, and the third doped region are formed by the same pre-fabricated epitaxial layer. The second doped region and the third doped region are both in-situ doped regions of the second conductivity type, and the fifth doped region is of the first conductivity type.
7. The trench gate semiconductor device according to claim 6, characterized in that, The pre-fabricated epitaxial layer is located on the outer wall of the trench and also on the surface of the body region away from the substrate; the gate oxide layer is obtained by oxidizing the pre-fabricated epitaxial layer, and the second doped region is formed by the unoxidized portion of the pre-fabricated epitaxial layer.
8. The trench gate semiconductor device according to claim 6, characterized in that, The thickness of the second doped region is 100 nm to 600 nm; the ion doping concentration of the second doped region is greater than 1 E16 cm-3.
9. The trench gate semiconductor device according to claim 4, characterized in that, The cell further includes a body contact region located between the source regions and extending from the side of the source region away from the substrate into the drift region; the surface of the body contact region near the substrate is higher than the surface of the trench near the substrate.
10. The trench gate semiconductor device according to claim 2, characterized in that, The source region is epitaxially formed on the surface of the body region away from the substrate, and is an in-situ doped region of the first conductivity type.
11. The trench gate semiconductor device according to claim 10, characterized in that, The cell further includes a fourth doped region located between the source regions; the fourth doped region extends from the side of the source region away from the substrate into the drift region and is of the second conductivity type; the surface of the fourth doped region near the substrate is lower than the surface of the trench near the substrate.
12. The trench gate semiconductor device according to claim 10, characterized in that, The thickness of the body region is 0.25 μm to 1 μm, and the ion doping concentration of the body region is 1E16 cm⁻³ to 1E18 cm⁻³.
13. The trench gate semiconductor device according to claim 10, characterized in that, The end of the second gate oxide layer away from the substrate is at least 0.1 μm higher than the surface of the source region near the substrate.
14. A method for fabricating a trench gate semiconductor device, characterized in that, include: The drift region and the bulk region are epitaxially grown sequentially on the substrate; Both the substrate and the drift region are of the first conductivity type; The body region is an in-situ doped region of the second conductivity type.
15. The method for fabricating a trench gate semiconductor device according to claim 14, characterized in that, The process of sequentially epitaxially growing a drift region and a bulk region on the substrate further includes: Multiple cells and grooves located between the cells are provided in the body region.
16. The method for fabricating a trench gate semiconductor device according to claim 15, characterized in that, The provision of multiple cells and grooves between the cells in the body region includes: A first groove is formed on the body region, and a first doped region is epitaxially grown on the inner sidewall of the first groove; the first groove extends from the side surface of the body region away from the substrate to the side surface of the drift region close to the substrate; the first doped region is an in-situ doped region of the second conductivity type. A second groove is formed on the surface of the drift area exposed above the first groove; the second groove is located at the bottom of the first groove and communicates with the bottom wall of the first groove; The body region and the first doped region are doped to form a source region; the source region extends from the surface of the body region away from the substrate toward the substrate, and extends from the surface of the first doped region away from the body region into the body region; The surface of the first doped region away from the body region and the surface of the drift region exposed in the second trench are oxidized to obtain a gate oxide layer, which surrounds the trench.
17. The method for fabricating a trench gate semiconductor device according to claim 14, characterized in that, The process of sequentially epitaxially growing a drift region and a bulk region on the substrate further includes: A plurality of cells and trenches located between the cells are provided on the side of the drift region away from the substrate; the cells are located at least in the body region.
18. The method for fabricating a trench gate semiconductor device according to claim 17, characterized in that, The provision of multiple cells and trenches between the cells on the side of the drift region away from the substrate includes: A third groove is formed on the body region; the third groove extends from the surface of the body region away from the substrate into the drift region; A first pre-epitaxial layer is grown in the third groove and on the surface of the body region away from the substrate; the first pre-epitaxial layer is of a second conductivity type; a portion of the first pre-epitaxial layer along the surface of the body region away from the substrate is configured as a third doped region, and a portion along the sidewall of the third groove is configured as a first doped region; The portion of the first pre-epitaxial layer along the inner sidewall of the third groove, the portion of the first pre-epitaxial layer along the surface of the body region away from the substrate, and the body region are doped to form a source region; The portion of the first doped region located near the substrate in the bulk region is inverted and doped to form a fifth doped region; the fifth doped region is of the first conductivity type. The first pre-fabricated epitaxial layer is oxidized to obtain a gate oxide layer; a portion of the first pre-fabricated epitaxial layer along the inner sidewall of the third groove is oxidized to form a first gate oxide layer, a portion along the inner bottom wall of the third groove is oxidized to form a second gate oxide layer, and a second doped region is formed along the unoxidized portion of the inner bottom wall of the third groove; the first gate oxide layer and the second gate oxide layer form a trench; the third doped region is located between the second gate oxide layer and the body region; the fifth doped region is in contact with the second doped region.
19. The method for fabricating a trench gate semiconductor device according to claim 18, characterized in that, The growth of a first pre-fabricated epitaxial layer within the third groove and on the surface of the body region away from the substrate includes: The first pre-epitaxial layer is grown in the third groove and on the surface of the body region away from the substrate, and the growth rate of the first pre-epitaxial layer on the bottom wall of the third groove is greater than the growth rate of the first pre-epitaxial layer on the side wall of the third groove.
20. The method for fabricating a trench gate semiconductor device according to claim 14, characterized in that, The process of sequentially epitaxially growing a drift region and a bulk region on the substrate further includes: A plurality of cells and trenches located between the cells are provided on the side of the substrate near the body region; the cells are located at least in the body region.
21. The method for fabricating a trench gate semiconductor device according to claim 20, characterized in that, The provision of multiple cells and trenches between the cells on the side of the substrate near the body region includes: A second pre-epitaxial layer is epitaxially grown on the surface of the body region away from the substrate; the second pre-epitaxial layer is of a first conductivity type; A fourth groove is formed on the second pre-epitaxial layer; the fourth groove extends from the surface of the second pre-epitaxial layer away from the substrate into the drift region; A fourth doped region of the cell is formed on the surface of the second pre-epitaxial layer away from the substrate; the fourth doped region extends from the surface of the second pre-epitaxial layer away from the substrate into the drift region and is of the second conductivity type; The portion of the second pre-fabricated epitaxial layer located between the fourth doped region and the trench is configured as the source region of the cell, and the source region is an in-situ doped region of the first conductivity type; The surface of the fourth groove is oxidized to obtain a gate oxide layer; the sidewall of the fourth groove is oxidized to form a first gate oxide layer, and the bottom wall of the fourth groove is oxidized to form a second gate oxide layer. The first gate oxide layer and the second gate oxide layer form a trench.