High aspect ratio metal gate cut

Abstract

Provided herein are techniques to form semiconductor devices that include one or more gate cuts having very high aspect ratios (e.g., aspect ratios of 5: 1 or greater, e.g., 10: 1). In examples, a semiconductor device includes a conductive material that is part of a transistor gate structure that surrounds a semiconductor region or is otherwise located on a semiconductor region. For example, the semiconductor region can be a fin of semiconductor material that extends between a source region and a drain region, or can be one or more nanowires or nanoribbons of semiconductor material that extend between a source region and a drain region. A gate cut that extends through an entire thickness of the gate structure can be employed to interrupt the gate structure between two transistors. A particular plasma etch process can be performed to form the gate cut with a very high height-to-width aspect ratio, enabling dense integrated devices.

Description

[0001] This application is a divisional application. The original application was filed with the China Patent Office on August 28, 2023, with application number 202311092456.0 and invention title "High Aspect Ratio Metal Gate Cutout". Technical Field

[0002] This disclosure relates to integrated circuits, and more particularly to metal gate cutouts fabricated in semiconductor devices. Background Technology

[0003] As integrated circuits continue to shrink in size, numerous challenges arise. For example, it becomes increasingly difficult to reduce the size of memory cells and logic cells, and reducing device spacing at device layers also becomes increasingly challenging. With the denser packing of transistors, the formation of certain device structures used to isolate adjacent transistors becomes challenging. Accordingly, there are many significant challenges in forming semiconductor devices. Attached Figure Description

[0004] Figure 1A and Figure 1B These are cross-sectional and plan views of some semiconductor devices according to embodiments of the present disclosure, showing gate cutouts with high aspect ratios between the devices.

[0005] Figure 2A-2N This is a cross-sectional view illustrating various stages in an exemplary process for forming a semiconductor device with a high aspect ratio gate cutout, according to some embodiments of the present disclosure.

[0006] Figure 3 A cross-sectional view of a chip package comprising one or more semiconductor dies according to some embodiments of the present disclosure is shown.

[0007] Figure 4 This is a flowchart of the fabrication process of a semiconductor device including a gate cutout with a high aspect ratio, according to embodiments of the present disclosure.

[0008] Figure 5 This is a flowchart of a more detailed fabrication process for forming a gate notch with a high aspect ratio, according to embodiments of the present disclosure.

[0009] Figure 6 A computing system comprising one or more integrated circuits described herein in various ways is illustrated according to embodiments of the present disclosure.

[0010] Although the detailed descriptions below are given with reference to exemplary embodiments, many alternatives, modifications, and variations of these embodiments will be apparent from this disclosure. It should also be understood that the drawings are not necessarily drawn to scale and are not intended to limit this disclosure to the specific configurations shown. For example, while some drawings generally indicate ideal straight lines, right angles, and smooth surfaces, actual implementations of integrated circuit structures may have less than ideal straight lines and right angles (e.g., some features may have tapered sidewalls and / or rounded corners), and some features may have surface topography or otherwise exhibit non-smoothness, given the real-world limitations of the fabrication equipment and techniques used. Detailed Implementation

[0011] This document provides techniques for forming semiconductor devices that include one or more gate cutouts with very high height-to-width ratios (e.g., 5:1 or greater, such as 10:1 or 11:1). These techniques can be used in any number of integrated circuit applications and are particularly useful for device-layer transistors such as finFETs or gate-all-around transistors (e.g., strip FETs or nanowire FETs). In the examples, the semiconductor device includes a gate structure surrounding or otherwise situated on a semiconductor region. For example, the semiconductor region may be a fin of semiconductor material extending from the source region to the drain region, or it may be one or more nanowires or nanoribbons of semiconductor material extending from the source region to the drain region. The gate structure includes a gate dielectric (e.g., a high-k gate dielectric material) and a gate electrode (e.g., a conductive material, such as a work function material, and / or a gate-fill metal). For example, a gate cutout may be used to interrupt the gate structure between two transistors, the gate cutout extending through the entire thickness of the gate structure and including a dielectric material that electrically isolates portions of the gate structure on either side of the gate cutout. Specific plasma etching processes can be performed to form gate cutouts with very high height-to-width ratios (e.g., 5:1 or higher, or 10:1 or higher, or 11:1 or higher) and low taper or even no taper, thereby enabling densely integrated devices. Many variations and embodiments will be apparent in light of this disclosure.

[0012] General Overview As noted earlier, there are many significant challenges in integrated circuit fabrication. More specifically, as devices become smaller and more densely packed, many structures become more difficult to fabricate because their critical dimensions (CD) are pushing current fabrication techniques to their limits. Exemplary structures such as gate nicks are used in integrated circuit designs to isolate gate structures from each other. One possible way to form a gate nick is using a gate patterning scheme via a poly-cut process, in which the gate nick is formed before the final metal gate is formed. Another approach is to use a gate patterning scheme via a metal gate dicing process. Such schemes typically etch trenches or other recesses through the thickness of the polysilicon or metal gate structure and fill the trenches with a dielectric material. Gate nicks formed after the metal gate structure can have some advantages compared to gate nicks formed during the polysilicon dicing process. However, such metal gate nicks tend to be relatively wide at the trench opening and / or include a significant amount of taper from the top to the bottom of the gate nick (e.g., sidewall tapers exceeding 8 nm). This is especially true for gate cutouts with a high length-to-width ratio (e.g., 5:1 or higher).

[0013] Therefore, according to embodiments of this disclosure, techniques for forming gate cutouts with high length-to-width ratios through the metal gate structure are provided herein. The gate cutouts have an aspect ratio of 5:1 or higher (e.g., 9:1, 10:1, 11:1, or even greater). A plasma-based etching process is described, which provides sidewalls with near-vertical profiles (e.g., sidewall tapers less than 2 nm or sidewall angles between 87° and 90°) and good selectivity relative to the dielectric spacer, mask material, and epitaxial regions (e.g., source or drain regions). The plasma etching process exhibits superior selectivity, allows for reduced operability / variability, demonstrates excellent material compatibility, and shows manufacturability with a cost reduction of approximately 25-35%.

[0014] According to some embodiments, the plasma etching process uses a repeated series of finely tuned passivation and etching processes to slowly etch portions of the gate electrode, thereby maintaining verticality (low taper or even no taper) throughout the etching process. Different etching chemicals are used to break through the passivation layer and etch the metal of the gate electrode. Furthermore, various flash operations can be performed during each cycle to remove etching byproducts from the sidewalls and further protect the sidewalls from future etching cycles (e.g., maintaining the verticality of the etching). Further details of the plasma etching process are described below.

[0015] According to an embodiment, an integrated circuit includes: a first semiconductor device having a first semiconductor region extending from a first source region along a first direction to a first drain region, and a first gate structure extending over the first semiconductor region along a second direction; a second semiconductor device having a second semiconductor region extending from a second source region along a first direction to a second drain region, and a second gate structure extending over the second semiconductor region along a second direction; and a gate cutout located between the first gate structure and the second gate structure and separating the first gate structure and the second gate structure. The gate cutout comprises a dielectric material and has a height-to-width ratio of at least 5:1 (e.g., at least 9:1 or at least 10:1). The first and second semiconductor regions may be fins of semiconductor material, or may each comprise a plurality of semiconductor nanoribbons or nanowires extending longitudinally along the first direction.

[0016] According to an embodiment, an integrated circuit includes: a first semiconductor device having a first semiconductor region extending from a first source region along a first direction to a first drain region, and a first gate structure extending over the first semiconductor region along a second direction; a second semiconductor device having a second semiconductor region extending from a second source region along a first direction to a second drain region, and a second gate structure extending over the second semiconductor region along a second direction; and a gate cutout located between the first gate structure and the second gate structure and separating the first gate structure and the second gate structure. The gate cutout includes a dielectric material and has a sidewall taper of less than 2 nm between the top surface of the first gate structure and the bottom surface of the second gate structure.

[0017] According to another embodiment, a method of forming an integrated circuit includes: forming a first fin comprising a semiconductor material and a second fin comprising a semiconductor material, the first fin and the second fin extending over a substrate and both extending along a first direction; forming a gate structure extending over the first fin and the second fin along a second direction different from the first direction; forming a recess through the gate structure between the first fin and the second fin; and forming a dielectric material within the recess. Forming the recess through the gate structure further includes: (i) forming an opening through a hard mask layer located over the gate structure; (ii) forming a liner material within the opening; (iii) forming a passivation layer within the opening; (iv) etching at least through the passivation layer located at the bottom of the opening; (v) etching through a portion of the gate structure; and (vi) repeating (iii)-(v) until the recess extends through at least the entire thickness of the gate structure.

[0018] This technology can be used for any type of nonplanar transistor, including finFETs (sometimes called tri-gate transistors), nanowire and nanoribbon transistors (sometimes called gate-all-around transistors), or forked transistors, to name just a few examples. The source and drain regions can be, for example, doped portions of a given fin or substrate, or epitaxial regions deposited during etching and replacement source / drain formation processes. The type of dopant in the source and drain regions will depend on the polarity of the corresponding transistor. The gate structure can be implemented using either a gate-before or gate-after process (sometimes called a replacement metal gate or RMG process). Any number of semiconductor materials can be used when forming the transistor, such as group IV materials (e.g., silicon, germanium, silicon-germanium) or group III-V materials (e.g., gallium arsenide, gallium arsenide indium).

[0019] The use of the techniques and structures provided herein can be detected using tools such as: electron microscopy including scanning / transmission electron microscopy (SEM / TEM), scanning transmission electron microscopy (STEM), nanobeam electron diffraction (NBD or NBED), and reflection electron microscopy (REM); compositional mapping; X-ray crystallography or diffraction (XRD); energy-dispersive X-ray spectroscopy (EDX); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atomic probe imaging or tomography; local electrode atomic probe (LEAP) technology; 3D tomography; or high-resolution physical or chemical analysis, to name only a few suitable exemplary analytical tools. For example, in some exemplary embodiments, such tools can indicate the presence of a gate cutout with a height-to-width ratio greater than 5:1 or 10:1 or even higher. In some such examples, the gate cutout may have a sidewall taper of less than 2 nm between the top surface and the bottom surface of the surrounding gate structure. Certain SEM or TEM cross-sections through the gate trench can also indicate that the gate dielectric located on the semiconductor region is not present on any sidewalls of the gate cutout. Given this disclosure, many constructions and variations will be obvious.

[0020] It should be understood that the meanings of "on" and "above" in this disclosure should be interpreted in the broadest possible sense, such that "above" and "above" not only refer to "directly located on" something, but also include the meaning of being located above something with an intermediate feature or layer between them. Furthermore, for ease of explanation, spatially relative terms such as "below," "below," "lower part," "above," "upper part," "top," "bottom," etc., may be used to describe the relationship between one element or feature and another element(s) or feature as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation other than those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly in a similar manner.

[0021] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A monoatomous layer is a layer consisting of a single layer of atoms of a given material. A layer may extend over the entire underlying or overlying structure, or may have a smaller extent than the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure, and the layer may have a thickness less than that of the continuous structure. For example, a layer may lie between any pair of horizontal planes between the top and bottom surfaces of a continuous structure, or at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a conical surface. A layer may conform to a given surface (whether flat or curved) with a relatively uniform thickness across the entire layer.

[0022] As used herein, “materials that are different in composition” or “materials with different compositions” refers to two materials with different chemical compositions. For example, this difference in composition may be due to one element being present in one material but not in the other (e.g., SiGe is different in composition from silicon), or due to one material having all the same elements as the second material, but intentionally providing at least one of these elements at a different concentration relative to the other material (e.g., SiGe with 70 atomic percent germanium is different in composition from SiGe with 25 atomic percent germanium). In addition to such differences in chemical composition, materials may also have different dopants (e.g., gallium and magnesium) or may have the same dopants at different concentrations. In other embodiments, materials with different compositions may also refer to two materials with different crystallographic orientations. For example, (110) silicon is different in composition from (100) silicon. The construction of stacks with different orientations may be achieved using, for example, uniform-thickness wafer layer transfer. If the two materials are different in elements, then one of the materials has elements different from those in the other material.

[0023] Architecture Figure 1A A cross-sectional view taken across two exemplary semiconductor devices 101 and 103 according to an embodiment of the present disclosure is shown. Figure 1B These are top-down views of adjacent semiconductor devices 101 and 103, where... Figure 1A A cross-sectional view taken across the dotted line is shown. It should be noted that... Figure 1B For clarity, some material layers (e.g., gate electrodes 118a and 118b) are omitted in the top-down view. Each of the semiconductor devices 101 and 103 can be a non-planar metal-oxide-semiconductor (MOS) transistor, such as a tri-gate transistor (e.g., a finFET) or a gate-all-around (GAA) transistor, but other transistor topologies and types can also benefit from the techniques provided herein. The embodiments illustrated herein use a GAA structure. Semiconductor devices 101 and 103 represent portions of an integrated circuit that can contain any number of similar semiconductor devices.

[0024] As can be seen, semiconductor devices 101 and 103 are formed on substrate 102. Any number of semiconductor devices can be formed on substrate 102, but two are used here as examples. Substrate 102 can be, for example, a bulk substrate comprising group IV semiconductor materials (e.g., silicon, germanium, or silicon-germanium), group III-V semiconductor materials (e.g., gallium arsenide, indium gallium arsenide, or indium phosphide), and / or any other suitable material capable of forming transistors thereon. Alternatively, substrate 102 can be a semiconductor-on-insulator substrate having a desired semiconductor layer (e.g., silicon over silicon dioxide) located above a buried insulating layer. Alternatively, substrate 102 can be a multilayer substrate or superlattice suitable for forming nanowires or nanoribbons (e.g., alternating silicon and SiGe layers, or alternating indium gallium arsenide and indium phosphide layers). Any number of substrates can be used. In some embodiments, a lower portion (or the entire substrate 102) is removed and replaced with one or more back-side interconnect layers to form back-side signal and power wiring.

[0025] Each of semiconductor devices 101 and 103 includes a source region and a drain region along one direction (e.g., Figure 1AOne or more nanoribbons 104 extending parallel to each other (in the first direction of the cross-section view, in and out of the paper). Nanoribbon 104 is an example of a semiconductor region or semiconductor body extending between a source region and a drain region. The term nanoribbon can also encompass other similar shapes, such as nanowires or nanosheets. The semiconductor material of the nanoribbon 104 can be formed from a substrate 102. In some embodiments, semiconductor devices 101 and 103 can both include semiconductor regions having a fin shape, for example, the fins can be native to the substrate 102 (formed by the substrate itself), such as silicon fins etched from a bulk silicon substrate. Alternatively, the fins can be formed from material deposited onto an underlying substrate. In one such exemplary case, a uniform-thickness layer of silicon germanium (SiGe) can be deposited onto a silicon substrate and subsequently patterned and etched to form a plurality of SiGe fins extending from the substrate. In another such example, non-native fins can be formed in a so-called aspect ratio-based trapping process, where native fins are etched away to leave fin-shaped trenches, which are then filled with an alternative semiconductor material (e.g., group IV or group III-V materials). In other embodiments, the fins comprise alternating layers of material (e.g., alternating silicon and SiGe layers) that facilitate the formation of the illustrated nanoribbon 104 during the gate formation process, where one type of alternating layer within the channel region is selectively etched away to free up another type of alternating layer, enabling a subsequent gate all-around (GAA) process. Again, the alternating layers can be deposited at a uniform thickness and then etched into fins, or they can be deposited into fin-shaped trenches.

[0026] It can also be seen that adjacent semiconductor devices are separated by a dielectric filler 106, which may include silicon oxide. The dielectric filler 106 provides shallow trench isolation (STI) between any adjacent semiconductor devices. The dielectric filler 106 can be any suitable dielectric material, such as silicon dioxide, alumina, or silicon carbonitride.

[0027] Semiconductor devices 101 and 103 both include a sub-fin region 108. According to some embodiments, the sub-fin region 108 comprises the same semiconductor material as the substrate 102 and is adjacent to a dielectric filler 106. According to some embodiments, a nanoribbon 104 (or other semiconductor body) extends along a first direction between the source and drain regions to provide an active region (e.g., a semiconductor region located below the gate) for a transistor. Figure 1A The source and drain regions are not shown in the cross-section, but in Figure 1BThe top-down view shows the source and drain regions, where the nanoribbon 104 of semiconductor device 101 extends between the source region 110a and the drain region 110b (similarly, the nanoribbon 104 of semiconductor device 103 extends between the source region 112a and the drain region 112b). Figure 1B Spacer structures 114 are also shown, extending around the ends of nanoribbons 104 and along the sidewalls of the gate structure located between the spacer structures 114. Spacer structures 114 may include a dielectric material, such as silicon nitride.

[0028] According to some embodiments, the source and drain regions are epitaxial regions provided using an "etch and replace" process. In other embodiments, one or both of the source and drain regions can be, for example, implanted and doped native portions of a semiconductor fin or substrate. Any semiconductor material suitable for the source and drain regions (e.g., group IV and III-V semiconductor materials) can be used. The source and drain regions can include multiple layers, such as a liner and a cap layer, to improve contact resistance. In any such case, the composition and doping of the source and drain regions can be the same or different, depending on the polarity of the transistor. In the example, for instance, one transistor is a p-type MOS (PMOS) transistor, and the other transistor is an n-type MOS (NMOS) transistor. Any number of source and drain configurations and materials can be used.

[0029] According to some embodiments, a first gate structure extends over the nanoribbon 104 of semiconductor device 101 along a second direction spanning the page, while a second gate structure extends over the nanoribbon 104 of semiconductor device 103 along the second direction. Each gate structure includes a corresponding gate dielectric 116a / 116b and a gate layer (or gate electrode) 118a / 118b. The gate dielectric 116a / 116b represents any number of dielectric layers present between the nanoribbon 104 and the gate layers 118a / 118b. The gate dielectric 116a / 116b may also be present on the surface of other structures within the gate trench, such as on the sub-fin region 108. The gate dielectric 116a / 116b may include any suitable gate dielectric material(s). In some embodiments, the gate dielectric 116a / 116b includes a native oxide material (e.g., silicon oxide) layer on the nanoribbon or other semiconductor region constituting the channel region of the device, and a high-k dielectric material (e.g., hafnium oxide) layer on the native oxide.

[0030] Gate layers 118a / 118b can represent any number of conductive layers, such as any metal layer, metal alloy layer, or doped polysilicon layer. In some embodiments, gate layers 118a / 118b include one or more work function metals surrounding nanoribbon 104. In some embodiments, one of semiconductor devices 101 and 103 is a p-channel device including a work function metal of titanium surrounding its nanoribbon 104, and the other semiconductor device is an n-channel device including a work function metal of tungsten surrounding its nanoribbon 104. Gate layers 118a / 118b may also include fill metal or other conductive material surrounding the work function metal to provide the overall gate electrode structure.

[0031] According to some embodiments, adjacent gate structures can be separated by a gate notch 120 along a second direction (e.g., a direction across a page), the gate notch 120 acting as a dielectric barrier similar to that between gate structures. The gate notch 120 can be formed of a sufficiently electrically insulating material (e.g., a dielectric material). Exemplary materials for the gate notch 120 include silicon nitride, silicon oxide, or silicon oxynitride. In some embodiments, the gate notch 120 includes more than one dielectric material, for example, a dielectric layer at its edges and a separate dielectric filler. The dielectric layer may include a high-k dielectric material, and the dielectric filler may include a low-k dielectric material.

[0032] According to some embodiments, due to the fabrication process discussed in more detail herein, the gate notch 120 has a very high height-to-width ratio. For example, the gate notch 120 may have an aspect ratio of 10:1 or greater. According to some embodiments, the gate notch 120 has a total height extending through the entire thickness of the gate layers 118a / 118b and into at least a portion of the dielectric filler 106. h For example, height h It can be greater than 140 nm, for example, between approximately 150 nm and approximately 200 nm (e.g., between approximately 160 nm and approximately 180 nm). According to some embodiments, the gate notch 120 has a first width at the top surface of the gate notch 120, i.e., at the top surface of the first gate structure (e.g., gate layer 118a) and the top surface of the second gate structure (e.g., gate layer 118b). w 1 Furthermore, the gate notch 120 has a second width at the portion where it intersects the bottom surface of the first gate structure (e.g., gate layer 118a) and the bottom surface of the second gate structure (e.g., gate layer 118b). w 2 In some examples, w 1 At most w 2 Larger than 2nm, or at most 2nmw 2 Larger by 1.5nm, or at most 1.5nm w 2 Larger than 1nm. In some examples, w 1 Compare w 2 Maximum 10%, maximum 8%, or maximum 5%. In some examples, w 1 Less than 24nm, for example, in the exemplary case, w 1 It is between approximately 15nm and approximately 20nm, and w 2 It is between approximately 14nm and approximately 19nm.

[0033] from Figure 1B As can be seen, the gate cutout 120 also extends along the first direction, such that it cuts across at least the entire width of the gate trench. According to some embodiments, the gate cutout 120 may further extend beyond the spacer structure 114. In some examples, the gate cutout 120 extends along the first direction across more than one gate trench (e.g., cutting through more than one gate structure that extends parallel to the second direction).

[0034] Production method Figure 2A-2N The figures include cross-sectional views illustrating an exemplary process for forming an integrated circuit having a semiconductor device and one or more gate cutouts with a high aspect ratio, according to embodiments of the present disclosure. Each figure shows an exemplary structure obtained from the process flow up to that point in time, and thus the illustrated structure evolves as the process flow continues, ultimately resulting in… Figure 2N The structure shown is similar to Figure 1A The structures shown are similar. The illustrated integrated circuit structure may be part of a larger integrated circuit that includes other integrated circuit systems not shown. It should be understood that although exemplary material and process parameters are given, this disclosure is not intended to be limited to any specific such material or parameter. Although the fabrication of a single gate slit is shown in the foregoing figures, it should be understood that any number of similar gate slits can be fabricated across an integrated circuit using the same processes discussed herein.

[0035] Figure 2AA cross-sectional view taken through a substrate 201 according to an embodiment of the present disclosure is shown, the substrate having a series of material layers formed thereon. Alternating material layers, including sacrificial layers 202 alternating with semiconductor layers 204, can be deposited on the substrate 201. The alternating layers are used to form a GAA transistor structure. Any number of alternating semiconductor layers 204 and sacrificial layers 202 can be deposited on the substrate 201. The description of substrate 102 above also applies to substrate 201.

[0036] According to some embodiments, the sacrificial layer 202 has a different material composition than the semiconductor layer 204. In some embodiments, the sacrificial layer 202 is silicon-germanium (SiGe), while the semiconductor layer 204 comprises a semiconductor material suitable for use as a nanoribbon, such as silicon (Si), SiGe, germanium, or a III-V material, such as indium phosphide (InP) or gallium arsenide (GaAs). In examples where SiGe is used in each of the sacrificial layers 202 and the semiconductor layer 204, the germanium concentration differs between the sacrificial layer 202 and the semiconductor layer 204. For example, the sacrificial layer 202 may include a higher germanium content compared to the semiconductor layer 204. In some examples, the semiconductor layer 204 may be doped with an n-type dopant (to produce a p-channel transistor) or a p-type dopant (to produce an n-channel transistor).

[0037] Although the form factor may vary from one exemplary embodiment to the next, the thickness of each sacrificial layer 202 can be between approximately 5 nm and approximately 20 nm. In some embodiments, the thickness of each sacrificial layer 202 is substantially the same (e.g., within 1-2 nm). The thickness of each of the semiconductor layers 204 can be approximately the same as the thickness of each sacrificial layer 202 (e.g., approximately 5-20 nm). Each of the sacrificial layers 202 and semiconductor layers 204 can be deposited using any known or proprietary material deposition technique such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0038] Figure 2B The illustration depicts the process after the cap layer 205 is formed and subsequently the fins below the cap layer 205 are formed, according to an embodiment. Figure 2A A cross-sectional view of the structure is shown. The cap layer 205 can be any suitable hard mask material, such as a carbon hard mask (CHM) or silicon nitride. The cap layer 205 is patterned into rows, thereby forming corresponding rows of fins from alternating stacks of sacrificial layer 202 and semiconductor layer 204. The rows of fins extend longitudinally along a first direction (e.g., the direction in and out of the paper).

[0039] According to some embodiments, the anisotropic etching process, which proceeds through the stacked layers, continues into at least a portion of the substrate 201. The etched portions of the substrate 201 may be filled with a dielectric filler 206, which acts as shallow trench isolation (STI) between adjacent fins. The dielectric filler 206 may be any suitable dielectric material, such as silicon oxide. According to some embodiments, sub-fin regions 208 represent reserved portions of the substrate 201 located between the dielectric fillers 206.

[0040] Figure 2C The illustration depicts a sacrificial gate 210 extending across the fin in a second direction different from the first direction, according to some embodiments. Figure 2B The diagram shows a cross-sectional view of the structure. The sacrificial gate 210 may extend across the fin along a second direction orthogonal to the first direction. According to some embodiments, the sacrificial gate material is formed as a parallel strip across the integrated circuit and is removed in all regions not protected by the gate mask layer. The sacrificial gate 210 may be any suitable material capable of being selectively removed without damaging the semiconductor material of the fin. In some examples, the sacrificial gate 210 comprises polysilicon.

[0041] After the sacrificial gate 210 is formed (and before it is replaced with a metal gate), additional semiconductor device structures, not shown in these cross-sectional views, are formed. These additional structures include spacer structures located on the sidewalls of the sacrificial gate 210 and source and drain regions located at both ends of each of the fins. The formation of such structures will be well understood by those skilled in the art.

[0042] Figure 2D The diagram illustrates the process after removing the sacrificial gate 210 and the sacrificial layer 202, according to some embodiments. Figure 2C The diagram shows a cross-sectional view of the structure. In examples where any gate mask layers still exist, these layers will also be removed at this point. Once the sacrificial gate 210 is removed, the fins that were previously located beneath it are exposed.

[0043] In examples where the fins include alternating semiconductor layers, the sacrificial layer 202 is selectively removed, thereby releasing nanoribbons 212 extending between corresponding source or drain regions. Each vertical group of nanoribbons 212 represents a semiconductor region of a different semiconductor device. It should be understood that the nanoribbons 212 can also be nanowires or nanosheets. The sacrificial gate 210 and the sacrificial layer 202 can be removed using the same isotropic etching process or different isotropic etching processes.

[0044] Figure 2EThe illustration depicts the process after forming the gate structure and subsequently polishing, according to some embodiments. Figure 2D The diagram shows a cross-sectional view of the structure. The gate structure includes a gate dielectric 214 and a conductive gate electrode 216. The gate dielectric 214 may be formed first around the nanoribbon 212 before the gate electrode 216 is formed. The gate dielectric 214 may include any suitable dielectric material (e.g., silicon dioxide and / or a high-k dielectric material). Examples of high-k dielectric materials include, for example, hafnium oxide, hafnium silicate, lanthanum oxide, lanthanum alumina, zirconium oxide, zirconium silicate, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, to provide some examples. According to some embodiments, the gate dielectric 214 includes a hafnium oxide layer with a thickness between about 1 nm and about 5 nm. In some embodiments, the gate dielectric 214 may include one or more silicates (e.g., titanium silicate, tungsten silicate, niobium silicate, and silicates of other transition metals). In some cases, the gate dielectric 214 may comprise a first layer on the nanoribbon 212 and a second layer on the first layer. The first layer may be, for example, an oxide (e.g., silicon dioxide) of the semiconductor material of the nanoribbon 212, and the second layer may be a high-k dielectric material (e.g., hafnium oxide). More generally, the gate dielectric 214 may comprise any number of dielectric layers. According to some embodiments, the gate dielectric 214 is formed along all surfaces exposed within the gate trench, for example, along the inner sidewalls of the spacer structure and along the top surface of the dielectric filler 206 and the sub-fin region 208.

[0045] As noted above, gate electrode 216 can represent any number of conductive layers. The conductive gate electrode 216 can be deposited using electroplating, electroless plating, CVD, PECVD, ALD, or PVD (to name just a few). In some embodiments, gate electrode 216 comprises doped polysilicon, a metal, or a metal alloy. Exemplary suitable metals or metal alloys include aluminum, tungsten, cobalt, molybdenum, ruthenium, titanium, tantalum, copper, and their carbides and nitrides. Gate electrode 216 may include, for example, a metal filler material along with one or more work function layers, resistance reduction layers, and / or barrier layers. The work function layer may include, for example, a p-type work function material (e.g., titanium nitride) for a PMOS gate or an n-type work function material (e.g., titanium aluminum carbide) for an NMOS gate. After forming the gate structure, the entire structure may be polished such that the top surface of the gate structure (e.g., the top surface of gate electrode 216) is coplanar with the top surfaces of other semiconductor elements (e.g., spacer structures defining gate trenches).

[0046] Figure 2F The following is shown after forming the mask structure 218 according to some embodiments. Figure 2EAnother cross-sectional view of the structure shown. Mask structure 218 may include any number of hard mask layers, such as any dielectric layer or carbon hard mask layer. An opening 220 may be formed through mask layer 218 to expose the portion of gate electrode 216 that will form the gate notch. The opening 220 may be formed using a reactive ion etching (RIE) process.

[0047] Figure 2G This illustrates the effect after the liner 222 is formed within the opening 220, according to some embodiments. Figure 2F Another cross-sectional view of the structure shown. The liner 222 may be formed using atomic layer deposition (ALD) or plasma-enhanced atomic layer deposition (PEALD) in a reaction chamber having a pressure between 80 mTorr and 100 mTorr, a temperature between 90°C and 140°C, and a gas containing helium and oxygen. In some embodiments, the liner 222 comprises a dielectric material, such as silicon oxide or other oxide-based materials. The liner 222 may be provided to adjust the critical dimension of the top width of the resulting gate cutout. Due to the conformal structure of the liner 222, the liner 222 is formed on the top surface of the exposed gate electrode 216 and on the sidewall surface of the opening 220.

[0048] Figure 2H This illustrates the effect after a passivation layer 224 is formed on the liner 222 within the opening 220, according to some embodiments. Figure 2G Another cross-sectional view of the structure shown. In some embodiments, the passivation layer 224 comprises a dielectric material, such as silicon oxide. The passivation layer 224 may be deposited using chemical vapor deposition (CVD) or plasma-enhanced atomic layer deposition (PEALD) in a reaction chamber having a pressure between 5 mTorr and 20 mTorr, a temperature between 90°C and 140°C, and a gas containing helium, oxygen, and silicon tetrachloride (SiCl4). The gas may be introduced into the reaction chamber at different flow rates. For example, helium may be introduced at a flow rate between 400 sccm and 800 sccm, oxygen may be introduced at a flow rate between 50 sccm and 100 sccm, and SiCl4 may be introduced at a flow rate between 70 sccm and 120 sccm.

[0049] According to some embodiments, the CVD or PECVD process for forming the passivation layer 224 can have two different deposition processes, each applying a different RF power. For example, a first CVD deposition can be performed without using the applied RF power or with a first RF power between 1W and 3000W, and a second CVD deposition can be performed with a second RF power different from the first RF power. Using two different CVD deposition processes to form the passivation layer 224 can balance the amount of passivation layer 224 deposited on the top surface of the mask structure 218 outside the opening 220 to protect the mask structure 218 with the amount of passivation layer 224 deposited on the sidewalls inside the opening 220 to prevent or minimize lateral etching.

[0050] Figure 2I The image shows the result of an etching process, according to some embodiments, following an etching process used to break through the portion of the substrate 222 and passivation layer 224 located on the bottom surface (e.g., the etch front) of the opening 220 to expose the surface portion 226 of the gate electrode 216. Figure 2H Another cross-sectional view of the structure shown. During this etching process, portions of the liner 222 and passivation layer 224 extending along the top surface of the mask structure 218 can also be removed, leaving only the portions of the liner 222 and passivation layer 224 located on the sidewalls of the opening 220. The RIE etching process can be used to perforate the portions of the liner 222 and passivation layer 224 located on the bottom surface of the opening 220. According to some embodiments, the RIE process occurs in a reaction chamber having a pressure between 5 mTorr and 20 mTorr, a temperature between 90°C and 140°C, and a gas containing helium, one or more hydrocarbons (e.g., methane (CH4)), and one or more fluorinated hydrocarbons (e.g., carbon tetrafluoride (CF4) or trifluoromethane (CHF3)). The gas can be introduced into the reaction chamber at different flow rates. For example, helium can be introduced at a flow rate between 50 sccm and 150 sccm, CH4 can be introduced at a flow rate between 50 sccm and 150 sccm, and CHF3 can be introduced at a flow rate between 5 sccm and 30 sccm. Using CH4 during the etching process can help add carbon-based passivation to the sidewalls and can also reduce etching of any exposed portions of the source or drain regions.

[0051] Figure 2J The image shows the result after an etching process, according to some embodiments, to remove portions of the gate electrode 216 and thus extend the opening 228 deeper. Figure 2IAnother cross-sectional view of the structure shown. The etching process can be adjusted to selectively etch the metallic material of the gate electrode 216. A recess can be etched into the exposed surface 226 of the gate electrode 216 using a RIE etching process. According to some embodiments, the RIE process occurs in a reaction chamber having a pressure between 10 mTorr and 25 mTorr, a temperature between 90°C and 140°C, and a gas containing boron trichloride (BCl3), argon, and methane (CH4). The gas can be introduced into the reaction chamber at different flow rates. For example, BCl3 can be introduced at a flow rate between 100 sccm and 300 sccm, CH4 can be introduced at a flow rate between 10 sccm and 40 sccm, and argon can be introduced at a flow rate between 100 sccm and 300 sccm. According to some embodiments, a high RF power between 1000 W and 3000 W can also be applied in the reaction chamber to help decompose BCl3 molecules and reduce the accumulation of unwanted surface residues. CH4 can be reused to help reduce etching of any exposed portions of the source or drain regions. In some embodiments, additional bias RF power between 0W and 1000W is applied to the wafer stage holding the wafer to vertically guide the material and reactants to the etch front.

[0052] After etching a portion of the gate electrode 216, any number of flash operations can be performed to help remove certain byproducts and / or other materials left behind. According to some embodiments, a first flash operation can be performed in a reaction chamber having a pressure between 5 mTorr and 10 mTorr, a temperature between 90°C and 140°C, and a gas containing argon, hydrogen, chlorine, methane (CH4), helium, and oxygen. The first flash operation can be used to remove any polymer byproducts left by the metal etching process and / or passivate any exposed portions of the source or drain regions. According to some embodiments, a second flash operation can be performed in a reaction chamber having a pressure between 5 mTorr and 10 mTorr, a temperature between 90°C and 140°C, and a gas containing methane (CH4) and helium. The second flash operation can be used in particular to remove any polymer byproducts from the sidewalls to prevent sidewall corrosion. According to some embodiments, a third flash operation can be performed in a reaction chamber having a pressure between 5 mTorr and 25 mTorr, a temperature between 90°C and 140°C, and a gas containing oxygen. The third flash operation can be used to cure some of the boron-based polymer remaining on the sidewalls, thereby enhancing sidewall protection against subsequent etching processes. Any of these exemplary flash operations can be performed, and they can be performed in any order.

[0053] Figure 2KThis illustrates the following, according to some embodiments, after forming another passivation layer 230 within the deeper opening 228 to protect the sidewalls of the deeper opening 228. Figure 2J Another cross-sectional view of the structure shown. A portion of the passivation layer 230 may be formed on top of a previous passivation layer 224 located on the sidewall of the opening 228. An exemplary deposition process for forming the passivation layer 230 may be the same as the deposition process for forming the previous passivation layer 224. The passivation layer 230 may be provided to protect the sidewall of the exposed portion of the gate electrode 216 within the deeper opening 228.

[0054] Figure 2L The illustration shows, according to some embodiments, a first etching that breaks through the passivation layer 230 on the bottom surface within the opening 228, and a second etching that continues to etch deeper into the gate electrode 216. Figure 2K Another cross-sectional view of the structure shown. The etching process for etching the metal material through the gate electrode 216 can be referenced above. Figure 2J The etching process described is the same. As a result of etching deeper into the gate electrode 216, a deeper recess 232 is formed. Similar to the previous description, any number of various flash operations can be performed to clean up any byproducts and provide further sidewall protection.

[0055] According to some embodiments, the process of forming a passivation layer, penetrating the bottom surface of this layer within the opening, and etching through a portion of the gate electrode is repeated until the entire thickness of the gate electrode 216 is etched through. In some examples, this process is repeated at least 15, at least 20, or at least 25 times to form a low-tapered or even non-tapered recess with a depth of 125 nm or greater, and the recess extends at least into a portion of the dielectric filler 206 or a portion of the substrate 201. Each iteration may penetrate a certain distance through the gate structure, for example, 5 to 10 nm per iteration. Later iterations in the cycle may penetrate the gate structure and the underlying dielectric and / or substrate a shorter distance compared to earlier iterations, due to factors such as load variations with increasing trench depth. Any number of various flash operations can also be performed in a given cycle. Figure 2M A cross-sectional view of the structure after a given number of passivation-etch cycles have been performed, ultimately forming the gate notch recess 236, is shown according to some embodiments. Due to the carefully controlled passivation and etching operations performed in each cycle, the gate notch recess 236 is formed in portions, maintaining high verticality.

[0056] Figure 2N The diagram illustrates the formation of a gate notch 238 within a gate notch recess 236 according to some embodiments, followed by the removal of the mask structure 218 and any passivation layer used during the formation of the gate notch recess 236. Figure 2MAnother cross-sectional view of the structure shown. The gate notch 238 can be formed of one or more dielectric materials. For example, the gate notch 238 can comprise only silicon oxide or silicon nitride. In some examples, the gate notch 238 includes a first dielectric layer at the edge and a dielectric filler within the remaining volume. The first dielectric layer may comprise a high-k dielectric material (e.g., a material having a dielectric constant higher than that of silicon oxide), while the dielectric filler may comprise a low-k dielectric material (e.g., a material having a dielectric constant equal to or lower than that of silicon oxide).

[0057] According to some embodiments, the gate cutout 238 has an aspect ratio of 5:1 or greater, or 9:1 or greater, or 10:1 or greater (e.g., 11:1). According to some embodiments, the gate cutout 238 has a total height extending through the entire thickness of the gate electrode 216 and into at least a portion of the dielectric fill 206. h In some examples, thickness h It can be between approximately 160 nm and approximately 180 nm. According to some embodiments, the gate notch 238 has a first width at its top surface (also at the top surface of the gate electrode 216). w 1 And has a second width at the portion where the gate cutout 238 intersects with the bottom surface of the gate electrode 216. w 2 In some examples, w 1 Compare w 2 At most 2nm or at most 1.5nm. In some examples, w 1 Compare w 2 Maximum 10%, maximum 8%, or maximum 5%. In some examples, w 1 Less than 24nm, for example, w 1 It is between approximately 18nm and approximately 20nm, and w 2 An exemplary case is between approximately 17nm and approximately 19nm.

[0058] Figure 3An exemplary embodiment of a chip package 300 according to embodiments of the present disclosure is shown. It can be seen that the chip package 300 includes one or more dies 302. The one or more dies 302 may include at least one integrated circuit having a semiconductor device (e.g., any semiconductor device disclosed herein). In some exemplary configurations, the one or more dies 302 may include any other circuitry for interfacing with other devices formed on the die or with other devices connected to the chip package 300.

[0059] It can also be seen that the chip package 300 includes a housing 304 bonded to the package substrate 306. The housing 304 can be any standard or proprietary housing and can provide, for example, electromagnetic shielding and environmental protection for the components of the chip package 300. One or more dies 302 can be electrically coupled to the package substrate 306 using connections 308, which can be implemented using any number of standard or proprietary connection mechanisms, such as solder bumps, ball grid arrays (BGAs), pins, or wire junctions, to name just a few examples. The package substrate 306 can be any standard or proprietary package substrate, but in some cases includes a dielectric material having conductive pathways (e.g., including conductive vias and wires) extending through the dielectric material between or at different locations on each face of the package substrate 306. In some embodiments, the package substrate 306 can have a thickness of less than 1 mm (e.g., between 0.1 mm and 0.5 mm), although any number of package geometries can be used. Additional conductive contacts 312 may be provided on the opposite surface of the package substrate 306 for conductive contact with, for example, a printed circuit board (PCB). One or more vias 310 extend through the thickness of the package substrate 306 to provide a conductive path between one or more of the connections 308 and one or more of the contacts 312. For simplicity of illustration, the via 310 is shown as a single straight post through the package substrate 306, but other constructions may be used (e.g., metal damascenes, dual metal damascenes, through-silicon vias, or interconnect structures meandering through the thickness of the substrate 306 to contact one or more intermediate locations therein). In other embodiments, the vias 310 are made of a plurality of smaller stacked vias, or staggered at different locations across the package substrate 306. In the illustrated embodiment, the contacts 312 are solder balls (e.g., bump-based connections or ball grid array arrangements), but any suitable package bonding mechanism may be used (e.g., pins in a pin grid array arrangement or pads in a pad grid array arrangement). In some embodiments, solder resist is provided between the contacts 312 to prevent short circuits.

[0060] In some embodiments, molding material 314 may be disposed around one or more dies 302 included within housing 304 (e.g., as an underfill material between die 302 and encapsulation substrate 306, and as an overfill material between die 302 and housing 304). While the dimensions and weight of molding material 314 may vary from one embodiment to the next, in some embodiments, the thickness of molding material 314 is less than 1 mm. Exemplary materials that may be used for molding material 314 where appropriate include epoxy molding materials. In some cases, molding material 314 is thermally conductive in addition to being electrically insulating.

[0061] method Figure 4 A flowchart of a method 400 for forming at least a portion of an integrated circuit according to an embodiment is shown. Figure 2A-2N Various operations of method 400 may be illustrated in the figures. However, the association of the various operations of method 400 with the specific components illustrated in the aforementioned figures is not intended to imply any structural and / or usage limitations. Rather, the aforementioned figures provide an exemplary embodiment of method 400. Other operations may be performed before, during, or after any operation of method 400. For example, method 400 is not explicitly described as all processes performed to form a common transistor structure. Some operations of method 400 may be performed in a different order than illustrated.

[0062] According to some embodiments, method 400 begins at operation 402, in which a plurality of parallel semiconductor fins are formed. The semiconductor material in the fins can be formed from a substrate such that the fins are integral part of the substrate (e.g., etched from a bulk silicon substrate). Alternatively, the fins can be formed from material deposited onto an underlying substrate. In one such exemplary case, a uniform-thickness layer of silicon germanium (SiGe) can be deposited onto a silicon substrate and subsequently patterned and etched to form a plurality of SiGe fins extending from the substrate. In another such example, the fins comprise alternating layers of material (e.g., alternating silicon and SiGe layers) that facilitate the formation of nanowires and nanoribbons during a gate formation process, in which one type of alternating layer within a channel region is selectively etched away to free up another type of alternating layer, thereby enabling a subsequent gate all-around (GAA) process. The alternating layers can be uniformly deposited and subsequently etched into fins, or they can be deposited into trenches shaped like fins. The fins may also include a cap structure located above each fin, the cap structure being used to define the position of the fin during, for example, a RIE process. The cap structure may be a dielectric material, such as silicon nitride.

[0063] According to some embodiments, a dielectric filler is formed around a sub-fin portion of one or more fins. In some embodiments, the dielectric filler extends between each pair of adjacent parallel fins and extends longitudinally in the same direction as the fins. In some embodiments, the anisotropic etching process forming the fins also etches into a portion of the substrate, and the dielectric filler may be formed within a recessed portion of the substrate. Accordingly, the dielectric filler acts as shallow trench isolation (STI) between adjacent fins. The dielectric filler can be any suitable dielectric material, such as silicon oxide.

[0064] Method 400 proceeds to operation 404, wherein a sacrificial gate and spacer structure are formed on the fin. The sacrificial gate can be patterned using a gate mask layer having a strip shape orthogonally extending on the fin (a plurality of mutually parallel gate mask layers and corresponding sacrificial gates can be formed (e.g., forming a cross-line pattern with the fin)). The gate mask layer can be any suitable hard mask material, such as CHM or silicon nitride. The sacrificial gate can be formed of any suitable material that can be selectively removed at a later time without damaging the semiconductor material of the fin. In one example, the sacrificial gate comprises polysilicon. The spacer structure can be deposited and subsequently etched back such that the spacer structure remains almost entirely on the sidewalls of any exposed structure. According to some embodiments, the spacer structure can be any suitable dielectric material, such as silicon nitride or silicon oxynitride.

[0065] Method 400 proceeds to operation 406, wherein a source or drain region is formed at the end of the semiconductor region in each of the fins. Any portion of the fin not protected by the sacrificial gate and spacer structures can be removed using, for example, an anisotropic etching process, followed by epitaxial growth of the source or drain region from the exposed end of the semiconductor layer in the fin. In some exemplary embodiments, the source or drain region is an NMOS source or drain region (e.g., epitaxial silicon) or a PMOS source or drain region (e.g., epitaxial SiGe). Another dielectric filler may be formed adjacent to the various source or drain regions for additional electrical isolation between adjacent regions. The dielectric filler may also extend over the top surface of the source or drain region. In some embodiments, top-side conductive contacts may be formed through the dielectric filler to contact one or more of the source or drain regions.

[0066] Method 400 proceeds to operation 408, in which the sacrificial gate is removed and replaced with a gate structure. The sacrificial gate can be removed using an isotropic etching process that selectively removes all material from the sacrificial gate, thus exposing the individual fins between the spacer body structure groups. In the exemplary case of using a GAA transistor, any sacrificial layer within the exposed fins between the spacer body structures can also be removed to release nanoribbons, nanosheets, or nanowires of the semiconductor material.

[0067] The gate structure can include both a gate dielectric and a gate electrode. According to some embodiments, the gate dielectric is first formed over an exposed semiconductor region between spacer structures, and then the gate electrode is formed within the remainder of the trench between the spacer structures. The gate dielectric can include any number of dielectric layers deposited using a CVD process (e.g., ALD). The gate electrode can include any number of conductive material layers, such as metal, metal alloy, or polysilicon. The gate electrode can be deposited using electroplating, electroless plating, CVD, ALD, PECVD, or PVD; only a few examples are given here.

[0068] Method 400 continues with operation 410, wherein a mask structure is formed over the gate structure, and an opening is formed through the mask structure to expose a portion of the underlying gate electrode. According to some embodiments, the opening through the mask structure is located at a position where a gate cutout through the underlying gate electrode will be formed. The mask structure may include any number of hard mask layers, such as any dielectric layer or carbon hard mask layer. The opening may be formed using a directional RIE process.

[0069] Method 400 continues with operation 412, wherein a deep recess is formed through the gate structure located beneath the opening in the through-mask structure. According to some embodiments, the deep recess has a high height-to-width ratio of at least 10:1 and extends through at least the entire thickness of the gate electrode. In some examples, the deep recess extends into the dielectric fill between devices or into the underlying substrate. Figure 5 Method 500 in the literature provides further details about the formation of deep depressions.

[0070] Method 400 proceeds to operation 414, wherein a dielectric material is used to fill the deep recess to form a gate cutout through the gate structure. The gate cutout may be formed of one or more dielectric materials. For example, the gate cutout may comprise only silicon oxide or silicon nitride. In some examples, the gate cutout includes a first dielectric layer at the edge and a dielectric filler within the remaining volume. The first dielectric layer may comprise a high-k dielectric material (e.g., a material having a dielectric constant higher than that of silicon oxide), while the dielectric filler may comprise a low-k dielectric material (e.g., a material having a dielectric constant equal to or lower than that of silicon oxide).

[0071] According to some embodiments, the gate cutout has a height-to-width ratio of 10:1 or greater (e.g., 11:1). According to some embodiments, the gate cutout has a total height extending through the entire thickness of the gate electrode and into at least a portion of the dielectric filler. The height of the gate cutout can be between approximately 160 nm and approximately 180 nm. According to some embodiments, the gate cutout has a first width at its top surface (which may be substantially planar with the top surface of the gate structure) and a second width at the portion where the gate cutout intersects with the bottom surface of the gate structure (e.g., the interface between the gate structure and the dielectric filler). In some examples, the first width of the gate cutout is at most 2 nm or at most 1.5 nm greater than the second width of the gate cutout. In some examples, the first width of the gate cutout is at most 10%, at most 8%, or at most 5% greater than the second width of the gate cutout. In some examples, the first width of the gate cutout is between approximately 18 nm and approximately 20 nm, and the second width of the gate cutout is between approximately 17 nm and approximately 19 nm.

[0072] Figure 5 This is a flowchart of a method 500 for forming a deep trench, as described above in operation 412 of method 400 according to an embodiment. Figure 2G-2M The various operations of method 500 can be illustrated in the figures. However, the association of the various operations of method 500 with the specific components shown in the aforementioned figures is not intended to imply any structural and / or usage limitations. Rather, the aforementioned figures provide an exemplary embodiment of method 500. Other operations may be performed before, during, or after any operation of method 500.

[0073] Method 500 begins with operation 502, wherein a liner is formed at least within the opening through the mask structure. The liner may be formed using atomic layer deposition (ALD) in a reaction chamber having a pressure between 80 mTorr and 100 mTorr, a temperature between 90°C and 140°C, and a gas containing helium and oxygen. In some embodiments, the liner comprises a dielectric material, such as silicon oxide. The liner may be provided to adjust the critical dimension of the top width of the resulting gate cutout. Due to the conformal structure of the liner, it is formed at least along the sidewall of the opening through the mask structure.

[0074] Method 500 continues to operation 504, wherein a passivation layer is formed at least within the opening. In some embodiments, the passivation layer comprises a dielectric material, such as silicon oxide. The passivation layer may be deposited using chemical vapor deposition (CVD) in a reaction chamber having a pressure between 5 mTorr and 20 mTorr, a temperature between 90°C and 140°C, and a gas containing helium, oxygen, and silicon tetrachloride (SiCl4). Various gases may be introduced into the reaction chamber at different flow rates. For example, helium may be introduced at a flow rate between 400 sccm and 800 sccm, oxygen may be introduced at a flow rate between 50 sccm and 100 sccm, and SiCl4 may be introduced at a flow rate between 70 sccm and 120 sccm. The passivation layer is formed at least on the sidewalls of the opening and serves to protect the sidewalls during each etching process to reduce lateral etching of the gate electrode, thereby creating a smaller taper in the sidewall profile.

[0075] Method 500 proceeds to operation 506, wherein an etching process is performed that penetrates at least the passivation layer (and possibly the liner) at the bottom of the opening. In this way, the passivation layer (and in some cases, the liner) remains on the sidewalls of the opening to protect them during subsequent metal etching processes. A RIE etching process can be used to penetrate at least the portion of the passivation layer located on the bottom surface of the opening. According to some embodiments, the RIE process occurs in a reaction chamber having a pressure between 5 mTorr and 20 mTorr, a temperature between 90°C and 140°C, and a gas containing helium, one or more hydrocarbons (e.g., methane (CH4)), and one or more fluorinated hydrocarbons (e.g., carbon tetrafluoride (CF4) or trifluoromethane (CHF3)). Various gases can be introduced into the reaction chamber at different flow rates. For example, helium can be introduced at a flow rate between 50 sccm and 150 sccm, CH4 can be introduced at a flow rate between 50 sccm and 150 sccm, and CHF3 can be introduced at a flow rate between 5 sccm and 30 sccm. Using CH4 during the etching process can help add carbon-based passivation to the sidewalls and can also reduce etching of any exposed portions of the source or drain regions.

[0076] Method 500 continues to operation 508, wherein the exposed portion of the gate electrode within the opening is etched. According to some embodiments, this etching process does not etch through the entire thickness of the gate electrode in a single etch, but rather etches only a portion of the gate electrode's thickness (e.g., etching to a depth of approximately 5-10 nm into the gate electrode). The RIE process can be tuned to selectively etch the metal material of the gate electrode. According to some embodiments, the metal etching process occurs in a reaction chamber having a pressure between 10 mTorr and 25 mTorr, a temperature between 90°C and 140°C, and a gas containing boron trichloride (BCl3), argon, and methane (CH4). Various gases can be introduced into the reaction chamber at different flow rates. For example, BCl3 can be introduced at a flow rate between 100 sccm and 300 sccm, CH4 can be introduced at a flow rate between 10 sccm and 40 sccm, and argon can be introduced at a flow rate between 100 sccm and 300 sccm. According to some embodiments, a high RF power between 1000W and 3000W can also be applied in the reaction chamber to help decompose BCl3 molecules and reduce the accumulation of unwanted surface residues. CH4 can be reused to help reduce etching of any exposed portions of the source or drain regions. In some embodiments, additional bias RF power between 0W and 1000W is applied to the wafer stage holding the wafer to vertically guide the material and reactants to the etching front.

[0077] Method 500 continues to operation 510, wherein one or more flash operations are performed to remove any byproducts generated by metal etching. According to some embodiments, a first flash operation can be performed in a reaction chamber having a pressure between 5 mTorr and 10 mTorr, a temperature between 90°C and 140°C, and a gas containing argon, hydrogen, chlorine, methane (CH4), helium, and oxygen. The first flash operation can be used to remove any polymer byproducts left by the metal etching process and / or passivate any exposed portions of the source or drain regions. According to some embodiments, a second flash operation can be performed in a reaction chamber having a pressure between 5 mTorr and 10 mTorr, a temperature between 90°C and 140°C, and a gas containing methane (CH4) and helium. The second flash operation can be used in particular to remove any polymer byproducts from the sidewalls to prevent sidewall corrosion. According to some embodiments, a third flash operation can be performed in a reaction chamber having a pressure between 5 mTorr and 25 mTorr, a temperature between 90°C and 140°C, and a gas containing oxygen. The third flash operation can be used to cure some of the boron-based polymer remaining on the sidewalls to enhance sidewall protection for subsequent etching processes. Any of these exemplary flash operations can be performed, and these flash operations can be performed in any order.

[0078] Method 500 proceeds to operation 512, wherein it is determined whether the etched recess has extended through the entire thickness of the gate structure (and more specifically, the gate electrode). This determination may be based on the use of inspection tools or ion scattering data to determine, after each etch process, whether the underlying dielectric filler has been exposed at the bottom of the recess. In some embodiments, a predetermined number of cyclic etch processes are performed, which produce a recess extending through the entire thickness of the gate structure, and the process ends once the number is reached. For example, a total of 15, 20, or 25 metal etch processes may be performed.

[0079] If the recess has not yet extended through the entire thickness of the gate structure, then method 500 cycles back to operation 504 and repeats the formation of the passivation layer, the passivation layer breaking etching, the etching of the metal gate electrode, and one or more flash operations, and then again determines whether the recess now extends through the entire thickness of the gate structure. If it has been determined that the recess extends through the entire thickness of the gate structure, then method 500 proceeds to operation 514, where a final flash operation may be performed to remove etching byproducts. The final flash operation may be similar to any or more of the flash operations mentioned above. In some embodiments, the final flash operation contains a higher concentration of hydrogen in the reaction chamber to provide enhanced protection for any exposed portions of the source or drain regions. At this point, the method may continue to fill the deep recess with a dielectric material, as described above in connection with operation 414 of method 400.

[0080] Exemplary System Figure 6 This is an exemplary computing system implemented according to some embodiments of the present disclosure, employing one or more of the integrated circuit structures disclosed herein. It can be seen that the computing system 600 houses a motherboard 602. The motherboard 602 may include several components, including but not limited to a processor 604 and at least one communication chip 606, each of which may be physically and electrically coupled to the motherboard 602, or otherwise integrated therein. It should be appreciated that the motherboard 602 may be, for example, any printed circuit board (PCB), whether it is a motherboard, a daughterboard mounted on a motherboard, or the sole board of system 600, etc.

[0081] Depending on its application, the computing system 600 may include one or more other components that may be physically and electrically coupled to the motherboard 602, or may not be physically and electrically coupled to the motherboard 602. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, displays, touchscreen displays, touchscreen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (e.g., hard disk drives, compact discs (CDs), digital versatile discs (DVDs), etc.). Any component included in the computing system 600 may include one or more integrated circuit structures or devices constructed according to exemplary embodiments, such as modules including integrated circuits on a substrate having semiconductor devices and at least one gate cutout having a very high height-to-width ratio (e.g., in some examples, 10:1 or greater). In some embodiments, multiple functions may be integrated into one or more chips (for example, note that the communication chip 606 may be part of the processor 604 or otherwise integrated into the processor 604).

[0082] The communication chip 606 enables wireless communication for transmitting data to and from the computing system 600. The term "wireless" and its derivatives can be used to describe circuits, apparatuses, systems, methods, techniques, communication channels, etc., that transmit data over a non-solid-state medium using modulated electromagnetic radiation. This term does not imply that the associated apparatus does not contain any wires, although they may not in some embodiments. The communication chip 606 can implement any of many wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, LTE, Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, their derivatives, and any other wireless protocols designated as 3G, 4G, 5G, and higher generations. The computing system 600 may include multiple communication chips 606. For example, the first communication chip 606 can be dedicated to short-range wireless communication such as Wi-Fi and Bluetooth, and the second communication chip 606 can be dedicated to long-range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0083] The processor 604 of the computing system 600 includes an integrated circuit die packaged within the processor 604. In some embodiments, the processor's integrated circuit die includes an onboard circuitry system implemented using one or more semiconductor devices described herein in various ways. The term "processor" can refer to any means or part of a means of processing, for example, electronic data from registers and / or memory to transform that electronic data into other electronic data that can be stored in registers and / or memory.

[0084] The communication chip 606 may also include an integrated circuit die packaged within the communication chip 606. According to some such exemplary embodiments, the integrated circuit die of the communication chip includes one or more semiconductor devices described herein in various ways. It should be appreciated that, in light of this disclosure, multi-standard wireless capabilities can be directly integrated into the processor 604 (e.g., where the functionality of any chip 606 is integrated into the processor 604, rather than having a separate communication chip). Furthermore, it should be noted that the processor 604 can be a chipset with such wireless capabilities. In short, any number of processors 604 and / or communication chips 606 can be used. Similarly, any chip or chipset can have multiple functions integrated therein.

[0085] In various embodiments, the computing system 600 may be a laptop, netbook, notebook, smartphone, tablet computer, personal digital assistant (PDA), super mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques as described in various ways herein.

[0086] It should be recognized that, in some embodiments, various components of the computing system 600 may be combined or integrated into a system-on-a-chip (SoC) architecture. In some embodiments, the components may be hardware components, firmware components, software components, or any suitable combination of hardware, firmware, or software.

[0087] Other exemplary embodiments The examples below relate to other embodiments, through which many combinations and constructions will become apparent.

[0088] Example 1 is an integrated circuit comprising: a first semiconductor device having a first semiconductor region extending along a first direction from a first source region to a first drain region and a first gate structure extending along a second direction over the first semiconductor region; a second semiconductor device having a second semiconductor region extending along the first direction from a second source region to a second drain region and a second gate structure extending along the second direction over the second semiconductor region; and a gate cutout located between the first gate structure and the second gate structure and separating the first gate structure and the second gate structure. The gate cutout has a dielectric material and has a height-to-width ratio of at least 8:1.

[0089] Example 2 includes the integrated circuit of Example 1, wherein the gate cutout has a height greater than 140 nm and a height-to-width ratio of at least 9:1.

[0090] Example 3 includes the integrated circuit of Example 1, wherein the gate cutout has a height greater than 150 nm and a height-to-width ratio of at least 10:1.

[0091] Example 4 includes an integrated circuit of any of Examples 1-3, wherein the gate cutout has a height between approximately 150 nm and approximately 180 nm.

[0092] Example 5 includes an integrated circuit of any of Examples 1-4, wherein a first semiconductor region includes a plurality of first semiconductor nanoribbons, and a second semiconductor region includes a plurality of second semiconductor nanoribbons.

[0093] Example 6 includes an integrated circuit of any one of Examples 1-5, wherein a first gate structure includes a first gate dielectric surrounding a first semiconductor region, and a second gate structure includes a second gate dielectric surrounding a second semiconductor region, and wherein the first gate dielectric and the second gate dielectric are not present on any sidewalls of the gate notch.

[0094] Example 7 includes an integrated circuit of any of Examples 1-6, wherein the gate cutout has a first width at the top surface of the first gate structure and the second gate structure and a second width at the bottom surface of the first gate structure and the second gate structure, the first width being at most 2 nm larger than the second width.

[0095] Example 8 includes an integrated circuit of any of Examples 1-7, wherein the gate cutout has a first width at the top surface of the first gate structure and the second gate structure and a second width at the bottom surface of the first gate structure and the second gate structure, the first width being at most 10% larger than the second width.

[0096] Example 9 is a printed circuit board that includes integrated circuits from any of Examples 1-8.

[0097] Example 10 is an electronic device including a chip package having one or more dies. At least one of the one or more dies includes: a first semiconductor device having a first semiconductor region extending in a first direction between a first source region and a first drain region and a first gate structure extending in a second direction over the first semiconductor region; a second semiconductor device having a second semiconductor region extending in the first direction between a second source region and a second drain region and a second gate structure extending in the second direction over the second semiconductor region; and a gate cutout located between the first gate structure and the second gate structure and separating the first gate structure and the second gate structure. The gate cutout has a first width at the top surface of the first gate structure and the second gate structure and a second width at the bottom surface of the first gate structure and the second gate structure. The first width is 20 nm or less and is at most 2 nm larger than the second width, and the gate cutout has a height greater than 125 nm.

[0098] Example 11 includes the electronic device of Example 10, wherein the gate cutout has a height between approximately 160 nm and approximately 180 nm.

[0099] Example 12 includes an electronic device of Example 10 or 11, wherein a first semiconductor region includes a plurality of first semiconductor nanoribbons and a second semiconductor region includes a plurality of second semiconductor nanoribbons.

[0100] Example 13 includes the electronic device of Example 10, wherein the first width is 15 nm or less, and the height of the gate cutout is in the range of 150 nm to 200 nm.

[0101] Example 14 includes an electronic device of any one of Examples 10-13, wherein a first gate structure includes a first gate dielectric surrounding a first semiconductor region, and a second gate structure includes a second gate dielectric surrounding a second semiconductor region.

[0102] Example 15 includes the electronic device of Example 14, wherein the first gate dielectric and the second gate dielectric are not present on any sidewall of the gate cutout.

[0103] Example 16 includes an electronic device of any one of Examples 10-15, wherein the gate cutout comprises a dielectric material and has a height-to-width ratio of at least 5:1.

[0104] Example 17 includes an electronic device comprising any one of Examples 10-16, wherein the gate cutout has a first width at the top surface of the first gate structure and the second gate structure and a second width at the bottom surface of the first gate structure and the second gate structure, the first width being at most 10% larger than the second width.

[0105] Example 18 includes an electronic device comprising any one of Examples 10-17, and further includes a printed circuit board, wherein the chip package is coupled to the printed circuit board.

[0106] Example 19 is a method of forming an integrated circuit. The method includes: forming a first fin comprising a semiconductor material and a second fin comprising a semiconductor material, the first fin and the second fin extending over a substrate and both extending along a first direction; forming a gate structure over the first fin and the second fin extending along a second direction different from the first direction; forming a recess through the gate structure between the first fin and the second fin; and forming a dielectric material within the recess. Forming the recess includes: (i) forming an opening through a hard mask layer located over the gate structure; (ii) forming a liner material within the opening; (iii) forming a passivation layer within the opening; (iv) etching at least through the passivation layer located at the bottom of the opening; (v) etching through a portion of the gate structure; and (vi) repeating (iii)-(v) until the recess extends through at least the entire thickness of the gate structure.

[0107] Example 20 includes the method of Example 19, wherein forming the liner material includes forming the liner using atomic layer deposition (ALD) or plasma-enhanced atomic layer deposition (PEALD).

[0108] Example 21 includes the methods of Example 19 or 20, wherein forming a passivation layer includes forming a passivation layer using chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD).

[0109] Example 22 includes the method of Example 21, wherein forming a passivation layer includes using a first CVD process having a first RF energy and a second CVD process having a second RF energy different from the first RF energy.

[0110] Example 23 includes the method of any of Examples 19-22, wherein etching through the passivation layer includes etching with a CH4-based gas or a CF4-based gas.

[0111] Example 24 includes the method of any of Examples 19-23, wherein etching through a portion of the gate structure includes etching with BCl3 / Cl2 gas.

[0112] Example 25 is an integrated circuit comprising: a first semiconductor device having a first semiconductor region extending along a first direction from a first source region to a first drain region and a first gate structure extending along a second direction over the first semiconductor region; a second semiconductor device having a second semiconductor region extending along the first direction from a second source region to a second drain region and a second gate structure extending along the second direction over the second semiconductor region; and a gate notch located between the first gate structure and the second gate structure and separating the first gate structure and the second gate structure. The gate notch comprises a dielectric material and has a sidewall taper of less than 2 nm between the top surface of the first gate structure and the bottom surface of the second gate structure.

[0113] Example 26 includes the integrated circuit of Example 25, wherein the gate cutout has a height between approximately 150 nm and approximately 180 nm.

[0114] Example 27 includes the integrated circuit of Example 25 or 26, wherein a first semiconductor region includes a plurality of first semiconductor nanoribbons, and a second semiconductor region includes a plurality of second semiconductor nanoribbons.

[0115] Example 28 includes the integrated circuit of Example 27, wherein the plurality of first semiconductor nanoribbons and the plurality of second semiconductor nanoribbons comprise germanium, silicon, or a combination thereof.

[0116] Example 29 includes an integrated circuit of any of Examples 25-28, wherein a first gate structure includes a first gate dielectric surrounding a first semiconductor region, and a second gate structure includes a second gate dielectric surrounding a second semiconductor region.

[0117] Example 30 includes the integrated circuit of Example 29, wherein the first gate dielectric and the second gate dielectric are not present on any sidewall of the gate notch.

[0118] Example 31 includes an integrated circuit of any of Examples 25-30, wherein the gate cutout has a height-to-width ratio of at least 5:1.

[0119] Example 32 includes an integrated circuit of any of Examples 25-31, wherein the gate cutout has a first width at the top surface of the first gate structure and the second gate structure and a second width at the bottom surface of the first gate structure and the second gate structure, the first width being at most 10% larger than the second width.

[0120] Example 33 is a printed circuit board that includes an integrated circuit of any of Examples 25-32.

[0121] The above description of embodiments of the present disclosure has been provided for illustrative and explanatory purposes. It is not intended to be exhaustive or to limit the disclosure to the exact forms disclosed. Many modifications and variations are possible according to the present disclosure. The scope of the disclosure is not intended to be limited by this detailed description, but rather by the appended claims.

Claims

1. An integrated circuit structure, comprising: The first plurality of nanoribbons (104) are located above the first sub-fin region (108); The second plurality of nanoribbons (104) are located above the second sub-fin region (108), and the second plurality of nanoribbons are laterally spaced from the first plurality of nanoribbons; The dielectric filler (106) is adjacent to the first sub-fin region and the second sub-fin region; A first gate layer (118a) surrounds the first plurality of nanoribbons; A second gate layer (118b) surrounds the second plurality of nanoribbons; as well as A gate cutout (120) is laterally located between the first plurality of nanoribbons and the second plurality of nanoribbons, and extends into the dielectric filler between the first sub-fin region and the second sub-fin region. The gate cutout contacts the first gate layer and the second gate layer. The gate cutout has a bottom surface above the bottom surface of the dielectric filler. The gate cutout has a height-to-width ratio of 5:1 or greater.

2. The integrated circuit structure according to claim 1, wherein, The side of the gate cutout (120) is aligned with the side of the first gate layer (118a) and the side of the second gate layer (118b) along the direction from the first gate layer to the second gate layer.

3. The integrated circuit structure according to claim 1 or 2, further comprising: The first spacer (114) is located along the first side of the first gate layer (118a) and the second gate layer (118b); as well as The second spacer (114) is located along the second side of the first gate layer (118a) and the second gate layer (118b).

4. The integrated circuit structure according to claim 3, wherein, The gate cutout (120) is confined between the first spacer (114) and the second spacer (114).

5. The integrated circuit structure according to any one of the preceding claims, wherein, The first gate layer (118a) has an uppermost surface that is at the same level as the uppermost surface of the second gate layer (118b).

6. The integrated circuit structure according to any one of the preceding claims, wherein, The gate cutout (120) has an uppermost surface at the same level as the uppermost surface of the first gate layer (118a).

7. The integrated circuit structure according to any one of the preceding claims, wherein, The gate cutout (120) has a first width (w1) at the top surface of the gate cutout and a second width in the dielectric filler, the second width being smaller than the first width.

8. An integrated circuit structure, comprising: The first plurality of nanoribbons are located above the first sub-fin region; The second plurality of nanoribbons are located above the second sub-fin region, and the second plurality of nanoribbons are laterally spaced from the first plurality of nanoribbons. A first dielectric structure is adjacent to the first sub-fin region and the second sub-fin region; A first gate layer surrounds the first plurality of nanoribbons; A second gate layer surrounds the second plurality of nanoribbons; as well as A second dielectric structure is laterally located between the first plurality of nanoribbons and the second plurality of nanoribbons, and extends into the first dielectric structure between the first sub-fin region and the second sub-fin region. The second dielectric structure is different from the first dielectric structure. The second dielectric structure is in contact with the first gate layer and the second gate layer. The second dielectric structure has a bottom surface above the bottom surface of the first dielectric structure. The second dielectric structure has a height-to-width ratio of 5:1 or greater. The second dielectric structure has a first width at its top surface and a second width in the first dielectric structure, the second width being smaller than the first width.

9. The integrated circuit structure according to claim 8, wherein, The side of the second dielectric structure is aligned with the side of the first gate layer and the side of the second gate layer along the direction from the first gate layer to the second gate layer.

10. The integrated circuit structure according to claim 8, further comprising: A first gate spacer is located along a first side of the first gate layer and the second gate layer; as well as The second gate spacer extends along the second side of the first gate layer and the second gate layer.

11. The integrated circuit structure according to claim 10, wherein, The second dielectric structure is confined between the first gate spacer and the second gate spacer.

12. The integrated circuit structure according to claim 8, wherein, The first gate layer has an uppermost surface that is at the same level as the uppermost surface of the second gate layer.

13. The integrated circuit structure according to claim 8, wherein, The second dielectric structure has an uppermost surface at the same level as the uppermost surface of the first gate layer, wherein the uppermost surface of the second dielectric structure is at the same level as the uppermost surface of the second gate layer.

14. A method for manufacturing an integrated circuit structure, the method comprising: The first plurality of nanoribbons are formed above the first sub-fin region; A second plurality of nanoribbons are formed above the second sub-fin region, and the second plurality of nanoribbons are laterally spaced from the first plurality of nanoribbons. A dielectric filler is formed adjacent to the first sub-fin region and the second sub-fin region; A first gate layer is formed around the first plurality of nanoribbons; A second gate layer is formed around the second plurality of nanoribbons; as well as A gate cutout is laterally formed between the first plurality of nanoribbons and the second plurality of nanoribbons, and the gate cutout extends into the dielectric filler between the first sub-fin region and the second sub-fin region. The gate cutout contacts the first gate layer and the second gate layer. The gate cutout has a bottom surface above the bottom surface of the dielectric filler. The gate cutout has a height-to-width ratio of 5:1 or greater. The gate cutout has a first width at the top surface of the gate cutout and a second width in the dielectric filler, the second width being smaller than the first width.

15. The method according to claim 14, wherein, The side of the gate cutout is aligned with the side of the first gate layer and the side of the second gate layer along the direction from the first gate layer to the second gate layer.

16. The method of claim 14, further comprising: A first gate spacer is formed along a first side of the first gate layer and the second gate layer; as well as A second gate spacer is formed along the second side of the first gate layer and the second gate layer.

17. The method according to claim 16, wherein, The gate cutout is restricted between the first gate spacer and the second gate spacer.

18. The method according to claim 14, wherein, The first gate layer has an uppermost surface that is at the same level as the uppermost surface of the second gate layer.

19. The method of claim 14, wherein, The gate notch has an uppermost surface at the same level as the uppermost surface of the first gate layer.

20. The method of claim 14, wherein, The gate notch has an uppermost surface at the same level as the uppermost surface of the second gate layer.

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