A high-voltage secondary back-ESD protection device and a preparation method thereof

Abstract

The application discloses a high-voltage secondary back-charge electrostatic protection device and a preparation method thereof, and relates to the technical field of semiconductor devices. The high-voltage secondary back-charge electrostatic protection device comprises at least five P wells and N wells which are arranged transversely and alternately, and the number of the P wells is one more than that of the N wells; each N well is provided with an alternating structure, the alternating structure comprises at least one first P+ injection area and at least one first N+ injection area which are arranged alternately in a first direction; a P well between two adjacent N wells is provided with a second N+ injection area; the first direction is perpendicular to the transverse direction, and a plane formed by the first direction and the transverse direction is perpendicular to the depth direction of the device; each alternating structure is connected to serve as an anode of the device, and the second N+ injection area serves as a cathode of the device; the N well, the corresponding first N+ injection area, the adjacent intermediate P well and the corresponding second N+ area form an NPN triode structure; and the N well, the corresponding first P+ injection area, the adjacent intermediate P well and the corresponding second N+ area form an SCR path.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and in particular to a high-voltage secondary hysteresis electrostatic discharge protection device and its preparation method. Background Technology

[0002] Electrostatic discharge (ESD) is one of the main causes of integrated circuit chip and electronic product failure. With the development of power semiconductor technology, high-voltage integrated circuits have been widely used in power management and automotive electronics, but their complex operating environment places higher demands on ESD protection devices. On the one hand, ESD protection devices need to have the ability to withstand high voltage and high current discharge, quickly conducting under electrostatic pulses to safely discharge high voltage and high current to ground, preventing damage to the core circuit. On the other hand, ESD protection devices also need to have a sustaining voltage higher than the normal operating voltage of the circuit, fundamentally eliminating the risk of latch-up, ensuring that the circuit is not falsely triggered under normal operating conditions, and guaranteeing the long-term stability and reliability of the system.

[0003] In existing technologies, PNP transistors are generally used as electrostatic discharge (ESD) protection devices for high-voltage integrated circuits. The ESD protection principle of PNP transistors is as follows: when an ESD pulse is applied to the anode of the device, avalanche breakdown occurs between the N-type and P-type wells inside the PNP transistor, triggering the transistor to conduct and forming a low-resistance current path. This rapidly discharges the ESD current, achieving clamping protection for the core circuit. However, the traditional structure of PNP transistors has a high on-resistance and a relatively large secondary clamping voltage. This can cause the clamping voltage to exceed the withstand voltage limit of the core circuit, resulting in overvoltage damage and low reliability of ESD protection. Summary of the Invention

[0004] This application provides a high-voltage secondary hysteresis electrostatic discharge (ESD) protection device and its fabrication method, which simultaneously forms an NPN transistor structure and an SCR path in the ESD protection device. The secondary hysteresis conduction is achieved through the NPN transistor structure and the SCR path, which quickly discharges current and stably controls the clamping voltage below the withstand voltage limit of the core circuit, thus solving the problem of low reliability of ESD protection in the prior art.

[0005] In a first aspect, this application provides a high-voltage secondary hysteresis electrostatic discharge protection device, comprising at least five transversely alternating P-wells and N-wells, wherein the number of P-wells is one more than the number of N-wells; Each of the N-wells is provided with an alternating structure, the alternating structure including at least one first P+ injection region and at least one first N+ injection region alternately arranged in a first direction; a second N+ injection region is provided in the P-well between two adjacent N-wells; the first direction is perpendicular to the lateral direction, and the plane formed by the first direction and the lateral direction is perpendicular to the depth direction of the high voltage secondary hysteresis electrostatic discharge protection device. Each of the alternating structures is connected to serve as the device anode, and the second N+ injection region serves as the device cathode; The N-well and the corresponding first N+ injection region, as well as the adjacent intermediate P-well and the corresponding second N+ region, constitute an NPN transistor structure. The N-well and the corresponding first P+ injection region, as well as the adjacent intermediate P-well and the corresponding second N+ region, form an SCR path.

[0006] Optionally, a second P+ injection region is provided in the left P-well, and a third P+ injection region is provided in the right P-well. The second P+ injection region and the third P+ injection region are connected to the second N+ injection region and serve as the device cathode.

[0007] Optionally, the high-voltage secondary hysteresis electrostatic discharge protection device also includes a P-type substrate, wherein an N-type buried layer is disposed in the P-type substrate, and at least five transversely arranged P-wells and N-wells are disposed above the N-type buried layer.

[0008] Optionally, the length of the first P+ injection region is less than 1 μm.

[0009] Optionally, the ratio of the length of the first P+ injection region to the length of the first N+ injection region is in the range of 1:1 to 1:3.

[0010] Optionally, the spacing between the N-well and the adjacent P-well is 0.4~2 μm.

[0011] Optionally, a shallow trench isolation structure is provided between the N-well and the adjacent P-well.

[0012] Optionally, a shallow trench isolation structure is provided on the left side of the left-end P-well, and a shallow trench isolation structure is provided on the right side of the right-end P-well.

[0013] Secondly, this application provides a method for preparing a high-voltage secondary hysteresis electrostatic discharge protection device, comprising: An N-type buried layer is formed in a P-type substrate; P-type dopant ions and N-type dopant ions are alternately implanted laterally above the N-type buried layer to generate at least five laterally alternating P-wells and N-wells, wherein the number of P-wells is one more than the number of N-wells; In each of the N-wells, P-type dopant ions and N-type dopant ions are alternately implanted in a first direction to form an alternating structure. The alternating structure includes at least one first P+ implantation region and at least one first N+ implantation region alternately arranged in the first direction. The first direction is perpendicular to the lateral direction, and the plane formed by the first direction and the lateral direction is perpendicular to the depth direction of the high-voltage secondary hysteresis electrostatic discharge protection device. N-type dopant ions are injected into the P-well between two adjacent N-wells to form a second N+ implantation region, and P-type dopant ions are injected into the P-wells at both ends to form a second P+ implantation region and a third P+ implantation region, respectively. Each of the alternating structures is electrically connected to form the device anode, and the second N+ injection region, the second P+ injection region, and the third P+ injection region are electrically connected to form the device cathode.

[0014] Optionally, after laterally alternatingly implanting P-type and N-type dopant ions above the N-type buried layer to generate at least five laterally alternating P-wells and N-wells, the method further includes: Shallow trench etching and insulating dielectric filling are performed on both sides of the P-well to form a shallow trench isolation structure.

[0015] In this application, a high-voltage secondary hysteresis electrostatic discharge (ESD) protection device is constructed with at least five laterally alternating P-wells and N-wells, the number of P-wells being one more than the number of N-wells. Each N-well contains an alternating structure, which includes at least one first P+ injection region and at least one first N+ injection region alternating in a first direction. A second N+ injection region is disposed in the P-well between two adjacent N-wells. The first direction is perpendicular to the lateral direction, and the plane formed by the first direction and the lateral direction is perpendicular to the depth direction of the high-voltage secondary hysteresis ESD protection device. Each alternating structure is connected to serve as the anode of the device, and the second N+ injection region serves as the cathode of the device. The N-well and its corresponding first N+ injection region, as well as the adjacent intermediate P-well and its corresponding second N+ region, constitute an NPN transistor structure. The N-well and its corresponding first P+ injection region, as well as the adjacent intermediate P-well and its corresponding second N+ region, form an SCR path. Through the above technical means, the device can conduct the NPN transistor structure when a high electrostatic voltage arrives. The NPN transistor discharges the electrostatic current to reduce the trigger voltage to a lower sustaining voltage, achieving voltage hysteresis and preventing the instantaneous high voltage from directly impacting the core circuit. When the electrostatic current increases, the SCR path in the device is turned on. The extremely low resistance characteristic causes the anode and cathode voltages of the device to drop significantly again, achieving voltage hysteresis. Ultimately, the clamping voltage of the device is stabilized below the withstand voltage limit of the core circuit, preventing the core circuit from being damaged by overvoltage. This solves the problem of low reliability of electrostatic protection in the prior art. Attached Figure Description

[0016] Figure 1This is one of the structural schematic diagrams of a high-voltage secondary hysteresis electrostatic protection device provided in the embodiments of this application; Figure 2 This is a second schematic diagram of the structure of a high-voltage secondary hysteresis electrostatic protection device provided in the embodiments of this application; Figure 3 This is the third schematic diagram of the structure of a high-voltage secondary hysteresis electrostatic protection device provided in the embodiments of this application; Figure 4 This is a partial schematic diagram of the high-voltage secondary hysteresis electrostatic protection device provided in the embodiments of this application; Figure 5 This is a comparison diagram of the electrical characteristics of the device of this application and a conventional device provided in the embodiments of this application; Figure 6 This is a flowchart of the preparation method of the high-voltage secondary hysteresis electrostatic protection device provided in the embodiments of this application. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this application clearer, specific embodiments of this application will be described in further detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely for explaining this application and not for limiting it. It should also be noted that, for ease of description, only the parts relevant to this application are shown in the drawings, not all of them. Before discussing exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe operations (or steps) as sequential processes, many of these operations can be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the operations can be rearranged. A process can be terminated when its operation is completed, but it may also have additional steps not included in the drawings. A process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0018] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0019] In common existing implementations, PNP transistors are generally used as electrostatic discharge (ESD) protection devices for high-voltage integrated circuits. The ESD protection principle of PNP transistors is as follows: when an ESD pulse is applied to the anode of the device, avalanche breakdown occurs between the N-type and P-type wells inside the PNP transistor, triggering the transistor to conduct and forming a low-resistance current path. This quickly discharges the ESD current, achieving clamping protection for the core circuit. However, the traditional structure of PNP transistors has a high on-resistance and a relatively large secondary clamping voltage, which can cause the clamping voltage to exceed the withstand voltage limit of the core circuit. This leads to the core circuit being damaged due to overvoltage, resulting in low reliability of ESD protection. Alternatively, NPN transistors can also be used as ESD protection devices. However, due to their deep hysteresis, traditional NPN transistors have a low sustaining voltage after conduction. They are easily mistried under normal circuit operating voltage, leading to latch-up and forming a continuous low-resistance short circuit between the power supply and ground. This causes uncontrolled chip current and overheating, severely limiting their widespread application in high-voltage integrated circuits. Therefore, traditional bipolar junction transistors cannot simultaneously meet the core requirements of low on-resistance and high holding voltage for electrostatic discharge (ESD) protection, resulting in poor long-term stability and reliability of ESD protection.

[0020] To address the aforementioned issues, this embodiment provides a high-voltage secondary hysteresis electrostatic discharge (ESD) protection device. This device simultaneously incorporates an NPN transistor structure and an SCR path, enabling secondary hysteresis conduction through the NPN transistor structure and the SCR path. This allows for rapid current discharge while maintaining the clamping voltage stably below the withstand voltage limit of the core circuit.

[0021] Figures 1-3 Schematic diagrams of a high-voltage secondary hysteresis electrostatic discharge protection device provided in embodiments of this application are shown respectively. Figure 1 This is a 3D diagram of a high-voltage secondary hysteresis electrostatic discharge (ESD) protection device. Figure 2 This is a sectional view from a top-down perspective. Figure 3 It is a sectional view taken from a frontal perspective. For example... Figure 1-3As shown, the high-voltage secondary hysteresis electrostatic discharge (ESD) protection device includes at least five transversely arranged P-wells 11 and N-wells 12, with one more P-well 11 than N-well 12. Each N-well 12 has an alternating structure, which includes at least one first P+ injection region 13 and at least one first N+ injection region 14 alternating in a first direction. A second N+ injection region 15 is provided in the P-well 11 between two adjacent N-wells 12. The first direction is perpendicular to the transverse direction, and the plane formed by the first direction and the transverse direction is perpendicular to the depth direction of the high-voltage secondary hysteresis ESD protection device. Each alternating structure is connected to serve as the anode of the device, and the second N+ injection region 15 serves as the cathode of the device. The N-well 12 and the corresponding first N+ injection region 14, as well as the adjacent intermediate P-well 11 and the corresponding second N+ region, constitute an NPN transistor structure. The N-well 12 and the corresponding first P+ injection region 13, as well as the adjacent intermediate P-well 11 and the corresponding second N+ region, form an SCR path.

[0022] refer to Figures 1-3 When the N-well 12 and the corresponding first N+ injection region 14, along with the adjacent intermediate P-well 11 and the corresponding second N+ region, form an NPN transistor structure, the first N+ injection region 14 can serve as the emitter, the N-well 12 as the base, the P-well 11 as the collector, and the second N+ region as the collector. The emitter of the NPN transistor is connected to the anode, and the collector is connected to the cathode. When a high-voltage electrostatic pulse arrives, it flows in from the positive terminal, causing avalanche breakdown of the reverse PN junction between the N-well 12 and the P-well 11 in the NPN transistor structure, triggering the NPN transistor to conduct. At this time, the electrostatic pulse flowing in from the anode can pass through the NPN transistor structure and flow into the ground from the cathode, completing the first voltage hysteresis of the electrostatic pulse.

[0023] It should be noted that since multiple first N+ injection regions 14 are provided in the N-well 12, each first N+ injection region 14 will form a corresponding NPN transistor structure with the corresponding N-well 12 and any second N+ injection region 15 in the adjacent P-well 11. Furthermore, when N-wells 12 are provided on both sides of the P-well 11, each second N+ injection region 15 of the P-well 11 will form a corresponding NPN transistor structure with any first N+ injection region 14 of the N-wells 12 on both sides. Therefore, the device contains multiple parallel NPN transistor structures, thereby further reducing the on-resistance of the NPN transistor structures in the device and effectively improving the discharge speed of electrostatic pulses.

[0024] To better understand the design of a device with multiple NPN transistors connected in parallel, this embodiment uses... Figure 4 The following description uses a partial schematic diagram of a high-voltage secondary hysteresis electrostatic discharge (ESD) protection device as an example. Figure 4As shown, the plurality of first N+ injection regions 14 in the high-voltage secondary hysteresis electrostatic discharge (ESD) device include a first first N+ injection region 141, a second first N+ injection region 142, a third first N+ injection region 143, and a fourth first N+ injection region 144. The plurality of second N+ injection regions 15 in the high-voltage secondary hysteresis ESD device include a first second N+ injection region 151. The plurality of N-wells 12 in the high-voltage secondary hysteresis ESD device include a first N-well 121 and a second N-well 122. The plurality of P-wells 11 in the high-voltage secondary hysteresis ESD device include a first P-well 111. The first N+ injection region 141, the first N-well 121, the first P-well 111, and the first second N+ injection region 151 form an NPN transistor structure. The second first N+ injection region 142, the first N-well 121, the first P-well 111, and the first second N+ injection region 151 also form an NPN transistor structure. Similarly, the remaining first N+ injection regions 14 in the first N-well 121 will also form an NPN transistor structure with the first N-well 121, the first P-well 111, and the first second N+ injection region 151. The third first N+ injection region 143, the second N-well 122, the first P-well 111, and the first second N+ injection region 151 form an NPN transistor structure. The fourth first N+ injection region 144, the second N-well 122, the first P-well 111, and the first second N+ injection region 151 also form an NPN transistor structure. Similarly, the remaining first N+ injection regions 14 in the second N-well 122 will also form an NPN transistor structure with the second N-well 122, the first P-well 111, and the first second N+ injection region 151.

[0025] refer to Figures 1-3 The N-well 12, together with the corresponding first P+ injection region 13, and the adjacent intermediate P-well 11, together with the corresponding second N+ region, form a PNPN four-layer SCR path. The first layer of the SCR path connects to the anode of the device, and the last layer connects to the cathode. After the first hysteresis, if the current of the electrostatic pulse increases, the SCR path turns on. At this time, the SCR path becomes a PNPN four-layer conductive channel with extremely low resistance. The extremely low resistance characteristic causes the anode and cathode voltages of the device to drop significantly again, completing the second voltage hysteresis of the electrostatic pulse. Finally, the clamping voltage is stabilized below the withstand voltage limit of the core circuit, solving the problem of excessive secondary clamping voltage in traditional PNP devices. Moreover, the existence of the SCR path allows the device provided in this embodiment to have a higher failure current than NPN transistors at the same clamping voltage, enhancing the robustness of the device.

[0026] It should be noted that since multiple first P+ injection regions are provided in the N-well 12, each first P+ injection region 13 will form a corresponding PNPN four-layer SCR path with the corresponding N-well 12 and any second N+ injection region 15 in the adjacent P-well 11. Furthermore, when N-wells 12 are provided on both sides of the P-well 11, each second N+ injection region 15 of the P-well 11 will form a corresponding PNPN four-layer SCR path with any first P+ injection region 13 of the N-wells 12 on both sides. Therefore, the device contains multiple parallel PNPN four-layer SCR paths, thereby further reducing the on-resistance of the SCR path in the device and effectively improving the discharge speed of electrostatic pulses.

[0027] To better understand the design of multiple parallel SCR paths in a device, this embodiment uses... Figure 4 The following description uses a partial schematic diagram of a high-voltage secondary hysteresis electrostatic discharge (ESD) protection device as an example. Figure 4 As shown, the multiple first P+ injection regions 13 in the high-voltage secondary hysteresis electrostatic discharge (ESD) device include a first first P+ injection region 131, a second first P+ injection region 132, a third first P+ injection region 133, and a fourth first P+ injection region 134. The first first P+ injection region 131, the first N-well 121, the first P-well 111, and the first second N+ injection region 151 form an SCR path. The second first P+ injection region 132, the first N-well 121, the first P-well 111, and the first second N+ injection region 151 also form an SCR path. Similarly, the remaining first P+ injection regions 13 in the first N-well 121 also form an SCR path with the first N-well 121, the first P-well 111, and the first second N+ injection region 151. The third first P+ injection region 133, the second N-well 122, the first P-well 111, and the first second N+ injection region 151 form an SCR path. Similarly, the fourth first P+ injection region 134, the second N-well 122, the first P-well 111, and the first second N+ injection region 151 also form an SCR path.

[0028] Furthermore, the length of the first P+ injection region 13 is less than 1µm. The ratio of the length of the first P+ injection region 13 to the length of the first N+ injection region 14 is in the range of 1:1 to 1:3. The length of the first P+ injection region 13 and the ratio of its length to the first N+ injection region 14 affect the secondary hysteresis start-up current, i.e., the current that enables the SCR path. The length of the first P+ injection region 13 can be set to less than 1µm, and the ratio of its length to the first N+ injection region 14 can be set to 1:1 to 1:3, so that the device exhibits secondary hysteresis when the current exceeds the latch-up holding current. This avoids additional voltage surges caused by false latch-up triggering, further improving protection reliability and fundamentally eliminating the risk of core circuitry being damaged by overvoltage.

[0029] Furthermore, the spacing between N-well 12 and the adjacent P-well 11 is 0.4~2µm. The spacing between N-well 12 and the adjacent P-well 11 affects the turn-on voltage of the NPN transistor structure, that is, the trigger voltage for the first hysteresis. Setting the spacing between N-well 12 and the adjacent P-well 11 to 0.4~2µm can increase the trigger voltage for the first hysteresis to 9~40V, so that the device can be used in high-voltage integrated circuit designs of 9~40V.

[0030] refer to Figure 1-3 A second P+ injection region 16 is disposed within the left-end P-well 11, and a third P+ injection region 17 is disposed within the right-end P-well 11. The second P+ injection region 16 and the third P+ injection region 17 are connected to the second N+ injection region 15 and serve as the cathode of the device. The left-end P-well 11 is the leftmost P-well 11 of the device, and the right-end P-well 11 is the rightmost P-well 11 of the device. The second P+ injection region 16 and the third P+ injection region 17 inside the left-end and right-end P-wells 11 correspond to the cathode lead-out points at both ends of the device, respectively. The second P+ injection region 16, the third P+ injection region 17, and the second N+ injection region 15 are connected as a single unit by a metal wire, serving as the cathode of the device for grounding and discharging electrostatic current. In this embodiment, the second P+ injection region 16 and the third P+ injection region 17 are highly doped P-type regions with excellent conductivity. After being connected to the second N+ injection region 15, they can keep the potential of the entire cathode consistent, ensuring that the electrostatic current is evenly distributed to each discharge path and improving the robustness of the device.

[0031] refer to Figure 1 The device also includes a P-type substrate with an N-type buried layer therein, and at least five horizontally alternating P-wells 11 and N-wells 12 above the N-type buried layer. The N-type buried layer is parallel to the upper surface of the P-type substrate and is used to isolate the P-type substrate from the well structure above it, reduce parasitic leakage current between the substrate and the well region, and improve the breakdown voltage performance of the device.

[0032] refer to Figure 1 A shallow trench isolation structure (STI) is provided between the N-well 12 and the adjacent P-well 11. The STI is filled with an insulating medium, with consistent depth and fabrication process to ensure consistent isolation performance. In this embodiment, a shallow trench isolation structure (STI) is provided between each N-well 12 and the adjacent P-well 11 to block parasitic conduction between adjacent well regions and suppress inter-well parasitic leakage, ensuring normal operation of the core structure while improving the device's insulation performance.

[0033] refer to Figure 1 A shallow trench isolation (STI) structure is provided on the left side of the left P-well 11 and on the right side of the right P-well 11. That is, a shallow trench isolation (STI) structure is provided between the left P-well 11 and the left wall of the P-type substrate, and a shallow trench isolation (STI) structure is provided between the right P-well 11 and the right arm of the P-type substrate. The shallow trench isolation (STI) structures at both ends can isolate the device from the external environment and surrounding circuits, ensuring independent and stable operation of the device.

[0034] To verify the performance advantages of the high-voltage secondary hysteresis electrostatic discharge protector provided in this application compared to traditional devices, experimental tests were conducted on the electrical performance of the device and the traditional device, and the results were obtained. Figure 5 A comparison diagram of the electrical characteristics of the device of this application and a conventional device is shown. (See figure.) Figure 5 As shown, the experimental procedure tested the IV curves of the device proposed in this application and a conventional device (the green triangle represents the IV curve of the device proposed in this application, and the orange square represents the IV curve of the conventional device). The IV curve characterizes the relationship between the voltage across the device (horizontal axis) and the conduction current (horizontal axis), reflecting the device's conduction characteristics, clamping voltage, and other electrostatic discharge protection performance. Figure 5 As shown in the IV curve of the device presented in this application, at a voltage of approximately 16V, when an electrostatic pulse (ESP) arrives, the device undergoes avalanche breakdown. The NPN transistor in the device conducts, and the voltage drops from 16V to 10V, achieving the first voltage hysteresis. As the current of the ESP increases, the SCR path in the device conducts, causing the voltage to rapidly hysteresis down to 4V. The ESP current gradually increases to 8A, and the voltage is finally clamped at 15V, completing the second voltage hysteresis. The withstand voltage limit of the core circuit is generally 20V~30V. The clamping voltage of the device in this application is much lower than the withstand voltage limit, effectively preventing the core circuit from being overvoltage-damaged. In contrast, the IV curve of conventional devices shows that conventional devices only exhibit voltage hysteresis once when an ESP arrives. Afterward, as the current of the ESP increases, the voltage across the device also increases, eventually clamping the voltage above 30V, exceeding the withstand voltage limit of the core circuit, which easily leads to the problem of the core circuit being overvoltage-damaged.

[0035] like Figure 5As shown, the experiment also tested the leakage current curves of the device of this application and conventional devices respectively (the green diamond represents the leakage current curve of the device of this application, and the orange circle represents the leakage current curve of the conventional device). The leakage current curve characterizes the static leakage current of the device at different voltages (top horizontal axis), reflecting the device's insulation performance, static power consumption, and latch-up risk. The leakage current of the device of this application is maintained at 5 during normal operation. ~ The extremely low level of A indicates that the device in this application is completely in a high-impedance cutoff state under normal operating voltage, with no additional leakage current, thus meeting the chip's low power consumption requirements. Therefore, the internal structure of the device in this application effectively blocks leakage current paths, ensuring circuit stability.

[0036] Based on the above embodiments, this application also provides a method for preparing a high-voltage secondary hysteresis electrostatic discharge protection device. Figure 6 This is a flowchart illustrating the fabrication method of the high-voltage secondary hysteresis electrostatic discharge protection device provided in this application embodiment. For example... Figure 6 As shown, the preparation method includes: S110, An N-type buried layer is formed in a P-type substrate.

[0037] For example, a P-type substrate is provided, and N-type dopant ions are implanted into the P-type substrate using an ion implantation process. After implantation, a high-temperature annealing treatment is performed to activate the dopant ions and form an N-type buried layer inside the P-type substrate.

[0038] S120. P-type dopant ions and N-type dopant ions are alternately injected laterally above the N-type buried layer to generate at least five P-wells and N-wells arranged alternately laterally, with the number of P-wells being one more than the number of N-wells.

[0039] For example, an oxide pad layer and a silicon nitride mask layer are grown above an N-type buried layer. The regions to be formed as P-wells 11 and N-wells 12 are sequentially exposed on the N-type buried layer using photolithography and etching processes. Then, an ion implantation process is used to laterally and alternately implant P-type and N-type dopants to generate at least five laterally alternating P-wells 11 and N-wells 12. After implantation, high-temperature annealing is performed to activate the dopants and form a stable well region structure.

[0040] Furthermore, after generating P-well 11 and N-well 12, shallow trench etching and insulating dielectric filling can be performed on both sides of P-well 11 to form a shallow trench isolation structure (STI). For example, the silicon nitride mask layer and the oxide pad layer on the substrate surface are removed, a thin oxide layer is regrown, and the areas to be formed for the STI are exposed on both sides of P-well 11 using photolithography. Then, shallow trench etching is performed using a high-density plasma etching process. After etching, the inner walls of the trench are cleaned to remove polymer residues. Subsequently, a thin oxide layer is grown on the inner walls of the trench, and then filled with silicon dioxide insulating dielectric. After filling, global planarization is achieved using a chemical mechanical polishing process to remove excess dielectric from the surface, forming the shallow trench isolation structure (STI).

[0041] S130. P-type dopant ions and N-type dopant ions are alternately injected in a first direction in each N-well to form an alternating structure. The alternating structure includes at least one first P+ injection region and at least one first N+ injection region alternately arranged in the first direction. The first direction is perpendicular to the lateral direction, and the plane formed by the first direction and the lateral direction is perpendicular to the depth direction of the high-voltage secondary hysteresis electrostatic discharge protection device.

[0042] For example, the oxide layers on the surfaces of N-well 12 and P-well 11 are removed, and new oxide layers are grown as implantation masks. The regions to be formed into the first P+ implantation region 13 and the first N+ implantation region 14 are exposed above the N-well 12 by photolithography. Using an ion implantation process, P-type dopant ions and N-type dopant ions are alternately implanted in the N-well 12 in a first direction to form the first P+ implantation region 13 and the first N+ implantation region 14 alternating in the first direction within the N-well 12.

[0043] S140. N-type dopant ions are injected into the P-well between two adjacent N-wells to form a second N+ implantation region, and P-type dopant ions are injected into the P-wells at both ends to form a second P+ implantation region and a third P+ implantation region, respectively.

[0044] For example, the oxide layers on the surfaces of N-well 12 and P-well 11 are removed, and new oxide layers are grown as implantation masks. Using photolithography, the region above the left-end P-well 11 to form the second P+ implantation region 16 is exposed, the region above the right-end P-well 11 to form the third P+ implantation region 17 is exposed, and the region above the middle P-well 11 to form the second N+ implantation region 15 is exposed. P-type doped ions are implanted into the left-end and right-end P-wells 11 using ion implantation to form the second P+ implantation region 16 and the third P+ implantation region 17, respectively. N-type doped ions are implanted into the middle P-well 11 using ion implantation to form the second N+ implantation region 15.

[0045] S150. Electrically connect each alternating structure to form the anode of the device, and electrically connect the second N+ injection region, the second P+ injection region and the third P+ injection region to form the cathode of the device, so that the N-well and the corresponding first N+ injection region and the adjacent intermediate P-well and the corresponding second N+ region form an NPN transistor structure, and the N-well and the corresponding first P+ injection region and the adjacent intermediate P-well and the corresponding second N+ region form an SCR path.

[0046] For example, the alternating structures within each N-well 12 are electrically connected to each other via metal wires to form the device anode; the second N+ implantation region 15, the second P+ implantation region 16, and the third P+ implantation region 17 are electrically connected to each other via metal wires to form the device cathode. Finally, passivation is performed to complete the fabrication of the entire device.

[0047] The fabrication method provided in this embodiment strictly defines the fabrication process of the device structure, achieving precise fabrication of the device, improving process compatibility and product yield, while ensuring the protective performance of the device.

[0048] In summary, the high-voltage secondary hysteresis electrostatic discharge (ESD) protection device provided in this application embodiment comprises at least five transversely arranged P-wells 11 and N-wells 12, with the number of P-wells 11 being one more than the number of N-wells 12. Each N-well 12 contains an alternating structure, which includes at least one first P+ injection region 13 and at least one first N+ injection region 14 alternating in a first direction. A second N+ injection region 15 is provided in the P-well 11 between two adjacent N-wells 12. The first direction is perpendicular to the transverse direction, and the plane formed by the first direction and the transverse direction is perpendicular to the depth direction of the high-voltage secondary hysteresis ESD protection device. Each alternating structure is connected to serve as the anode of the device, and the second N+ injection region 15 serves as the cathode of the device. The N-well 12 and the corresponding first N+ injection region 14, as well as the adjacent intermediate P-well 11 and the corresponding second N+ region, constitute an NPN transistor structure. The N-well 12 and the corresponding first P+ injection region 13, as well as the adjacent intermediate P-well 11 and the corresponding second N+ region, form an SCR path. Through the aforementioned technical means, the device can conduct the NPN transistor structure when a high electrostatic discharge (ESD) voltage arrives. The NPN transistor discharges the ESD current to reduce the trigger voltage to a lower sustaining voltage, achieving primary voltage hysteresis and preventing the instantaneous high voltage from directly impacting the core circuit. When the ESD current increases, the SCR path in the device conducts, and its extremely low resistance characteristic causes the anode and cathode voltages of the device to drop significantly again, achieving secondary voltage hysteresis. Ultimately, the clamping voltage of the device is stabilized below the withstand voltage limit of the core circuit, preventing the core circuit from being damaged by overvoltage and solving the problem of low reliability of ESD protection in existing technologies.

[0049] The above description is merely a preferred embodiment and the technical principles employed in this application. This application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions that can be made by those skilled in the art will not depart from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of this application. The scope of this application is determined by the scope of the claims.

Claims

1. A high-voltage secondary hysteresis electrostatic discharge protection device, characterized in that, It includes at least five horizontally alternating P-wells and N-wells, wherein the number of P-wells is one more than the number of N-wells; Each of the N-wells is provided with an alternating structure, the alternating structure including at least one first P+ injection region and at least one first N+ injection region alternately arranged in a first direction; a second N+ injection region is provided in the P-well between two adjacent N-wells; the first direction is perpendicular to the lateral direction, and the plane formed by the first direction and the lateral direction is perpendicular to the depth direction of the high voltage secondary hysteresis electrostatic discharge protection device. Each of the alternating structures is connected to serve as the device anode, and the second N+ injection region serves as the device cathode; The N-well and the corresponding first N+ injection region, as well as the adjacent intermediate P-well and the corresponding second N+ region, constitute an NPN transistor structure. The N-well and the corresponding first P+ injection region, as well as the adjacent intermediate P-well and the corresponding second N+ region, form an SCR path.

2. The high-voltage secondary hysteresis electrostatic discharge protection device according to claim 1, characterized in that, A second P+ injection region is provided in the left P-well, and a third P+ injection region is provided in the right P-well. The second P+ injection region and the third P+ injection region are connected to the second N+ injection region and serve as the device cathode.

3. The high-voltage secondary hysteresis electrostatic discharge protection device according to claim 1, characterized in that, It also includes a P-type substrate, in which an N-type buried layer is disposed, and at least five transversely arranged P-wells and N-wells are disposed above the N-type buried layer.

4. The high-voltage secondary hysteresis electrostatic discharge protection device according to claim 1, characterized in that, The length of the first P+ injection region is less than 1 μm.

5. The high-voltage secondary hysteresis electrostatic discharge protection device according to claim 4, characterized in that, The ratio of the length of the first P+ injection region to the length of the first N+ injection region is in the range of 1:1 to 1:

3.

6. The high-voltage secondary hysteresis electrostatic discharge protection device according to claim 1, characterized in that, The spacing between the N-well and the adjacent P-well is 0.4~2 μm.

7. The high-voltage secondary hysteresis electrostatic discharge protection device according to claim 1, characterized in that, A shallow trench isolation structure is provided between the N-well and the adjacent P-well.

8. The high-voltage secondary hysteresis electrostatic discharge protection device according to claim 2, characterized in that, A shallow trench isolation structure is provided on the left side of the left-end P-well, and a shallow trench isolation structure is provided on the right side of the right-end P-well.

9. A method for preparing a high-voltage secondary hysteresis electrostatic discharge protection device, characterized in that, include: An N-type buried layer is formed in a P-type substrate; P-type dopant ions and N-type dopant ions are alternately implanted laterally above the N-type buried layer to generate at least five laterally alternating P-wells and N-wells, wherein the number of P-wells is one more than the number of N-wells; In each of the N-wells, P-type dopant ions and N-type dopant ions are alternately implanted in a first direction to form an alternating structure. The alternating structure includes at least one first P+ implantation region and at least one first N+ implantation region alternately arranged in the first direction. The first direction is perpendicular to the lateral direction, and the plane formed by the first direction and the lateral direction is perpendicular to the depth direction of the high-voltage secondary hysteresis electrostatic discharge protection device. N-type dopant ions are injected into the P-well between two adjacent N-wells to form a second N+ implantation region, and P-type dopant ions are injected into the P-wells at both ends to form a second P+ implantation region and a third P+ implantation region, respectively. Each of the alternating structures is electrically connected to form the anode of the device, and the second N+ injection region, the second P+ injection region, and the third P+ injection region are electrically connected to form the cathode of the device, so that the N-well and the corresponding first N+ injection region and the adjacent intermediate P-well and the corresponding second N+ region constitute an NPN transistor structure, and the N-well and the corresponding first P+ injection region and the adjacent intermediate P-well and the corresponding second N+ region form an SCR path.

10. The preparation method according to claim 9, characterized in that, After laterally alternating implantation of P-type and N-type dopant ions above the N-type buried layer to generate at least five laterally alternating P-wells and N-wells, the process further includes: Shallow trench etching and insulating dielectric filling are performed on both sides of the P-well to form a shallow trench isolation structure.

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