A back contact cell, cell assembly and photovoltaic system

Abstract

The application is suitable for the field of photovoltaic technology, and provides a back contact cell, a cell assembly and a photovoltaic system. The back contact cell comprises: a silicon substrate, the silicon substrate comprising a back surface; a first doped polysilicon layer and a second doped polysilicon layer arranged on the back surface; a first tunneling layer arranged between the first doped polysilicon layer and the silicon substrate; a second tunneling layer arranged between the second doped polysilicon layer and the silicon substrate; a first isolation layer arranged between the second doped polysilicon layer and the first doped polysilicon layer, the doping concentration of the first isolation layer being less than the doping concentration of the first doped polysilicon layer, and the doping concentration of the first isolation layer being less than 5E17 / cm 3 ; a leakage tunneling layer connecting the second doped polysilicon layer and the first doped polysilicon layer; a first electrode directly contacting the first doped polysilicon layer; and a second electrode directly contacting the second doped polysilicon layer. The back contact cell can avoid serious recombination loss caused by groove opening and reduce the risk of hot spot.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic technology, and in particular to a back-contact battery, battery module and photovoltaic system. Background Technology

[0002] A solar cell is a semiconductor device that converts solar energy into electrical energy. Under sunlight, a solar cell generates a photocurrent, which is then output as electrical energy through electrodes. In recent years, solar cell manufacturing technology has continuously improved, production costs have decreased, and conversion efficiency has increased. Solar cell power generation has become increasingly widespread and is an important energy source for electricity supply. In particular, because the grid lines of the back-contact cell are all located on the back side, the grid lines can avoid shading the front side of the cell. Compared to bifacial cells with grid lines on both the front and back sides, this improves cell efficiency.

[0003] In related technologies, the back side of a back-contact battery typically features a first doped polysilicon layer and a second doped polysilicon layer with opposite doping types. To achieve isolation between the first and second doped polysilicon layers, trenches are usually created on the silicon substrate between them. However, creating trenches on the silicon substrate can lead to high-temperature thermal stress on the substrate surface due to laser etching, causing damage to the crystal structure. The trenches can become carrier recombination centers, resulting in significant recombination losses on the silicon substrate and affecting the battery conversion efficiency. Furthermore, during actual use, back-contact batteries may be obstructed by objects such as leaves and dust. When these objects are obstructed, the temperature of the battery cells rises, creating hot spots. If the temperature of these hot spots exceeds a certain value, it will damage the battery cells, preventing them from generating electricity normally, and may even cause a fire, posing a serious risk of hot spots. Summary of the Invention

[0004] This invention provides a back-contact battery, which aims to solve the problems of existing back-contact batteries, such as large recombination losses due to trenching in the silicon substrate and serious hot spot risks.

[0005] This invention is implemented by providing a back contact battery, comprising: Silicon substrate, the silicon substrate including a back side; A first doped polysilicon layer is disposed on the back side; A second doped polysilicon layer is disposed on the back side, the doping type of the second doped polysilicon layer is opposite to that of the first doped polysilicon layer, and the second doped polysilicon layer and the first doped polysilicon layer are alternately disposed on the back side along a first direction; A first tunneling layer is disposed between the first doped polysilicon layer and the silicon substrate; The second tunneling layer is disposed between the second doped polysilicon layer and the silicon substrate; A first isolation layer is disposed between the second doped polysilicon layer and the first doped polysilicon layer. The doping concentration of the first isolation layer is less than that of the first doped polysilicon layer, and the doping concentration of the first isolation layer is less than 5E17 / cm². 3 ; A leakage tunneling layer is disposed between the second doped polysilicon layer and the first doped polysilicon layer, and the leakage tunneling layer connects the second doped polysilicon layer and the first doped polysilicon layer. The first electrode is in direct contact with the first doped polycrystalline silicon layer; and The second electrode is in direct contact with the second doped polycrystalline silicon layer.

[0006] Preferably, the first isolation layer is an intrinsic semiconductor layer or a doped semiconductor layer.

[0007] Preferably, the intrinsic semiconductor layer is at least one of an intrinsic polycrystalline silicon layer, an intrinsic amorphous silicon layer, an intrinsic microcrystalline silicon layer, and an intrinsic nanocrystalline silicon layer.

[0008] Preferably, the doped semiconductor layer is at least one of a doped polycrystalline silicon layer, a doped amorphous silicon layer, a doped microcrystalline silicon layer, and a doped nanocrystalline silicon layer.

[0009] Preferably, the first isolation layer and the first doped polycrystalline silicon layer are an integral structure.

[0010] Preferably, the first tunneling layer is further disposed between the first isolation layer and the silicon substrate.

[0011] Preferably, the thickness of the first isolation layer is greater than 0.05 micrometers.

[0012] Preferably, the doping concentration of the first isolation layer is less than 2E17 / cm. 3 .

[0013] Preferably, the doping concentration of the first isolation layer is less than 1E17 / cm. 3 .

[0014] Preferably, both the first doped polysilicon layer and the first isolation layer are doped with group VA elements, the second doped polysilicon layer is doped with group IIIA elements, and the doping concentration of the first isolation layer is less than 3E17 / cm³. 3 .

[0015] Preferably, both the first doped polysilicon layer and the first isolation layer are doped with Group IIIA elements, the second doped polysilicon layer is doped with Group VA elements, and the doping concentration of the first isolation layer is less than 1E17 / cm³. 3 .

[0016] Preferably, the doping concentration of both the second doped polysilicon layer and the first doped polysilicon layer is greater than 1E19 / cm. 3 .

[0017] Preferred options also include: The second isolation layer is disposed between the first isolation layer and the second doped polysilicon layer.

[0018] Preferably, the thickness of the second isolation layer is greater than or equal to the thickness of the leakage tunneling layer.

[0019] Preferably, the ratio of the thickness of the second insulating layer to the thickness of the leakage tunneling layer is 1 to 5.

[0020] Preferably, the ratio of the thickness of the second insulating layer to the thickness of the leakage tunneling layer is 1.1 to 2.

[0021] Preferably, the doping concentration of the second isolation layer is less than the doping concentration of the leakage tunneling layer.

[0022] Preferably, the second isolation layer is made of the same material as the second tunneling layer.

[0023] Preferably, the second isolation layer and the second tunneling layer are an integral structure.

[0024] Preferably, the leakage tunneling layer is made of the same material as the second tunneling layer.

[0025] Preferably, the leakage tunneling layer and the second tunneling layer are an integral structure.

[0026] Preferred options also include: A passivation layer covers the second doped polysilicon layer and the first doped polysilicon layer, and the passivation layer continuously covers the back side of the silicon substrate. The first electrode passes through the passivation layer and contacts the first doped polysilicon layer, and the second electrode passes through the passivation layer and contacts the second doped polysilicon layer.

[0027] Preferably, the second doped polysilicon layer includes a main body portion located on the second tunneling layer, and along the first direction, the first isolation layer is located between the main body portion and the first doped polysilicon layer.

[0028] Preferably, the second doped polysilicon layer further includes: A first extension portion connected to one end of the main body portion, the first extension portion being bent relative to the main body portion, and the first extension portion extending in a direction away from the back side; A second extension connected to the first extension, the second extension being bent relative to the first extension, the second extension extending along the first direction and toward the side where the second isolation layer is located, and the projection of the second extension along the thickness direction of the silicon substrate at least covering a portion of the second isolation layer.

[0029] Preferred options also include: The third isolation layer is located between the second extension and the first isolation layer.

[0030] Preferably, the thickness of the third isolation layer is greater than the thickness of the second isolation layer.

[0031] Preferably, the orthographic projection of the second extension on the back surface does not coincide with the orthographic projection of the first doped polysilicon layer on the back surface.

[0032] Preferably, the second doped polysilicon layer further includes: A third extension is connected to the other end of the main body, the third extension is bent relative to the main body, and the third extension extends away from the back side; A fourth extension is connected to the third extension, the fourth extension is bent relative to the third extension, the fourth extension extends along the first direction and toward the side where the leakage tunneling layer is located, and the projection of the fourth extension along the thickness direction of the silicon substrate at least covers the leakage tunneling layer.

[0033] Preferred options also include: A fourth isolation layer is located between the fourth extension and the first doped polysilicon layer.

[0034] Preferably, the first tunneling layer and the second tunneling layer are one or a combination of at least two of the following: silicon oxide layer, aluminum oxide layer, silicon nitride layer, and silicon oxynitride layer.

[0035] Preferably, the second isolation layer is one or a combination of at least two of the following: silicon oxide layer, aluminum oxide layer, silicon nitride layer, and silicon oxynitride layer.

[0036] Preferably, the leakage tunneling layer is one or a combination of at least two of the following: silicon oxide layer, aluminum oxide layer, silicon nitride layer, and silicon oxynitride layer.

[0037] Preferred options also include: A barrier layer is disposed in at least a portion of the area between the first isolation layer and the second isolation layer.

[0038] Preferably, the barrier layer is one or a combination of at least two of borosilicate glass, phosphosilicate glass, silicon oxide, silicon nitride, and silicon oxynitride.

[0039] Preferably, it also includes: The boundary portion located between the first isolation layer and the first doped polysilicon layer, along the first direction, has a doping concentration at the end of the boundary portion closer to the first doped polysilicon layer that is greater than the doping concentration at the end of the boundary portion closer to the first isolation layer.

[0040] Preferably, both the first isolation layer and the first doped polysilicon layer are provided with pores, and the number of pores per unit area of ​​the first isolation layer is less than the number of pores per unit area of ​​the first doped polysilicon layer.

[0041] Preferably, both the first isolation layer and the first doped polysilicon layer are provided with holes, and the average maximum radial size of the holes per unit area of ​​the first isolation layer is smaller than the average maximum radial size of the holes per unit area of ​​the first doped polysilicon layer.

[0042] Preferably, both the second doped polysilicon layer and the first doped polysilicon layer extend along a second direction, which intersects with the first direction. The ratio of the sum of the lengths of the leakage tunneling layer's orthographic projection along the second direction on the back surface to the area of ​​the back surface is 0.01~0.2 mm / mm. 2 .

[0043] Preferably, the surface of the third isolation layer facing away from the silicon substrate is provided with a first textured structure.

[0044] Preferably, the surface of the fourth isolation layer facing away from the silicon substrate is provided with a second textured structure.

[0045] The present invention also provides a battery assembly including the aforementioned back contact battery.

[0046] The present invention also provides a photovoltaic system including the above-described battery module.

[0047] The present invention provides a back contact battery in which a first isolation layer is disposed in a portion of the region between a second doped polycrystalline silicon layer and a first doped polycrystalline silicon layer, and the doping concentration of the first isolation layer is controlled to be less than the doping concentration of the first doped polycrystalline silicon layer, wherein the doping concentration of the first isolation layer is less than 5E17 / cm³. 3A low-doped first isolation layer is used, resulting in weak current transport capability. This first isolation layer effectively isolates the second-doped polysilicon layer from the first-doped polysilicon layer, preventing conduction between them and achieving good electrical isolation. Therefore, it eliminates the need for trenches in the silicon substrate to isolate the first and second-doped polysilicon layers, avoiding severe recombination losses caused by trenching and thus improving battery conversion efficiency. Simultaneously, the second doped... A leakage tunneling layer is provided in a portion of the area between the polycrystalline silicon layer and the first doped polycrystalline silicon layer. The leakage tunneling layer connects the second doped polycrystalline silicon layer and the first doped polycrystalline silicon layer. When the back contact cell is blocked and a certain reverse voltage is provided to the blocked back contact cell, the leakage tunneling layer can conduct the first doped polycrystalline silicon layer and the second doped polycrystalline silicon layer. This prevents the blocked back contact cell from becoming a load and consuming the energy generated by other cells, ensuring that the conversion efficiency of the back contact cell is basically not lost, and also prevents overheating when the back contact cell is blocked, thereby reducing the risk of hot spots. Attached Figure Description

[0048] Figure 1 A cross-sectional schematic diagram of a back contact battery according to an embodiment of the present invention; Figure 2 for Figure 1 A magnified schematic diagram of part A in the middle; Figure 3 A schematic diagram of the back side structure of a back contact battery provided in an embodiment of the present invention; Figure 4 A cross-sectional schematic diagram of a back-contact battery according to another embodiment of the present invention; Figure 5 A cross-sectional schematic diagram of a back-contact battery according to another embodiment of the present invention; Figure 6 A cross-sectional schematic diagram of a back-contact battery according to another embodiment of the present invention.

[0049] Explanation of key symbols: Back contact battery 100, silicon substrate 1, back side 101, front side 102, first doped polycrystalline silicon layer 2, second doped polycrystalline silicon layer 3, first tunneling layer 4, second tunneling layer 5, first isolation layer 6, leakage tunneling layer 7, first electrode 8, second electrode 9, second isolation layer 12, passivation layer 11, main body 30, first extension 31, second extension 32, third extension 33, fourth extension 34, third isolation layer 13, fourth isolation layer 14, barrier layer 15, boundary portion 16, first textured structure 131, second textured structure 141. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. Examples of embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the invention, and should not be construed as limiting the invention. Furthermore, it should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0051] In the description of this invention, it should be understood that the terms "upper", "lower", "backlight", "front", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0052] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0053] The following disclosure provides numerous different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0054] Please refer to Figures 1-3 This invention provides a back contact battery 100, comprising: Silicon substrate 1, silicon substrate 1 includes a back surface 101; A first doped polysilicon layer 2 is disposed on the back side 101; A second doped polysilicon layer 3 is provided on the back side 101. The doping type of the second doped polysilicon layer 3 is opposite to that of the first doped polysilicon layer 2. The second doped polysilicon layer 3 and the first doped polysilicon layer 2 are alternately disposed on the back side 101 along the first direction X. The first tunneling layer 4 is disposed between the first doped polysilicon layer 2 and the silicon substrate 1; The second tunneling layer 5 is disposed between the second doped polysilicon layer 3 and the silicon substrate 1; A first isolation layer 6 is disposed between the second doped polysilicon layer 3 and the first doped polysilicon layer 2. The doping concentration of the first isolation layer 6 is less than the doping concentration of the first doped polysilicon layer 2, and the doping concentration of the first isolation layer 6 is less than 5E17 / cm. 3 ; The leakage tunneling layer 7 is disposed between the second doped polysilicon layer 3 and the first doped polysilicon layer 2, and the leakage tunneling layer 7 connects the second doped polysilicon layer 3 and the first doped polysilicon layer 2. The first electrode 8 is in direct contact with the first doped polycrystalline silicon layer 2; and The second electrode 9 is in direct contact with the second doped polycrystalline silicon layer 3.

[0055] An embodiment of the present invention provides a back contact battery 100 by providing a first isolation layer 6 in a portion of the region between a second doped polysilicon layer 3 and a first doped polysilicon layer 2. The doping concentration of the first isolation layer 6 is lower than that of the first doped polysilicon layer 2, and the doping concentration of the first isolation layer 6 is less than 5E17 / cm³. 3 By configuring the first isolation layer 6 with a low doping concentration, its current transport capability is weakened, preventing conduction between the second doped polysilicon layer 3 and the first doped polysilicon layer 2. This achieves electrical isolation between the two layers, eliminating the need for trenches on the silicon substrate 1 to isolate the first and second doped polysilicon layers 2 and 3. This avoids severe recombination losses caused by trenches on the silicon substrate 1, thus improving battery conversion efficiency. Simultaneously, a leakage tunneling layer 7 is formed in a portion of the area between the second doped polysilicon layer 3 and the first doped polysilicon layer 2, connecting the second doped polysilicon layer 3... When the back contact cell is shaded and a certain reverse voltage is supplied to the shaded back contact cell, the leakage tunneling layer 7 conducts the first doped polysilicon layer 2 and the second doped polysilicon layer 3. The current can be transmitted through the first doped polysilicon layer 2, the leakage tunneling layer 7 and the second doped polysilicon layer 3. This prevents the shaded cell from becoming a load and consuming the energy generated by other illuminated cells, ensuring that the conversion efficiency of the back contact cell is basically not lost. It can also prevent overheating when the back contact cell is shaded, reduce the risk of hot spots, and ensure the safety and reliable power generation of the battery module.

[0056] In this embodiment of the invention, the silicon substrate 1 includes a back side 101 and a front side 102 disposed opposite to each other. The back side 101 of the silicon substrate 1 is the side of the silicon substrate 1 that is away from sunlight when the back contact battery 100 is working normally, and the front side 102 of the silicon substrate 1 is the side of the silicon substrate 1 that faces sunlight when the back contact battery 100 is working normally.

[0057] In this embodiment of the invention, one of the first doped polysilicon layer 2 and the second doped polysilicon layer 3 is a P-type doped polysilicon layer, and the other is an N-type doped polysilicon layer. The specific doping types of the first doped polysilicon layer 2 and the second doped polysilicon layer 3 are not limited. Specifically, the first doped polysilicon layer 2 can be a P-type doped polysilicon layer, and the second doped polysilicon layer 3 can be an N-type doped polysilicon layer; or, the first doped polysilicon layer 2 can be an N-type doped polysilicon layer, and the second doped polysilicon layer 3 can be a P-type doped polysilicon layer. The P-type doped polysilicon layer is doped with a P-type dopant, and the N-type doped polysilicon layer is doped with an N-type dopant. The P-type dopant is a dopant of a Group IIIA element in the periodic table, and the N-type dopant is a dopant of a Group VA element in the periodic table. For example, the P-type dopant can be a boron dopant, and the N-type dopant can be a phosphorus dopant.

[0058] In this configuration, there are multiple first-doped polysilicon layers 2 and second-doped polysilicon layers 3, both extending along a second direction Y. The first-doped polysilicon layers 2 and 3 are alternately arranged along a first direction X. A first isolation layer 6 is provided in a portion of the area between the first-doped polysilicon layers 2 and 3, providing good electrical isolation between them. In the area between the first-doped polysilicon layers 2 and 3 where the first isolation layer 6 is not provided, a leakage tunneling layer 7 is provided. When the solar cell is shaded, the leakage tunneling layer 7 forms a leakage path between the first-doped polysilicon layers 2 and 3, thereby reducing the risk of hot spots. The distribution of the first isolation layer 6 and the leakage tunneling layer 7 on the back side 101 is not limited. It can be that the first isolation layer 6 and the leakage tunneling layer 7 are simultaneously provided on any adjacent first doped polysilicon layer 2 and second doped polysilicon layer 3, or the first isolation layer 6 can be provided between only a portion of the first doped polysilicon layer 2 and the second doped polysilicon layer 3, and the leakage tunneling layer 7 can be provided between a portion of the first doped polysilicon layer 2 and the second doped polysilicon layer 3.

[0059] In this embodiment of the invention, a first tunneling layer 4 is disposed between a first doped polysilicon layer 2 and a silicon substrate 1, and a second tunneling layer 5 is disposed between a second doped polysilicon layer 3 and a silicon substrate 1. The first tunneling layer 4 and the second tunneling layer 5 passivate the surface of the silicon substrate 1 and allow carriers to pass through efficiently. The materials of the first tunneling layer 4 and the second tunneling layer 5 can be the same or different.

[0060] As an embodiment of the present invention, the first tunneling layer 4 and the second tunneling layer 5 are one or more of the following: silicon oxide layer, aluminum oxide layer, silicon nitride layer, and silicon oxynitride layer.

[0061] In this embodiment of the invention, the first electrode 8 is in direct contact with the first doped polysilicon layer 2, and the second electrode 9 is in direct contact with the second doped polysilicon layer 3. This means that no conductive layer is required between the first electrode 8 and the first doped polysilicon layer 2; similarly, no conductive layer is required between the second electrode 9 and the second doped polysilicon layer 3. This reduces production costs and ensures good current transfer between the first electrode 8 and the first doped polysilicon layer 2, as well as between the second electrode 9 and the second doped polysilicon layer 3.

[0062] In this embodiment of the invention, the doping concentration of the first isolation layer 6 is less than 5E17 / cm. 3 This can be understood as the concentration of active impurity atoms per unit volume of the first isolation layer 6 being less than 5E17 / cm³. 3 For example, if the doped atom in the first isolation layer 6 is a phosphorus atom, then the concentration of activated phosphorus atoms in the first isolation layer 6 is less than 5E17 / cm³. 3 If the doped atoms in the first doped polysilicon layer 2 are boron atoms, then the concentration of active boron atoms in the first isolation layer 6 is less than 5E17 / cm³. 3 .

[0063] In this embodiment of the invention, the doping concentration of the first isolation layer 6 can be less than 5E17 / cm. 3 Any value in the range. For example, the doping concentration of the first isolation layer 6 can be 0 / cm. 3 1E3 / cm 3 1E4 / cm 3 1E5 / cm 3 1E6 / cm 3 1E8 / cm 3 1E9 / cm 3 1E10 / cm 3 1E11 / cm 3 1E12 / cm 31E13 / cm 3 1E14 / cm 3 1E15 / cm 3 1E16 / cm 3 1E17 / cm 3 2E17 / cm 3 3E17 / cm 3 4E17 / cm 3 Any value in the range.

[0064] As an embodiment of the present invention, the first isolation layer 6 is an intrinsic semiconductor layer or a doped semiconductor layer.

[0065] In this embodiment of the invention, the first isolation layer 6 may be made of the same material as the first doped polysilicon layer 2, or it may be made of a different material. The first isolation layer 6 may be an intrinsic semiconductor layer or a doped semiconductor layer, as long as the doping concentration of the first isolation layer 6 is controlled to be less than 5E17 / cm. 3 Therefore, within this doping concentration range, the current transport capability of the first isolation layer 6 is relatively weak, yet isolation between the first doped polysilicon layer 2 and the second doped polysilicon layer 3 can still be achieved. Of course, in some embodiments, the first isolation layer 6 can also be an oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0066] As an embodiment of the present invention, the intrinsic semiconductor layer is at least one of the following: intrinsic polycrystalline silicon layer, intrinsic amorphous silicon layer, intrinsic microcrystalline silicon layer, and intrinsic nanocrystalline silicon layer.

[0067] In one embodiment of the present invention, the doped semiconductor layer is at least one of a doped polycrystalline silicon layer, a doped amorphous silicon layer, a doped microcrystalline silicon layer, and a doped nanocrystalline silicon layer. Preferably, the first isolation layer 6 is a doped polycrystalline silicon layer, and the doping type of the first isolation layer 6 is the same as the doping type of the first doped polycrystalline silicon layer 2, which facilitates the integral fabrication of the first isolation layer 6 and the first doped polycrystalline silicon layer 2.

[0068] As an embodiment of the present invention, the first isolation layer 6 and the first doped polysilicon layer 2 are an integral structure.

[0069] In this embodiment, the first isolation layer 6 is a doped polysilicon layer. In this embodiment, an intrinsic polysilicon layer can be formed first, and then a low-concentration doped polysilicon layer can be formed at the location of the first isolation layer 6 as the first isolation layer 6. At the location of the first doped polysilicon layer 2, a higher concentration doped polysilicon layer can be formed as the first doped polysilicon layer 2, which facilitates processing.

[0070] As an embodiment of the present invention, the first tunneling layer 4 is also disposed between the first isolation layer 6 and the silicon substrate 1.

[0071] In this embodiment, a first tunneling layer 4 is also provided between the first isolation layer 6 and the silicon substrate 1. The first tunneling layer 4 can passivate the position of the first isolation layer 6, which can further improve the battery efficiency.

[0072] As an embodiment of the present invention, the thickness D6 of the first isolation layer 6 is greater than 0.05 micrometers.

[0073] In this embodiment, the thickness D6 of the first isolation layer 6 is the dimension of the first isolation layer 6 along the thickness direction Z of the silicon substrate 1. If the thickness D6 of the first isolation layer 6 is too small, the reverse breakdown voltage between the first doped polysilicon layer 2 and the second doped polysilicon layer 3 will be too low, easily causing local leakage. Therefore, the thickness D6 of the first isolation layer 6 is controlled to be greater than 0.05 micrometers to ensure good isolation effect of the first isolation layer 6 and avoid leakage between the first doped polysilicon layer 2 and the second doped polysilicon layer 3. The thickness D6 of the first isolation layer 6 can be the same as or different from the thickness of the first doped polysilicon layer 2. Preferably, the thickness D6 of the first isolation layer 6 is the same as the thickness of the first doped polysilicon layer 2.

[0074] In one embodiment of the present invention, the doping concentration of the first isolation layer 6 is less than 2E17 / cm. 3 .

[0075] In this embodiment, the doping concentration of the first isolation layer 6 is controlled to be less than 2E17 / cm. 3 This further reduces the doping concentration of the first isolation layer 6, which helps to ensure the good isolation effect of the first isolation layer 6.

[0076] As an embodiment of the present invention, the doping concentration of the first isolation layer 6 is less than 1E17 / cm. 3 .

[0077] In this embodiment, the doping concentration of the first isolation layer 6 is controlled to be less than 1E17 / cm. 3 This further reduces the doping concentration of the first isolation layer 6, which helps to ensure the good isolation effect of the first isolation layer 6.

[0078] In one embodiment of the present invention, both the first doped polysilicon layer 2 and the first isolation layer 6 are doped with group VA elements, the second doped polysilicon layer 3 is doped with group IIIA elements, and the doping concentration of the first isolation layer 6 is less than 3E17 / cm³. 3 .

[0079] In this embodiment, both the first doped polysilicon layer 2 and the first isolation layer 6 are doped with group VA elements from the periodic table, and the second doped polysilicon layer 3 is doped with group IIIA elements from the periodic table. The doping concentration of the first isolation layer 6 is controlled to be less than 3E17 / cm³. 3This ensures good isolation effect of the first isolation layer 6, while also facilitating the control of the doping concentration of the first isolation layer 6 and making it easier to process.

[0080] In one embodiment of the present invention, both the first doped polysilicon layer 2 and the first isolation layer 6 are doped with group IIIA elements, the second doped polysilicon layer 3 is doped with group VA elements, and the doping concentration of the first isolation layer 6 is less than 1E17 / cm³. 3 .

[0081] In this embodiment, both the first doped polysilicon layer 2 and the first isolation layer 6 are doped with Group IIIA elements from the periodic table, and when the second doped polysilicon layer 3 is doped with Group VA elements from the periodic table, the doping concentration of the first isolation layer 6 is controlled to be less than 1E17 / cm³. 3 This ensures good isolation effect of the first isolation layer 6, while also facilitating the control of the doping concentration of the first isolation layer 6 and making it easier to process.

[0082] In one embodiment of the present invention, the doping concentrations of both the second doped polysilicon layer 3 and the first doped polysilicon layer 2 are greater than 1E19 / cm². 3 .

[0083] In this embodiment, the doping concentrations of both the second doped polysilicon layer 3 and the first doped polysilicon layer 2 are controlled to be greater than 1E19 / cm. 3 This ensures a lower contact resistance between the second doped polysilicon layer 3 and the second electrode 9, and between the first doped polysilicon layer 2 and the first electrode 8, which is more conducive to improving battery efficiency.

[0084] As an embodiment of the present invention, the ratio of the length of the first isolation layer 6 along the first direction X to the length of the first doped polysilicon layer 2 along the first direction X is 0.006~15.

[0085] In this embodiment, the length of the first isolation layer 6 along the first direction X can be less than the length of the first doped polysilicon layer 2 along the first direction X, or the length of the first isolation layer 6 along the first direction X can be greater than the length of the first doped polysilicon layer 2 along the first direction X, or the length of the first isolation layer 6 along the first direction X can be equal to the length of the first doped polysilicon layer 2 along the first direction X. The ratio of the length of the first isolation layer 6 along the first direction X to the length of the first doped polysilicon layer 2 along the first direction X is controlled to be between 0.006 and 15. This avoids the first isolation layer 6 being too short along the first direction X, ensuring good isolation between the first doped polysilicon layer 2 and the second doped polysilicon layer 3, and also avoids the first isolation layer 6 being too long along the first direction X, which would result in the first doped polysilicon layer 2 being too short along the first direction X, thus ensuring good contact between the first electrode 8 and the first doped polysilicon layer 2.

[0086] In this embodiment, the ratio of the length of the first isolation layer 6 along the first direction X to the length of the first doped polysilicon layer 2 along the first direction X can be any value among 0.006, 0.01, 0.1, 0.2, 0.5, 1.0, 1.5, 2, 3, 3.5, 5, 5.5, 6, 6.5, 7, 8, 8.5, 9, 10, 10.5, 11, 12, 12.5, 13, 14, 14.5, and 15.

[0087] As one embodiment of the present invention, it also includes: The second isolation layer 12 is disposed between the first isolation layer 6 and the second doped polysilicon layer 3.

[0088] In this embodiment, a second isolation layer 12 is provided between the first isolation layer 6 and the second doped polysilicon layer 3. The second isolation layer 12 further physically isolates the first isolation layer 6 and the second doped polysilicon layer 3, further improving the electrical isolation effect between the second doped polysilicon layer 3 and the first doped polysilicon layer 2, and ensuring the reliability of the isolation between the second doped polysilicon layer 3 and the first doped polysilicon layer 2. Moreover, the isolation layer 6 can block the mutual diffusion of doped atoms between the second doped polysilicon layer 3 and the first doped polysilicon layer 2, preventing doped atoms in the second doped polysilicon layer 3 from diffusing into the first doped polysilicon layer 2, and at the same time preventing doped atoms in the first doped polysilicon layer 2 from diffusing into the second doped polysilicon layer 3. This avoids the first tunneling layer 4 and the second tunneling layer 5 being attacked by doped atoms from the second doped polysilicon layer 3 and the first doped polysilicon layer 2 at the same time, thus avoiding excessive pore structure caused by the simultaneous attack of doped atoms from the second doped polysilicon layer 3 and the first doped polysilicon layer 2. This ensures a good passivation effect for the first tunneling layer 4 and the second tunneling layer 5, which is more conducive to further improving battery efficiency.

[0089] As an embodiment of the present invention, the thickness D12 of the second isolation layer 12 is greater than or equal to the thickness D7 of the leakage tunneling layer 7.

[0090] In this embodiment, the thickness D12 of the second isolation layer 12 is the dimension of the second isolation layer 12 along the first direction X, and the thickness D7 of the leakage tunneling layer 7 is the dimension of the leakage tunneling layer 7 along the first direction X. Controlling the thickness of the second isolation layer 12 along the first direction X to be greater than or equal to the thickness of the leakage tunneling layer 7 along the first direction X can improve the isolation effect of the second isolation layer 12. Furthermore, when the battery cell is blocked, it facilitates the formation of a leakage channel between the second doped polycrystalline silicon layer 3 and the first doped polycrystalline silicon layer 2 through the leakage tunneling layer 7, which can reduce the risk of hot spots and improve the safety and reliable power generation of the battery. Preferably, the thickness D12 of the second isolation layer 12 is greater than the thickness D7 of the leakage tunneling layer 7.

[0091] As an embodiment of the present invention, the ratio of the thickness D12 of the second isolation layer 12 to the thickness D7 of the leakage tunneling layer 7 is 1 to 5.

[0092] In this embodiment, the ratio of the thickness D12 of the second isolation layer 12 to the thickness D7 of the leakage tunneling layer 7 is controlled to be 1~5, so as to achieve a good isolation effect of the second isolation layer 12 and ensure that the leakage tunneling layer 7 can conduct the second doped polysilicon layer 3 and the first doped polysilicon layer 2 when the cell is blocked.

[0093] In this embodiment, the ratio of the thickness D12 of the second isolation layer 12 to the thickness D7 of the leakage tunneling layer 7 can be any value among 1, 1.1, 1.2, 1.3, 1.5, 1.6, 1.8, 1.9, 2, 2.3, 2.5, 2.8, 3, 3.5, 4, 4.5, and 5.

[0094] As an embodiment of the present invention, the ratio of the thickness D12 of the second isolation layer 12 to the thickness D7 of the leakage tunneling layer 7 is 1.1 to 2.

[0095] In this embodiment, the ratio of the thickness D12 of the second isolation layer 12 to the thickness D7 of the leakage tunneling layer 7 is further controlled to be 1.1~2, which further ensures the good isolation effect of the second isolation layer 12 and ensures that the leakage tunneling layer 7 conducts the second doped polysilicon layer 3 and the first doped polysilicon layer 2 when the cell is blocked.

[0096] As an embodiment of the present invention, the thickness D12 of the second isolation layer 12 is 1~20 nanometers.

[0097] In this embodiment, the thickness D12 of the second isolation layer 12 is the dimension of the second isolation layer 12 along the first direction X. The thickness D12 of the second isolation layer 12 is controlled to be 1~20 nanometers to ensure good isolation effect of the second isolation layer 12.

[0098] The thickness D12 of the second insulating layer 12 can be any value from 1 to 20 nanometers. For example, the thickness D12 of the second insulating layer 12 can be 1.1 nanometers, 1.3 nanometers, 1.5 nanometers, 1.7 nanometers, 1.9 nanometers, 2.0 nanometers, 2.3 nanometers, 2.5 nanometers, 2.6 nanometers, 3 nanometers, 3.3 nanometers, 3.5 nanometers, 4.0 nanometers, 4.1 nanometers, 4.3 nanometers, 4.8 nanometers, 5.0 nanometers, 5.6 nanometers, 6.2 nanometers, 7 nanometers, 7.4 nanometers, 8.0 nanometers, 8.5 nanometers, 9 nanometers, 10 nanometers, 11 nanometers, 13 nanometers, 15 nanometers, 18 nanometers, or 20 nanometers.

[0099] As an embodiment of the present invention, the second isolation layer 12 is one or a combination of silicon oxide layer, aluminum oxide layer, silicon nitride layer, and silicon oxynitride layer.

[0100] As an embodiment of the present invention, the second isolation layer 12 is made of the same material as the second tunneling layer 5.

[0101] In this embodiment, the second isolation layer 12 and the second tunneling layer 5 can both be one or more of the following: silicon oxide layer, aluminum oxide layer, silicon nitride layer, and silicon oxynitride layer. This facilitates the simultaneous preparation and formation of the second isolation layer 12 and the second tunneling layer 5, which simplifies the production process and reduces production costs.

[0102] As an embodiment of the present invention, the second isolation layer 12 and the second tunneling layer 5 are an integral structure, which facilitates the simultaneous preparation and formation of the second isolation layer 12 and the second tunneling layer 5, thereby simplifying the production process and reducing production costs.

[0103] As an embodiment of the present invention, the ratio of the thickness D12 of the second isolation layer 12 to the thickness D5 of the second tunneling layer 5 is 1 to 10.

[0104] In this embodiment, the thickness D5 of the second tunneling layer 5 is the dimension of the second tunneling layer 5 along the thickness direction Z of the silicon substrate 1. The ratio of the thickness D12 of the second isolation layer 12 to the thickness D5 of the second tunneling layer 5 can be any value among 1, 2, 3, 4, 5, 6, 7, 8, 9, and 10.

[0105] In this embodiment, the ratio of the thickness D12 of the second isolation layer 12 to the thickness D5 of the second tunneling layer 5 is controlled to be 1~10, so as to achieve a good isolation effect of the second isolation layer 12 and ensure the good tunneling passivation effect of the first tunneling layer 4.

[0106] As an embodiment of the present invention, the ratio of the thickness D12 of the second isolation layer 12 to the thickness D5 of the second tunneling layer 5 is 1.1 to 5.

[0107] In this embodiment, the ratio of the thickness D12 of the second isolation layer 12 to the thickness D5 of the second tunneling layer 5 is further controlled to be 1.1 to 5, so as to achieve a good isolation effect of the second isolation layer 12.

[0108] As an embodiment of the present invention, the leakage tunneling layer 7 is made of the same material as the second tunneling layer 5.

[0109] In this embodiment, both the leakage tunneling layer 7 and the second tunneling layer 5 can be one or more of the following: silicon oxide layer, aluminum oxide layer, silicon nitride layer, and silicon oxynitride layer. This allows the leakage tunneling layer 7 and the second tunneling layer 5 to be prepared simultaneously in one step, which simplifies the production process and reduces production costs.

[0110] As an embodiment of the present invention, the leakage tunneling layer 7 and the second tunneling layer 5 are an integral structure, which facilitates the one-time preparation and formation of the leakage tunneling layer 7 and the second tunneling layer 5, and helps to simplify the production process and reduce production costs.

[0111] As an embodiment of the present invention, the thickness D7 of the leakage tunneling layer 7 is less than or equal to the thickness D5 of the second tunneling layer 5.

[0112] In this embodiment, controlling the thickness D7 of the leakage tunneling layer 7 to be less than or equal to the thickness D5 of the second tunneling layer 5 is beneficial for the leakage tunneling layer 7 to conduct the first doped polysilicon layer 2 and the second doped polysilicon layer 3 when the solar cell is shaded. This allows current to be transmitted through the first doped polysilicon layer 2, the leakage tunneling layer 7, and the second doped polysilicon layer 3, preventing the shaded solar cell from becoming a load and consuming the energy generated by other illuminated solar cells, and reducing the risk of hot spots. Preferably, the thickness D7 of the leakage tunneling layer 7 is less than the thickness D5 of the second tunneling layer 5, which can further reduce the reverse voltage breakdown threshold of the leakage tunneling layer 7 and further reduce the risk of hot spots.

[0113] As an embodiment of the present invention, the ratio of the thickness D7 of the leakage tunneling layer 7 to the thickness D5 of the second tunneling layer 5 is 0.5 to 0.9, which can further reduce the thickness D7 of the leakage tunneling layer 7, further reduce the threshold of the leakage tunneling layer 7 being broken down by reverse voltage, and further reduce the risk of hot spots.

[0114] As an embodiment of the present invention, the thickness D7 of the leakage tunneling layer 7 is less than the thickness D5 of the second tunneling layer 5, and the thickness D12 of the second isolation layer 12 is greater than the thickness D5 of the second tunneling layer 5. Under this combined design, the good isolation effect of the second isolation layer 12 can be guaranteed, and the good anti-hot spot effect can be achieved by using the leakage tunneling layer 7.

[0115] As one embodiment of the present invention, it also includes: Passivation layer 11 covers the second doped polysilicon layer 3 and the first doped polysilicon layer 2, and the passivation layer 11 continuously covers the back side 101 of the silicon substrate 1. The first electrode 8 passes through the passivation layer 11 and contacts the first doped polysilicon layer 2, and the second electrode 9 passes through the passivation layer 11 and contacts the second doped polysilicon layer 3.

[0116] In this embodiment, since the first electrode 8 directly contacts the first doped polysilicon layer 2 through the passivation layer 11 and the second electrode 9 directly contacts the second doped polysilicon layer 3 through the passivation layer 11, the first electrode 8 does not need to contact the first doped polysilicon layer 2 through the conductive layer, and the second electrode 9 does not need to contact the second doped polysilicon layer 3 through the conductive layer. Therefore, there is no need to provide an opening-spaced conductive layer in the passivation layer 11. As a result, the passivation layer 11 can continuously cover the back side 101 of the silicon substrate 1, which can ensure the passivation performance of the passivation layer 11.

[0117] As an embodiment of the present invention, the second doped polysilicon layer 3 includes a main body portion 30 located on the second tunneling layer 5, and along the first direction X, the first isolation layer 6 is located between the main body portion 30 and the first doped polysilicon layer 2.

[0118] In this embodiment, the first isolation layer 6 is located between the main body 30 of the second doped polysilicon layer 3 and the first doped polysilicon layer 2 to isolate the main body 30 of the second doped polysilicon layer 3 from the first doped polysilicon layer 2, thereby achieving isolation between the first doped polysilicon layer 2 and the second doped polysilicon layer 3. When a second isolation layer 12 is provided, the second isolation layer 12 is located between the first isolation layer 6 and the main body 30.

[0119] As an embodiment of the present invention, the second doped polysilicon layer 3 further includes: A first extension 31 is connected to one end of the main body 30. The first extension 31 is bent relative to the main body 30 and extends in a direction away from the back surface 101. The second extension 32 is connected to the first extension 31. The second extension 32 is bent relative to the first extension 31. The second extension 32 extends along the first direction X and toward the side where the second isolation layer 12 is located. The projection of the second extension 32 along the thickness direction Z of the silicon substrate 1 covers at least a portion of the second isolation layer 12.

[0120] In this embodiment, the projection of the second extension 32 along the thickness direction Z of the silicon substrate 1 can cover the entire area of ​​the second isolation layer 12, or the projection of the second extension 32 along the thickness direction Z of the silicon substrate 1 can only cover a portion of the second isolation layer 12. Due to the presence of the second extension 32, the projection of the second extension 32 along the thickness direction Z of the silicon substrate 1 at least covers a portion of the second isolation layer 12. The second extension 32 can reflect sunlight emitted from the position of the second isolation layer 12 on the back surface 101 back into the silicon substrate 1, increasing the absorption of sunlight by the silicon substrate 1 and further improving battery efficiency. Due to the presence of the first extension 31, the distance between the second extension 32 of the second doped polysilicon layer 3 and the first doped polysilicon layer 2 along the thickness direction Z of the silicon substrate 1 can be increased, thereby improving the isolation effect between the second doped polysilicon layer 3 and the first doped polysilicon layer 2.

[0121] In one embodiment of the present invention, the doping concentration of the second isolation layer 12 is less than the doping concentration of the leakage tunneling layer 7. In this embodiment, controlling the doping concentration of the second isolation layer 12 to be less than the doping concentration of the leakage tunneling layer 7 is more conducive to improving the isolation effect of the second isolation layer 12 on the second doped polysilicon layer 3 and the first doped polysilicon layer 2, and is also conducive to the formation of a leakage channel between the second doped polysilicon layer 3 and the first doped polysilicon layer 2 through the leakage tunneling layer 7.

[0122] As one embodiment of the present invention, it also includes: The third isolation layer 13 is located between the second extension 32 and the first isolation layer 6.

[0123] In this embodiment, a third isolation layer 13 is provided between the second extension 32 and the first isolation layer 6. The isolation effect between the second doped polysilicon layer 3 and the first doped polysilicon layer 2 can be further improved by using the third isolation layer 13.

[0124] As an embodiment of the present invention, the thickness D13 of the third isolation layer 13 is greater than the thickness D12 of the second isolation layer 12.

[0125] In this embodiment, the thickness D13 of the third isolation layer 13 is the dimension of the third isolation layer 13 along the thickness direction Z of the silicon substrate 1. By controlling the thickness D13 of the third isolation layer 13 to be greater than the thickness D12 of the second isolation layer 12, the increased thickness D13 of the third isolation layer 13 is beneficial to improving the isolation effect of the third isolation layer 13 on the second doped polysilicon layer 3 and the first doped polysilicon layer 2.

[0126] As an embodiment of the present invention, the third isolation layer 13 is a stack of one or more of the following: silicon oxide layer, aluminum oxide layer, silicon oxynitride layer, silicon nitride layer, borosilicate glass, and phosphosilicate glass.

[0127] The materials of the third isolation layer 13 and the second isolation layer 12 can be the same or different. Preferably, the third isolation layer 13 is borosilicate glass or phosphosilicate glass, which facilitates the fabrication of the third isolation layer 13 of the back contact battery 100.

[0128] As an embodiment of the present invention, the refractive index of the third isolation layer 13 is greater than that of the second isolation layer 12.

[0129] In this embodiment, since the third isolation layer 13 is located between the first doped polysilicon layer 2 and the second doped polysilicon layer 3, the refractive index of the third isolation layer 13 is controlled to be greater than that of the second isolation layer 12, which is more conducive to the third isolation layer 13 reflecting the sunlight emitted from the back side 101 back into the silicon substrate 1, thereby improving the utilization rate of sunlight.

[0130] As an embodiment of the present invention, the thickness D13 of the third isolation layer 13 is 5~100 nanometers.

[0131] In this embodiment, the thickness D13 of the third isolation layer 13 is the dimension of the third isolation layer 13 along the thickness direction Z of the silicon substrate 1. The thickness D13 of the third isolation layer 13 is controlled to be 5~100 nanometers to ensure good isolation effect of the third isolation layer 13.

[0132] In this embodiment, the thickness D13 of the third isolation layer 13 can be any value among 5 nanometers, 10 nanometers, 15 nanometers, 20 nanometers, 25 nanometers, 30 nanometers, 35 nanometers, 40 nanometers, 45 nanometers, 50 nanometers, 55 nanometers, 60 nanometers, 65 nanometers, 70 nanometers, 75 nanometers, 80 nanometers, 85 nanometers, 90 nanometers, 95 nanometers, and 100 nanometers.

[0133] As an embodiment of the present invention, the orthographic projection of the second extension 32 on the back surface 101 does not coincide with the orthographic projection of the first doped polysilicon layer 2 on the back surface 101.

[0134] In this embodiment, the orthographic projection of the second extension 32 on the back surface 101 does not coincide with the orthographic projection of the first doped polysilicon layer 2 on the back surface 101, which can improve the isolation effect between the second extension 32 and the first doped polysilicon layer 2.

[0135] As an embodiment of the present invention, the second doped polysilicon layer 3 further includes: A third extension 33 is connected to the other end of the main body 30. The third extension 33 is bent relative to the main body 30 and extends away from the back surface 101. A fourth extension 34 is connected to the third extension 33. The fourth extension 34 is bent relative to the third extension 33. The fourth extension 34 extends along the first direction X and toward the side where the leakage tunneling layer 7 is located. The projection of the fourth extension 34 along the thickness direction Z of the silicon substrate 1 at least covers the leakage tunneling layer 7.

[0136] In this embodiment, due to the presence of the fourth extension 34, the projection of the fourth extension 34 along the thickness direction Z of the silicon substrate 1 at least covers the leakage tunneling layer 7. The fourth extension 34 can reflect the sunlight emitted from the leakage tunneling layer 7 on the back side 101 back into the silicon substrate 1, increasing the absorption of sunlight by the silicon substrate 1 and further improving the battery efficiency.

[0137] As one embodiment of the present invention, it also includes: The fourth isolation layer 14 is located between the fourth extension 34 and the first doped polysilicon layer 2.

[0138] In this embodiment, the fourth isolation layer 14 is disposed between the fourth extension 34 and the first doped polysilicon layer 2. The isolation effect between the second doped polysilicon layer 3 and the first doped polysilicon layer 2 can be further improved by using the fourth isolation layer 14.

[0139] In one embodiment of the present invention, the leakage tunneling layer 7 is one or a combination of at least two of the following: a silicon oxide layer, an aluminum oxide layer, a silicon nitride layer, and a silicon oxynitride layer. Preferably, the leakage tunneling layer 7 is a silicon oxide layer. Please refer to Figure 4As one embodiment of the present invention, it further includes: The barrier layer 15 is disposed in at least a portion of the area between the first isolation layer 6 and the second isolation layer 12.

[0140] In this embodiment, a barrier layer 15 is further included between the first doped polysilicon layer 2 and the second doped polysilicon layer 3. The barrier layer 15 can further improve the isolation effect between the first doped polysilicon layer 2 and the second doped polysilicon layer 3.

[0141] In this embodiment, the entire area between the first isolation layer 6 and the second isolation layer 12 may be provided with a barrier layer 15, or only a portion of the area between the first isolation layer 6 and the second isolation layer 12 may be provided with a barrier layer 15.

[0142] As an embodiment of the present invention, the barrier layer 15 is one or a combination of at least two of borosilicate glass, phosphosilicate glass, silicon oxide, silicon nitride, and silicon oxynitride.

[0143] In this embodiment, when the first isolation layer 6 is a boron-doped polycrystalline silicon layer, the barrier layer 15 is borosilicate glass, and the barrier layer 15 can be formed simultaneously with the boron doping of the first isolation layer 6; when the first isolation layer 6 is a phosphorus-doped polycrystalline silicon layer, the barrier layer 15 is phosphosilicate glass, and the barrier layer 15 can be formed simultaneously with the phosphorus doping of the first isolation layer 6, which facilitates the processing of the barrier layer 15. Additionally, in other embodiments, the barrier layer 15 can also be one or a combination of at least two of silicon oxide, silicon nitride, and silicon oxynitride.

[0144] Please refer to Figure 5 As one embodiment of the present invention, it further includes: The boundary portion 16 located between the first isolation layer 6 and the first doped polysilicon layer 2 has a higher doping concentration at the end of the boundary portion 16 closer to the first doped polysilicon layer 2 than at the end of the boundary portion 16 closer to the first isolation layer 6 along the first direction X.

[0145] In this embodiment, the boundary portion 16 is made of the same material as the first isolation layer 6 or the first doped polysilicon layer 2. A boundary portion 16 exists between the first isolation layer 6 and the first doped polysilicon layer 2. Along the first direction X, the boundary portion 16 includes a first end near the first doped polysilicon layer 2 and a second end near the first isolation layer 6. The doping concentration at the first end of the boundary portion 16 is greater than the doping concentration at the second end of the boundary portion 16. That is, the closer the boundary portion 16 is to the first isolation layer 6, the lower the doping concentration. Therefore, the closer the boundary portion 16 is to the first isolation layer 6, the worse its current transport performance. Conversely, the closer the boundary portion 16 is to the first doped polysilicon layer 2, the higher the doping concentration. Therefore, the closer the boundary portion 16 is to the first doped polysilicon layer 2, the better its current transport performance. This better prevents the first doped polysilicon layer 2 from conducting with the second doped polysilicon layer 3, thus improving the isolation effect between the second doped polysilicon layer 3 and the first doped polysilicon layer 2. Furthermore, the presence of the boundary portion 16 allows for a good concentration difference between the first isolation layer 6 and the first doped polysilicon layer 2, which is more conducive to maintaining a low concentration of the first isolation layer 6 and achieving a better isolation effect between the second doped polysilicon layer 3 and the first doped polysilicon layer 2. Simultaneously, maintaining a high concentration of the first doped polysilicon layer 2 helps maintain a low contact resistance between the first electrode 8 and the first doped polysilicon layer 2. Preferably, along the first direction X, the doping concentration of the boundary portion 16 decreases sequentially from the first doped polysilicon layer 2 to the first isolation layer 6, ensuring that the doping concentration of the boundary portion 16 decreases sequentially from the first doped polysilicon layer 2 to the first isolation layer 6. This further facilitates better isolation between the second doped polysilicon layer 3 and the first doped polysilicon layer 2, while also helping to maintain a low contact resistance between the first electrode 8 and the first doped polysilicon layer 2.

[0146] As an embodiment of the present invention, the length W1 of the boundary portion 16 along the first direction X is 0.1 to 5 micrometers.

[0147] In this embodiment, the length W1 of the control boundary portion 16 along the first direction X is 0.1~5 micrometers, which can create a concentration difference between the first isolation layer 6 and the first doped polysilicon layer 2, which is more conducive to ensuring that the first isolation layer 6 maintains a low concentration, achieving a better isolation effect between the second doped polysilicon layer 3 and the first doped polysilicon layer 2, while maintaining a high concentration of the first doped polysilicon layer 2, which is conducive to maintaining a low contact resistance between the first electrode 8 and the first doped polysilicon layer 2.

[0148] In this embodiment, the length W1 of the boundary portion 16 along the first direction X can be any value among 0.1 micrometers, 0.2 micrometers, 0.3 micrometers, 0.5 micrometers, 0.8 micrometers, 0.9 micrometers, 1 micrometer, 1.1 micrometers, 1.2 micrometers, 1.5 micrometers, 2 micrometers, 2.1 micrometers, 2.3 micrometers, 2.5 micrometers, 3 micrometers, 3.1 micrometers, 3.5 micrometers, 3.8 micrometers, 3.9 micrometers, 4 micrometers, 4.1 micrometers, 4.2 micrometers, 4.5 micrometers, 4.6 micrometers, 4.8 micrometers, and 5 micrometers.

[0149] In one embodiment of the present invention, both the first isolation layer 6 and the first doped polysilicon layer 2 are provided with holes, and the number of holes per unit area of ​​the first isolation layer 6 is less than the number of holes per unit area of ​​the first doped polysilicon layer 2.

[0150] In this embodiment, the number of pores per unit area of ​​the first isolation layer 6 is less than the number of pores per unit area of ​​the first doped polysilicon layer 2. That is, under the same unit area, the number of pores per unit area of ​​the first isolation layer 6 is less than the number of pores per unit area of ​​the first doped polysilicon layer 2, which is beneficial to improving the isolation effect of the first isolation layer 6 and also to improving the passivation effect of the first isolation layer 6 and reducing recombination loss.

[0151] In one embodiment of the present invention, both the first isolation layer 6 and the first doped polysilicon layer 2 are provided with holes, and the average maximum radial size of the holes per unit area of ​​the first isolation layer 6 is smaller than the average maximum radial size of the holes in the first doped polysilicon layer 2.

[0152] In this embodiment, the maximum radial dimension of the holes in the first isolation layer 6 is the same as the maximum radial dimension of the holes in the first doped polysilicon layer 2. The average maximum radial dimension of the holes in the first isolation layer 6 is the average of the maximum radial dimensions of all holes within a unit area of ​​the first isolation layer 6, and the average maximum radial dimension of the holes in the first doped polysilicon layer 2 is the average of the maximum radial dimensions of all holes within a unit area of ​​the first doped polysilicon layer 2. Controlling the average maximum radial dimension of the holes in the first isolation layer 6 to be smaller than the average maximum radial dimension of the first doped polysilicon layer 2 is beneficial for improving the isolation effect of the first isolation layer 6, and can further improve the passivation effect of the first isolation layer 6, reducing recombination losses.

[0153] Please refer to Figure 6 As an embodiment of the present invention, the surface of the third isolation layer 13 facing away from the silicon substrate 1 is provided with a first textured structure 131.

[0154] In this embodiment, the first textured structure 131 can be an upright pyramid structure or an inverted pyramid structure. By providing the first textured structure 131 on the surface of the third isolation layer 13 facing away from the silicon substrate 1, the first textured structure 131 can reflect sunlight emitted from the back side 101 back into the silicon substrate 1, increasing the optical path of sunlight within the silicon substrate 1 and thus improving the utilization rate of sunlight.

[0155] As an embodiment of the present invention, the surface of the fourth isolation layer 14 facing away from the silicon substrate 1 is provided with a second textured structure 141.

[0156] In this embodiment, the second textured structure 141 can be a regular pyramid structure or an inverted pyramid structure. By providing the second textured structure 141 on the surface of the fourth isolation layer 14 facing away from the silicon substrate 1, the second textured structure 141 can reflect the sunlight emitted from the back side 101 back into the silicon substrate 1, further increasing the optical path of sunlight in the silicon substrate 1 and improving the utilization rate of sunlight.

[0157] Please refer to this again. Figure 3 In one embodiment of the present invention, both the second doped polysilicon layer 3 and the first doped polysilicon layer 2 extend along the second direction Y, which intersects the first direction X. The ratio of the sum of the lengths L7 of the leakage tunneling layer 7 projected onto the back surface 101 along the second direction Y to the area of ​​the back surface 101 is 0.01~0.2 mm / mm. 2 .

[0158] In this embodiment, the second direction Y may or may not be perpendicular to the first direction X. Preferably, the second direction Y is perpendicular to the first direction X. The orthographic projection of the leakage tunneling layer 7 on the back surface 101 is the projection of the leakage tunneling layer 7 along the thickness direction Z of the silicon substrate 1. The sum of the lengths L7 of the orthographic projections of the leakage tunneling layers 7 on the back surface 101 along the second direction Y is the sum of the lengths L7 of the orthographic projections of all leakage tunneling layers 7 on the back surface 101 along the second direction Y; for example, if there are 50 locations on the back surface 101 where leakage tunneling layers 7 are disposed, then the sum of the lengths L7 of the orthographic projections of the leakage tunneling layers 7 on the back surface 101 along the second direction Y is the sum of the lengths L7 of the orthographic projections of the 50 leakage tunneling layers 7 on the back surface 101 along the second direction Y; the area of ​​the back surface 101 is the total area of ​​the back surface 101 along the silicon substrate 1. For example, if the area of ​​the back face 101 is square, and the width L11 of the back face 101 is 182 mm and the length L12 is 192 mm, then the area of ​​the back face 101 is 34944 mm². 2 The sum of the lengths L7 of the orthographic projection of the leakage tunneling layer 7 onto the back surface 101 along the second direction Y is 1200 mm. Therefore, the ratio of the sum of the lengths L7 of the orthographic projection of the leakage tunneling layer 7 onto the back surface 101 along the second direction Y to the area of ​​the back surface 101 is 0.034 mm / mm. 2 .

[0159] In practical applications, the ratio of the sum of the lengths L7 of the leakage tunneling layer 7 projected onto the back surface 101 along the second direction Y to the area of ​​the back surface 101 can be 0.01~0.2 mm / mm. 2 Any value in the range; for example, the ratio of the two can be 0.01 mm / mm. 2 0.02mm / mm 2 0.03mm / mm 2 0.05mm / mm 2 0.08mm / mm 2 0.09mm / mm 2 0.1mm / mm 2 0.13mm / mm 2 0.15mm / mm 2 0.17mm / mm 2 0.18mm / mm 2 0.19mm / mm 2 0.2mm / mm 2 Any value in the range.

[0160] In this embodiment, the ratio of the sum of the lengths L7 of the leakage tunneling layer 7 projected onto the back surface 101 along the second direction Y to the area of ​​the back surface 101 is controlled to be 0.01~0.2mm / mm. 2 This design avoids a small ratio between the two, which would result in a small leakage current through the leakage tunneling layer 7, preventing the back contact cell from burning out due to local overheating and further reducing the risk of hot spots in the photovoltaic module composed of the back contact cell. Conversely, it avoids a large ratio between the two, which would result in a large leakage current in the back contact cell under normal operating conditions due to an excessively large total length of the leakage tunneling layer 7. This ensures that the photovoltaic module composed of the back contact cell has a high photoelectric conversion efficiency. Therefore, it can effectively control hot spots and ensure good power generation efficiency of the back contact cell.

[0161] This invention also provides a battery assembly, which includes the back contact battery 100 described in the above embodiments. It should be noted that this battery assembly has the same or similar beneficial effects as the back contact battery 100, and the related aspects between the two can be referred to each other; to avoid repetition, they will not be repeated here.

[0162] In this embodiment, multiple back-contact batteries 100 in the battery assembly are connected in series by solder strips to form a battery string, thereby achieving series current collection and output.

[0163] It is understood that in such embodiments, the battery assembly may further include a metal frame, a backsheet, photovoltaic glass, and an encapsulating film. The encapsulating film may be filled between the front and back surfaces of the back contact battery 100, the photovoltaic glass, adjacent battery cells, etc. As a filler, it may be a transparent colloid with good light transmittance and aging resistance. For example, the encapsulating film may be an EVA film or a POE film, and the specific choice can be made according to the actual situation, without limitation.

[0164] Photovoltaic glass can be applied to the encapsulating film on the front side of the back contact cell 100. The photovoltaic glass can be ultra-clear glass, which has high light transmittance, high transparency, and superior physical, mechanical, and optical properties. For example, ultra-clear glass can achieve a light transmittance of over 92%. It can protect the back contact cell 100 while minimizing impact on its efficiency. Simultaneously, the encapsulating film bonds the photovoltaic glass and the back contact cell 100 together, providing sealing, insulation, and waterproofing / moisture protection for the back contact cell 100.

[0165] The backsheet can be attached to the adhesive film on the back side of the back contact cell 100. The backsheet provides protection and support for the back contact cell 100, and offers reliable insulation, water resistance, and aging resistance. Multiple options are available for the backsheet, typically tempered glass, acrylic glass, or aluminum alloy TPT composite adhesive film, etc., and the specific choice is determined based on the specific circumstances and is not limited here. The backsheet, back contact cell 100, adhesive film, and photovoltaic glass can be mounted on a metal frame. The metal frame serves as the main external support structure for the entire battery module, providing stable support and installation. For example, the battery module can be installed at the desired location using the metal frame.

[0166] This invention also provides a photovoltaic system, which includes the battery module described in the above embodiments. It should be noted that this photovoltaic system has the same or similar beneficial effects as the back-contact battery 100 described above, and the related aspects between the two can be referred to each other; to avoid repetition, they will not be repeated here.

[0167] In this embodiment, the photovoltaic system can be applied in photovoltaic power plants, such as ground-mounted power plants, rooftop power plants, and floating power plants. It can also be applied to equipment or devices that utilize solar energy to generate electricity, such as user solar power supplies, solar streetlights, solar cars, and solar buildings. Of course, it is understood that the application scenarios of the photovoltaic system are not limited to these; that is, the photovoltaic system can be applied in all fields that require solar energy to generate electricity. Taking a photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a combiner box, and an inverter. The photovoltaic array may be an array combination of multiple battery modules; for example, multiple battery modules can form multiple photovoltaic arrays. The photovoltaic array is connected to the combiner box, which can collect the current generated by the photovoltaic array. The collected current flows through the inverter and is converted into AC power required by the mains power grid before being connected to the mains power grid to achieve solar power supply.

[0168] In the description of this specification, references to terms such as "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0169] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A back-contact battery, characterized in that, include: Silicon substrate, the silicon substrate including a back side; A first doped polysilicon layer is disposed on the back side; A second doped polysilicon layer is disposed on the back side, the doping type of the second doped polysilicon layer is opposite to that of the first doped polysilicon layer, and the second doped polysilicon layer and the first doped polysilicon layer are alternately disposed on the back side along a first direction; A first tunneling layer is disposed between the first doped polysilicon layer and the silicon substrate; The second tunneling layer is disposed between the second doped polysilicon layer and the silicon substrate; A first isolation layer is disposed between the second doped polysilicon layer and the first doped polysilicon layer. The doping concentration of the first isolation layer is less than that of the first doped polysilicon layer, and the doping concentration of the first isolation layer is less than 5E17 / cm². 3 ; A leakage tunneling layer is disposed between the second doped polysilicon layer and the first doped polysilicon layer, and the leakage tunneling layer connects the second doped polysilicon layer and the first doped polysilicon layer. The first electrode is in direct contact with the first doped polysilicon layer; and The second electrode is in direct contact with the second doped polycrystalline silicon layer.

2. The back contact battery according to claim 1, characterized in that, The first isolation layer is an intrinsic semiconductor layer or a doped semiconductor layer.

3. The back contact battery according to claim 2, characterized in that, The intrinsic semiconductor layer is at least one of intrinsic polycrystalline silicon layer, intrinsic amorphous silicon layer, intrinsic microcrystalline silicon layer, and intrinsic nanocrystalline silicon layer.

4. The back contact battery according to claim 2, characterized in that, The doped semiconductor layer is at least one of the following: a doped polycrystalline silicon layer, a doped amorphous silicon layer, a doped microcrystalline silicon layer, and a doped nanocrystalline silicon layer.

5. The back contact battery according to claim 1, characterized in that, The first isolation layer and the first doped polysilicon layer are an integral structure.

6. The back contact battery according to claim 1, characterized in that, The first tunneling layer is also disposed between the first isolation layer and the silicon substrate.

7. The back contact battery according to claim 1, characterized in that, The thickness of the first isolation layer is greater than 0.05 micrometers.

8. The back contact battery according to claim 1, characterized in that, The doping concentration of the first isolation layer is less than 2E17 / cm 3 .

9. The back contact battery according to claim 1, characterized in that, The doping concentration of the first isolation layer is less than 1E17 / cm 3 .

10. The back contact battery according to claim 1, characterized in that, Both the first doped polysilicon layer and the first isolation layer are doped with group VA elements, the second doped polysilicon layer is doped with group IIIA elements, and the doping concentration of the first isolation layer is less than 3E17 / cm³. 3 .

11. The back contact battery according to claim 1, characterized in that, Both the first doped polysilicon layer and the first isolation layer are doped with group IIIA elements, the second doped polysilicon layer is doped with group VA elements, and the doping concentration of the first isolation layer is less than 1E17 / cm³. 3 .

12. The back contact battery according to claim 1, characterized in that, The doping concentrations of both the second doped polysilicon layer and the first doped polysilicon layer are greater than 1E19 / cm. 3 .

13. The back contact battery according to claim 1, characterized in that, Also includes: The second isolation layer is disposed between the first isolation layer and the second doped polysilicon layer.

14. The back contact battery according to claim 13, characterized in that, The thickness of the second isolation layer is greater than or equal to the thickness of the leakage tunneling layer.

15. The back contact battery according to claim 14, characterized in that, The ratio of the thickness of the second isolation layer to the thickness of the leakage tunneling layer is 1 to 5.

16. The back contact battery according to claim 15, characterized in that, The ratio of the thickness of the second isolation layer to the thickness of the leakage tunneling layer is 1.1 to 2.

17. The back contact battery according to claim 13, characterized in that, The doping concentration of the second isolation layer is less than that of the leakage tunneling layer.

18. The back contact battery according to claim 13, characterized in that, The second isolation layer is made of the same material as the second tunneling layer.

19. The back contact battery according to claim 18, characterized in that, The second isolation layer and the second tunneling layer are an integral structure.

20. The back contact battery according to claim 1, characterized in that, The leakage tunneling layer is made of the same material as the second tunneling layer.

21. The back contact battery according to claim 20, characterized in that, The leakage tunneling layer and the second tunneling layer are an integral structure.

22. The back contact battery according to claim 1, characterized in that, Also includes: A passivation layer covers the second doped polysilicon layer and the first doped polysilicon layer, and the passivation layer continuously covers the back side of the silicon substrate. The first electrode passes through the passivation layer and contacts the first doped polysilicon layer, and the second electrode passes through the passivation layer and contacts the second doped polysilicon layer.

23. The back contact battery according to claim 13, characterized in that, The second doped polysilicon layer includes a main body portion located on the second tunneling layer, and along the first direction, the first isolation layer is located between the main body portion and the first doped polysilicon layer.

24. The back contact battery according to claim 23, characterized in that, The second doped polysilicon layer further includes: A first extension portion connected to one end of the main body portion, the first extension portion being bent relative to the main body portion, and the first extension portion extending in a direction away from the back side; A second extension connected to the first extension, the second extension being bent relative to the first extension, the second extension extending along the first direction and toward the side where the second isolation layer is located, and the projection of the second extension along the thickness direction of the silicon substrate at least covering a portion of the second isolation layer.

25. The back contact battery according to claim 24, characterized in that, Also includes: The third isolation layer is located between the second extension and the first isolation layer.

26. The back contact battery according to claim 25, characterized in that, The thickness of the third isolation layer is greater than the thickness of the second isolation layer.

27. The back contact battery according to claim 24, characterized in that, The orthographic projection of the second extension on the back side does not coincide with the orthographic projection of the first doped polysilicon layer on the back side.

28. The back contact battery according to claim 24, characterized in that, The second doped polysilicon layer further includes: A third extension is connected to the other end of the main body, the third extension is bent relative to the main body, and the third extension extends away from the back side; A fourth extension is connected to the third extension, the fourth extension is bent relative to the third extension, the fourth extension extends along the first direction and toward the side where the leakage tunneling layer is located, and the projection of the fourth extension along the thickness direction of the silicon substrate at least covers the leakage tunneling layer.

29. The back contact battery according to claim 28, characterized in that, Also includes: A fourth isolation layer is located between the fourth extension and the first doped polysilicon layer.

30. The back contact battery according to claim 1, characterized in that, The first tunneling layer and the second tunneling layer are respectively one or a combination of at least two of the following: silicon oxide layer, aluminum oxide layer, silicon nitride layer, and silicon oxynitride layer.

31. The back contact battery according to claim 13, characterized in that, The second isolation layer is one or a combination of at least two of the following: silicon oxide layer, aluminum oxide layer, silicon nitride layer, and silicon oxynitride layer.

32. The back contact battery according to claim 1, characterized in that, The leakage tunneling layer is one or a combination of at least two of the following: silicon oxide layer, aluminum oxide layer, silicon nitride layer, and silicon oxynitride layer.

33. The back contact battery according to claim 13, characterized in that, Also includes: A barrier layer is disposed in at least a portion of the area between the first isolation layer and the second isolation layer.

34. The back contact battery according to claim 33, characterized in that, The barrier layer is one or a combination of at least two of borosilicate glass, phosphosilicate glass, silicon oxide, silicon nitride, and silicon oxynitride.

35. The back contact battery according to claim 1, characterized in that, Also includes: The boundary portion located between the first isolation layer and the first doped polysilicon layer, along the first direction, has a doping concentration at the end of the boundary portion closer to the first doped polysilicon layer that is greater than the doping concentration at the end of the boundary portion closer to the first isolation layer.

36. The back contact battery according to claim 1, characterized in that, Both the first isolation layer and the first doped polysilicon layer have pores, and the number of pores per unit area of ​​the first isolation layer is less than the number of pores per unit area of ​​the first doped polysilicon layer.

37. The back contact battery according to claim 1, characterized in that, Both the first isolation layer and the first doped polysilicon layer are provided with holes, and the average maximum radial size of the holes per unit area of ​​the first isolation layer is smaller than the average maximum radial size of the holes per unit area of ​​the first doped polysilicon layer.

38. The back contact battery according to claim 1, characterized in that, Both the second doped polysilicon layer and the first doped polysilicon layer extend along a second direction, which intersects with the first direction. The ratio of the sum of the lengths of the leakage tunneling layer's orthographic projection along the second direction on the back surface to the area of ​​the back surface is 0.01~0.2 mm / mm. 2 .

39. The back contact battery according to claim 25, characterized in that, The surface of the third isolation layer facing away from the silicon substrate has a first textured structure.

40. The back contact battery according to claim 29, characterized in that, The fourth isolation layer has a second textured surface structure on the surface opposite to the silicon substrate.

41. A battery assembly, characterized in that, Includes the back contact battery as described in any one of claims 1 to 40.

42. A photovoltaic system, characterized in that, Includes the battery assembly as described in claim 41.

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