Passivated contact cell and method of making and using same

Abstract

The application discloses a passivated contact cell and a preparation method and application thereof. By replacing the continuous removal mode with the intermittent removal mode in the form of left-right direction interval when selectively removing the doped polysilicon and the tunneling oxide layer in the non-metallized area, the design unexpectedly reduces the lateral transmission distance and the lateral transmission resistance. The application has obvious complementary effect on the partial carrier convergence function failure caused by the failure of part of the fine grid lines and the corresponding doped polysilicon, and has strong risk resistance. In addition, the application can directly make part of the fine grid lines into an intermittent design, so that the fine grid lines are partially disconnected. The application not only almost does not reduce the core indicators of the cell, but also has the characteristics of reducing the required silver paste amount and metal composite. The preparation of the grid lines adopts a steel plate printing method, a laser transfer printing method or an electroplating method, which not only has the advantage of preventing paste leakage, but also can realize finer grid line printing, non-contact printing and reduce the risk of silicon chip fragmentation.

Description

Technical Field

[0001] This invention relates to the field of solar cells, specifically to a passivated contact cell, its preparation method, and its application. Background Technology

[0002] The emergence of TOPCon tunneling oxide passivated contact solar cells has attracted significant attention to high-efficiency crystalline silicon solar cell technology. TOPCon cells use N-type silicon as the substrate material and consist of an ultrathin silicon oxide layer and a doped polycrystalline silicon layer forming the passivation contact structure. This structure reduces carrier recombination between the metal electrode and silicon, and facilitates full-area passivation, thereby improving the efficiency of TOPCon solar cells. However, the presence of doped polycrystalline silicon in TOPCon cells also causes severe parasitic absorption, leading to a decrease in the photocurrent and resulting in efficiency loss. Therefore, currently, this tunneling silicon oxide layer and doped polycrystalline silicon layer structure is only used on the back surface of TOPCon cells. Meanwhile, in the solar spectrum, photons with wavelengths greater than 950 nm will be transmitted to the back surface of the silicon wafer. The doped polycrystalline silicon layer will also exhibit parasitic absorption of these infrared photons, resulting in efficiency loss. In order to reduce the efficiency loss caused by parasitic absorption of doped polycrystalline silicon, selective polycrystalline silicon passivation contact technology is currently used. This technology removes some of the polycrystalline silicon in the non-metallized region while retaining the polycrystalline silicon structure in the metallized region. This reduces the area ratio of doped polycrystalline silicon on the back surface of the cell, reduces parasitic absorption of infrared photons, and improves the efficiency of solar cells.

[0003] However, in the current selective polysilicon passivation contact structure, the doped polysilicon layer between two adjacent fine gate lines is continuously removed (except at the main gate line position). Although this significantly reduces the parasitic loss of the doped polysilicon layer, it also increases the lateral transport resistance of the back carriers, resulting in a low fill factor FF of the cell and limiting the improvement in efficiency.

[0004] Meanwhile, when some fine grid lines and the corresponding doped polycrystalline silicon within their orthographic projection range fail, making it difficult or even impossible to transport electrons, the entire fine grid line in the current structural design is prone to directly losing its function of collecting charge carriers. This will cause some charge carriers generated on the silicon substrate to have to travel a long distance before being collected. As a result, it will easily lead to increased carrier recombination, increased series resistance, and ultimately significant deterioration of the battery's core indicators such as short-circuit current, fill factor, and conversion efficiency. In other words, the current structural design is not resilient enough.

[0005] Although Chinese invention patent CN119486360 B shortens the transmission distance in the longitudinal direction by separating the laser ablation area, it does not fundamentally improve the above-mentioned problems.

[0006] It should be noted that the information disclosed in the background section above is only for understanding the background of this application. Therefore, the background section of this invention may include background information about the problems or environment of this invention, and is not necessarily a description of the prior art. Thus, the content included in the background section does not constitute an admission of the prior art by the applicant. Summary of the Invention

[0007] The purpose of this invention is to overcome one or more shortcomings in the prior art and provide an improved method for preparing a passivated contact battery and the passivated contact battery made therefrom. The passivated contact battery structure prepared by the method of this invention can help shorten the lateral transport distance of charge carriers on the back side and reduce the total lateral resistance. At the same time, it has excellent resilience when local charge carrier transport path fails. In addition, the passivated contact battery structure of this invention can also reduce the amount of paste used in the metal electrode while ensuring good charge carrier transport effect, which greatly saves costs.

[0008] The present invention also provides an application of the above-mentioned passivated contact battery in a solar photovoltaic power generation system.

[0009] To achieve the above objectives, the present invention employs the following technical solution: A method for fabricating a passivated contact cell includes: sequentially fabricating a tunneling oxide layer and a polycrystalline silicon layer on the back surface of a silicon wafer, followed by phosphorus diffusion to form a phosphorus-doped polycrystalline silicon layer, and then forming a phosphosilicate glass layer on the phosphorus-doped polycrystalline silicon layer. Specifically, the back surface includes multiple unit regions, each unit region including n first sub-regions and n second sub-regions, where n is greater than or equal to 2; the n first sub-regions are sequentially spaced along a left-right direction, and the spacer regions extend along a vertical direction; the second sub-regions surround the n first sub-regions, and the spacer regions are part of the second sub-regions. The method for preparing the passivated contact battery further includes: Patterned film opening is performed on the phosphorosilicate glass layer. After film opening, the phosphorosilicate glass layer in each first sub-region is removed, and the tunneling oxide layer and phosphorus-doped polysilicon layer corresponding to each first sub-region are removed from the film opening area. Then, the phosphorosilicate glass layer in the second sub-region is removed. Passivation layers are deposited on the front and back surfaces, and fine and main grid lines are prepared separately. When preparing the back fine grid lines, at least one of them is partially broken, and the length of the partially broken part is controlled to be less than 20% of the length of the corresponding back fine grid line. The fine and main grid lines on the front and back surfaces are prepared by steel plate printing, laser transfer or electroplating.

[0010] According to the present invention, the method can also prevent paste leakage during the manufacturing process. The appearance of the solar cell is one of the criteria for judging its quality. In the traditional screen printing process, paste leakage may occur due to long-term wear or puncture during production, leaving silver paste in the non-metallized areas of the solar cell, causing contamination of the cell surface and affecting the quality of the solar cell. In traditional cells with full-surface polycrystalline silicon deposition on the back, the back-side ablation-type silver paste cannot directly contact the silicon substrate due to the obstruction of polycrystalline silicon, so the paste leakage problem only affects the appearance of the solar cell. However, in solar cells with selective polycrystalline silicon passivation contact structures, if the paste leakage problem exists in the polycrystalline silicon opening removal area in the non-metallic region, after high-temperature sintering, the burn-through silver paste directly contacts the silicon substrate of the cell, resulting in severe metal recombination, causing a decrease in electrical performance Voc and FF (Voc decreases by 2~4 mV, FF decreases by 0.2~0.5%), thereby reducing the efficiency of the solar cell (0.15~0.30%). This invention uses steel plate printing, laser transfer, or electroplating to prepare fine grid lines and main grid lines on the front and back surfaces. It not only has the advantage of preventing ink leakage, but also enables the printing of finer grid lines and non-contact printing, reducing the risk of silicon wafer breakage.

[0011] Furthermore, traditional screen printing stencils are composed of stainless steel wire woven into meshes of varying sizes, PI film, and photosensitive emulsion. Depending on the mesh angle, they can be categorized as conventional or knotless stencils. However, due to prolonged production and printing processes, as well as the punctures from particles, traditional stencils are prone to ink leakage, leading to poor cell appearance or short stencil lifespan. The steel plate printing method used in this invention employs a fully open steel plate, where the graphic design is performed using laser etching or electroforming on a single piece of steel. The base steel plate is typically made of high-hardness stainless steel with a surface coating, extending the stencil's lifespan and significantly reducing ink leakage. This method is particularly suitable for batteries with selective polysilicon passivation contact structures, preventing contact between the silver paste and the polysilicon open-removal area, which can reduce Voc and FF electrical performance. Moreover, while conventional screen printing has a minimum linewidth of 16-18 μm, the current fully open steel plate reduces the minimum grid line width to 10-12 μm, minimizing optical shading loss and silver paste consumption.

[0012] Furthermore, laser transfer printing is a non-contact printing technology that involves applying the required paste to a light-transmitting material and then using a high-power laser beam for high-speed patterning scanning. During this process, the paste is precisely transferred from the light-transmitting material to the surface of the passivated contact battery. Subsequently, through high-temperature sintering, metal grid lines are ultimately formed. Moreover, compared to the narrowest line width of 16-18μm in conventional screen printing, current laser transfer technology can reduce the narrowest grid line width to 8-10μm, thereby reducing optical occlusion loss and silver paste consumption.

[0013] Furthermore, copper electroplating technology can also reduce the narrowest width of the grid lines to 8~10μm, and through a silver-free solution, significantly reduce costs, bringing higher conversion efficiency and performance improvement to photovoltaic cells. By electrolytically depositing metallic copper on the substrate surface, this technology not only reduces the dependence on silver paste, but also optimizes key properties such as the conductivity, shaping and aspect ratio of the grid lines.

[0014] In some embodiments of the present invention, the steel plate printing method includes: A rigid metal mesh with openings is used to print on silicon wafers. The rigid metal mesh is suspended directly above the silicon wafer and kept in a non-contact state. Conductive paste is evenly applied to the surface of the rigid metal mesh. A squeegee scrapes across the rigid metal mesh at a uniform speed and with pressure from one side. Under pressure, the paste passes through the mesh and falls onto the surface of the silicon wafer to form grid lines. The wafer is then dried and sintered. During the pressure scraping process, the printing pressure applied by the squeegee is 10-80N, the printing speed is 100-1000mm / s, and the spacing between the rigid metal mesh and the silicon wafer is 1-5mm.

[0015] In some embodiments of the present invention, the laser transfer method includes: Grooves with grid lines of a battery cell are fabricated on a transparent material. A pulsed laser is used to focus the internal area of ​​the non-processed area on both sides of the groove. Then, the paste corresponding to the grid lines is placed in the groove to obtain a transfer substrate. A silicon wafer with a passivation layer is placed below the transfer substrate with the trench facing the silicon wafer. Then, a shaping laser is used to irradiate the trench containing the paste, causing the paste in the trench to transfer onto the silicon wafer. After drying and sintering, fine gate lines or main gate lines are fabricated.

[0016] Furthermore, during the laser transfer process, the pulsed laser is a picosecond laser and / or a femtosecond laser with a wavelength range of 343–1064 nm.

[0017] Furthermore, during the laser transfer process, the laser wavelength of the shaping laser is in the range of 343–2000 nm, and the spot shape is a Gaussian beam or a flat-top beam.

[0018] In some embodiments of the present invention, the electroplating method is a copper electroplating method, which includes: forming grooves on the surface of the passivation layer on the back surface of the silicon wafer according to the grid pattern by laser processing, cleaning, obtaining an intermediate silicon wafer with patterned grooves, and then placing it in a copper electroplating solution for electroplating.

[0019] In some embodiments of the present invention, the sheet resistance of the phosphorus-doped polycrystalline silicon layer is 40~80 Ω / sq, and the phosphorus atom doping concentration is 4.0×10⁻⁶. 20 ~8.0×10 20 cm -3 .

[0020] In some embodiments of the present invention, the silicon wafer is an N-type silicon wafer.

[0021] In some embodiments of the present invention, patterning is performed on the phosphosilicate glass layer using laser etching.

[0022] In some embodiments of the present invention, wet chemical etching is used to remove the tunneling oxide layer and phosphorus-doped polysilicon layer corresponding to each first sub-region from the open film region, and to remove the phosphorus-silicon glass layer in the second sub-region.

[0023] In some embodiments of the present invention, in the first sub-region, a silicon wafer and a first back passivation layer are sequentially disposed along a direction perpendicular to the first sub-region; in the second sub-region, a silicon wafer, a tunneling oxide layer, a polysilicon layer, and a second back passivation layer are sequentially disposed along a direction perpendicular to the second sub-region. The back fine gate line and the back main gate line are both located in the second sub-region. The back fine gate line passes through the second back passivation layer and is connected to the polysilicon layer. The back main gate line is connected to the back fine gate line.

[0024] Furthermore, the first back passivation layer and the second back passivation layer are integrally formed.

[0025] Furthermore, the first back passivation layer and the second back passivation layer independently include a passivation film and a selective antireflection film.

[0026] In some embodiments of the present invention, the distance between two adjacent first sub-regions in the n first sub-regions is 50-200 μm.

[0027] According to some specific aspects of the present invention, the distance between two adjacent first sub-regions in the n first sub-regions includes, but is not limited to, 50μm, 55μm, 60μm, 65μm, 70μm, 75μm, 80μm, 85μm, 90μm, 95μm, 100μm, 105μm, 110μm, 115μm, 120μm, 125μm, 130μm, 135μm, 140μm, 145μm, 150μm, 155μm, 160μm, 165μm, 170μm, 175μm, 180μm, 185μm, 190μm, 195μm, 200μm, etc.

[0028] In some embodiments of the present invention, the total area of ​​the n first sub-regions accounts for 40%-96% of the area of ​​the unit region. Further, the total area of ​​the n first sub-regions accounts for 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, 95%, etc., of the area of ​​the unit region.

[0029] In some embodiments of the present invention, the length of the partial break is 0.1-2 mm. Further, the length of the partial break includes, but is not limited to, 0.1 mm, 0.15 mm, 0.20 mm, 0.25 mm, 0.30 mm, 0.35 mm, 0.4 mm, 0.45 mm, 0.5 mm, 0.55 mm, 0.60 mm, 0.65 mm, 0.70 mm, 0.75 mm, 0.8 mm, 0.85 mm, 0.90 mm, 0.95 mm, 1.0 mm, 1.1 mm, 1.2 mm, 1.3 mm, 1.4 mm, 1.5 mm, 1.6 mm, 1.7 mm, 1.8 mm, 1.9 mm, 2.0 mm, etc.

[0030] In some embodiments of the invention, each of the back-side fine grid lines has multiple partial breaks.

[0031] In some embodiments of the present invention, the total length of the plurality of said partial breaks accounts for 1%-20% of the length of the corresponding back-side fine grid line, for example, including but not limited to 1%, 1.5%, 2.0%, 2.5%, 3.0%, 3.5%, 4.0%, 4.5%, 5.0%, 5.5%, 6.0%, 6.5%, 7.0%, 7.5%, 8.0%, 8.5%, 9.0%, 9.5%, 10.0%, 10.5%, 11.0%, 11.5%, 12.0%, 12.5%, 13.0%, 13.5%, 14.0%, 14.5%, 15.0%, 15.5%, 16.0%, 16.5%, 17.0%, 17.5%, 18.0%, 18.5%, 19.0%, 19.5%, etc.

[0032] In some embodiments of the invention, the lengths of the respective partial breaks on each of the back-side fine grid lines remain the same or different.

[0033] In some embodiments of the present invention, the position and length of the partial breaks on any two of the back-side fine grid lines remain the same or different.

[0034] In some embodiments of the present invention, the n first sub-regions are arranged at intervals along the length direction of the back fine grid lines.

[0035] In some embodiments of the present invention, the spacing region extends along the width direction of the back fine grid lines.

[0036] In some embodiments of the present invention, the spacing regions of each of the unit regions located between two adjacent back main grid lines are distributed on the same extension line or on multiple parallel extension lines.

[0037] In some embodiments of the present invention, the polysilicon layer in the second sub-region forms a multidimensional carrier transport path. A "multidimensional carrier transport path" means that the carrier transport path is not singular, and carrier transport can be achieved in multiple directions.

[0038] In some embodiments of the present invention, a continuous carrier transport path is formed between any two points in the polysilicon layer corresponding to the second sub-region.

[0039] In some embodiments of the present invention, the polysilicon layer corresponding to the interval region and the polysilicon layer corresponding to the partial disconnection are directly connected.

[0040] In some embodiments of the present invention, in the preparation of the passivated contact battery, the silicon wafer is first subjected to boron diffusion treatment to form emitters on the front and back surfaces of the silicon wafer, respectively; the emitters on the back surface of the silicon wafer are removed, and a tunneling oxide layer and a polycrystalline silicon layer are sequentially prepared on the back surface.

[0041] Another technical solution provided by the present invention: a passivated contact battery prepared by the above-described method for preparing passivated contact batteries.

[0042] Another technical solution provided by the present invention is a solar photovoltaic power generation system, wherein the solar photovoltaic power generation system includes the passivated contact battery described above.

[0043] Due to the application of the above technical solution, the present invention has the following advantages compared with the prior art: Based on the problems of high lateral transport distance, high lateral resistance, and insufficient risk resistance of the current selective polysilicon passivation contact structure, the inventors of this invention discovered during extensive experimental research that by replacing the continuous removal method with intermittent removal in the left-right direction when selectively removing part of the doped polysilicon and tunnel oxide layer in the non-metallized region, this structural design achieved an unexpected reduction in lateral transport distance and lateral transport resistance. In particular, this structural design has a significant compensatory effect on the failure of partial carrier aggregation function caused by the failure of some fine grid lines and the corresponding doped polysilicon within their orthogonal projection range, reducing carrier recombination, avoiding the increase of series resistance, and thus ensuring that the battery has good core indicators such as short-circuit current, fill factor, and conversion efficiency. In particular, according to the structural design of this invention, some fine grid lines can also be made into an intermittent design, making them partially disconnected. This not only hardly reduces the core indicators of the battery, but also has the following advantages: 1) The reduction in printing area helps to reduce the amount of silver paste required for printing; 2) The reduction in printing area helps to reduce the metal composite of the battery and improve the open circuit voltage of the battery; 3) The metal grid lines on the back of the battery reduce the obstruction of incident light, optimize the utilization rate of light on the back of the battery, and combined with the special selective passivation battery structure of this invention, further improve the double-sided utilization rate of the passivated contact battery.

[0044] Furthermore, the preparation method of the present invention not only has the advantage of preventing paste leakage during the preparation of fine grid lines and main grid lines on the front and back surfaces, but also enables the printing of finer grid lines and non-contact printing, reducing the risk of silicon wafer breakage. Attached Figure Description

[0045] Figure 1 This is one of the top views of the passivated contact battery back surface in an embodiment of the present invention; Figure 2This is a second top view of the passivated contact battery back surface in an embodiment of the present invention; Figure 3 This is the third top view schematic diagram of the passivated contact battery back surface in an embodiment of the present invention; Figure 4 This is the fourth top view schematic diagram of the passivated contact battery back surface in an embodiment of the present invention; Figure 5 This is one of the schematic diagrams of carrier transport on the back surface of the passivated contact battery in an embodiment of the present invention; Figure 6 This is a second schematic diagram of carrier transport on the back surface of the passivated contact battery in an embodiment of the present invention (in the case of local failure). Figure 7 This is a schematic diagram of carrier transport on the back surface of a passivated contact battery under local failure conditions in the prior art; Figure 8 This is the third schematic diagram of carrier transport on the back surface of the passivated contact battery in an embodiment of the present invention (in the case of local failure). Figure 9 This is a top view of the back surface of the passivated contact battery in Comparative Example 1. Figure 10 This is a top view of the back surface of the passivated contact battery in Comparative Example 2. Figure 11 This is a top view of the back surface of the passivated contact battery in Comparative Example 3. Figure 12 This is a top view of the back surface of the passivated contact battery in Comparative Example 4. In the attached figures, the following are the reference numerals: 1, unit area; 11, fine grid line on the back side; 111, partially broken portion; 12, main grid line on the back side; 13, first sub-region; 14, second sub-region; 141, interval area; 15, continuous open film area. Detailed Implementation

[0046] The main concept of this invention is as follows: On the one hand, this invention does not adopt the current selective polysilicon passivation contact structure design. Instead, it divides the original transversely complete polysilicon opening region between two fine gates into two or more opening regions spaced apart in the left-right direction. That is, the doped polysilicon layer between two adjacent fine gates is not continuously removed in the left-right direction. A portion of doped polysilicon extending in the up-down direction is retained between two adjacent opening regions. The transport of charge carriers in doped polysilicon is similar to that in metal materials. The structural design in this invention allows charge carriers to be transported through polysilicon channels that are closer together after generation. In particular, the transport distance in the left-right direction is greatly shortened. Furthermore, since the resistance of doped polysilicon is significantly lower than that of silicon wafers, i.e. silicon substrates, the shortening of the transport distance in the left-right direction is beneficial to improving the carrier transport efficiency and improving indicators such as the battery fill factor (FF). On the other hand, the back-side fine grid pattern design in this invention does not adopt the traditional pattern scheme, but instead breaks up the through-through fine grid pattern; The reason why the traditional back-side full-surface polysilicon passivation contact structure cannot adopt the solution of this invention is that, in the traditional back-side full-surface polysilicon structure, in order to ensure that the parasitic absorption loss of the polysilicon layer is not too high, the doping concentration or the thickness of the polysilicon is limited, such as: doping concentration N≤4.0E+20 cm. -3 With a thickness ≤120 nm, the sheet resistance of the doped polysilicon layer is as high as 100~150 Ω / sq, resulting in high sheet resistance for lateral transport. Although the disconnected gate structure of this invention can save silver paste, the excessively high resistance of the disconnected portion leads to a decrease in the efficiency of the passivated contact cell. As mentioned above, in the traditional full-surface polysilicon structure on the back side, if the solution of this invention is adopted, while avoiding the high sheet resistance problem caused by the disconnected portion, it is necessary to increase the doping concentration or the thickness of the polysilicon to reduce the surface sheet resistance of the disconnected area and avoid efficiency loss in the disconnected fine gate area. However, the two solutions mentioned above for reducing surface sheet resistance will aggravate the parasitic absorption of polysilicon, resulting in greater efficiency loss. Therefore, this novel gate structure design is not applicable to the traditional polysilicon passivation structure. However, this structure can be matched with the novel selective polycrystalline silicon passivation contact structure proposed in this invention for the following reasons: 1) In the selective passivation structure, a large area of ​​polycrystalline silicon is removed, leaving only a small portion of the polycrystalline silicon layer between the fine grid lines. In particular, the discontinuous design structure along the left and right directions is adopted during removal. The two schemes mentioned above for reducing the sheet resistance of the polycrystalline layer surface—increasing the doping concentration or increasing the thickness of the doped polycrystalline silicon layer—can be applied to the structure of this invention, and the influence of polycrystalline silicon parasitic absorption can be greatly reduced, without a sharp increase in parasitic absorption; 2) At the same time, a small portion of the polycrystalline silicon layer between the fine grid lines is retained. This portion of the polycrystalline silicon layer connects two adjacent fine grid lines, which is beneficial for carriers to select a shorter transmission distance, further reducing resistance loss and improving the fill factor FF of the battery; In particular, metallization is an important step in the manufacturing process of passivated contact batteries, and achieving cost reduction and efficiency improvement is the eternal goal of the metallization process of passivated contact batteries. Silver paste is an important auxiliary material in the metallization process. With the rise in silver prices, the price of silver paste has exceeded 10,000 yuan / kg. It accounts for more than 80% of the non-silicon cost (excluding the cost of silicon wafers) of passivated contact batteries. The design of partial disconnection of fine grid lines in this invention can reduce the cost of silver paste. Furthermore, it is precisely because of the special selective passivation contact structure design of this invention that the overall battery performance is basically not negatively affected after the active disconnection of local fine grids. This effect means that when the battery structure of this invention faces sudden situations, such as the failure of some fine grid lines and the corresponding doped polycrystalline silicon within their orthogonal projection range, the structure of this invention has a significant compensatory effect on the loss of partial carrier aggregation function that may be caused by the aforementioned failure, reducing carrier recombination, avoiding the increase of series resistance, and thus ensuring that the battery has good core indicators such as short-circuit current, fill factor and conversion efficiency. This effect is surprising.

[0047] Meanwhile, the preparation method of this invention can also prevent paste leakage during the preparation process. The appearance of the solar cell is one of the criteria for judging its quality. In the printing process, traditional screen printing may cause paste leakage due to wear or puncture during long-term production, leaving silver paste in the non-metallized areas of the solar cell, causing contamination of the surface appearance and affecting the quality of the solar cell. In traditional back-side polycrystalline silicon deposition solar cells, the back-side ablation-type silver paste cannot directly contact the silicon substrate due to the obstruction of polycrystalline silicon, so the paste leakage problem only affects the appearance of the solar cell. However, in solar cells with selective polycrystalline silicon passivation contact structures, if the paste leakage problem exists in the polycrystalline silicon opening removal area of ​​the non-metallic region, after high-temperature sintering, the burn-through silver paste directly contacts the silicon substrate of the cell, resulting in severe metal recombination, causing a decrease in electrical performance (Voc) and FF, thereby reducing the efficiency of the solar cell. This invention uses steel plate printing, laser transfer, or electroplating to prepare fine grid lines and main grid lines on the front and back surfaces. It not only has the advantage of preventing ink leakage, but also enables the printing of finer grid lines and non-contact printing, reducing the risk of silicon wafer breakage.

[0048] Based on this, the present invention provides a method for fabricating a passivated contact battery. The method includes: sequentially fabricating a tunneling oxide layer and a polycrystalline silicon layer on the back surface of a silicon wafer, then performing phosphorus diffusion to form a phosphorus-doped polycrystalline silicon layer, and forming a phosphorus-silicon glass layer on the phosphorus-doped polycrystalline silicon layer. Specifically, the back surface includes multiple unit regions, each unit region including n first sub-regions and second sub-regions, where n is greater than or equal to 2; the n first sub-regions are sequentially spaced along the left-right direction, and the spacer region extends along the up-down direction; the second sub-region surrounds the n first sub-regions, and the spacer region is a part of the second sub-region. The method for preparing the passivated contact battery further includes: Patterned film opening is performed on the phosphorosilicate glass layer. After film opening, the phosphorosilicate glass layer in each first sub-region is removed, and the tunneling oxide layer and phosphorus-doped polysilicon layer corresponding to each first sub-region are removed from the film opening area. Then, the phosphorosilicate glass layer in the second sub-region is removed. Passivation layers are deposited on the front and back surfaces, and fine and main grid lines are prepared separately. When preparing the back fine grid lines, at least one of them is partially broken, and the length of the partially broken part is controlled to be less than 20% of the length of the corresponding back fine grid line. The fine and main grid lines on the front and back surfaces are prepared by steel plate printing, laser transfer or electroplating.

[0049] The following is combined with Figures 1 to 4 The selective passivation contact structure of the present invention will be further described; in the present invention, both the left-right direction and the up-down direction are based on... Figure 1 From the perspective of the image, the direction of the arrangement of each back main grid line is left and right, that is, multiple back main grid lines are arranged sequentially in the left and right direction, and the direction of the arrangement of each back fine grid line is up and down, that is, multiple back fine grid lines are arranged sequentially in the up and down direction.

[0050] See Figure 1 As shown, within each unit region 1, two spaced first sub-regions 13 are arranged sequentially along the left and right directions of the back fine grid line 11, specifically along the length direction of the back fine grid line 11. The shape of the first sub-region 13 is rectangular, and each first sub-region 13 is surrounded by a second sub-region 14. Each back fine grid line 11 is provided with a partial break portion 111 that avoids contact with the back main grid line 12, and the spaced regions 141 and the partial break portions 111 in all unit regions 1 between every two adjacent back main grid lines 12 extend along the same path.

[0051] See Figure 2 As shown, within each unit region 1, two spaced first sub-regions 13 are sequentially arranged along the left-right direction of the back fine grid line 11, specifically along the length direction of the back fine grid line 11. The shape of the first sub-region 13 is trapezoidal, with the shorter side of the two parallel sides of the trapezoid close to the back main grid line 12 and the longer side close to the spaced area 141. Each first sub-region 13 is surrounded by a second sub-region 14. Each back fine grid line 11 is provided with a partial break portion 111 that avoids contact with the back main grid line 12. The spaced area 141 and the partial break portion 111 in all unit regions 1 between every two adjacent back main grid lines 12 extend along the same path.

[0052] See Figure 3As shown, within each unit region 1, three spaced first sub-regions 13 are arranged sequentially along the left and right directions of the back fine grid line 11, specifically along the length direction of the back fine grid line 11. The shape of the first sub-region 13 is rectangular, and each first sub-region 13 is surrounded by a second sub-region 14. Each back fine grid line 11 has a partially broken portion 111 that avoids contact with the back main grid line 12. In this example, the three first sub-regions 13 within each unit region 1 form two spaced regions 141, which are arranged on the left and right sides of the partially broken portion 111. The two segments of the fine grid formed by the broken back fine grid line 11 within each unit region 1 are of approximately the same length.

[0053] See Figure 4 As shown, within each unit region 1, three spaced first sub-regions 13 are sequentially arranged along the left-right direction of the back fine grid line 11, specifically along the length direction of the back fine grid line 11. The shape of the first sub-region 13 is rectangular, and each first sub-region 13 is surrounded by a second sub-region 14. Each back fine grid line 11 has a partially broken portion 111 that avoids contact with the back main grid line 12. In this example, the three first sub-regions 13 within each unit region 1 form two spaced regions 141. One spaced region 141 is located below the partially broken portion 111, and the other is far away from the partially broken portion 111. The two segments of the fine grid formed by the broken back fine grid line 11 within each unit region 1 have different lengths.

[0054] The following is combined with Figures 5 to 8 The special selective passivation contact structure of the present invention can maintain a short carrier transport distance under both normal and special conditions as explained below: In actual battery design, the length of each cell area is much greater than its width, generally more than 10 times. The figure in this invention uses 10 times as an example for illustration. See Figure 5 As shown, the present invention extends the spacing region 141 in the vertical direction. That is, within each unit region, multiple spaced first sub-regions are sequentially arranged along the length direction of the back fine gate line 11. In this case, taking the charge carrier generated at the center as an example, the distance it travels to the nearest side in the length direction decreases from 5d to 2.5d. Since the absolute amount of decrease in the length direction is much greater than the order of magnitude of the transmission distance in the width direction, overall, the design of the selective passivation contact structure of the present invention is beneficial to reducing the carrier transmission distance. In particular, the more spaced first sub-regions are arranged, the greater the decrease in the distance it travels to the nearest side in the length direction will be. For example... Figure 5 The lower schematic diagram shows that when there are 10 interval regions 141, the first sub-region has 11 corresponding regions, and the distance transmitted to the nearest side in the length direction is shortened to 5d / 11.

[0055] Further, see Figure 6 As shown, the method of sequentially arranging multiple spaced first sub-regions along the length of the back fine grid line 11 in this invention actually forms a longitudinal anti-breakage grid design. If the back fine grid line 11 and the corresponding doped polysilicon experience an unexpected carrier transport failure, this longitudinal anti-breakage grid design, relying on the spaced regions 141 extending vertically (the spaced regions themselves are polysilicon layers, such as phosphorus-doped polysilicon, whose conductivity is close to that of metal; therefore, although their carrier transport capability is not as good as metal, it still possesses good carrier transport capability), can transfer some of the carriers gathered on the fine grid line back to the adjacent back fine grid line to complete the carrier aggregation. This avoids the complete failure of the entire back fine grid line when it fails locally, ultimately ensuring that the overall carrier transport capability of the battery is maintained under special circumstances. However, if the design in CN119486360 B is adopted, it cannot possess the ability of this invention to reduce the lateral transmission distance (e.g., ...). Figure 7 As shown, its structure consists of multiple spaced first sub-regions arranged sequentially along the width direction of the back fine grid line 11. Moreover, in the case of such sudden events, it is difficult to guarantee a short carrier transmission distance, and its carrier transmission distance becomes longer. Specifically, see Figure 8 As shown, even if the longitudinal anti-breakage grid design of the present invention, i.e. the interval region 141 extending in the vertical direction, experiences local failure, the charge carriers can still be converged through other back fine grid lines adjacent to it, and the lateral transport distance of the charge carriers does not increase. This structure makes the advantages of the longitudinal anti-breakage grid design of the present invention more obvious, and has a significant positive effect on ensuring that the battery has good short-circuit current, fill factor and conversion efficiency and other core indicators, and has outstanding risk resistance.

[0056] Based on the above research and findings, this invention proposes a partial disconnection design for the fine grid lines on the back side. This design not only does not reduce the core performance indicators of the battery, but also has the following advantages: 1) The reduction in printing area helps to reduce the amount of silver paste required for printing; 2) The reduction in printing area helps to reduce the metal composite of the battery and improve the open-circuit voltage of the battery; 3) The metal grid lines on the back side of the battery reduce the obstruction of incident light, optimize the utilization rate of light on the back side of the battery, and combined with the special selective passivation battery structure of this invention, further improve the double-sided utilization rate of the passivated contact battery.

[0057] The passivated contact battery of the present invention will be further explained below in conjunction with the preparation method.

[0058] In some embodiments, the method for preparing the passivated contact battery of the present invention includes: 1) Take a monocrystalline silicon wafer, such as an N-type monocrystalline silicon wafer, and perform wet cleaning on the N-type monocrystalline silicon wafer to remove the damaged layer on the silicon wafer surface, clean the surface metal impurities and oil stains, and create a textured surface. At a reaction temperature of 70±10℃, use a 10% (v / v) sodium hydroxide aqueous solution to etch the damaged layer on the silicon wafer surface caused by wire cutting. The etched thickness on both sides is approximately 10µm. Then, use an alkaline solution + texturing additive wet chemical process to generate a random pyramidal surface texture, and perform standard RCA wet cleaning. The resulting random pyramid height is approximately 0.5~2µm. That is, a pyramidal textured surface structure is obtained on both sides of the N-type monocrystalline silicon wafer.

[0059] 2) A double-sided boron diffusion process is performed on the texturized silicon wafer to form surface emitters. The boron source used in the boron diffusion process is boron tribromide (BBr3) or boron trichloride (BCl3), and the peak diffusion temperature is 1000–1100℃. After the boron diffusion process, the sheet resistance of the boron emitter is measured to be 300Ω / sq–400Ω / sq using a four-probe testing method. That is, boron-doped emitters are formed on both the front and back surfaces of the N-type single-crystal silicon wafer.

[0060] 3) Wet polishing of the battery back surface. The BSG layer on the back and edges of the boron-doped silicon wafer is removed using a 3%–10% HF aqueous solution. Then, the back surface of the silicon wafer is polished using a wet additive + KOH / NaOH + water solution (ratio 1:5:90) at a reaction temperature of 60±10℃. This ensures that only the boron-doped emitter on the front side is retained on the N-type single-crystal silicon wafer.

[0061] 4) A tunneling oxide layer and an intrinsic amorphous silicon layer are grown on the back surface of the battery. Low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD) are used to deposit an ultrathin tunneling oxide layer and an intrinsic amorphous silicon layer on the back surface of the silicon wafer under low-pressure conditions using oxygen and silane. The structural material of the ultrathin tunneling oxide layer is SiO2, the deposition reaction temperature is 580–630℃, and the thickness is selected to be 1.0–2.5 nm. The deposition reaction temperature of the intrinsic amorphous silicon is 580–650℃, and the thickness is selected to be 60–200 nm. 5) Phosphorus diffusion, forming a phosphorus-doped polycrystalline silicon structure. The phosphorus diffusion process is as follows: Under oxygen conditions, phosphorus oxychloride decomposes at high temperature (approximately 790°C) to generate phosphorus pentachloride and phosphorus pentoxide. The generated phosphorus pentoxide reacts with silicon at the diffusion temperature (approximately 875°C) to generate silicon dioxide and phosphorus atoms. The phosphorus atoms enter the intrinsic amorphous silicon layer, forming a phosphorus-doped polycrystalline silicon layer. Phosphorus silicate glass (PSG) is formed on the surface of the doped polycrystalline silicon layer. The sheet resistance of the phosphorus-doped polycrystalline silicon layer is 40~80 Ω / sq, and the phosphorus atom doping concentration is 4.0E+20~8.0E+20 cm⁻¹. -3The thickness of PSG is 25~35 nm.

[0062] 6) Laser-assisted patterning is performed on the back PSG layer to remove the doped polysilicon in the non-metallized area on the back surface of the battery. (i.e., patterning is performed at the location corresponding to the first sub-region. The multiple first sub-regions of this invention are spaced apart, and the corresponding patterning areas are also spaced apart.) This removes the PSG protective layer on the surface of the doped polysilicon layer and completes the patterning. The wavelength of the laser used for patterning is a picosecond laser of 300–600 nm, preferably a 355 nm ultraviolet laser or a 532 nm green laser. The laser spot length is 100–800 µm, the width is 50–400 µm, the laser frequency is 100–1000 kHz, the laser scanning speed is 25–75 m / s, and the laser energy of a single spot is 40–150 µJ. Within a single cell (corresponding to the aforementioned cell region) formed by the intersection of two adjacent main grid lines and two adjacent fine grid lines (or the extensions of two adjacent fine grid lines), the area of ​​laser-etched film accounts for 40% to 96% of the area of ​​the single cell. The pattern of laser-etched film can be a rectangle, trapezoid, triangle, or other shapes.

[0063] 7) Wet chemical etching to form a selective polysilicon layer. First, the silicon wafer is passed through a chain-machine HF aqueous solution to remove excess doped polysilicon layers on the front and edges. Then, the wafer undergoes an RCA process using a mixed solution of wet additives + KOH / NaOH + water (ratio 1:5:90) to etch away the doped polysilicon layer at the back trench area and the tunneling oxide layer on the back. The doped polysilicon layer in the areas not laser-etched is protected by PSG and remains intact in the solution. The reaction temperature is 60±10℃, the reaction time is 5~8 min, and the etching depth is 3~5 μm. Finally, the remaining PSG layer on the back of the wafer is completely removed using an HF aqueous solution.

[0064] 8) Deposition of passivation / antireflection film on the front and back surfaces of the battery. The passivation / antireflection film on the front and back surfaces adopts a stacked film design, which is a combination of two materials such as alumina, silicon dioxide, and silicon oxynitride. Preferably, an alumina + silicon nitride passivation / antireflection film stacked design is adopted, wherein the preferred thickness of alumina is 3-8 nm and the preferred thickness of silicon nitride is 60-100 nm.

[0065] 9) Metal electrode printing and sintering on the front and back surfaces. Metallized patterns are formed on the front and back surfaces. The metal grid lines can be made of silver paste, silver-aluminum paste, or other metal materials (aluminum, copper, titanium, nickel, etc.). The width of the fine grid lines on the front and back surfaces is 5–30 µm, the height is 2–15 µm, the spacing between adjacent fine grid lines is 0.4–1.2 mm, and the number is 150–400. The width of the main grid lines is 40–80 µm, the height is 1–10 µm, the spacing between adjacent main grid lines is 9–18 mm, and the number is 12–20. The fine grid lines on the back surface have local breaks. The position and length of the break between two adjacent fine grid lines can be the same or different. That is, the length of the fine grid lines leading from the main grids on both sides can be consistent or inconsistent, with a break width of 0.1 mm–2 mm, accounting for approximately 1%–20% of the length of a single cell's fine grid.

[0066] Furthermore, the fine grid lines and main grid lines on the front and back surfaces are prepared using steel plate printing, laser transfer, or electroplating methods. After the metal grid lines are formed, they are sintered or annealed for curing. The sintering temperature is 650–800℃, and the annealing temperature is 200–450℃. Laser-assisted sintering can be used in combination to enhance the contact between the metal grid lines and silicon and reduce the contact resistivity.

[0067] in: (1) Steel plate printing method: The steel plate printing method is the same as the traditional screen printing process, the only difference being that the traditional screen is replaced with a steel plate, and the pattern on the steel plate is exactly the same as the pattern on the screen.

[0068] Specifically, the steel plate printing method includes: printing on a silicon wafer using a rigid metal mesh plate with perforations, suspending the rigid metal mesh plate directly above the silicon wafer and keeping it in a non-contact state, uniformly applying conductive paste to the surface of the rigid metal mesh plate, scraping the rigid metal mesh plate at a uniform speed and pressure from one side, the paste passing through the perforations under pressure and falling onto the surface of the silicon wafer to form grid lines, drying, and sintering; During the pressure scraping process, the printing pressure applied by the squeegee is 10-80N, the printing speed is 100-1000mm / s, and the spacing between the rigid metal mesh and the silicon wafer is 1-5mm.

[0069] Furthermore, the drying and sintering process conditions are the traditional process conditions, consistent with those for screen printing, and will not be elaborated upon here.

[0070] (2) Laser transfer method: The laser transfer method includes: preparing grooves for the grid line pattern of the battery cell on a transparent material, using a pulsed laser to focus internally in the non-processed areas on both sides of the groove, and then placing the paste corresponding to the grid lines into the groove to obtain a transfer substrate; A silicon wafer with a passivation layer is placed below the transfer substrate with the trench facing the silicon wafer. Then, a shaping laser is used to irradiate the trench containing the paste, causing the paste in the trench to transfer onto the silicon wafer. After drying and sintering, fine gate lines or main gate lines are fabricated.

[0071] Furthermore, during the laser transfer process, the pulsed laser is a picosecond laser and / or a femtosecond laser with a wavelength range of 343–1064 nm, and the shaping laser has a wavelength range of 343–2000 nm with a spot shape of Gaussian or flat light.

[0072] Specifically, the laser transfer method includes: 1. First, grooves for the metal grid pattern of the battery cell are fabricated on a transparent material (e.g., a transparent glass substrate); 2. Using pulsed laser (picosecond / femtosecond level, wavelength range 343~1064nm) to perform internal focusing in the non-processed area on both sides of the trench, the transparent material is locally modified through nonlinear absorption, forming a fogging layer of light scattering particles. This area can reduce the transmitted laser power by 50%~90%, ensuring that the residual energy is below the damage threshold of the photovoltaic silicon wafer. 3. The required slurry for the grid lines is evenly scraped into the grooves set in the carrier plate using a coating machine module; 4. Place the solar cells under the carrier plate; 5. A shaping laser is used to irradiate the grooves of a carrier plate containing paste (commercially available). The paste irradiated by the laser will rapidly expand thermally, and the resulting downward pressure will push the paste in the groove onto the solar cell placed below, thereby forming a complete grid pattern. The laser wavelength range of the shaping laser is 343-2000nm, and the spot shape can be a circular, rectangular, or flat-topped Gaussian beam. 6. The solar cells with grid lines printed on them are dried, sintered, light-injected, and laser-assisted sintered (the process conditions for this part are the traditional process conditions, which are the same as those for screen printing, and will not be described in detail here) to obtain the final finished solar cells.

[0073] (3) Electroplating method: The electroplating method is a copper electroplating method, which includes: forming grooves on the surface of the passivation layer on the back surface of the silicon wafer according to the grid pattern by laser processing, cleaning, obtaining an intermediate silicon wafer with patterned grooves, and then placing it in a copper electroplating solution for electroplating.

[0074] Specifically, the copper electroplating method includes: 1. A groove is formed on the passivation layer surface of the solar cell by laser processing according to the grid pattern; 2. Clean the solar cell with thick film to remove the oxide layer on the surface of the patterned area, and obtain an intermediate silicon wafer with patterned grooves; 3. A silicon wafer with patterned grooves is placed in a copper plating solution. An LED is used to continuously illuminate the copper plating solution, with the silicon wafer as the cathode and a pure copper sheet as the anode. Periodic forward and reverse pulses are applied between the cathode and anode for electroplating. The copper content in the plating solution is... 2+ The concentration is 80 g / L, the H2SO4 concentration is 130 g / L, and the Cl concentration is... - The concentration is 85 mg / L, the brightener concentration is 8 mL / L; the positive pulse current density is 10 A / dm³. 2 The reverse pulse current density is 20 A / dm. 2 The ratio of the forward pulse time to the reverse pulse time is 18:2, and the pulse frequency is 50Hz.

[0075] The above-mentioned solution will be further described below with reference to specific embodiments; it should be understood that these embodiments are used to illustrate the basic principles, main features and advantages of the present invention, and the present invention is not limited to the scope of the following embodiments; the implementation conditions used in the embodiments can be further adjusted according to specific requirements, and the implementation conditions not specified are usually the conditions in conventional experiments.

[0076] Unless otherwise specified in the following examples, all raw materials are commercially available or prepared by conventional methods in the art.

[0077] Example 1: This example provides a method for preparing a passivated contact battery and the passivated contact battery made therefrom.

[0078] The aforementioned specific preparation method is adopted, wherein: Figure 1 The structure shown has two rectangular sub-regions spaced 200 μm apart. The total area of ​​these two sub-regions accounts for 80% of the area of ​​the unit region. The fine grid lines on both sides of the partially broken sections are of equal length, with a spacing of 1.5 mm between the breaks, and corresponding fine grid lines on the back side are 10 mm long. The fine grid lines and main grid lines on the front and back surfaces are fabricated using a steel plate printing method with a printing pressure of 40 N, a printing speed of 550 mm / s, and a spacing of 2.2 mm.

[0079] Example 2: This example provides a method for preparing a passivated contact battery and the passivated contact battery made therefrom.

[0080] The aforementioned specific preparation method is adopted, wherein: Figure 2The structure shown has two trapezoidal first sub-regions spaced 200 μm apart. The total area of ​​these two first sub-regions accounts for 84% of the unit area. The fine grid lines on both sides of the partially broken sections are of equal length, with a spacing of 1.5 mm between the breaks, and corresponding back-side fine grid line lengths of 10 mm. The fine grid lines and main grid lines on the front and back surfaces are fabricated using a steel plate printing method with a printing pressure of 40 N, a printing speed of 550 mm / s, and a spacing of 2.2 mm.

[0081] Example 3: This example provides a method for preparing a passivated contact battery and the passivated contact battery made therefrom.

[0082] The aforementioned specific preparation method is adopted, wherein: Figure 3 The structure shown has three rectangular sub-regions spaced 150 μm apart. The total area of ​​these three sub-regions accounts for 80% of the unit area. The fine grid lines on both sides of the partially broken sections are of equal length, with a spacing of 2.0 mm between the breaks, corresponding to a fine grid line length of 10 mm. The fine grid lines and main grid lines on the front and back surfaces are fabricated using a laser transfer method with a 532 nm green laser. The laser spot is rectangular, 180 × 180 μm in size, and the scanning speed is 10000 mm / s.

[0083] Example 4: This example provides a method for preparing a passivated contact battery and the passivated contact battery made therefrom.

[0084] The aforementioned specific preparation method is adopted, wherein: Figure 4 The structure shown has three rectangular sub-regions spaced 150 μm apart. The total area of ​​these three sub-regions accounts for 80% of the area of ​​the unit region. The fine grid lines on the back side of the partially broken areas are of unequal length, with a spacing of 1.5 mm between the breaks, and the corresponding length of the fine grid lines on the back side is 10 mm. The fine grid lines and main grid lines on the front and back surfaces are fabricated using the copper electroplating method described above.

[0085] Comparative Example 1: The traditional TOPCon passivated contact battery structure is used, and its structure is described in [reference needed]. Figure 9 As shown, the tunneling oxide layer and polysilicon layer were not removed within the cell region 1 formed by the back fine gate line 11 and the back main gate line 12. The fabrication of the fine gate line and main gate line on the front and back surfaces is the same as in Example 1.

[0086] Comparative Example 2: It adopts a conventional selective TOPCon passivated contact cell structure, the structure of which is described in [reference needed]. Figure 10As shown, the cell region 1 formed by the back fine gate line 11 and the back main gate line 12 has undergone continuous removal of the tunneling oxide layer and polysilicon layer, i.e., a continuous open film region 15 is provided. The fabrication of the fine gate line and main gate line on the front surface and back surface is the same as in Example 1.

[0087] Comparative Example 3: Employing a conventional selective TOPCon passivated contact cell structure, the cell region 1 formed by the back fine grid lines 11 and the back main grid lines 12 undergoes continuous removal of the tunneling oxide layer and polycrystalline silicon layer, i.e., a continuous open-film region 15 is provided. Furthermore, the design of the back fine grid lines with a partially disconnected region 111 is adopted, the structure of which is described in [reference needed]. Figure 11 As shown. The fabrication of the fine grid lines and main grid lines on the front and back surfaces is the same as in Example 1.

[0088] Comparative Example 4: The selective TOPCon passivated contact battery structure described in CN119486360 B is adopted. Within the cell region 1, two first sub-regions 13 and one second sub-region are spaced apart in the vertical direction (i.e., along the width direction of the back fine grid lines). A spacing region 141 extending in the horizontal direction (i.e., the length direction of the back fine grid lines) is formed between the two first sub-regions 13. The design incorporates a partially broken back fine grid line region 111, as described in the present invention. (See attached diagram for details.) Figure 12 As shown. The fabrication of the fine grid lines and main grid lines on the front and back surfaces is the same as in Example 1.

[0089] Performance testing: The batteries obtained in Examples 1-4 and Comparative Examples 1-4 were subjected to the following performance tests: The test method was to use an IV tester to test the photoelectric conversion efficiency and related electrical performance parameters of the batteries under standard illumination power under simulated solar light. The specific test results are shown in Table 1 (Eta: conversion efficiency, Voc: open-circuit voltage, Jsc: short-circuit current density, FF: fill factor).

[0090] Table 1 As shown in Table 1, the conversion efficiency of the battery of the present invention has been significantly improved. Compared with Comparative Example 1, the conversion efficiency of Example 1 has increased by 0.18%. For crystalline silicon passivated contact batteries, a change of 0.1% is usually a huge improvement. It can be seen that the improved battery structure of the present invention can optimize short-circuit current density, open-circuit voltage, and fill factor, and the synergistic effect promotes a significant improvement in battery efficiency. Moreover, it can reduce the amount of paste used for the fine grid line electrodes on the back, which greatly reduces costs. In addition, the preparation method of the present invention not only has the advantage of preventing paste leakage in the preparation process of fine grid lines and main grid lines on the front and back surfaces, but also enables the printing of finer grid lines and contactless printing, reducing the risk of silicon wafer breakage.

[0091] The above embodiments are only for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

[0092] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of the various ranges, the endpoint values ​​of the various ranges and individual point values, and individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein.

Claims

1. A method for preparing a passivated contact battery, the method comprising: A tunneling oxide layer and a polycrystalline silicon layer are sequentially prepared on the back surface of a silicon wafer, followed by phosphorus diffusion to form a phosphorus-doped polycrystalline silicon layer. A phosphorus-silicon glass layer is then formed on the phosphorus-doped polycrystalline silicon layer. The back surface comprises multiple unit regions, each unit region comprising n first sub-regions and n second sub-regions, where n is greater than or equal to 2. The n first sub-regions are sequentially spaced along the left-right direction, and the spacer regions extend along the up-down direction. The second sub-regions surround the n first sub-regions, and the spacer regions are part of the second sub-regions. The method for preparing the passivated contact battery further includes: Patterned film opening is performed on the phosphorosilicate glass layer. After film opening, the phosphorosilicate glass layer in each first sub-region is removed, and the tunneling oxide layer and phosphorus-doped polysilicon layer corresponding to each first sub-region are removed from the film opening area. Then, the phosphorosilicate glass layer in the second sub-region is removed. Passivation layers are deposited on the front and back surfaces, and fine and main grid lines are prepared separately. When preparing the back fine grid lines, at least one of them is partially broken, and the length of the partially broken part is controlled to be less than 20% of the length of the corresponding back fine grid line. The fine and main grid lines on the front and back surfaces are prepared by steel plate printing, laser transfer or electroplating.

2. The method for preparing a passivated contact battery according to claim 1, characterized in that: The steel plate printing method includes: printing on a silicon wafer using a rigid metal mesh plate with perforations; suspending the rigid metal mesh plate directly above the silicon wafer and keeping it in a non-contact state; uniformly applying conductive paste to the surface of the rigid metal mesh plate; scraping the rigid metal mesh plate at a constant speed and pressure from one side; the paste passing through the perforations under pressure and falling onto the surface of the silicon wafer to form grid lines; drying; and sintering. During the pressure scraping process, the printing pressure applied by the squeegee is 10-80N, the printing speed is 100-1000mm / s, and the spacing between the rigid metal mesh and the silicon wafer is 1-5mm.

3. The method for preparing a passivated contact battery according to claim 1, characterized in that: The laser transfer method includes: Grooves with grid lines of a battery cell are fabricated on a transparent material. A pulsed laser is used to focus the internal area of ​​the non-processed area on both sides of the groove. Then, the paste corresponding to the grid lines is placed in the groove to obtain a transfer substrate. A silicon wafer with a passivation layer is placed below the transfer substrate with the trench facing the silicon wafer. Then, a shaping laser is used to irradiate the trench containing the paste, causing the paste in the trench to transfer onto the silicon wafer. After drying and sintering, fine gate lines or main gate lines are fabricated.

4. The method for preparing a passivated contact battery according to claim 3, characterized in that: The pulsed laser is a picosecond laser and / or a femtosecond laser with a wavelength range of 343–1064 nm; and / or, the shaping laser has a wavelength range of 343–2000 nm and a spot shape of a Gaussian beam or a flat-top beam.

5. The method for preparing a passivated contact battery according to claim 1, characterized in that: The electroplating method is a copper electroplating method, which includes: forming grooves on the surface of the passivation layer on the back surface of the silicon wafer according to the grid pattern by laser processing, cleaning, obtaining an intermediate silicon wafer with patterned grooves, and then placing it in a copper electroplating solution for electroplating.

6. The method for preparing a passivated contact battery according to claim 1, characterized in that: The sheet resistance of the phosphorus-doped polycrystalline silicon layer is 40~80 Ω / sq, and the phosphorus atom doping concentration is 4.0×10⁻⁶. 20 ~8.0×10 20 cm -3 ; and / or, the silicon wafer is an N-type silicon wafer.

7. The method for preparing a passivated contact battery according to claim 1, characterized in that: Patterning is performed on the phosphorosilicate glass layer using laser etching; and / or, the tunneling oxide layer and phosphorus-doped polysilicon layer corresponding to each of the first sub-regions are removed from the etched area using wet chemical etching, and the phosphorosilicate glass layer in the second sub-region is removed.

8. The method for preparing a passivated contact battery according to claim 1, characterized in that: In the first sub-region, a silicon wafer and a first back passivation layer are sequentially disposed along a direction perpendicular to the first sub-region; in the second sub-region, a silicon wafer, a tunneling oxide layer, a polysilicon layer, and a second back passivation layer are sequentially disposed along a direction perpendicular to the second sub-region. The back fine gate line and the back main gate line are both located in the second sub-region. The back fine gate line passes through the second back passivation layer and is connected to the polysilicon layer. The back main gate line is connected to the back fine gate line.

9. The method for preparing a passivated contact battery according to claim 1, characterized in that: In the n first sub-regions, the distance between any two adjacent first sub-regions is 50-200 μm.

10. The method for preparing a passivated contact battery according to claim 1, characterized in that: The total area of ​​the n first sub-regions accounts for 40%-96% of the area of ​​the unit region.

11. The method for preparing a passivated contact battery according to claim 1, characterized in that: The length of the partial break is 0.1-2 mm.

12. The method for preparing a passivated contact battery according to claim 1, characterized in that: Each of the aforementioned back-side fine grid lines has multiple local breaks.

13. The method for preparing a passivated contact battery according to claim 12, characterized in that: The total length of the plurality of said partial breaks accounts for 1%-20% of the length of the corresponding back fine grid line; and / or, the length of each of the said partial breaks on each of the back fine grid lines remains the same or different.

14. The method for preparing a passivated contact battery according to claim 1, characterized in that: The positions and lengths of the partial breaks on any two of the back fine grid lines are the same or different; and / or, the n first sub-regions are sequentially spaced along the length direction of the back fine grid lines; and / or, the spaced regions extend along the width direction of the back fine grid lines.

15. The method for preparing a passivated contact battery according to claim 1, characterized in that: The spacing regions of each of the cell regions located between two adjacent back main gate lines are distributed on the same extension line or on multiple parallel extension lines; and / or, the polysilicon layer in the second sub-region forms a multidimensional carrier transport path.

16. The method for preparing a passivated contact battery according to claim 1, characterized in that: A continuous carrier transport path is formed between any two points in the polysilicon layer corresponding to the second sub-region; and / or, the polysilicon layer corresponding to the interval region and the polysilicon layer corresponding to the partial disconnection are directly connected.

17. A passivated contact battery prepared by the method of any one of claims 1-16.

18. A solar photovoltaic power generation system, characterized in that, The solar photovoltaic power generation system includes the passivated contact cell as described in claim 17.

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