Passive array micro LED display device and chip

Abstract

The application provides a passive matrix MicroLED display device and chip, which comprises a support substrate; a pixel layer comprising a plurality of pixel units arranged in an array; a plurality of first metal wiring layers and a plurality of second metal wiring layers, which are used for respectively connecting a plurality of pixel units along a first direction and a plurality of pixel units along a second direction in the array, and adjacent two first metal wiring layers and adjacent two second metal wiring layers are electrically isolated from each other; a bonding metal electrode is arranged at the periphery of the array, and comprises a plurality of first bonding electrodes and a plurality of second bonding electrodes, which are used for respectively connecting corresponding first metal wiring layers and second metal wiring layers. The application adopts passive matrix driving, does not need alignment bonding, has a simple structure, and is beneficial to improving product yield and expanding product application range; the wiring of the first metal wiring layer and the second metal wiring layer is located below each pixel unit, which can reduce light resistance, reduce pixel matrix resistance, improve the uniformity of display device brightness, and reduce power consumption and heat generation.

Description

Technical Field

[0001] The embodiments in this specification relate to the field of semiconductor fabrication technology, and in particular to a passive array MicroLED display device and chip. Background Technology

[0002] In recent years, with the continuous development and breakthroughs in MicroLED technology, it has been applied to an increasing number of products and fields. When used in automotive headlights, MicroLED technology offers advantages over DLP (Digital Light Processing) and LCD (Liquid Crystal Display) solutions, including higher luminous efficiency and simpler, lighter modules, making it a promising candidate for large-scale application in this field. However, most current mainstream MicroLED pixel headlight products utilize active matrix driving, integrating the driver chip with the LED array through gold-to-gold bonding. This results in complex manufacturing processes and higher costs, limiting its application to high-end vehicles and hindering further expansion.

[0003] In view of this, the embodiments of this specification aim to provide a passive matrix MicroLED display device and chip. Summary of the Invention

[0004] In view of the problems of existing technologies that require gold-to-gold alignment bonding, resulting in complex product processes, high manufacturing costs, and difficulty in widespread application, the purpose of the embodiments in this specification is to provide a passive matrix MicroLED display device and chip.

[0005] To solve the above-mentioned technical problems, the specific technical solutions of the embodiments in this specification are as follows:

[0006] In a first aspect, embodiments of this specification provide a passive matrix MicroLED display device, comprising:

[0007] Support substrate;

[0008] A pixel layer, disposed on the support substrate, includes multiple pixel units arranged in an array;

[0009] Multiple first metal wiring layers are disposed between the support substrate and the pixel layer to correspondingly connect multiple pixel units in the array along the first direction, and adjacent first metal wiring layers are electrically isolated from each other.

[0010] Multiple second metal wiring layers are disposed between the first metal wiring layer and the support substrate for correspondingly connecting multiple pixel units in the array along the second direction, and adjacent two second metal wiring layers are electrically isolated from each other.

[0011] The bonding metal electrodes are disposed on the periphery of the array and include multiple first bonding electrodes and multiple second bonding electrodes. The first bonding electrodes are electrically connected to the first metal wiring layer, and the second bonding electrodes are electrically connected to the second metal wiring layer.

[0012] Secondly, embodiments of this specification provide a passive matrix MicroLED chip, including a driver circuit board, a wafer adhesive, and a passive matrix MicroLED display device provided by the above-described technical solution;

[0013] The wafer adhesive is used to attach the passive matrix MicroLED display device to the driving circuit board;

[0014] The driving circuit board is provided with a wire bonding electrode, and the bonding metal electrode of the passive matrix MicroLED display device is electrically connected to the wire bonding electrode of the driving circuit board through bonding leads.

[0015] Preferably, the pixel layer surface of the passive matrix MicroLED display device is further coated with a color conversion layer.

[0016] Using the above technical solution, the passive matrix MicroLED display device and chip provided in this specification employ passive matrix driving, resulting in a simple structure and low manufacturing cost. Subsequent pixel units can be connected to the driver circuit board leads via bonding metal electrodes, eliminating the need for alignment bonding, simplifying the process, and improving product yield and expanding the product's application range. Furthermore, the traces of both the first and second metal wiring layers are located below each pixel unit, reducing light obstruction to the pixel units. Using more suitable metals for the wiring layers helps reduce pixel matrix resistance, improves the uniformity of brightness in the display device, and reduces power consumption and heat generation.

[0017] To make the above and other objects, features and advantages of the embodiments of this specification more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments or prior art of this specification, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This specification shows a schematic diagram of the structure of a passive matrix MicroLED display device provided in an embodiment.

[0020] Figure 2 for Figure 1 A cross-sectional view along the AA direction;

[0021] Figure 3 for Figure 2 Enlarged view of point a in the middle;

[0022] Figure 4 for Figure 2 Enlarged view of point b in the middle;

[0023] Figure 5 for Figure 1 A cross-sectional view along the "BB" direction;

[0024] Figure 6 A schematic diagram of a passive array MicroLED chip provided in an embodiment of this specification is shown.

[0025] Figures 7a to 7k A schematic flowchart illustrating the fabrication method of a passive matrix MicroLED display device is shown.

[0026] Explanation of reference numerals in the attached figures:

[0027] 100. Passive matrix MicroLED display devices;

[0028] 10. Pixel layer; 11. Array; 12. Pixel unit; 13. Second contact area; 14. First contact area; 15. First doped semiconductor layer; 16. Active layer; 17. Second doped semiconductor layer; 18. Ohmic contact layer;

[0029] 21. First metal wiring layer; 22. Second metal wiring layer;

[0030] 30. Bonded metal electrode; 31. First bonded electrode; 32. Second bonded electrode;

[0031] 41. First passivation layer; 42. Second passivation layer; 43. Third passivation layer; 44. Fourth passivation layer; 45. Fifth passivation layer; 46. Sixth passivation layer; 47. Metal reflector;

[0032] 50. Supporting substrate; 51. Supporting base plate; 52. Bonding layer;

[0033] 61. First via; 62. Second via; 63. Third via; 64. Fourth via;

[0034] 70. Epitaxial substrate;

[0035] 200. Driver circuit board; 201. Wire bonding electrode of driver circuit board; 202. Bonding wire;

[0036] 300. Wafer adhesive;

[0037] 400, Color Conversion Layer. Detailed Implementation

[0038] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this specification.

[0039] It should be noted that the terms "first," "second," etc., used in this specification, claims, and the foregoing drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, apparatus, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0040] Active matrix driving schemes require the integration of the driver chip and LED array via gold-to-gold bonding, a complex and costly process. Therefore, some solutions have adopted passive driving technology. However, existing passive driving schemes typically place two metal layers on the top and bottom surfaces of the pixel layer, respectively. This top metal layer can obstruct light emission from the pixel layer, affecting display quality. To address the problems of complex processes, high manufacturing costs, and limited application range of traditional active matrix driving schemes, as well as the poor display quality of passive driving schemes, this specification provides a passive matrix MicroLED display device, chip, and its fabrication method. Specifically, as shown... Figures 1 to 6 As shown in the embodiments of this specification, a passive matrix MicroLED display includes:

[0041] The support substrate 51 is used to support and dissipate heat for the pixel layer 10 disposed thereon. The support substrate 51 can be made of high thermal conductivity materials such as silicon, SiC, AlN or diamond.

[0042] A pixel layer 10, disposed on the support substrate 51, includes a plurality of pixel units 12 arranged in an array. Specifically, in the embodiments of this specification, the plurality of pixel units 12 may be a plurality of blue LED pixel units arranged in an array to form a pixel array, which, in conjunction with phosphor, emits white light for use in automotive low beam / high beam headlights; or they may be LED pixel units of other colors, such as red LED pixel units for use in automotive brake lights; or yellow LED pixel units for use in automotive turn signals. Furthermore, the passive matrix MicroLED display device and its chip provided in the embodiments of this specification can be applied not only to automotive headlights but also to other products and other fields.

[0043] Multiple first metal wiring layers 21 are disposed between the support substrate 51 and the pixel layer 10 for correspondingly connecting multiple pixel units 12 in the array along the first direction, and adjacent first metal wiring layers 21 are electrically isolated from each other.

[0044] Multiple second metal wiring layers 22 are disposed between the first metal wiring layer 21 and the support substrate 51 for correspondingly connecting multiple pixel units in the array 11 along the second direction, and adjacent two second metal wiring layers 22 are electrically isolated from each other.

[0045] The bonding metal electrode 30 is disposed around each pixel unit 12 in the array 11, and includes a plurality of first bonding electrodes 31 and a plurality of second bonding electrodes 32; the first bonding electrodes 31 are electrically connected to the first metal wiring layer 21, and the second bonding electrodes 32 are electrically connected to the second metal wiring layer 22.

[0046] Specifically, each of the first metal wiring layers 21 has a corresponding first bonding electrode 31 at both ends outside the array. Each first bonding electrode 31 is electrically connected to each pixel unit 12 in the array 11 along the first direction through the corresponding first metal wiring layer 21. Each of the second metal wiring layers 22 has a corresponding second bonding electrode 32 at both ends outside the array 11. Each second bonding electrode 32 is electrically connected to each pixel unit 12 in the array 11 along the second direction through the corresponding second metal wiring layer 22.

[0047] In other words, each pixel unit 12 can be connected to the corresponding first bonding electrode 31 through the first metal wiring layer 21, and to the corresponding second bonding electrode 32 through the second metal wiring layer 22; further, it can be connected to the driving circuit board 200 through the first bonding electrode 31 and the second bonding electrode 32, so as to realize independent addressing and control of each pixel unit 12.

[0048] It should be noted that, in the embodiments of this specification, the first direction can be as follows: Figure 1 The direction of the row shown can be as follows: the second direction can be as follows. Figure 1The direction in which the middle column is located. The first metal wiring layer 21 is connected to each row of pixel units in the array along the first direction, and the second metal wiring layer 22 is connected to each column of pixel units in the array along the second direction. Figure 1 The orientation of the rows and columns shown is illustrated using an example. Those skilled in the art will understand that when the display orientation of the MicroLED display is adjusted, the rows or columns of pixel units in the array connected to the first and second metal wiring layers will change accordingly.

[0049] Furthermore, specifically, in the embodiments of this specification, the bonding metal electrode 30 may be made of one or more of Ti / Cr / Al / Ni / Au / Pt / Cu (and wherein at least Au / Cu / Al is included) using a metal lift-off process.

[0050] This specification provides a passive matrix MicroLED display device that employs passive matrix driving, resulting in a simple structure and low manufacturing cost. Subsequent pixel units can be connected to the driver circuit board leads via bonding metal electrodes, eliminating the need for alignment bonding, simplifying the process and improving product yield. Furthermore, the traces of both the first and second metal wiring layers are located below each pixel unit, reducing light obstruction. By fabricating a more suitable metal wiring layer, the pixel matrix resistance is reduced, thereby improving the uniformity of brightness in the LED display device and reducing power consumption and heat generation.

[0051] Furthermore, each pixel unit 12 includes at least a first doped semiconductor layer 15, an active layer 16, and a second doped semiconductor layer 17 connected in sequence, wherein the second doped semiconductor layer 17 is located on the side of the active layer 16 away from the support substrate 51.

[0052] In the embodiments described in this specification, the first doped semiconductor layer 15 can be a P-type semiconductor layer, and the second doped semiconductor layer 17 can be an N-type semiconductor layer, so that the P-type semiconductor layer and the N-type semiconductor layer are located on both sides of the active layer 16.

[0053] Specifically, the first metal wiring layer 21 is electrically connected to the first doped semiconductor layer 15 of each pixel unit 12 in the array along the first direction.

[0054] The second metal wiring layer 22 is electrically connected to the second doped semiconductor layer 17 of each pixel unit 12 in the array along the second direction.

[0055] In the embodiments described in this specification, a first metal wiring layer 21 close to the first doped semiconductor layer 15 is electrically connected to the first doped semiconductor layer 15, and a second metal wiring layer 22 located at the bottom of the first metal wiring layer 21 is electrically connected to the second doped semiconductor layer 17, which facilitates a simplified fabrication process. In some other feasible embodiments, the first metal wiring layer 21 may also be electrically connected to the second doped semiconductor layer 17 of each pixel unit 12, while the second metal wiring layer 22 is electrically connected to the first doped semiconductor layer 15 of each pixel unit 12.

[0056] In this embodiment of the specification, the first metal wiring layer 21 and the first doped semiconductor layer 15 of the target pixel unit 12 form a first contact area 14;

[0057] The second metal wiring layer 22 and the second doped semiconductor layer 17 of the corresponding pixel unit 12 form a second contact area 13;

[0058] The first contact area 14 and the second contact area 13 are electrically isolated from each other.

[0059] In the embodiments of this specification, the first contact area 14 and the second contact area 13 of each pixel unit 12 are naturally separated in space, which helps to reduce the risk of short circuit between the first metal wiring layer 21 and the second metal wiring layer 22 and reduce the difficulty of the process.

[0060] Furthermore, in the embodiments of this specification, such as Figure 1 As shown, the second contact area 13 is located in the central region of the pixel unit 12, and the first contact area 14 is located on the periphery of the central region;

[0061] Furthermore, multiple first contact areas 14 are provided, and the first contact areas 14 are evenly distributed around the second contact area 13.

[0062] By providing the second contact area 13 only in the central region of each pixel unit 12, the second doped semiconductor layer 17 (i.e., the N-type semiconductor layer), which typically has low resistivity and good conductivity, can achieve better electrical connection. Conversely, by providing multiple first contact areas 14 in the peripheral region of the pixel unit 12, the problem of the first doped semiconductor layer 15 (P-type semiconductor layer), which typically has high resistivity and poor lateral current expansion capability, can be solved, thereby improving the connection quality of the P-type semiconductor layer. Thus, through the coordinated arrangement of the number and distribution of the second contact areas 13 and the first contact areas 14, the impact of the contact areas on the light-emitting area of ​​the pixel unit 12 can be reduced, improving the uniformity of brightness in the light-emitting area of ​​the pixel unit 12; furthermore, it can prevent local current congestion in the P-type semiconductor layer and avoid local overheating; thereby helping to slow down material aging, improve the long-term reliability and lifespan of the pixel, and prevent brightness decay and color shift.

[0063] like Figure 2 and Figure 3 As shown in the embodiments of this specification, a first passivation layer 41 is also included. The first passivation layer 41 is disposed on the side of the pixel layer 10 facing the support substrate 51 and on the periphery of the array 11. Thus, the first passivation layer 41 covers the bottom of each pixel unit 12 to passivate each pixel unit 12 and isolate each pixel unit 12 from each other; simultaneously, the first passivation layer 41 also covers the second doped semiconductor layer 17 on the periphery of the array 11 to electrically isolate the second doped semiconductor layer 17 from the bonding metal electrode 30. The first passivation layer 41 can be made of one or more of SiO2, SiN, and Al2O3.

[0064] The first passivation layer 41 is provided with a through-hole 61;

[0065] The first metal wiring layer 21 is electrically connected to the first doped semiconductor layer 15 of the corresponding pixel unit 12 through the first via 61 to form each first contact area 14.

[0066] Specifically, a photoresist mask can be formed by photolithography, and plasma etching can be used to etch away at least a portion of the first passivation layer 41 in the peripheral area of ​​each pixel unit 12 to form a first via 61.

[0067] Before depositing the first passivation layer 41, plasma etching is used to remove the first doped semiconductor layer 15, the active layer 16, and at least a portion of the second doped semiconductor layer 17 in the first and second regions, thereby isolating each pixel unit 12 from each other to form a pixel array. The first region is the spacing region between two adjacent pixel units 12, and the second region is the spacing region between the pixel unit 12 located at the edge of the array and the outer region of the array 11. Simultaneously, the first doped semiconductor layer 15, the active layer 16, and at least a portion of the second doped semiconductor layer 17 in the central region of each pixel unit 12 are also etched away to form pixel vias (corresponding to the second contact region 13).

[0068] Furthermore, the bonding metal electrode 30 is disposed on the side of the first passivation layer 41 facing the support substrate 51;

[0069] The first bonding electrode 31 has a second via 62 on the side facing the support substrate 51, and the first metal wiring layer 21 is electrically connected to the corresponding first bonding electrode 31 through the second via 62.

[0070] like Figure 3As shown, the passive matrix MicroLED display device provided in this embodiment further includes a third passivation layer 43. The third passivation layer 43 is disposed at the bottom of each pixel unit 12 in the array and located between the first metal wiring layer 21 and the second metal wiring layer 22 and on the periphery of the array 11. That is, when fabricating the passive matrix MicroLED display device, the third passivation layer 43 is first deposited on the first metal wiring layer 21, and then the second metal wiring layer 22 is deposited on the third passivation layer 43 to ensure electrical isolation between the first metal wiring layer 21 and the second metal wiring layer 22.

[0071] Similar to the formation process of the first contact area 14, at least a portion of the first metal wiring layer 21 located in the central region of each pixel unit 12 is removed by a metal stripping process or an etching process to form a through-hole. At the same time, the first passivation layer 41 and the third passivation layer 43 are provided with through-hole third vias 63, so that the second metal wiring layer 22 is electrically connected to the second doped semiconductor layer 17 at the pixel via of the corresponding pixel unit 12 through the third via 63 and the through-hole, forming the second contact area 13.

[0072] Furthermore, a fourth via 64 is provided on the side of the second bonding electrode 32 facing the support substrate 51, and the second metal wiring layer 22 is electrically connected to the corresponding second bonding electrode 32 through the fourth via 64.

[0073] Thus, by creating the first via 61 and the third via 63, electrical connections are achieved between the first metal wiring layer 21 and the P-type semiconductor layer of the pixel unit, and between the second metal wiring layer 22 and the N-type semiconductor layer of the pixel unit. This process is simple and precisely determines the location of the current injection point. By creating the second via 62 and the fourth via 64, electrical connections are achieved between the first metal wiring layer 21 and the first bonding electrode 31, and between the second metal wiring layer 22 and the second bonding electrode 32, ensuring the integrity of the display device's structure and function. The third passivation layer 43 provides reliable insulation protection between the two metal wiring layers, preventing potential short circuits. Finally, the entire display device can be covered and sealed by the underlying support substrate, leaving only the top bonding metal electrode 30 as the connection point, providing a robust and stable chip foundation for subsequent mass transfer, bonding, and module packaging.

[0074] In some specific embodiments, after depositing the first passivation layer 41 and depositing the first bonding electrode 31 around the array, a second passivation layer 42 may be deposited at the bottom of the first passivation layer 41, such that the second passivation layer 42 covers each bonding metal electrode 30.

[0075] At this time, the first via 61 needs to penetrate the first passivation layer 41 and the second passivation layer 42 in the peripheral area of ​​each pixel unit 12; the third via 63 needs to penetrate the first passivation layer 41, the second passivation layer 42 and the third passivation layer 43 in the central area of ​​each pixel unit 12 (e.g., Figure 3 As shown, it should be noted that, for ease of indicating the first via 61 and the third via 63, Figure 3 The filling patterns of the first metal wiring layer 21 and the second metal wiring layer 22 have been removed. The second via 62 is formed on the second passivation layer 42 to expose the bottom surface of the first bonding electrode 31 (similarly, for easy indication of the second via 62, ...). Figure 4 The fill patterns of the first metal wiring layer 21 and the second metal wiring layer 22 were also removed.

[0076] In some feasible embodiments, during the fabrication of the first metal wiring layer 21, a stripping process can be used to isolate the first metal wiring layers 21 in adjacent rows, that is, the first metal wiring layers 21 between pixel units in adjacent rows are "disconnected"; at the same time, the first metal wiring layer 21 located at the edge of the array is also "disconnected" from the first metal wiring layer deposited at the bottom of the second bonding electrode 32 (e.g., Figure 5 (As shown). This allows the third passivation layer 43 and the second metal wiring layer 22 at the periphery of the subsequent array to be deposited at the bottom of the first metal wiring layer 21. At this time, a fourth via 64 is formed on the side of the second bonding electrode 32 facing the supporting substrate and is specifically located on the third passivation layer 43 to expose the first metal wiring layer 21, so that the second metal wiring layer 22 is electrically connected to the first metal wiring layer 21 through the fourth via 64 and then connected to the corresponding second bonding electrode 32. That is, as shown... Figure 5 The first metal wiring layer 21 at the second bonding electrode 32 shown only serves to electrically connect the second bonding electrode 32 and the second metal wiring layer 22. In some other feasible embodiments, the first metal wiring layer 21 located at the second bonding electrode 32 can be stripped, allowing the subsequent third passivation layer and the second metal wiring layer 22 to be directly deposited at the second bonding electrode 32. In this case, the fourth via 64 will be formed on the side of the second bonding electrode 32 facing the supporting substrate and specifically located at the third passivation layer 43 to expose the second bonding electrode 32. That is, the second metal wiring layer 22 can be directly electrically connected to the second bonding electrode 32.

[0077] Similarly, in some feasible embodiments, when fabricating the second metal wiring layer 22, a stripping process can be used to isolate adjacent columns of the second metal wiring layer 22 from each other, that is, the second metal wiring layer 22 between adjacent pixel units is "disconnected"; at the same time, the second metal wiring layer 22 located at the edge of the array is "disconnected" from the second metal wiring layer 22 deposited at the bottom of the first bonding electrode 31 (e.g., Figure 2 (As shown). It should be noted that, Figure 2 In this configuration, the first metal wiring layer 21 is also "disconnected" in the middle region below each pixel unit 12. This is because the cross-section passes through the second contact area 13 of each pixel unit 12. The first metal wiring layer 21 at the second contact area 13 is removed by a metal stripping process or an etching process so that the second metal wiring layer 22 can "pass through" it and be electrically connected to the second doped semiconductor layer 17. In other feasible embodiments, while using a stripping process to disconnect two adjacent second metal wiring layers, the second metal wiring layer 22 located at the bottom of the first metal wiring layer 21 at the first bonding electrode 31 can also be stripped. This ensures that the bottom of the first bonding electrode 31 is electrically connected only to the first metal wiring layer 21.

[0078] The above-described preparation of the metal wiring layer and deposition of the passivation layer are merely exemplary. For the sake of simplicity, those skilled in the art can flexibly adjust them according to actual application needs.

[0079] In this embodiment, an ohmic contact layer 18 is also included. The ohmic contact layer 18 is located between the first doped semiconductor layer 15 and the first metal wiring layer 21 of each pixel unit 12, thus allowing the first metal wiring layer 21 to be electrically connected to the first doped semiconductor layer 15 via the ohmic contact layer 18. Alternatively, the ohmic contact layer 18 may be disposed between the second doped semiconductor layer 17 and the second metal wiring layer 22. For example, before depositing the second metal wiring layer 22 to the third via 63, an ohmic contact layer is first deposited within the third via, thereby electrically connecting the second metal wiring layer 22 to the second doped semiconductor layer 17 via the ohmic contact layer. The ohmic contact layer 18 may be made of a transparent conductive oxide such as SnO2, ITO, or ZnO.

[0080] Preferably, the width of the first metal wiring layer 21 is greater than the width of each pixel unit 12 in the array corresponding to the first direction, and the width of the second metal wiring layer 22 is greater than the width of each pixel unit 12 in the array corresponding to the second direction. That is, as... Figure 1 As shown, the projection of each pixel unit 12 falls completely within the projection area of ​​the overlapping first metal wiring layer 21 and second metal wiring layer 22 below it, so that the first metal wiring layer 21 and the second metal wiring layer 22 can completely cover each pixel unit 12 to form a reflector.

[0081] like Figure 2 As shown, the passive matrix MicroLED display device provided in the embodiments of this specification further includes a fourth passivation layer 44 and a bonding layer 52;

[0082] The fourth passivation layer 44 is deposited on the side of the second metal wiring layer 22 away from the pixel layer 10, and the bonding layer 52 is located between the fourth passivation layer 44 and the support substrate 51. The bonding layer 52 and the support substrate 51 constitute the support substrate 50.

[0083] The fourth passivation layer 44 can be obtained by deposition of inorganic materials such as SiO2, PSG, and BPSG, or by spin coating of organic materials such as polyimide and styrene-cyclobutene resin; preferably, the obtained fourth passivation layer 44 is subjected to mechanical and chemical polishing or planarization treatment.

[0084] The bonding layer 52 is used to connect the fourth passivation layer 44 and the support substrate 51. Specifically, bonding metals can be deposited on the surfaces of the epitaxial wafer (i.e., the display device intermediate after the fourth passivation layer is deposited) and the support substrate 51, respectively, and the support substrate 51 and the epitaxial wafer can be connected by hot-press bonding. Alternatively, bonding adhesive can be spin-coated on the surfaces of the epitaxial wafer and the support substrate 51, respectively, and the support substrate 51 and the epitaxial wafer can be connected by bonding adhesive. Alternatively, silicon oxide can be deposited on the surfaces of the epitaxial wafer and the support substrate 51, and both sides can be treated with isohydrophilicity to use van der Waals force bonds.

[0085] The supporting substrate 51 may be made of high thermal conductivity materials such as silicon, SiC, AlN or diamond.

[0086] In the embodiments of this specification, the passive matrix MicroLED display device further includes a fifth passivation layer 45, which is disposed on the top edge and side surface of the second doped semiconductor layer 17 of each pixel unit 12. The fifth passivation layer 45 cooperates with the first passivation layer 41 to isolate each pixel unit 12 from each other.

[0087] Preferably, such as Figure 2 As shown, the passive matrix MicroLED display device provided in the embodiments of this specification further includes a metal reflector 47 and a sixth passivation layer 46. The metal reflector 47 is disposed on the side of the fifth passivation layer 45 away from each pixel unit and located on the sidewall and top edge of the second doped semiconductor layer 17 of each pixel unit 12.

[0088] Specifically, the metal reflector 47 can be formed through a peeling process. The metal reflector 47 can efficiently reflect light that was originally directed toward the side of the pixel unit 12 back to the front light emission direction, thereby improving light extraction efficiency and luminous efficiency.

[0089] The sixth passivation layer 46 is located on the top and side surfaces of the second doped semiconductor layer of each pixel unit and on the periphery of the array, so as to passivate and protect each pixel unit 12, isolate water and oxygen, effectively suppress the aging rate of the pixel unit, and extend the service life of the device.

[0090] Preferably, the surface of the second doped semiconductor layer 17 exposed at the fifth passivation layer 45 of the pixel unit 12 is a rough surface.

[0091] Specifically, the fifth passivation layer 45 can be made of materials such as SiO2 and SiN and deposited on the surface of each pixel unit 12. Then, a photoresist mask can be formed using photolithography, and a portion of the fifth passivation layer 45 located in the central region of the top surface of each pixel unit 12 (i.e., retaining the portions located at the edges and sides of the top surface of each pixel unit 12) can be removed using plasma etching to allow light to pass through and form the passivation layer mask. The area on the surface of each pixel unit 12 where the fifth passivation layer 45 has been etched away (i.e., the top surface of the second doped semiconductor layer 17 at the central region of each pixel unit 12 where the fifth passivation layer 45 is exposed) is roughened to reduce surface reflection and improve the light extraction efficiency of the light-emitting device.

[0092] Furthermore, each bonded metal electrode 30 has an opening on its top surface that penetrates the first passivation layer 41 and the fifth passivation layer, i.e., the passivation layers deposited on the top surface of each bonded metal electrode 30 are etched away to expose at least a portion of the surface of the bonded metal electrode 30 so as to facilitate electrical connection with the drive circuit board 200.

[0093] like Figure 6 As shown in the figure, this specification also provides a passive matrix MicroLED chip, including a driver circuit board 200, a wafer adhesive 300, and a passive matrix MicroLED display device 100 provided by the above technical solution;

[0094] The wafer adhesive 300 is used to attach the passive matrix MicroLED display device 100 to the driving circuit board 200;

[0095] The driving circuit board 200 is provided with a driving circuit board wire bonding electrode 201, and the bonding metal electrode 30 of the passive matrix MicroLED display device 100 is electrically connected to the driving circuit board wire bonding electrode 201 through bonding leads 202.

[0096] The passive matrix MicroLED chip provided in the embodiments of this specification has a display device and a driving circuit board connected by wire bonding, which does not require alignment bonding. The process is simple and helps to improve product yield.

[0097] Furthermore, the pixel layer 10 of the passive matrix MicroLED display device is also coated with a color conversion layer 400. The color conversion layer 400 can be a phosphor layer and / or quantum dots.

[0098] To further illustrate the passive matrix MicroLED display device provided in the embodiments of this specification, the fabrication method of the display device is briefly described below.

[0099] The fabrication method of this passive matrix MicroLED display device may include the following steps (taking the AA'' direction of the passive matrix MicroLED display device as an example):

[0100] S100: The LED epitaxial wafer is etched to form several pixel units and a pixel via is formed at the center of each pixel unit.

[0101] The LED epitaxial wafer includes an epitaxial substrate 70, a second doped semiconductor layer 17, an active layer 16, and a first doped semiconductor layer 15 (e.g., ...) connected in sequence. Figure 7a (As shown). Specifically, the first doped semiconductor layer 15 can be a P-type semiconductor layer, and the second doped semiconductor layer 17 can be an N-type semiconductor layer. An ohmic contact layer 18 can also be provided on the side of the first doped semiconductor layer 15 away from the epitaxial substrate 70. The ohmic contact layer 18 can be formed by annealing transparent conductive oxides such as SnO2, ITO, and ZnO, and it is deposited on the first doped semiconductor layer 15 to form an ohmic contact with it.

[0102] Specifically, photolithography can be used to form a photoresist mask. Using the photoresist as a mask, the via area of ​​the pixel unit, the spacing area between different pixel units, and the ohmic contact layer of the area surrounding the array formed by the pixel units are etched away. Then, plasma etching is used to remove the first doped semiconductor layer 15, the active layer 16, and part of the second doped semiconductor layer 17 in the aforementioned areas. Finally, multiple pixel units 12 are formed and constitute a pixel array. The first doped semiconductor layer 15 and the active layer 16 between each pixel unit 12 in the array are electrically isolated from each other. Each pixel unit 12 includes a pixel via located in its central region.

[0103] S200: A first passivation layer is deposited on top of the ohmic contact layer, and multiple bonded metal electrodes are formed on the periphery of the array.

[0104] The bonding metal electrode 30 includes a plurality of first bonding electrodes 31 (e.g. Figure 7b As shown in the figure, the first bonding electrode 31 is electrically connected to a plurality of pixel units 12 in the array along the first direction, and the second bonding electrode 32 is electrically connected to a plurality of pixel units 12 in the array along the second direction.

[0105] The first passivation layer 41 can be prepared from one or more of SiO2, SiN, and Al2O3. The first passivation layer 41 covers each pixel unit 12 in the array to passivate each pixel unit 12; at the same time, it also covers the second doped semiconductor layer 17 on the periphery of the array to electrically isolate the second doped semiconductor layer 17 from the subsequent bonding electrode metal layer.

[0106] Specifically, the bonded metal electrode 30 can be prepared by metal stripping process from two or more of Ti / Cr / Al / Ni / Au / Pt (at least including Au), and the thickness of the bonded metal electrode is 100-500 nm.

[0107] S300: Deposit the second passivation layer and etch to obtain the first and second vias.

[0108] The second passivation layer 42 is located above the first passivation layer 41, and the second passivation layer 42 can be one or more of SiO2, SiN, and Al2O3. The first via 61 is obtained by etching away at least a portion of the first passivation layer 41 and at least a portion of the second passivation layer 42 in the peripheral region of each pixel unit 12 to expose the ohmic contact layer 18 on the surface of the pixel unit 12. The second via 62 is obtained by etching away at least a portion of the second passivation layer 42 on the surface of each bonding metal electrode 30 to expose the surface of the bonding metal electrode 30 (e.g., ...). Figure 7c (As shown).

[0109] Specifically, the first via 61 and the second via 62 can be formed by photolithography to create a photoresist mask and then obtained by plasma etching.

[0110] S400: Deposit a first metal wiring layer to cover the first via so that the first metal wiring layer is electrically connected to the first doped semiconductor layer of each pixel unit through the first via, and cover the second via so that the first metal wiring layer is electrically connected to the bonding metal electrode (e.g. Figure 7d (As shown).

[0111] The first metal wiring layer 21 is formed by metal stripping or etching processes, so that the first metal wiring layers 21 corresponding to different pixel unit rows in the array are electrically isolated from each other (e.g., Figure 5 (As shown). The first metal wiring layer 21 covers the first via 61, thereby electrically connecting to each pixel unit 12 in the corresponding row of the array (i.e., forming a first contact area 13 between the first metal wiring layer 21 and the first doped semiconductor layer 15 of the corresponding pixel unit 12). The first metal wiring layer 21 covers the second via 62, thereby connecting each pixel unit 12 in the row to the corresponding wire bonding electrode (i.e., the first bonding electrode 31). The size of the first metal wiring layer 21 is larger than the size of each pixel unit 12 to completely cover each pixel unit 12 to form a reflective mask. In the embodiments of this specification, the first metal wiring layer 21 may be made of one or more of Ti / Cr / Al / Ag / Ni / Pt. Preferably, the first metal wiring layer 21 is made of high reflectivity metals Al and / or Ag.

[0112] S500: Deposit the third passivation layer and etch to obtain the third and fourth vias.

[0113] The third passivation layer 43 can be made of one or more of SiO2, SiN, and Al2O3. It can be formed by photolithography to create a photoresist mask, followed by plasma etching to form the third via 63 and the fourth via 64. Figure 7e As shown, the third via 63 is obtained by etching away the third passivation layer 43, the second passivation layer 42 and the first passivation layer 41 in the central region of each pixel unit 12 to expose the second doped semiconductor layer 17 in the central region of each pixel unit 12; the fourth via 64 is obtained by etching away at least part of the third passivation layer 43 on the surface of each bonding metal electrode 30 to expose the surface of the bonding metal electrode 30.

[0114] S600: Deposit a second metal wiring layer to cover a third via so that the second metal wiring layer is electrically connected to the second doped semiconductor of each pixel unit through the second via, and cover a fourth via so that the second metal wiring layer is electrically connected to the bonding metal electrode.

[0115] Similarly, the second metal wiring layers corresponding to different pixel unit columns of the array are electrically isolated from each other (e.g., Figure 7f As shown, at the interval between two pixel units 12 included in this row, the second metal wiring layer 22 is disconnected to electrically isolate them from each other. The size of the second metal wiring layer 22 is larger than the size of each pixel unit 12 in its corresponding column, so as to completely cover each pixel unit 12 to form a reflector. The second metal wiring layer 22 covers the third via 63, thereby electrically connecting to each pixel unit 12 in the corresponding column of the array (i.e., forming a second contact area 14 between the second metal wiring layer 22 and the second doped semiconductor layer 17 of the corresponding pixel unit 12); the second metal wiring layer 22 covers the fourth via 64, thereby connecting each pixel unit 12 in this column to the corresponding wire bonding electrode (i.e., the second bonding electrode 32).

[0116] S700: After flipping the device, a fourth passivation layer 44 and a bonding layer 52 are deposited and connected to a support substrate (e.g., Figure 7g (As shown).

[0117] Specifically, an inorganic passivation material or an organic passivation material can be deposited to cover and fill the surface structure, and the passivation layer can be planarized using mechanical-chemical polishing to form a fourth passivation layer 44. The fourth passivation layer 44 can be made of inorganic materials such as SiO2, PSG, or BPSG, or of organic materials such as polyimide or styrene-cyclobutene resin. The supporting substrate 51 can be made of high thermal conductivity wafer materials such as silicon, SiC, AlN, or diamond.

[0118] S800: Surface processing of each pixel unit.

[0119] This involves processing the light-emitting surface of each pixel unit. This includes:

[0120] The epitaxial substrate is removed using wet etching, dry etching, or laser lift-off. A portion of the second doped semiconductor layer 17 is removed by plasma etching to thin it. A photoresist mask is formed using photolithography. The remaining second doped semiconductor layer between pixel units is removed by plasma etching, forming inter-pixel isolation (i.e., each pixel unit 12 is isolated from each other, such as...). Figure 7h (As shown).

[0121] A fifth passivation layer 45 is deposited and at least a portion of the passivation layer in the central region of the top surface of each pixel unit 12 is etched away to form a passivation layer mask; and the area on the surface of each pixel unit 12 where the fifth passivation layer 45 has been etched away is roughened (e.g., ...). Figure 7i (As shown). The fifth passivation layer 45 can be SiO2, SiN, etc. After photolithography to form a photoresist mask to remove at least part of the passivation layer, the formed passivation layer mask will be located on the sidewall and top edge of the second doped semiconductor layer 17 of each pixel unit 12. Specifically, alkaline solutions such as KOH, TAMH, NaOH, and NH4OH can be used for roughening treatment, and the surface particle size after roughening is 800nm-1um.

[0122] Metal reflectors 47 are formed on the sidewalls and top edges of the second doped semiconductor layer 17 of each pixel unit 12 using a stripping process (e.g., ...). Figure 7j (As shown).

[0123] A sixth passivation layer 46 is deposited to passivate and protect each pixel unit 12. The sixth passivation layer 46 can be one or more of SiO2, SiN, Al2O3, etc. The first passivation layer 41, the fifth passivation layer 45, and the sixth passivation layer 46 deposited on the surface of the bonded metal electrode are then removed (e.g., ...). Figure 7k As shown), to expose the surface of the bonding metal electrode to facilitate lead connection to the drive circuit board.

[0124] Thus, the passive matrix MicroLED display device provided in the embodiments of this specification can be obtained. Based on this, the diced MicroLED display device can be mounted onto the driving circuit board using conductive or non-conductive wafer adhesive, and then connected to the wire bonding electrodes of the driving circuit board via wire bonding leads, thereby fabricating a passive matrix MicroLED chip. The fabrication method provided in the embodiments of this specification is simple, easy to promote, and widely applicable. It should be noted that the above fabrication method is only one feasible method, and those skilled in the art can adjust it according to actual needs to obtain other methods different from the above-described method, and fabricate the same passive matrix MicroLED display device product as provided in the embodiments of this specification.

[0125] It should be noted that, in the embodiments of this specification, the use of the terms "comprising" or "including" to describe combinations of elements, components, parts, or steps herein also contemplates embodiments essentially composed of these elements, components, parts, or steps. The use of the term "may" herein is intended to indicate that any described attribute "may" include is optional. Multiple elements, components, parts, or steps can be provided by a single integrated element, component, part, or step. Alternatively, a single integrated element, component, part, or step can be divided into multiple separate elements, components, parts, or steps. The use of "a" or "an" to describe an element, component, part, or step does not imply exclusion of other elements, components, parts, or steps.

[0126] The various embodiments described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from the others. Similar or identical parts between embodiments can be referred to interchangeably. The above embodiments are only for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made according to the spirit and essence of the present invention should be included within the scope of protection of the present invention.

Claims

1. A passive matrix MicroLED display device, characterized in that, include: Support substrate; A pixel layer, disposed on the support substrate, includes multiple pixel units arranged in an array; Multiple first metal wiring layers are disposed between the support substrate and the pixel layer to correspondingly connect multiple pixel units in the array along the first direction, and adjacent first metal wiring layers are electrically isolated from each other. Multiple second metal wiring layers are disposed between the first metal wiring layer and the support substrate for correspondingly connecting multiple pixel units in the array along the second direction, and adjacent two second metal wiring layers are electrically isolated from each other. The bonding metal electrodes are disposed on the periphery of the array and include multiple first bonding electrodes and multiple second bonding electrodes. The first bonding electrodes are electrically connected to the first metal wiring layer, and the second bonding electrodes are electrically connected to the second metal wiring layer.

2. The passive matrix MicroLED display device according to claim 1, characterized in that, Each pixel unit includes at least a first doped semiconductor layer, an active layer, and a second doped semiconductor layer connected in sequence, wherein the second doped semiconductor layer is located on the side of the active layer away from the supporting substrate; The first metal wiring layer is electrically connected to the first doped semiconductor layer of each pixel unit in the array along the first direction; The second metal wiring layer is electrically connected to the second doped semiconductor layer of each pixel unit in the array along the second direction.

3. The passive matrix MicroLED display device according to claim 2, characterized in that, The first metal wiring layer forms a first contact area with the first doped semiconductor layer of the corresponding pixel unit; The second metal wiring layer forms a second contact area with the second doped semiconductor layer of the corresponding pixel unit; The first contact area and the second contact area are electrically isolated from each other.

4. The passive matrix MicroLED display device according to claim 3, characterized in that, The second contact area is located in the central region of the pixel unit, and the first contact area is located on the periphery of the central region; Multiple first contact areas are provided, and the first contact areas are evenly distributed around the second contact area.

5. The passive matrix MicroLED display device according to claim 3, characterized in that, It also includes a first passivation layer, which is disposed on the side of the pixel layer facing the support substrate and on the periphery of the array; The first passivation layer is provided with a through-hole; The first metal wiring layer is electrically connected to the first doped semiconductor layer of the corresponding pixel unit through the first via, forming each first contact area.

6. The passive matrix MicroLED display device according to claim 5, characterized in that, The bonding metal electrode is disposed on the side of the first passivation layer facing the supporting substrate; A second via is provided on the side of the first bonding electrode facing the supporting substrate, and the first metal wiring layer is electrically connected to the corresponding first bonding electrode through the second via.

7. The passive matrix MicroLED display device according to claim 5, characterized in that, It also includes a third passivation layer, which is disposed between the first metal wiring layer and the second metal wiring layer; The first metal wiring layer is provided with a through-hole; The first passivation layer and the third passivation layer are provided with a through third via, and the second metal wiring layer is electrically connected to the second doped semiconductor of the corresponding pixel unit through the third via and the clearance hole to form the second contact area.

8. The passive matrix MicroLED display device according to claim 7, characterized in that, A fourth via is provided on the side of the second bonding electrode facing the support substrate, and the second metal wiring layer is electrically connected to the corresponding second bonding electrode through the fourth via.

9. The passive matrix MicroLED display device according to claim 5, characterized in that, An ohmic contact layer is provided between the first doped semiconductor layer and the first metal wiring layer, and / or between the second doped semiconductor layer and the second metal wiring layer.

10. The passive matrix MicroLED display device according to claim 1, characterized in that, The width of the first metal wiring layer is greater than the size of each pixel unit in the array along the first direction, and the width of the second metal wiring layer is greater than the size of each pixel unit in the array along the second direction.

11. The passive matrix MicroLED display device according to claim 1, characterized in that, It also includes a fourth passivation layer and a bonding layer; The fourth passivation layer is disposed on the side of the second metal wiring layer away from the pixel layer, and the bonding layer is located between the fourth passivation layer and the supporting substrate.

12. The passive matrix MicroLED display device according to claim 6, characterized in that, It also includes a fifth passivation layer; The fifth passivation layer is disposed on the top edge and side surface of the second doped semiconductor layer of each pixel unit; the fifth passivation layer cooperates with the first passivation layer to isolate each pixel unit from each other.

13. The passive matrix MicroLED display device according to claim 12, characterized in that, It also includes a metal reflector and a sixth passivation layer; The metal reflector is disposed on the side of the fifth passivation layer away from each pixel unit and located at the top edge and side of the second doped semiconductor layer of each pixel unit; The sixth passivation layer is located on the top and side surfaces of the second doped semiconductor layer of each pixel unit and on the periphery of the array.

14. The passive matrix MicroLED display device according to claim 13, characterized in that, The second doped semiconductor surface of the pixel unit exposed at the fifth passivation layer is a rough surface.

15. The passive matrix MicroLED display device according to claim 14, characterized in that, The top surface of the bonded metal electrode is provided with an opening that penetrates the first passivation layer, the fifth passivation layer, and the sixth passivation layer.

16. A passive matrix MicroLED chip, characterized in that, Includes a driver circuit board, a wafer adhesive, and a passive matrix MicroLED display device as described in any one of claims 1 to 15; The wafer adhesive is used to attach the passive matrix MicroLED display device to the driving circuit board; The driving circuit board is provided with a wire bonding electrode, and the bonding metal electrode of the passive matrix MicroLED display device is electrically connected to the wire bonding electrode of the driving circuit board through bonding leads.

17. The passive matrix MicroLED chip according to claim 16, characterized in that, The pixel layer surface of the passive matrix MicroLED display device is also coated with a color conversion layer.

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