Indium oxide / indium gallium tin oxide dual channel layer thin film transistor and preparation method thereof

Abstract

This invention proposes an indium oxide / indium gallium tin oxide (IGa Tin) dual-channel thin-film transistor and its fabrication method. The specific fabrication method involves using heavily doped p-type silicon and silicon dioxide as the gate and insulating layers, respectively, as the substrate. First, an ultrathin layer of indium oxide is grown on the substrate using radio frequency magnetron sputtering. Then, a thicker layer of IGa Tin oxide is grown using radio frequency magnetron sputtering. Next, aluminum is grown as the metal electrode using DC magnetron sputtering. Finally, aluminum oxide is used as the passivation layer. All deposition layers are patterned using a mask to fabricate the IGa Tin / indium gallium tin oxide dual-channel thin-film transistor. This invention utilizes the highly conductive ultrathin layer of indium oxide to provide carrier concentration and the thicker IGa Tin oxide film to regulate the carrier transport characteristics of the device. The thin-film transistor of this invention exhibits advantages such as high mobility, low threshold voltage, and low subthreshold swing. It also possesses advantages such as good electrical stability, high on / off current ratio, and simple fabrication method.

Description

Technical Field

[0001] This invention belongs to the field of thin film materials and thin film devices, specifically relating to an indium oxide / indium gallium tin oxide dual-channel thin film transistor and its fabrication method. Background Technology

[0002] In recent years, the display field has seen continuous development, including virtual displays, foldable screens, wearable screens, and microcomputers. This marks humanity's entry into the information age. Flat panel displays have made significant progress, with more and more information being accessed through screens. Everyday devices such as mobile phones, tablets, and televisions all utilize flat panel displays. Currently, flat panel displays are developing towards higher resolution, thinner and lighter designs, greater flexibility, and energy efficiency. Thin-film transistors (TFTs), as the core component of the driving circuitry in flat panel displays, directly affect the quality of the display due to their electrical performance.

[0003] Traditional hydrogenated amorphous thin-film transistor (TFT) technology is a widely adopted mainstream technology, with significant advantages including high technological maturity, a yield rate of 97% to 99%, and relatively low cost. However, a major challenge facing this technology is its low carrier mobility, a deficiency that limits its application in high-definition large-screen displays, primarily confining it to small-scale display products. Compared to hydrogenated amorphous TFTs, polycrystalline silicon TFTs have emerged in recent years, characterized by their high carrier mobility. Unfortunately, polycrystalline silicon TFTs suffer from high fabrication temperatures, complex manufacturing processes, high costs, and poor uniformity of mobility distribution due to grain boundary effects. These shortcomings hinder their large-scale application. Furthermore, both hydrogenated amorphous and polycrystalline silicon TFTs have low transmittance in the visible light region and lack flexibility, further restricting the development of transparent and flexible display technologies. To address these challenges, researchers have developed organic thin-film transistors (OTCs), a technology that has received considerable attention and application in recent years. Organic thin-film transistors (TFTs) have become a research hotspot due to their advantages such as high mobility, flexibility, large-area production capability, and simple fabrication process. However, compared to other types of TFTs, organic TFTs do not exhibit significant superiority. More importantly, some organic materials are sensitive to water and oxygen in the air, and their performance gradually degrades with prolonged exposure. The aforementioned TFT devices all have insurmountable drawbacks in various aspects. To meet the current demands for high resolution, thinness, flexibility, and energy efficiency, semiconductor materials that simultaneously possess high mobility, simple fabrication, good uniformity, and high visible light transmittance are needed as the channel layer of TFT devices. InGaSnO, as an amorphous metal oxide material, not only has a large bandgap (4.2 eV) but also high carrier mobility. This is because In... 3+ and Sn4+ With special 4D 10 5s 0 The outer electron orbitals, with their spherical symmetry, can overlap over a large area even in the amorphous state, forming pathways for carrier transport and maintaining high carrier mobility. Furthermore, they are easily and uniformly deposited on large-area substrates at relatively low processing temperatures. Dual-channel thin-film transistors can effectively control carrier concentration, thereby increasing mobility and threshold voltage. Simultaneously, the bonding of interstitial indium and tin ions reduces the formation energy of oxygen vacancies, further increasing carrier concentration. Therefore, the rational design of dual-channel layer processes is crucial for enhancing the electrical performance and stability of InGaSnO-based thin-film transistors, and is of great significance for their commercial application. Summary of the Invention

[0004] The core objective of this invention is to overcome the limitations and defects in the current technology, and to propose an indium oxide / indium gallium tin oxide dual-channel thin-film transistor with a simple fabrication process, high carrier mobility and good stability, while also providing its fabrication process.

[0005] The specific solution of the present invention is as follows:

[0006] An indium oxide / indium gallium tin oxide dual-channel thin-film transistor. A schematic diagram and electron microscopy characterization of the indium oxide / indium gallium tin oxide thin-film transistor are shown below. Figure 1 , 2 As shown, it consists of a passivation layer, source / drain electrodes, a dual-channel layer, an insulating layer, and a gate. The passivation layer is made of aluminum oxide with a thickness of 30–50 nm; the source / drain electrode material is 40–60 nm of metallic aluminum; the dual-channel layer consists of an ultrathin indium oxide layer (4–10 nm is optimal) and a thick indium gallium tin oxide layer (15–30 nm is optimal); the insulating layer is 90–110 nm of silicon dioxide; and the p-type heavily doped silicon serves as both the substrate and the gate.

[0007] The fabrication method of the indium oxide / indium gallium tin oxide dual-channel thin-film transistor is as follows: an ultrathin layer of indium oxide and a thick layer of indium gallium tin oxide are deposited using radio frequency magnetron sputtering; then, aluminum electrodes are deposited using DC radio frequency sputtering; finally, aluminum oxide is deposited as a passivation layer using electron beam evaporation. The specific steps are as follows:

[0008] (1) Using P-type heavily doped silicon and silicon dioxide grown on it as a substrate, radio frequency magnetron sputtering is performed on it using pure indium oxide target, and patterning is performed using a mask.

[0009] (2) Continue to use an indium gallium tin oxide ceramic target to perform radio frequency sputtering deposition of a thick indium gallium tin oxide layer in step (1).

[0010] (3) In step (2), a metal aluminum electrode is sputtered using DC magnetron sputtering and patterned using a mask. This yields an indium oxide / indium gallium tin oxide dual-channel thin-film transistor.

[0011] (4) Electron beam evaporation is used in step (3) to deposit aluminum oxide as an indium oxide / indium gallium tin oxide dual-channel thin film transistor.

[0012] The thickness of the silicon dioxide mentioned in step (1) is preferably 90-110 nm.

[0013] The preferred conditions for radio frequency magnetron sputtering in step (1) are: sputtering atmosphere is argon, sputtering pressure is 0.5-0.8 Pa, sputtering power is 30-60 W, and substrate temperature is 25-100 °C.

[0014] The preferred conditions for radio frequency magnetron sputtering in step (2) are: the sputtering atmosphere is an argon-oxygen mixture with a mixing ratio of 20:8; the sputtering pressure is 0.8–1.2 Pa; the sputtering power is 30–60 W; and the substrate temperature is 25–100 °C.

[0015] The conditions for DC sputtering in step (3) are: the sputtering carrier gas is pure argon, the sputtering pressure is 0.8 to 1.2 Pa, and the power is 40 to 60 W.

[0016] In step (4), the thickness of the alumina protective layer is preferably 30-50 nm.

[0017] Compared with the prior art, the present invention has the following advantages and benefits:

[0018] (1) The indium oxide / indium gallium tin oxide dual-channel thin-film transistor of the present invention increases the carrier concentration and improves the mobility by forming a quasi-two-dimensional electron gas at the heterojunction interface through the formation of a heterojunction. Since indium oxide has fewer defects, the defect state density can be improved.

[0019] (2) The process for fabricating indium oxide / indium gallium tin oxide dual-channel thin-film transistors according to this invention is simple, requires a low fabrication temperature, and allows for adjustment of the threshold voltage. This enables the device to have a lower threshold voltage, thereby reducing power consumption. Simultaneously, the combination of interstitial indium and tin elements reduces the formation energy of oxygen vacancies, thus increasing the carrier concentration at the heterojunction. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the structure of the indium oxide / indium gallium tin oxide dual-channel thin-film transistor of the present invention: wherein, 1 is a passivation layer, 2 is an aluminum metal source / drain electrode, 3 is an indium gallium tin oxide channel layer, 4 is an indium oxide channel layer, 5 is a silicon dioxide insulating layer, and 6 is a gate P-type heavily doped silicon.

[0021] Figure 2This is a high-resolution electron microscope image of an indium oxide / indium gallium tin oxide dual-channel thin-film transistor.

[0022] Figure 3 The graph shows the electrical transfer characteristics of the monolayer indium oxide thin-film transistor, the monolayer indium gallium tin oxide thin-film transistor, and the indium oxide / indium gallium tin oxide dual-channel thin-film transistor fabricated in Examples 1, 2, and 3. The left vertical axis represents the relationship between source and drain currents under gate voltage, and the right vertical axis represents the relationship between mobility under different gate voltages.

[0023] Figure 4 These are the electrical output characteristics of the monolayer indium oxide thin-film transistor, the monolayer indium gallium tin oxide thin-film transistor, and the indium oxide / indium gallium tin oxide dual-channel thin-film transistor fabricated in Examples 1, 2, and 3.

[0024] Figure 5 This is a schematic diagram of carrier flow in the indium oxide / indium gallium tin oxide dual-channel thin-film transistor prepared in Example 3 at zero gate voltage and above the threshold voltage.

[0025] Figure 6 The graph shows the transfer curves of dual-channel thin-film transistors with different indium oxide thicknesses (0-10 nm) and indium gallium tin oxide (20 nm) prepared in Example 4.

[0026] Figure 7 The figures show the hysteresis curve and leakage current of the indium gallium tin oxide thin-film transistor prepared in Example 2.

[0027] Figure 8 The figures show the hysteresis curve and leakage current of the indium oxide / indium gallium tin oxide dual-channel thin-film transistor prepared in Example 3.

[0028] Figure 9 This is an evolution diagram of the electrical transfer characteristic curve of the indium oxide / indium gallium tin oxide dual-channel thin film transistor prepared in Example 5 under atmospheric conditions with negative bias voltage (-20V) stress stability test; "←" indicates that when a negative bias voltage is applied, the electrical transfer characteristic curve of the thin film transistor shifts from the left (100s) to the left (3600s).

[0029] Figure 10 This is an evolution diagram of the electrical transfer characteristic curve of the indium oxide / indium gallium tin oxide dual-channel thin film transistor prepared in Example 5 under atmospheric conditions with positive bias voltage (20V) stress stability test; "→" indicates that when a positive bias voltage is applied, the electrical transfer characteristic curve of the thin film transistor shifts from the left (100s) to the right (3600s).

[0030] Figure 11This is an evolution diagram of the electrical transfer characteristic curve of the indium oxide / indium gallium tin oxide dual-channel thin film transistor prepared in step 5 under atmospheric conditions with negative bias voltage (-20V) light stress stability test; "←" indicates that when negative bias voltage light is applied, the electrical transfer characteristic curve of the thin film transistor shifts from the left (100s) to the right (3600s).

[0031] Figure 12 This is an evolution diagram of the electrical transfer characteristic curve of the indium oxide / indium gallium tin oxide dual-channel thin film transistor prepared in Example 5 under atmospheric conditions with positive bias (20V) light stress stability test; "→" indicates that when positive bias light is applied, the electrical transfer characteristic curve of the thin film transistor shifts from the left (100s) to the left (3600s). Detailed Implementation

[0032] The present invention will be further described in detail below with reference to examples, but the implementation methods of the present invention include, but are not limited to, these examples.

[0033] Example 1

[0034] (1) A heavily doped P-type silicon wafer with 100 nm silicon dioxide was cleaned with acetone and deionized water, dried with nitrogen, and then a pure indium oxide (30 nm) thin film was deposited on it and patterned with a mask. The sputtering temperature was 100 °C, the gas pressure was 1 Pa, the sputtering atmosphere was pure argon, and the sputtering power was 40 W.

[0035] (2) Based on (1), a 50 nm aluminum electrode was sputtered at room temperature using DC RF at a power of 50 W. The sputtering atmosphere was pure argon and the sputtering pressure was 1 Pa. A single-layer indium oxide thin film transistor was finally obtained.

[0036] Example 2

[0037] (1) A heavily doped P-type silicon wafer with 100 nm silicon dioxide was cleaned with acetone and deionized water, dried with nitrogen, and then an indium gallium tin oxide (30 nm) thin film was deposited on it and patterned with a mask. The sputtering temperature was 100 °C, the gas pressure was 1 Pa, the sputtering atmosphere was a mixture of argon and oxygen, and the sputtering power was 45 W.

[0038] (2) Based on (1), a 50nm aluminum electrode was sputtered at room temperature using DC RF at a power of 50W. The sputtering atmosphere was pure argon and the sputtering pressure was 1Pa. A single-layer indium gallium tin oxide thin film transistor was finally obtained.

[0039] Example 3

[0040] (1) A heavily doped P-type silicon wafer with 100 nm silicon dioxide was cleaned with acetone and deionized water, dried with nitrogen, and then a pure indium oxide (30 nm) thin film was deposited on it and patterned with a mask. The sputtering temperature was 100 °C, the gas pressure was 1 Pa, the sputtering atmosphere was pure argon, and the sputtering power was 40 W.

[0041] (2) Based on (1), radio frequency magnetron sputtering of indium gallium tin oxide thin film was used. The sputtering temperature was 100℃, the gas pressure was 1Pa, the sputtering atmosphere was a mixture of argon and oxygen, and the sputtering power was 45W.

[0042] (3) Based on (2), a 50nm aluminum electrode was sputtered at room temperature using DC RF at a power of 50W. The sputtering atmosphere was pure argon and the sputtering pressure was 1Pa. Finally, an indium oxide / indium gallium tin oxide dual-channel thin-film transistor was obtained.

[0043] The electrical transfer characteristic curves and electrical output characteristic curves of the thin-film transistors fabricated in Examples 1, 2, and 3 are shown below. Figure 3 and 4 As shown. By Figure 3 and 4 It is evident that the indium oxide / indium gallium tin oxide dual-channel thin-film transistor prepared according to the method of this invention exhibits a field-effect mobility of up to 43.6 cm⁻¹. 2 / V·s, switching current ratio higher than 10 10 The high-performance thin-film transistor with a threshold voltage of 1.2V and a subthreshold swing of less than 250mV / decade exhibits superior electrical performance. This indicates that the electrical performance of the hydrogen passivated zinc oxide-based dual-channel thin-film transistor is significantly improved compared to the original thin films in Examples 1 and 2.

[0044] Example 4

[0045] (1) A heavily doped P-type silicon wafer with 100 nm silicon dioxide was cleaned with acetone and deionized water, dried with nitrogen, and then a pure indium oxide (4-10 nm) thin film was deposited on it and patterned with a mask. The sputtering temperature was 100 °C, the gas pressure was 1 Pa, the sputtering atmosphere was pure argon, and the sputtering power was 40 W.

[0046] (2) Based on (1), radio frequency magnetron sputtering of indium gallium tin oxide thin film was used. The sputtering temperature was 100℃, the gas pressure was 1Pa, the sputtering atmosphere was a mixture of argon and oxygen, and the sputtering power was 45W.

[0047] (3) Based on (2), a 50 nm aluminum electrode was sputtered at room temperature using DC RF at a power of 50 W. The sputtering atmosphere was pure argon and the sputtering pressure was 1 Pa. Finally, indium oxide / indium gallium tin oxide dual-channel thin-film transistors of different thicknesses were obtained.

[0048] The electrical transfer characteristic curves of the thin-film transistor fabricated in Example 4 are shown below. Figure 6 As shown. By Figure 6 It is evident that with increasing indium oxide (IO) film thickness, the thin-film transistor's mobility increases, while the threshold voltage becomes negatively biased and the subthreshold swing deteriorates. The IO / IGaTi dual-channel thin-film transistor exhibits optimal electrical performance when the IO film thickness is 4 nm.

[0049] Example 5

[0050] (1) A heavily doped P-type silicon wafer with 100 nm silicon dioxide was cleaned with acetone and deionized water, dried with nitrogen, and then a pure indium oxide (30 nm) thin film was deposited on it and patterned with a mask. The sputtering temperature was 100 °C, the gas pressure was 1 Pa, the sputtering atmosphere was pure argon, and the sputtering power was 40 W.

[0051] (2) Based on (1), radio frequency magnetron sputtering of indium gallium tin oxide thin film was used. The sputtering temperature was 100℃, the gas pressure was 1Pa, the sputtering atmosphere was a mixture of argon and oxygen, and the sputtering power was 45W.

[0052] (3) Based on (2), a 50nm aluminum electrode was sputtered at room temperature using DC RF at a power of 50W. The sputtering atmosphere was pure argon and the sputtering pressure was 1Pa. Finally, a single-layer indium oxide thin film transistor was obtained.

[0053] (4) Based on (3), a 40 nm aluminum oxide passivation layer is deposited at room temperature by electron beam evaporation and annealed at 250 °C in air for 10 minutes to obtain an indium oxide / indium gallium tin oxide dual-channel thin film transistor with an aluminum oxide passivation layer.

[0054] The indium oxide / indium gallium tin oxide dual-channel thin-film transistor with an alumina passivation layer prepared in Example 5 underwent positive / negative bias stability testing and positive / negative bias illumination stability testing in an atmospheric environment. The transfer curves are shown below. Figure 9 , 10 As shown in Figures 11 and 12, the results demonstrate that after 1 hour of positive / negative bias stress and positive / negative bias illumination stress, the indium oxide / indium gallium tin oxide (IGaTi) thin-film dual-channel layer thin-film transistor exhibits good stability, with a threshold voltage less than 1V. Furthermore, the high carrier concentration indium oxide layer possesses a large number of oxygen vacancy states, which affects the stability of the IGaTi / indium gallium tin oxide (IGaTi) thin-film dual-channel layer thin-film transistor. The excellent electrical performance and stability exhibited indicate that the IGaTi / indium gallium tin oxide (IGaTi) thin-film dual-channel layer thin-film transistor of this invention has good application prospects.

[0055] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. An indium oxide / indium gallium tin oxide dual-channel thin-film transistor, characterized in that: A thin-film transistor with indium oxide as an ultrathin layer and indium gallium tin oxide as a thick layer as a dual-channel layer; the thickness of the indium oxide ultrathin layer is 4-10 nm, and the thickness of the indium gallium tin oxide thick layer is 15-30 nm.

2. The indium oxide / indium gallium tin oxide dual-channel thin-film transistor according to claim 1, characterized in that: Includes substrate, gate, insulating layer, dual-channel layer, source / drain electrodes, and passivation layer; In this case, the P-type heavily doped silicon wafer serves as both the substrate and the gate. A layer of silicon dioxide is grown on the silicon wafer as an insulating layer; The dual-channel layer consists of an ultrathin indium oxide layer and a thick indium gallium tin oxide layer; Aluminum is used as the source and drain electrode material; Aluminum oxide serves as the passivation layer.

3. The indium oxide / indium gallium tin oxide dual-channel thin-film transistor according to claim 2, characterized in that: The thickness of the silicon dioxide insulating layer is 90–110 nm.

4. The indium oxide / indium gallium tin oxide dual-channel thin-film transistor according to claim 2, characterized in that: The thickness of the passivation layer is 30–50 nm.

5. The method for fabricating the indium oxide / indium gallium tin oxide dual-channel thin-film transistor according to claim 1, characterized in that... Includes the following steps: (1) Using heavily doped P-type silicon and silicon oxide grown on it as substrates, patterning is first performed using a mask, and then pure indium oxide ultrathin layer is deposited using radio frequency magnetron sputtering with pure indium oxide as the target material. (2) The pure indium oxide prepared in step (1) is further deposited by radio frequency magnetron sputtering of a thick layer of indium gallium tin oxide; (3) Aluminum electrodes are deposited on the indium oxide ultrathin layer and indium gallium tin oxide thick layer prepared in step (2) by DC magnetron sputtering and patterned by a mask to obtain an indium oxide / indium gallium tin oxide dual-channel thin film transistor.

6. The method for fabricating an indium oxide / indium gallium tin oxide dual-channel thin-film transistor according to claim 5, characterized in that: After obtaining the indium oxide / indium gallium tin oxide dual-channel thin-film transistor, aluminum oxide is deposited as its passivation layer by electron beam evaporation.

7. The method for fabricating an indium oxide / indium gallium tin oxide dual-channel thin-film transistor according to claim 5, characterized in that: The conditions for radio frequency magnetron sputtering in step (1) are: the sputtering atmosphere is pure argon, the sputtering pressure is 0.5 to 0.8 Pa, the sputtering power is 30 to 60 W, and the substrate temperature is 25 to 100 °C.

8. The method for fabricating an indium oxide / indium gallium tin oxide dual-channel thin-film transistor according to claim 5, characterized in that: The conditions for radio frequency magnetron sputtering described in step (2) are as follows: the sputtering atmosphere is a mixture of argon and oxygen with a gas flow ratio of 12:

8. The sputtering pressure is 0.8–1.2 Pa, the sputtering power is 30–60 W, and the substrate temperature is 25–100 °C.

9. The method for fabricating an indium oxide / indium gallium tin oxide dual-channel thin-film transistor according to claim 5, characterized in that: The DC sputtering conditions described in step (3) are: the sputtering atmosphere is argon, the sputtering pressure is 0.8 to 1.2 Pa, and the power is 40 to 60 W.

10. The method for fabricating a hydrogen passivated zinc oxide-based dual-channel thin-film transistor according to claim 6, characterized in that: The thickness of the alumina protective layer is 30–50 nm.

Images