Electronic device

Abstract

An electronic device can include signal lines and pads. Each of the pads can include a first lower conductive pattern on a base layer, a first insulating pattern with a contact hole defined therethrough to expose a portion of the first lower conductive pattern, the first insulating pattern covering the first lower conductive pattern, a second lower conductive pattern including a first portion covering the first portion of the first lower conductive pattern exposed through the contact hole and a second portion extending from a side surface of the first insulating pattern defining the contact hole, and the second portion covering an upper surface of the first insulating pattern, a second-first insulating pattern on the first portion, a first upper conductive pattern on the second-first insulating pattern, and a second upper conductive pattern on the first upper conductive pattern and in contact with the first upper conductive pattern.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0177292, filed with the Korean Intellectual Property Office on December 3, 2024, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] One or more embodiments of this disclosure relate to electronic devices. For example, one or more embodiments of this disclosure relate to electronic devices including solder pads. Background Technology

[0003] Various electronic devices are being developed for use in multimedia devices such as televisions, mobile phones, tablet computers, navigation devices, and / or gaming devices. These electronic devices comprise multiple electronic components. These components include display panels, driver chips, and / or circuit boards, etc. The electronic components are electrically connected in one or more suitable ways. Summary of the Invention

[0004] One or more aspects of the embodiments of this disclosure relate to an electronic device that has improved or enhanced electrical bonding reliability and reduces defects in the pads of the pad portion of the electronic device.

[0005] Additional aspects of the embodiments will be set forth in part in the description which follows, and will be apparent in part from the description, or may be learned by practicing the embodiments presented in this disclosure.

[0006] One or more embodiments of this disclosure provide an electronic device including a substrate, a pixel located on the substrate, a signal line electrically connected to the pixel, and a pad connected to the signal line.

[0007] Each of the pads includes: a first lower conductive (e.g., electrically conductive) pattern disposed on a substrate layer; a first insulating (e.g., electrically insulating) pattern, wherein a contact hole is defined through the first insulating pattern to expose a portion of the first lower conductive pattern, the first insulating pattern covering the first lower conductive pattern; a second lower conductive (e.g., electrically conductive) pattern including a first portion covering the first lower conductive pattern exposed through the contact hole and a second portion extending from the side surface of the first insulating pattern defining the contact hole, the second portion covering the upper surface of the first insulating pattern; a second-first insulating (e.g., electrically insulating) pattern disposed on the first portion; a first upper conductive (e.g., electrically conductive) pattern disposed on the second-first insulating pattern; and a second upper conductive (e.g., electrically conductive) pattern disposed on and in contact with the first upper conductive pattern.

[0008] The first conductive pattern may not be in contact with the first part, but may be in contact with the second part.

[0009] When viewed (e.g., in a planar view), the contact hole may overlap with the first lower conductive pattern.

[0010] When viewed in a plane (e.g., in a planar diagram), the second upper conductive pattern may have a larger area than the first upper conductive pattern.

[0011] Each edge of the second upper conductive pattern may be separated from and / or isolated from the edge of the first insulating pattern (e.g., spaced apart or separated), and may be arranged between the edge of the first insulating pattern and the edge of the second-first insulating pattern.

[0012] The first upper conductive pattern may be separated from and / or isolated from the first lower conductive pattern (e.g., spaced apart or separated).

[0013] At least a portion of the second-first insulating pattern may be arranged inside the contact hole.

[0014] The distance between the uppermost part of the second lower conductive pattern and the first lower conductive pattern can be greater than the distance between the upper surface of the second-first insulating pattern and the first lower conductive pattern.

[0015] The electronic device may further include a second-second insulation (e.g., electrical insulation) pattern disposed on the first insulation pattern and spaced apart from and / or separated from the second-first insulation pattern (e.g., spaced apart or separated).

[0016] The second insulating pattern can cover the second conductive pattern.

[0017] Each of the first upper conductive pattern and the second upper conductive pattern may include a first layer containing titanium, a second layer containing aluminum, and a third layer containing titanium, wherein the first, second, and third layers are stacked sequentially in a direction away from the first lower conductive pattern.

[0018] The electronic device may further include: a circuit board that applies electrical signals to the pixels, and includes bumps connected to the second upper conductive pattern and the first upper conductive pattern.

[0019] The electronic device may further include an input sensing layer disposed on a substrate layer. The input sensing layer may include: a first sensing insulating (e.g., electrically insulating) layer, a second sensing insulating (e.g., electrically insulating) layer, and a third sensing insulating (e.g., electrically insulating) layer, stacked sequentially in a direction away from the first lower conductive pattern; a first sensing conductive (e.g., electrically conductive) layer disposed between the first sensing insulating layer and the second sensing insulating layer; and a second sensing conductive (e.g., electrically conductive) layer disposed between the second sensing insulating layer and the third sensing insulating layer.

[0020] Each of the pads may further include a third upper conductive (e.g., electrically conductive) pattern, comprising substantially the same material as one of the first sensing conductive layer and the second sensing conductive layer.

[0021] One or more embodiments of this disclosure provide an electronic device including a substrate, pixels disposed on the substrate, signal lines electrically connected to the pixels, and pads connected to the signal lines. Each of the pads includes: a first lower conductive (e.g., electrically conductive) pattern disposed on the substrate; a first insulating (e.g., electrically insulating) pattern having a plurality of contact holes defined through the first insulating pattern to expose the first lower conductive pattern, the contact holes being spaced apart and / or separated (e.g., spaced apart or separated), and the first insulating pattern covering the first lower conductive pattern; a second lower conductive (e.g., electrically conductive) pattern including a plurality of first portions covering the first lower conductive pattern exposed through the contact holes and a plurality of second portions extending from the side surfaces of the first insulating pattern defining the contact holes, and the second portions covering the upper surface of the first insulating pattern; a plurality of second-first insulating (e.g., electrically insulating) patterns disposed on the first portions; a first upper conductive (e.g., electrically conductive) pattern disposed on the second-first insulating pattern and the second lower conductive pattern; and a second upper conductive (e.g., electrically conductive) pattern disposed on and in contact with the first upper conductive pattern.

[0022] The second-first insulating patterns can be arranged in contact holes adjacent to each other and have a shape extending in one direction when viewed in a plane (e.g., in a plan view).

[0023] The first conductive pattern may not be in contact with the first part, but may be in contact with the second part.

[0024] The electronic device may further include: a second-second insulating (e.g., electrical insulating) pattern disposed on the first insulating pattern and spaced apart from and / or separated from the second-first insulating pattern (e.g., spaced apart or separated), and the second-second insulating pattern may cover the second lower conductive pattern.

[0025] The electronic device may further include an input sensing layer disposed on a substrate layer. The input sensing layer may include: a first sensing insulating (e.g., electrically insulating) layer, a second sensing insulating (e.g., electrically insulating) layer, and a third sensing insulating (e.g., electrically insulating) layer, stacked sequentially in a direction away from a first lower conductive pattern; a first sensing conductive (e.g., electrically conductive) layer, located between the first sensing insulating layer and the second sensing insulating layer; and a second sensing conductive (e.g., electrically conductive) layer, located between the second sensing insulating layer and the third sensing insulating layer, and each of the pads may further include: a third upper conductive (e.g., electrically conductive) pattern, comprising substantially the same material as one selected from the first sensing conductive layer and the second sensing conductive layer.

[0026] Each of the second-first insulating patterns may include: a second-first insulating (e.g., electrically insulating) portion disposed on the first portion, at least a portion of the second-first insulating portion being disposed inside the contact hole; and a second-second insulating (e.g., electrically insulating) portion extending from the second-first insulating portion and protruding beyond the upper surface of the second portion, and the third upper conductive pattern may include a protruding portion that protrudes in a direction away from the first lower conductive pattern and overlaps with the second-second insulating portion.

[0027] In one or more embodiments, electronic devices with improved or enhanced electrical reliability can be provided. Improved electrical reliability ensures that the electronic device maintains stable and consistent performance over time, thereby reducing the likelihood of electrical failures and improving the overall user experience.

[0028] In one or more embodiments, peeling or separation of a portion of the conductive pattern caused by bending occurring in the conductive pattern included in the pads can be prevented (or the degree or incidence of peeling or separation of a portion of the conductive pattern caused by bending occurring in the conductive pattern included in the pads can be reduced). Reduction in peeling or separation helps maintain the integrity of electrical connections within the electronic device, thereby improving its durability and lifespan. By addressing these issues, electronic devices can achieve higher standards of reliability and performance, making them more reliable and dependable for a wide range of applications. Attached Figure Description

[0029] The accompanying drawings are included to provide a further understanding of embodiments of the subject matter of this disclosure, and these drawings are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the subject matter of this disclosure and, together with the description, serve to explain the principles of embodiments of the subject matter of this disclosure. In the drawings:

[0030] Figure 1 This is a perspective view of an electronic device according to one or more embodiments of the present disclosure;

[0031] Figure 2A and Figure 2B This is an exploded perspective view of an electronic device according to one or more embodiments of the present disclosure;

[0032] Figure 3 This is a block diagram of an electronic device according to one or more embodiments of the present disclosure;

[0033] Figure 4 This is a cross-sectional view of a display module according to one or more embodiments of the present disclosure;

[0034] Figure 5A This is a plan view of a display panel according to one or more embodiments of the present disclosure;

[0035] Figure 5B This is a cross-sectional view of a display panel according to one or more embodiments of the present disclosure;

[0036] Figure 6A This is a cross-sectional view of the input sensing layer according to one or more embodiments of the present disclosure;

[0037] Figure 6B This is a plan view of the input sensing layer according to one or more embodiments of the present disclosure;

[0038] Figure 6C It is along Figure 6B A cross-sectional view of the input sensing layer taken by line X-X';

[0039] Figure 7 This is an enlarged exploded perspective view of the pad area of ​​an electronic device according to one or more embodiments of the present disclosure;

[0040] Figure 8A This is an enlarged cross-sectional view of the pad area of ​​the electronic device in the comparative example;

[0041] Figure 8B yes Figure 8A A magnified view of region AA';

[0042] Figure 9A This is an enlarged cross-sectional view of the pad area of ​​an electronic device according to one or more embodiments of the present disclosure;

[0043] Figure 9B yes Figure 9A A magnified view of region BB';

[0044] Figure 9C This is an enlarged plan view of the pad area according to one or more embodiments of the present disclosure;

[0045] Figure 9D This is a cross-sectional view of the combined structure of an electronic device according to one or more embodiments of the present disclosure;

[0046] Figure 10A This is an enlarged cross-sectional view of the pad area of ​​an electronic device according to one or more embodiments of the present disclosure;

[0047] Figure 10B This is an enlarged plan view of the pad area of ​​an electronic device according to one or more embodiments of the present disclosure;

[0048] Figure 10C This is a cross-sectional view of the combined structure of an electronic device according to one or more embodiments of the present disclosure;

[0049] Figure 11This is an enlarged cross-sectional view of the pad area of ​​an electronic device according to one or more embodiments of the present disclosure; and

[0050] Figure 12 This is an enlarged cross-sectional view of the pad area of ​​an electronic device according to one or more embodiments of the present disclosure. Detailed Implementation

[0051] Reference will be made in more detail to one or more embodiments illustrated in the accompanying drawings, wherein the same reference numerals refer to the same elements throughout the drawings and written description, and their repetition may not be provided in this specification. In this regard, the subject matter of this disclosure may be embodied in different forms and should not be construed as limited to the one or more embodiments set forth herein. Rather, these embodiments are provided as examples with reference to the accompanying drawings to explain aspects and features of this disclosure to those skilled in the art.

[0052] When describing embodiments of this disclosure, the word “may” means “one or more embodiments of this disclosure”.

[0053] In the context of this application, and unless otherwise defined, the term “use” and its variations may be regarded as synonymous with the term “utilize” and its variations, respectively.

[0054] The term “and / or” as used herein includes any and all combinations of one or more of the listed related items. For example, “A and / or B” indicates either A or B, or both A and B (e.g., both).

[0055] Throughout this disclosure, "at least one of a, b, and c" refers to only a, only b, only c, both a and b (e.g., in combination), both a and c (e.g., in combination), both b and c (e.g., in combination), all of a, b, and c, or variations thereof.

[0056] In this disclosure, it will be understood that when an element (or region, layer, or portion) is referred to as being "located" on, "connected to," or "linked to" another element, the element may be directly located on, directly connected to, or directly linked to the other element, or there may be an intermediary element between them. Conversely, when an element is referred to as being "directly located" on, "directly connected to," or "directly linked to" another element, there is no intermediary element between them.

[0057] In the accompanying drawings, the thickness, proportions, and dimensions of the components may be exaggerated in order to effectively depict the technical content.

[0058] It will be understood that although the terms “first” and / or “second” may be used herein to describe one or more suitable elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Therefore, the first element discussed herein may be referred to as the second element without departing from the scope of this disclosure.

[0059] The singular forms “a” and “the (said)” used in this document are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0060] For ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” and / or “above” may be used in this document to describe the relationship of an element or feature illustrated in the accompanying drawings to other elements or features.

[0061] It will also be understood that, when used (for example, when) in this disclosure, the terms “having,” “comprising,” “including,” and / or variations thereof indicate the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. For example, it should be understood that the terms “comprising / variations thereof,” “including / variations thereof,” or “having / variations thereof” indicate the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Furthermore, the terms “comprising / variations thereof,” “including / variations thereof,” or “having / variations thereof,” etc., include or support the terms “consisting of…” and “substantially consisting of…”, which indicate the presence of the described features, integers, steps, operations, elements, and / or components, while other features, integers, steps, operations, elements, components, and / or groups thereof are absent or substantially absent.

[0062] In the context of this disclosure, and unless otherwise defined, a plan view is an orthographic projection of a three-dimensional object onto a horizontal plane intersecting the object. For example, it is a top-down view showing the layout and spatial relationships of one or more elements within an object or structure. A plan view based on the z-axis (thickness) direction refers to a top-down view of the object when viewed directly downwards from above. In this context, the z-axis direction is perpendicular or orthogonal to the horizontal plane defined by the x-axis and y-axis directions.

[0063] Unless otherwise defined, all terms used herein have substantially the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms such as those defined in commonly used or generally available dictionaries should be interpreted as having a meaning substantially consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0064] In the following, one or more embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0065] Figure 1 This is a perspective view of an electronic device according to one or more embodiments of the present disclosure. Figure 2A and Figure 2B This is an exploded perspective view of an electronic device according to one or more embodiments of the present disclosure.

[0066] According to one or more embodiments of this disclosure, the electronic device ED can be applied to large electronic devices such as televisions and / or monitors, and / or small to medium-sized electronic devices such as tablet computers, in-vehicle navigation units, game consoles, and / or smartwatches. As an example, Figure 1 The illustration shows a smart phone terminal as an electronic device (ED); however, the embodiments disclosed herein are not limited thereto.

[0067] The electronic device ED may have a rectangular shape (e.g., a basic rectangular shape) defined by a long side extending in a first direction DR1 and a short side extending in a second direction DR2 that intersects (e.g., crosses) the first direction DR1. However, the shape of the electronic device ED should not be limited to a rectangular shape, and the electronic device ED may have one or more suitable shapes such as a circular shape (e.g., a basic circular shape) and other polygonal shapes (e.g., a basic polygonal shape).

[0068] In the following text, a direction substantially orthogonal (e.g., perpendicular) to the plane defined by the first direction DR1 and the second direction DR2 may be referred to as the third direction DR3. In this disclosure, the expression "when (e.g., when) viewed in a plane (e.g., in a plan view)" may refer to the state of being viewed in the third direction DR3.

[0069] Electronic devices (EDs) can be rigid or flexible. The term "flexible" as used herein refers to the property of being able to be bent, ranging from fully bendable structures to structures that bend at the nanometer scale. For example, flexible EDs can be curved, rollable, or foldable electronic devices.

[0070] The electronic device ED can be used to display an image IM via a display surface DD-IS. An icon image is illustrated as an example of an image IM. The display surface DD-IS can be substantially parallel to the plane defined by a first direction DR1 and a second direction DR2.

[0071] The display surface DD-IS may include a display area DD-DA through which an image IM is displayed, and a non-display area DD-NDA adjacent to the display area DD-DA. The image IM may not be displayed through the non-display area DD-NDA. According to one or more embodiments, the non-display area DD-NDA may be defined as being adjacent to one side of the display area DD-DA, or the non-display area DD-NDA may not be provided.

[0072] refer to Figure 2A and Figure 2B The electronic device ED may include a window WM, a display module DM, and a housing component BC. Figure 2B The diagram shows Figure 2A The bending state of the bending region BA of the display module DM is shown in the figure.

[0073] A window (WM) can be arranged on a display module (DM). The window (WM) can be used to transmit an image (IM) provided by the display module (DM) to the outside of the display module (DM). The window (WM) can include a transmissive region (TA) and a non-transmissive region (NTA). The transmissive region (TA) can be... Figure 1 The display areas DD-DA shown in the figure overlap and can have a shape corresponding to the shape of the display areas DD-DA.

[0074] In one or more embodiments, the window WM may include a base layer and a functional layer disposed on the base layer. The functional layer may include a protective layer and / or an anti-fingerprint layer, etc. The base layer of the window WM may include glass, sapphire, and / or plastic materials. The base layer of the window WM may include an optically transparent (e.g., substantially transparent) insulating (e.g., electrically insulating) material. For example, the base layer of the window WM may include glass and / or a plastic film, or it may include a glass substrate and a plastic film bonded to the glass substrate by an adhesive.

[0075] Non-transmittent region NTA can be with Figure 1 The non-display area DD-NDA shown in the figure overlaps and may have a shape corresponding to the shape of the non-display area DD-NDA. The non-transmittent area NTA may have a relatively low transmittance compared to the transmittance of the transmittant area TA. The non-transmittent area NTA may be defined within a portion of the base layer of the window WM by a border pattern, and the area where the border pattern is not arranged may be defined as the transmittant area TA. However, embodiments of this disclosure are not limited thereto, and a non-transmittent area NTA may not be provided.

[0076] In one or more embodiments, an anti-reflective layer may be disposed between the window WM and the display module DM. The anti-reflective layer can reduce the reflectivity (e.g., the degree or frequency of reflection) of the electronic device ED to external light supplied from outside the electronic device ED. The anti-reflective layer may include color filters. The color filters may be arranged in a selected (e.g., predetermined or pre-defined) arrangement. As an example, the color filters may be arranged taking into account the emission colors of pixels included in the display panel DP, as described in more detail herein. In one or more embodiments, the anti-reflective layer may further include a black matrix disposed adjacent to the color filters.

[0077] The display module (DM) may include a display panel (DP) and an input sensing layer (ISU).

[0078] Display panel DP can be selected from liquid crystal display panels, electrophoretic display panels, microelectromechanical systems (MEMS) display panels, electrowetting display panels, organic light-emitting display panels, inorganic light-emitting display panels, and quantum dot light-emitting display panels. In the following text, organic light-emitting display panels will be described in more detail as display panel DPs, but the type (category) of display panel DPs should not be limited.

[0079] The input sensing layer (ISU) may include one selected from capacitive sensors, optical sensors, ultrasonic sensors, and electromagnetic induction sensors. The input sensing layer (ISU) can be formed or arranged on the display panel (DP) through a substantially continuous process, or it can be attached to the top of the display panel (DP) using an adhesive layer after being manufactured separately.

[0080] The electronic device ED may further include a driver chip DC mounted on the display panel DP.

[0081] The electronic device ED may further include a circuit board PB mounted on the display panel DP.

[0082] In one or more embodiments of this disclosure, the circuit board PB may be a flexible circuit board; however, the embodiments of this disclosure are not limited thereto. As an example, the circuit board PB may be rigid. The circuit board PB may be electrically connected to the display panel DP and the main circuit board.

[0083] The driver chip DC may include, for example, driving elements of a data driving circuit to drive the pixels of the display panel DP. Figure 2A The illustration shows a structure in which the driver chip DC can be mounted on the display panel DP; however, embodiments of this disclosure are not limited thereto. As an example, the driver chip DC can be mounted on a circuit board PB.

[0084] In one or more embodiments, the driver chip DC and the circuit board PB, which are directly mounted on the display panel DP, can be collectively referred to as "electronic components". In addition to the circuit board PB, the bonding structure between the display panel DP and the circuit board PB, which will be described in more detail below, can also be applied to the driver chip DC and other electronic components.

[0085] The display panel DP may include a curved region BA, a first non-curved region NBA1, and a second non-curved region NBA2 that is separated from and / or separated (e.g., spaced apart or separated) from the first non-curved region NBA1 in a first direction DR1, and the curved region BA may be arranged between the first non-curved region NBA1 and the second non-curved region NBA2.

[0086] The curved region BA can be the area where the display panel DP is bent about an imaginary bending axis BX extending in the second direction DR2. The first non-curved region NBA1 can overlap with the transmissive region TA, and the circuit board PB can be connected to the second non-curved region NBA2.

[0087] refer to Figure 2B When (for example, when) the bending region BA is bent about the bending axis BX, the circuit board PB and the driver chip DC can be bent in a direction toward the rear surface of the display panel DP, and thus can be arranged below the rear surface of the display panel DP. When a portion of the display panel DP is bent, the circuit board PB electrically bonded to the display panel DP can be arranged on the rear surface of the display panel DP.

[0088] The receiving member BC can provide space to house the display module DM. The receiving member BC can be used to protect the display module DM from external impacts. In one or more embodiments, the receiving member BC can prevent foreign objects from entering the electronic device ED (or reduce the degree or incidence of foreign objects entering the electronic device ED). The receiving member BC can be coupled to the window WM.

[0089] Figure 3 This is a block diagram of an electronic device according to one or more embodiments of the present disclosure.

[0090] refer to Figure 3The electronic device ED can communicate with the external electronic device 102 via a network (e.g., a short-range wireless communication network or a long-range wireless communication network). According to one or more embodiments, the electronic device ED may include a processor 110, a memory 120, an input module 130, a display module DM, a power module 150, an internal module 160, and an external module 170. According to one or more embodiments, at least one component selected from the components described in one or more embodiments may not be provided in the electronic device ED, or one or more other components may be added. According to one or more embodiments, one or more of the components described in one or more embodiments (e.g., sensor module 161, antenna module 162, and / or audio output module 163) may be integrated into another component (e.g., display module DM).

[0091] Processor 110 may be used to execute software to control at least one other component (e.g., hardware component and / or software component) connected to electronic device ED, and may be used to perform one or more appropriate data processing or computation operations. According to one or more embodiments, as at least part of the data processing or computation operation, processor 110 may be used to store commands or data received from other components (e.g., input module 130, sensor module 161, and / or communication module 173) in volatile memory 121, may be used to process commands or data stored in volatile memory 121, and may be used to store result data in non-volatile memory 122.

[0092] Processor 110 may include a main processor 111 and an auxiliary processor 112. The main processor 111 may include one or both (e.g., in combination) selected from a central processing unit (CPU) 111-1 and an application processor (AP). The main processor 111 may further include any one or more selected from a graphics processing unit (GPU) 111-2, a communication processor (CP), and an image signal processor (ISP).

[0093] The main processor 111 may further include a neural processing unit (NPU) 111-3. The NPU 111-3 may be a processor specifically designed for processing artificial intelligence models, which can be generated through machine learning. The artificial intelligence model may include multiple layers of artificial neural networks. The artificial neural networks may be selected from one of deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), restricted Boltzmann machines (RBMs), deep belief networks (DBNs), bidirectional recurrent deep neural networks (BRDNNs), deep Q-networks, and / or two or more combinations of the above (e.g., any suitable combination), but are not limited to the examples described in one or more embodiments. In one or more embodiments, additionally or alternatively, in addition to the hardware architecture, the artificial intelligence model may also include a software architecture. At least two of the processing units and processors selected from one or more embodiments may be implemented as a single integrated component (e.g., a single chip) or discrete components (e.g., multiple chips).

[0094] The auxiliary processor 112 may include a controller 112-1. The controller 112-1 may include interface conversion circuitry and timing control circuitry. The controller 112-1 may be used to receive image signals from the main processor 111, convert the data format of the image signals according to the interface specification with the display module DM, and output image data. The controller 112-1 may be used to output one or more appropriate control signals required to drive the display module DM.

[0095] The auxiliary processor 112 may further include a data conversion circuit 112-2, a gamma correction circuit 112-3, and / or a rendering circuit 112-4, etc. The data conversion circuit 112-2 may be used to receive image data from the controller 112-1 and compensate the image data based on the characteristics of the electronic device ED and / or user settings to display an image with desired or appropriate brightness, or to convert the image data to reduce power consumption or compensate for image retention.

[0096] The gamma correction circuit 112-3 can be used to convert image data and / or gamma reference voltage, etc., so that the image displayed on the electronic device ED has the desired or appropriate gamma characteristics. The rendering circuit 112-4 can be used to receive image data from the controller 112-1 and render the image data taking into account the pixel arrangement of the display panel DP applied to the electronic device ED.

[0097] At least one of the data conversion circuit 112-2, gamma correction circuit 112-3, and rendering circuit 112-4 can be integrated into other components (e.g., main processor 111 or controller 112-1). At least one of the data conversion circuit 112-2, gamma correction circuit 112-3, and rendering circuit 112-4 can be integrated into the data driver DDV, which is described in more detail herein. The data driver DDV may be included in... Figure 2A and Figure 2B The diagram shows a portion of the circuitry in the DC driver chip.

[0098] The memory 120 may be used to store one or more appropriate data used by at least one component of the electronic device ED (e.g., processor 110 or sensor module 161), as well as input or output data associated with corresponding commands. The memory 120 may include at least one selected from volatile memory 121 and non-volatile memory 122.

[0099] The input module 130 can be used to receive commands or data from an external source of the electronic device ED (e.g., a user or external electronic device 102) to be used by components of the electronic device ED (e.g., processor 110, sensor module 161, or audio output module 163).

[0100] The input module 130 may include a first input module 131 that receives commands or data from a user and a second input module 132 that receives commands or data from an external electronic device 102. The first input module 131 may include a microphone, mouse, keyboard, key (e.g., button) and / or pen (e.g., passive pen and / or active pen).

[0101] The second input module 132 may be used to support specified protocols that enable connection to external electronic device 102 via wired and / or wireless connections. According to one or more embodiments, the second input module 132 may include a High Definition Multimedia Interface (HDMI), a Universal Serial Bus (USB) interface, an SD card interface, or an audio interface. The second input module 132 may include a connector capable of physically connecting to external electronic device 102, such as an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0102] The display module (DM) can be used to provide visual information to the user. The display module (DM) may include a display panel (DP), a scan driver (SDV), and a data driver (DDV). The display module (DM) may further include a window, a base, and a bracket for protecting the display panel (DP).

[0103] The display panel DP may include a liquid crystal display panel, an organic light-emitting display panel, or an inorganic light-emitting display panel, and the type (variety) of the display panel DP should not be limited. The display panel DP may be a rigid type (variety) or a flexible type (variety) that can be rolled or folded. The display module DM may further include supports, brackets, and / or heat dissipation components that support the display panel DP.

[0104] The scan driver SDV can be mounted as a driver chip on the display panel DP. In one or more embodiments, the scan driver SDV can be integrated into the display panel DP. For example, the scan driver SDV may include an amorphous (e.g., amorphous silicon TFT gate (ASG) driver circuit, a low-temperature polycrystalline silicon (LTPS) TFT gate driver circuit, or an oxide semiconductor TFT gate (OSG) driver circuit built into the display panel DP. The scan driver SDV can be used to receive control signals from the controller 112-1 and output scan signals to the display panel DP in response to the control signals.

[0105] The display panel DP may further include a transmit driver. The transmit driver can be used to output a transmit control signal to the display panel DP in response to a control signal received from the controller 112-1. The transmit driver may be formed or arranged separately from the scan driver SDV, or it may be integrated into the scan driver SDV.

[0106] The data driver DDV can be used to receive control signals from the controller 112-1, convert image data into analog voltages (e.g., data voltages or data signals) in response to the control signals, and then output the data voltages to the display panel DP.

[0107] The data driver DDV can be integrated into other components (e.g., controller 112-1). The functions of the interface conversion circuitry and timing control circuitry of controller 112-1 described in one or more embodiments can be integrated into the data driver DDV.

[0108] The display module DM may further include a transmitter driver and / or voltage generation circuitry. The voltage generation circuitry can be used to output one or more appropriate voltages desired or required to drive the display panel DP.

[0109] Power module 150 can be used to supply power to components of an electronic device ED. Power module 150 may include a battery charged with electrical voltage. The battery may include a non-rechargeable primary battery, a rechargeable secondary battery, and / or a fuel cell. Power module 150 may include a power management integrated circuit (PMIC). The PMIC can be used to supply improved (or enhanced) or optimized power to each of the modules described in one or more embodiments. Power module 150 may include wireless power transmission / reception components electrically connected to the battery. The wireless power transmission / reception components may include multiple antenna radiators in the form of coils.

[0110] The electronic device ED may further include an internal module 160 and an external module 170. The internal module 160 may include a sensor module 161, an antenna module 162, and an audio output module 163. The external module 170 may include a camera module 171, an optical module 172, and a communication module 173.

[0111] The sensor module 161 can be used to sense input made through a user's body or through a pen in the first input module 131, and can be used to generate an electrical signal or data value corresponding to the input. The sensor module 161 may include at least one selected from the fingerprint sensor 161-1, the input sensing layer 161-2, and the digitizer 161-3.

[0112] The fingerprint sensor 161-1 can be used to generate data values ​​corresponding to a user's fingerprint. The fingerprint sensor 161-1 may include any one selected from optical (type) fingerprint sensors and capacitive (type) fingerprint sensors.

[0113] The input sensing layer 161-2 can be used to generate data values ​​corresponding to the coordinate information of input made through the user's body or through a pen. The input sensing layer 161-2 can be used to generate data values ​​based on capacitance changes caused by the input. The input sensing layer 161-2 can be used to sense input made through a passive pen, or it can be used to send / receive data to / from an active pen.

[0114] The input sensing layer 161-2 can measure biometric signals related to biometric information such as blood pressure, hydration level, and / or body fat. For example, when a user touches the sensor layer and / or sensing panel with a part of their body and remains still for a specific (e.g., set or predetermined) period of time, the input sensing layer 161-2 can be used to sense biometric signals based on changes in the electric field caused by the body part and output the user's desired or appropriate information to the display module DM.

[0115] The digitizer 161-3 can be used to generate data values ​​corresponding to coordinate information of input via a pen. The digitizer 161-3 can also generate data values ​​based on changes in the electromagnetic field caused by the input. The digitizer 161-3 can be used to sense input via a passive pen, or to send / receive data to / from an active pen.

[0116] At least one of the fingerprint sensor 161-1, the input sensing layer 161-2, and the digitizer 161-3 (e.g., the input sensing layer 161-2) can be implemented as a sensor layer formed or disposed on the display panel DP by a substantially continuous process. In this case, the input sensing layer 161-2 can correspond to a reference. Figure 2A and Figure 2B The input sensing layer ISU is described. The fingerprint sensor 161-1, the input sensing layer 161-2, and the digitizer 161-3 can be arranged on the display panel DP, or any one of the fingerprint sensor 161-1, the input sensing layer 161-2, and the digitizer 161-3 (e.g., the digitizer 161-3) can be arranged below the display panel DP.

[0117] At least two of the fingerprint sensor 161-1, the input sensing layer 161-2, and the digitizer 161-3 can be integrated into a single sensing panel using substantially the same process. When at least two of the fingerprint sensor 161-1, the input sensing layer 161-2, and the digitizer 161-3 are integrated into a single sensing panel, the sensing panel can be arranged between the display panel DP and a window arranged on the display panel DP. According to one or more embodiments, the sensing panel can be arranged on the window, and the position of the sensing panel is not limited.

[0118] At least one of the fingerprint sensor 161-1, the input sensing layer 161-2, and the digitizer 161-3 can be embedded in the display panel DP. For example, at least one of the fingerprint sensor 161-1, the input sensing layer 161-2, and the digitizer 161-3 can be formed or arranged synchronously (e.g., simultaneously) by a process for forming or arranging the elements (e.g., light-emitting elements and / or transistors, etc.) included in the display panel DP.

[0119] In one or more embodiments, sensor module 161 may be used to generate electrical signals or data values ​​corresponding to the internal or external states of electronic device ED. Sensor module 161 may further include, for example, a gesture sensor, a gyroscope sensor, a barometric pressure sensor, a magnetic sensor, an accelerometer, a grip sensor, a proximity sensor, a color sensor, an infrared (IR) sensor, a biometric sensor, a temperature sensor, a humidity sensor, and / or an illuminance sensor.

[0120] Antenna module 162 may include one or more antennas for transmitting or receiving signals or power from an external source. According to one or more embodiments, communication module 173 may be used to transmit signals to or receive signals from external electronic device 102 via an antenna suitable for a communication method. The antenna pattern of antenna module 162 may be integrated into a component of input sensing layer 161-2 or display module DM (e.g., display panel DP).

[0121] The audio output module 163 may be a device that outputs audio signals to an external electronic device ED, and may include, for example, a speaker for general purposes (such as multimedia playback and / or recording playback) and a receiver specifically for answering telephone calls. According to one or more embodiments, the receiver may be integrally formed or arranged with the speaker or separately formed or arranged from the speaker. The audio output mode of the audio output module 163 may be integrated into the display module DM.

[0122] Camera module 171 can be used to capture still images and / or videos. According to one or more embodiments, camera module 171 may include one or more lenses, image sensors, or image signal processors. Camera module 171 may further include an infrared camera capable of measuring the presence or absence of a user, the user's position, and / or the user's line of sight.

[0123] The light module 172 can be used to provide light. The light module 172 may include a light-emitting diode and / or a xenon lamp. The light module 172 can be used to operate in conjunction with the camera module 171, or it can operate independently.

[0124] Communication module 173 can be used to support the establishment of wired and / or wireless communication channels between electronic device ED and external electronic device 102, and communication via the established communication channels. Communication module 173 may include one or both (e.g., both) of wireless communication modules (such as cellular communication modules, short-range wireless communication modules, and / or Global Navigation Satellite System (GNSS) communication modules) and wired communication modules (such as local area network (LAN) communication modules and / or power line communication modules). Communication module 173 can be used to communicate with external electronic device 102 via short-range communication networks (such as Bluetooth, WiFi Direct, and / or Infrared Data Association (IrDA)) and / or long-range communication networks (such as cellular networks, the Internet, and / or computer networks (e.g., LAN or WAN)). One or more suitable types (classes) of communication modules 173 described in one or more embodiments may be implemented as a single chip or discrete chips.

[0125] Input module 130, sensor module 161 and / or camera module 171, etc., can be used in conjunction with processor 110 to control the operation of display module DM.

[0126] The processor 110 can be used to output commands or data to the display module DM, audio output module 163, camera module 171, and / or optical module 172 based on input data received from the input module 130. For example, the processor 110 can be used to generate image data and output the image data to the display module DM in response to input data applied by a mouse and / or an active pen, or it can be used to generate command data and output the command data to the camera module 171 or optical module 172 in response to input data. When no input data is received from the input module 130 for a specific (e.g., set or predetermined) time period, the processor 110 can switch the operating mode of the electronic device ED to a low-power mode or a sleep mode to reduce the power consumed in the electronic device ED.

[0127] Processor 110 can be used to output commands or data to display module DM, audio output module 163, camera module 171, or optical module 172 based on sensing data received from sensor module 161. For example, processor 110 can be used to compare authentication data applied by fingerprint sensor 161-1 with authentication data stored in memory 120, and then execute an application based on the comparison result. Processor 110 can be used to execute commands based on sensing data sensed by input sensing layer 161-2 or digitizer 161-3, or can be used to output image data corresponding to the sensing data to display module DM. When sensor module 161 includes a temperature sensor, processor 110 can receive temperature data measured by sensor module 161 and further perform brightness correction and / or similar operations on image data based on the temperature data.

[0128] Processor 110 can be used to receive measurement data from camera module 171 regarding the presence or absence of a user, the user's location, and / or the user's gaze. Processor 110 can be further used to perform brightness correction and / or similar operations on image data based on the measurement data. For example, when processor 110 determines the presence or absence of a user based on input from camera module 171, processor 110 can output image data whose brightness has been corrected by data conversion circuit 112-2 or gamma correction circuit 112-3 to display module DM.

[0129] In one or more embodiments, one or more suitable components may be connected to each other via peripheral device communication methods (e.g., bus, general purpose input / output (GPIO), serial peripheral interface (SPI), mobile industry processor interface (MIPI), or hyperpath interconnect (UPI) link) to exchange signals (e.g., commands or data). Processor 110 may be used to communicate with display module DM via an agreed-upon interface (e.g., any of the communication methods selected from one or more embodiments), and the communication methods should not be limited to those described in one or more embodiments.

[0130] The electronic device ED according to one or more embodiments of this disclosure can be applied to one or more suitable types (classes) of devices. The electronic device ED may include at least one selected from, for example, portable communication devices (e.g., smartphones), computer devices, portable multimedia devices, portable medical devices, cameras, wearable devices, and home appliance devices. The electronic device ED according to one or more embodiments of this disclosure should not be limited to the devices described in the one or more embodiments.

[0131] Figure 4This is a cross-sectional view of a display module according to one or more embodiments of the present disclosure.

[0132] refer to Figure 4 The display module DM may include a display panel DP and an input sensing layer ISU disposed on the display panel DP.

[0133] The display panel DP may include a substrate layer BL, a circuit element layer DP-CL disposed on the substrate layer BL, a display element layer DP-OLED disposed on the circuit element layer DP-CL, and an encapsulation layer TFL disposed on the display element layer DP-OLED.

[0134] The display panel DP can include a display area DP-DA and a non-display area DP-NDA. The display area DP-DA of the display panel DP can be the same as the display area DD-DA (see reference). Figure 1 ) and / or transmission region TA (reference) Figure 2A Corresponding to, and the non-display area DP-NDA of the display panel DP can be matched with the non-display area DD-NDA (reference). Figure 1 ) and / or non-transmissive region NTA (reference) Figure 2A Corresponding to ).

[0135] The substrate layer BL may include at least one plastic film. The substrate layer BL may be a flexible substrate and may include a plastic substrate, a glass substrate, a metal substrate, and / or an organic / inorganic composite substrate.

[0136] The circuit element layer DP-CL may include an insulating (e.g., electrically insulating) layer and circuit elements.

[0137] The insulating layer can be provided in multiple forms. The insulating layer may include inorganic and / or organic layers.

[0138] Circuit elements may include signal lines and pixel driving circuitry. Insulating layers, semiconductor layers, and conductive (e.g., electrically conductive) layers may be formed or arranged by coating and / or deposition processes. The insulating layers, semiconductor layers, and conductive layers may then be selectively patterned by photolithography and / or etching processes.

[0139] Semiconductor patterns, conductive (e.g., electrically conductive) patterns, and signal lines can be formed or arranged using the processes described in one or more embodiments. Patterns arranged on substantially the same layers can be formed or arranged using substantially the same processes. As used herein, the expression "patterns are formed or arranged using substantially the same processes" means that the patterns comprise substantially the same materials and have substantially the same stacked structure.

[0140] The display element layer of a DP-OLED may include light-emitting elements. The display element layer of a DP-OLED may further include an organic layer such as a pixel defining layer.

[0141] The encapsulation layer TFL can encapsulate the display element layer DP-OLED. The encapsulation layer TFL can be disposed on the display element layer DP-OLED. The encapsulation layer TFL can overlap with the display area DP-DA and the non-display area DP-NDA. The encapsulation layer TFL can overlap with at least a portion of the non-display area DP-NDA.

[0142] The encapsulation layer TFL can have a stacked structure of inorganic layers, organic layers, and inorganic layers. The encapsulation layer TFL can protect the display element layer DP-OLED from moisture, oxygen, and / or foreign matter such as dust particles.

[0143] The input sensing layer (ISU) can be directly disposed on the display panel (DP). In one or more embodiments, the input sensing layer (ISU) can be formed or disposed on the display panel (DP) through a substantially continuous process. However, embodiments of this disclosure are not limited thereto. As an alternative example, the input sensing layer (ISU) can be provided as a separate panel and then attached to the display panel (DP) via an adhesive layer.

[0144] Figure 5A This is a plan view of a display panel according to one or more embodiments of the present disclosure.

[0145] refer to Figure 5A The display panel DP may include multiple pixels (PX), gate drive circuit (GDC), multiple signal lines (SGL), and multiple signal pads (DP-PD).

[0146] Pixels (PX) can be arranged in the display area DP-DA. Each pixel (PX) may include a light-emitting element and pixel driving circuitry connected to the light-emitting element. In one or more embodiments, the light-emitting element may be an organic light-emitting element.

[0147] The gate drive circuit GDC can correspond to the reference. Figure 3 The described scan driver SDV can be used to sequentially output gate signals (which may correspond to scan signals) to multiple gate lines GL. The gate drive circuit GDC may include transistors formed or arranged using substantially the same process as the transistors of the pixel PX (e.g., low-temperature polycrystalline silicon (LTPS) process and / or low-temperature polycrystalline oxide (LTPO) process). The display panel DP may further include another drive circuit (which may correspond to an emitt driver) that applies emitt control signals to the pixel PX.

[0148] The signal line SGL may include gate lines GL, data lines DL, power lines PL, and control signal lines CSL. Each gate line GL can be connected to a corresponding pixel PX, and each data line DL can be connected to a corresponding pixel PX. The power line PL can be connected to a pixel PX. The control signal line CSL can be used to provide control signals to the gate drive circuit GDC.

[0149] Signal lines SGL may overlap with the display area DP-DA and the non-display area DP-NDA. Each signal line SGL may include a line portion LP. Signal lines SGL may further include pad portions. Line portions LP may overlap with the display area DP-DA and the non-display area DP-NDA. Pad portions may be connected to the ends of line portions LP.

[0150] The signal pad DP-PD may include a first pad PD1, a second pad PD2, and a third pad PD3.

[0151] In this disclosure, the area where the first pad PD1 and the second pad PD2 are arranged can be referred to as the first pad area PA1, and the area where the third pad PD3 is arranged can be referred to as the second pad area PA2.

[0152] The first pad area PA1 can be the driver chip DC (see reference). Figure 2A The area overlapping with the display panel DP. The second pad area PA2 can be the circuit board PB (refer to) Figure 2A The area overlapping with the display panel DP.

[0153] The first pad region PA1 and the second pad region PA2 can be arranged in the non-display area DP-NDA. The first pad region PA1 and the second pad region PA2 can be spaced apart and / or separated from each other in the first direction DR1 (e.g., spaced apart or separated). The first pad region PA1 may include a first region B1 in which the first pad PD1 is arranged and a second region B2 in which the second pad PD2 is arranged.

[0154] In this disclosure, the first pad region PA1 or the second pad region PA2 may be referred to as a pad region. For example, a pad region may refer to at least one region selected from the first pad region PA1 and the second pad region PA2.

[0155] Figure 5A The illustration shows two pad rows arranged in the first pad area PA1 and one pad row arranged in the second pad area PA2. However, the number of pad rows arranged in each pad area of ​​PA1 and PA2 should not be limited.

[0156] Each of the first pads PD1 can be connected to a corresponding data line DL in the data lines DL. In one or more embodiments, the second pad PD2 can be electrically connected to the third pad PD3. The second pad PD2 can be connected to the third pad PD3 via a connection signal line SCLn.

[0157] The circuit board PB may include a substrate bump PB-BP. The substrate bump PB-BP may be arranged on the second direction DR2. The substrate bump PB-BP of the circuit board PB may contact the third pad PD3 of the second pad region PA2.

[0158] Figure 5B This is a cross-sectional view of a display panel according to one or more embodiments of the present disclosure.

[0159] Figure 5B The illustration shows one pixel PX of the display panel DP (reference). Figure 5A Cross-sectional view of ).

[0160] refer to Figure 5B The display area DP-DA may include a light-emitting area PXA and a non-light-emitting area NPXA adjacent to the light-emitting area PXA.

[0161] Pixel PX (reference) Figure 5A Each of these may include a light-emitting element (OLED) and pixel driving circuitry connected to the OLED. For example, a pixel PX (reference) Figure 5A This can include light-emitting elements (OLEDs) and transistors (TRs).

[0162] Figure 5B Only the pixel PX (reference) is shown in the illustration. Figure 5A The example shown is a transistor TR in a pixel PX; however, embodiments of this disclosure are not limited thereto. As an example, a pixel PX may include seven transistors and at least one capacitor, and the capacitor and the seven transistors may be electrically connected to each other. However, the number of transistors and capacitors forming a pixel PX should not be limited.

[0163] The display panel (DP) may include multiple insulating (e.g., electrically insulating) layers, semiconductor patterns, conductive (e.g., electrically conductive) patterns, and signal lines. The insulating (e.g., electrically insulating) layers, semiconductor layers, and conductive (e.g., electrically conductive) layers may be formed or arranged by coating and / or deposition processes. The insulating, semiconductor, and conductive layers may then be selectively patterned by photolithography processes. The semiconductor patterns, conductive patterns, and signal lines included in the circuit element layer (DP-CL) and the display element layer (DP-OLED) may be formed or arranged by the methods described in one or more embodiments.

[0164] The substrate layer BL may include a synthetic resin film. The substrate layer BL may have a multilayer structure. For example, the substrate layer BL may have a three-layer structure consisting of a synthetic resin layer, an inorganic layer, and a synthetic resin layer. The synthetic resin layer may include a polyimide resin; however, the embodiments disclosed herein are not limited thereto. The substrate layer BL may include a glass substrate, a metal substrate, and / or an organic / inorganic composite substrate.

[0165] The circuit element layer DP-CL may include a barrier layer BRL, a buffer layer BFL, a first insulating layer 10, a second insulating layer 20, a third insulating layer 30, a fourth insulating layer 40, a fifth insulating layer 50, a sixth insulating layer 60, a transistor TR, a connection signal line SCLd, an upper electrode UE, a first connection electrode CNE1, and a second connection electrode CNE2.

[0166] The barrier layer BRL can be disposed on the substrate layer BL. The buffer layer BFL can be disposed on the barrier layer BRL. Each of the barrier layer BRL and the buffer layer BFL can be an inorganic layer.

[0167] Semiconductor patterns can be disposed on the buffer layer BFL. The semiconductor patterns may include polycrystalline silicon; however, embodiments of this disclosure are not limited thereto. According to one or more embodiments, the semiconductor patterns may include amorphous (e.g., non-crystalline) silicon and / or metal oxides.

[0168] Figure 5B The illustration shows a portion of a semiconductor pattern, and when viewed in a planar plane (e.g., in a planar view), the semiconductor pattern can be further arranged in other areas of the pixel PX. The semiconductor pattern can be arranged across multiple pixels PX according to specific (e.g., set or predetermined) rules. The semiconductor pattern can have different electrical characteristics depending on whether it is doped. The semiconductor pattern can include a first region and a second region. The first region can be doped with a negative (class) dopant (e.g., an N-type (class) dopant) or a positive (class) dopant (e.g., a P-type (class) dopant). A positive (class) transistor (e.g., a P-type (class) transistor) can include a doped region doped with P-type (class) dopant.

[0169] The first region may have a higher conductivity (e.g., lower conductivity) than the second region and may substantially serve as or be used as an electrode or signal line. The second region may be an undoped region or a region doped at a lower concentration than the first region and may substantially correspond to the active portion (or channel) of a transistor. A portion of the semiconductor pattern may be the active portion of the transistor, another portion of the semiconductor pattern may be the source or drain of the transistor, and yet another portion of the semiconductor pattern may be a connection electrode or a connection signal line.

[0170] like Figure 5BAs shown, the source S, active portion A, and drain D of transistor TR can be formed or arranged by semiconductor patterns.

[0171] Figure 5B The illustration shows a portion of a connection signal line SCLd formed or arranged by a semiconductor pattern. The connection signal line SCLd can be electrically connected to the drain of one of the transistors selected from the pixel PX.

[0172] A first insulating layer 10 may be disposed on a buffer layer BFL. The first insulating layer 10 may cover a semiconductor pattern. The first insulating layer 10 may commonly overlap with multiple pixels PX. A gate G may be disposed on the first insulating layer 10. The gate G may be part of a metal pattern. The gate G may overlap with an active portion A. The gate G may be used as a mask in a process of doping the semiconductor pattern.

[0173] A second insulating layer 20 may be disposed on the first insulating layer 10 and may cover the gate G. The second insulating layer 20 may commonly overlap with a plurality of pixels PX. An upper electrode UE may be disposed on the second insulating layer 20. The upper electrode UE may overlap with the gate G of the transistor TR. The upper electrode UE may be part of a metal pattern. A portion of the gate G and the upper electrode UE overlapping that portion of the gate G may define a capacitor.

[0174] The third insulating layer 30 can be disposed on the second insulating layer 20 and can cover the upper electrode UE. The first connection electrode CNE1 disposed on the third insulating layer 30 can be connected to the connection signal line SCLd via a contact hole CNT-1 defined through the first insulating layer 10, the second insulating layer 20 and the third insulating layer 30.

[0175] The fourth insulating layer 40 may be disposed on the third insulating layer 30 and may cover the first connecting electrode CNE1. The first to fourth insulating layers 10 to 40 may be inorganic layers and / or organic layers, and may have a single-layer structure or a multi-layer structure.

[0176] A fifth insulating layer 50 may be disposed on the fourth insulating layer 40. The fifth insulating layer 50 may be an organic layer. A second connecting electrode CNE2 may be disposed on the fifth insulating layer 50. The second connecting electrode CNE2 may be connected to the first connecting electrode CNE1 via a contact hole CNT-2 defined through the fourth insulating layer 40 and the fifth insulating layer 50.

[0177] A sixth insulating layer 60 may be disposed on the fifth insulating layer 50 and may cover the second connecting electrode CNE2. The sixth insulating layer 60 may be an organic layer. A first electrode AE ​​may be disposed on the sixth insulating layer 60. The first electrode AE ​​may be connected to the second connecting electrode CNE2 via a contact hole CNT-3 defined through the sixth insulating layer 60.

[0178] The display element layer DP-OLED may include a pixel defining layer PDL and a light-emitting element OLED. A pixel aperture OPN may be defined through the pixel defining layer PDL. At least a portion of the first electrode AE ​​may be exposed through the pixel aperture OPN of the pixel defining layer PDL. In one or more embodiments, the light-emitting region PXA may be defined to correspond to the portion of the first electrode AE ​​exposed through the pixel aperture OPN.

[0179] A hole control layer (HCL) can be commonly arranged in the light-emitting region (PXA) and the non-light-emitting region (NPXA). The hole control layer (HCL) may include a hole transport layer and may further include a hole injection layer. A light-emitting layer (EML) can be arranged on the hole control layer (HCL). The light-emitting layer (EML) can be arranged in the region corresponding to the pixel aperture (OPN). For example, the light-emitting layer (EML) can be divided into multiple parts, and the multiple parts of the light-emitting layer (EML) can be arranged separately in multiple pixels (PX); however, embodiments of this disclosure are not limited thereto. According to one or more embodiments, the light-emitting layer (EML) can be formed or arranged by utilizing an aperture mask to commonly extend across multiple pixels (PX).

[0180] An electronic control layer (ECL) can be disposed on the light-emitting layer (EML). The ECL may include an electron transport layer and may further include an electron injection layer. A hole control layer (HCL) and the ECL can be formed or disposed together across multiple pixels (PX) using an aperture mask. A second electrode (CE) can be disposed on the ECL. The second electrode (CE) may have a monolithic shape (e.g., a substantially monolithic shape) and may be disposed together across multiple pixels (PX).

[0181] The encapsulation layer TFL can be disposed on the second electrode CE. In one or more embodiments, the encapsulation layer TFL can have a structure in which inorganic and organic layers are stacked alternately. Accordingly, oxygen and / or moisture can be effectively or appropriately prevented from entering the light-emitting element OLED (or the extent or occurrence of oxygen and / or moisture entering the light-emitting element OLED can be effectively or appropriately reduced).

[0182] Figure 6A This is a cross-sectional view of the input sensing layer according to one or more embodiments of the present disclosure. Figure 6B This is a plan view of the input sensing layer according to one or more embodiments of the present disclosure. Figure 6C It is along Figure 6B A cross-sectional view of the input sensing layer taken by line X-X'.

[0183] Figure 6C This is a cross-sectional view of a bridging pattern of an input sensing layer (ISU) according to one or more embodiments of the present disclosure, and the bridging pattern will be described in more detail herein.

[0184] The input sensing layer ISU may include a first sensing insulating layer IS-IL1, a second sensing insulating layer IS-IL2, a third sensing insulating layer IS-IL3, a first sensing conductive layer IS-CL1 disposed between the first sensing insulating layer IS-IL1 and the second sensing insulating layer IS-IL2, and a second sensing conductive layer IS-CL2 disposed between the second sensing insulating layer IS-IL2 and the third sensing insulating layer IS-IL3.

[0185] The first sensing insulating layer IS-IL1 may be directly disposed on the encapsulation layer TFL.

[0186] The first sensing conductive layer IS-CL1 may include a plurality of first sensing conductive (e.g., electrically conductive) layers, and the second sensing conductive layer IS-CL2 may include a plurality of second sensing conductive (e.g., electrically conductive) layers. Hereinafter, the first sensing conductive layer IS-CL1 and the plurality of first sensing conductive layers may be assigned the same reference numeral, and the second sensing conductive layer IS-CL2 and the plurality of second sensing conductive layers may be assigned the same reference numeral.

[0187] Each of the first sensing conductive layer IS-CL1 and the second sensing conductive layer IS-CL2 may have a single-layer structure or a multi-layer structure of a plurality of layers stacked in a third direction DR3. The sensing conductive layer having a multi-layer structure may include two or more layers of a transparent (e.g., substantially transparent) conductive (e.g., electrically conductive) layer and a metal layer. The sensing conductive layer having a multi-layer structure may include metal layers containing different metals from each other. The transparent conductive layer may include one selected from indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (e.g., ZnO x , where 0 < x ≤ 2; e.g., ZnO), indium tin zinc oxide (ITZO), poly(3,4-ethylenedioxythiophene) (PEDOT), metal nanowires, and / or graphene. The metal layer may include one selected from molybdenum, silver, titanium, copper, aluminum, and their alloys.

[0188] In one or more embodiments, each of the first sensing insulating layer IS-IL1, the second sensing insulating layer IS-IL2, and the third sensing insulating layer IS-IL3 may include an inorganic layer and / or an organic layer. In one or more embodiments, each of the first sensing insulating layer IS-IL1, the second sensing insulating layer IS-IL2, and the third sensing insulating layer IS-IL3 may include an inorganic layer. The inorganic layer may include silicon oxide, silicon nitride, and / or silicon oxynitride.

[0189] According to one or more embodiments, at least one of the first sensing insulating layer IS-IL1, the second sensing insulating layer IS-IL2, and the third sensing insulating layer IS-IL3 may be an organic layer. For example, the third sensing insulating layer IS-IL3 may include an organic layer. The organic layer may include at least one selected from acrylic resins, methacrylic resins, polyisoprene resins, vinyl resins, epoxy resins, urethane resins, cellulose resins, siloxane resins, polyimide resins, polyamide resins, and perylene resins.

[0190] refer to Figure 6B and Figure 6C The input sensing layer ISU may include a sensing area IS-DA and a non-sensing area IS-NDA adjacent to the sensing area IS-DA.

[0191] The sensing area IS-DA and the non-sensing area IS-NDA can be respectively compared with Figure 4 The display area DP-DA and the non-display area DP-NDA are shown in the diagram.

[0192] The input sensing layer ISU may include sensing electrodes E1-1 to E1-5 and E2-1 to E2-4 arranged in the sensing area IS-DA. The sensing electrodes E1-1 to E1-5 and E2-1 to E2-4 may include first electrodes E1-1 to E1-5 and second electrodes E2-1 to E2-4 that are insulated (e.g., electrically insulated) from and intersect (e.g., cross) the first electrodes E1-1 to E1-5.

[0193] The input sensing layer ISU may include a first signal line SL1 disposed in the non-sensing area IS-NDA and electrically connected to the first electrodes E1-1 to E1-5, and a second signal line SL2 disposed in the non-sensing area IS-NDA and electrically connected to the second electrodes E2-1 to E2-4.

[0194] The first electrodes E1-1 to E1-5, the second electrodes E2-1 to E2-4, the first signal line SL1, and the second signal line SL2 can be defined by the first sensing conductive layer IS-CL1 and the second sensing conductive layer IS-CL2.

[0195] Each of the first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 may include conductive (e.g., electrically conductive) lines that intersect each other. The intersecting conductive lines may define an opening. Accordingly, each of the first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 may define a grid shape (e.g., a basic grid shape).

[0196] Each of the openings defined by the conductive lines can be connected to the pixel-defined layer (PDL) (reference). Figure 5B The limited pixel aperture OPN (refer to) Figure 5B Corresponding to ).

[0197] The electrode selected from the first electrode E1-1 to E1-5 and the second electrode E2-1 to E2-4 may have an integral shape (e.g., a substantially integral shape). Figure 6B The diagram illustrates the structure in which each of the first electrodes E1-1 to E1-5 has an integral shape.

[0198] Each of the first electrodes E1-1 to E1-5 may include a sensing portion SP1 and an intermediate portion CP1. The sensing portion SP1 and the intermediate portion CP1 may be a second sensing conductive layer IS-CL2 (see reference). Figure 6A The sensing portion SP1 and the intermediate portion CP1 can be composed of a second sensing conductive layer IS-CL2 (reference). Figure 6A () to limit.

[0199] Each of the second electrodes E2-1 to E2-4 may include a sensing pattern SP2 and a bridging pattern CP2. As an example, Figure 6B and Figure 6C The diagram illustrates a structure in which two adjacent sensing patterns SP2 are connected to each other via two bridging patterns CP2 through a contact hole CH-I defined through the second sensing insulating layer IS-IL2. However, the number of bridging patterns CP2 connecting the sensing patterns SP2 should not be limited.

[0200] The sensing pattern SP2 can be the second sensing conductive layer IS-CL2 (reference). Figure 6A The bridging pattern CP2 can be multiple parts of the first sensing conductive layer IS-CL1 (reference). Figure 6A The sensing pattern SP2 and bridging pattern CP2 can be formed by the second sensing conductive layer IS-CL2 (reference). Figure 6A ) and the first sensing conductive layer IS-CL1 (reference) Figure 6A () to limit.

[0201] However, embodiments of this disclosure are not limited thereto. As an example, the first electrodes E1-1 to E1-5 and the sensing pattern SP2 can be formed by the first sensing conductive layer IS-CL1 (see reference). Figure 6A The bridging pattern CP2 can be defined by the second sensing conductive layer IS-CL2 (see reference). Figure 6A () to limit.

[0202] One of the first signal line SL1 and the second signal line SL2 can be used to receive and transmit signals to sense external input from external circuitry. The other of the first signal line SL1 and the second signal line SL2 can be used to transmit the capacitance change between the first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 as a received signal to the external circuitry.

[0203] In one or more embodiments, the first signal line SL1 and the second signal line SL2 may be multiple portions of the second sensing conductive layer IS-CL2. The first signal line SL1 and the second signal line SL2 may have a multilayer structure and may include a first layer line formed or arranged by the first sensing conductive layer IS-CL1 and a second layer line formed or arranged by the second sensing conductive layer IS-CL2. The first layer line and the second layer line may be transmitted via a path through the second sensing insulating layer IS-IL2 (reference...). Figure 6A The defined contact holes are connected to each other.

[0204] Figure 7 This is an enlarged exploded perspective view of the pad area of ​​an electronic device according to one or more embodiments of the present disclosure.

[0205] Figure 7 This is an enlarged exploded perspective view of the pad regions PA1 and PA2 of an electronic device according to one or more embodiments of the present disclosure.

[0206] The driver chip DC can be bonded to the first pad region PA1 via the first adhesive layer CF1. The circuit board PB can be bonded to the second pad region PA2 via the second adhesive layer CF2. The adhesive layers CF1 and CF2 can be anisotropic conductive films (ACF). Accordingly, the adhesive layers CF1 and CF2 can comprise synthetic resins having adhesive properties and conductive (e.g., electrically conductive) spheres. In this disclosure, the adhesive layers CF1 and CF2 can be referred to as conductive (e.g., electrically conductive) films.

[0207] The driver chip DC may include a driver integrated circuit D-IC and a chip bump DC-BP provided in the driver chip DC.

[0208] The driver integrated circuit (D-IC) may include an upper surface DC-US and a lower surface DC-DS. The lower surface DC-DS of the driver integrated circuit (D-IC) may be opposite (e.g., facing) the first pad PD1 and the second pad PD2.

[0209] Chip bump DC-BP can be disposed on the lower surface DC-DS of the driver integrated circuit D-IC. Chip bump DC-BP may include a first bump BP1 electrically connected to a first pad PD1 and a second bump BP2 electrically connected to a second pad PD2. The first bump BP1 may be disposed on a second direction DR2, and the second bump BP2 may be spaced apart from and / or separated from the first bump BP1 on a first direction DR1 (e.g., spaced apart or separated) and may be disposed on a second direction DR2.

[0210] The driver chip DC can be used to receive a first signal via the second pad PD2 and the second bump BP2. The driver chip DC can be used to generate a second signal based on the first signal, and can be used to apply the second signal to the first pad PD1 via the first bump BP1.

[0211] As an example, the driver chip DC may include data driving circuitry. The first signal may be an image signal, provided externally as a digital signal, and the second signal may be a data signal, provided as an analog signal. The driver chip DC can be used to generate an analog voltage corresponding to the grayscale value of the image signal. The data signal can be transmitted via a data line DL (reference). Figure 5A ) is applied to pixel PX (reference) Figure 5A ).

[0212] In one or more embodiments, the first bump BP1 and the second bump BP2 may protrude from the lower surface DC-DS of the driver integrated circuit D-IC and be exposed to the outside. When (for example) the first adhesive layer CF1 is cured, the first pad PD1 may be attached and secured to the first bump BP1, and the second pad PD2 may be attached and secured to the second bump BP2.

[0213] The circuit board PB may include a substrate layer P-BS and substrate bumps PB-BP provided in the circuit board PB.

[0214] The circuit board PB may include an upper surface PB-US and a lower surface PB-DS, and the lower surface PB-DS of the circuit board PB may be opposite (e.g., facing) the third pad PD3. A substrate bump PB-BP may be disposed on the lower surface PB-DS of the substrate layer P-BS. The substrate bump PB-BP may be electrically connected to the third pad PD3. The substrate bump PB-BP may be disposed on the second direction DR2. The circuit board PB may provide image signals, drive voltages, and control signals to the driver chip DC.

[0215] In one or more embodiments, the substrate bump PB-BP may protrude from the lower surface PB-DS of the base layer P-BS and be exposed to the outside. When (e.g.) the second adhesive layer CF2 is cured, the third pad PD3 may be attached and secured to the substrate bump PB-BP.

[0216] The electronic component may include a substrate and bumps disposed beneath the substrate. For example, when the electronic component corresponds to a driver chip DC, the substrate may correspond to the driver integrated circuit D-IC of the driver chip DC, and the bumps may correspond to chip bumps DC-BP. According to one or more embodiments, when the electronic component corresponds to a circuit board PB, the substrate may correspond to the base layer P-BS of the circuit board PB, and the bumps may correspond to substrate bumps PB-BP.

[0217] However, each of pads PD1, PD2, and PD3 may have a structure in which conductive (e.g., electrically conductive) patterns are stacked to electrically connect to corresponding bumps in bumps BP1, BP2, and BP3. However, the stacked conductive patterns may bend due to the insulating layer having a step difference, and therefore may be peeled or detached. However, since pads according to one or more embodiments of this disclosure may include a structure in which the step difference is compensated, bending of the conductive patterns can be prevented (or the degree or incidence of bending of the conductive patterns can be reduced). Accordingly, peeling or detachment of the conductive patterns can be effectively or appropriately prevented (or the degree or incidence of peeling or detachment of the conductive patterns can be effectively or appropriately reduced), and the reliability of the electronic device can be improved or enhanced.

[0218] In the following text, reference will be made to Figures 8A to 8B The step difference compensation structure of this disclosure and its effects are described in more detail.

[0219] Figure 8A This is an enlarged cross-sectional view of the pad area of ​​the electronic device based on the comparative example. Figure 8B yes Figure 8A A magnified view of region AA'.

[0220] exist Figure 8A and Figure 8B In the reference, the pad area can correspond to the area selected from the reference. Figure 5A At least one of the first pad region PA1 and the second pad region PA2 described.

[0221] Figure 8A and Figure 8B The comparative examples shown in the figures can be commonly available or frequently used electronic devices.

[0222] refer to Figure 8AThe electronic device according to the comparative example may include a substrate insulating layer ILD0, a first insulating pattern ILD1 disposed on the substrate insulating layer ILD0, and a pad PD' disposed on the substrate insulating layer ILD0.

[0223] According to the comparative example, the pad PD' may include a first lower conductive pattern LC1, a first upper conductive pattern UC1', a second upper conductive pattern UC2', and a third upper conductive pattern UC3'.

[0224] The first lower conductive pattern LC1, the first upper conductive pattern UC1', the second upper conductive pattern UC2', and the third upper conductive pattern UC3' can be electrically connected to each other.

[0225] The contact hole CNT' can be defined through the upper and lower surfaces of the first insulating pattern ILD1. The first lower conductive pattern LC1 can be exposed through the contact hole CNT' and can contact the first upper conductive pattern UC1'.

[0226] In one or more embodiments, step differences may sequentially appear in the first upper conductive pattern UC1', the second upper conductive pattern UC2', and the third upper conductive pattern UC3' due to the contact hole CNT' defined through the first insulating pattern ILD1. For example, bending may occur in the first upper conductive pattern UC1' due to the height difference between the upper surface of the first insulating pattern ILD1 and the upper surface of the first lower conductive pattern LC1. In this disclosure, the phenomenon of bending may be referred to as a reverse taper phenomenon.

[0227] In one or more embodiments, bending may occur in the second upper conductive pattern UC2' due to bending of the first upper conductive pattern UC1', and bending may also occur in the third upper conductive pattern UC3' due to bending of the second upper conductive pattern UC2'. Figure 8A The bending that occurs in the third upper conductive pattern UC3' is illustrated in region AA'.

[0228] Figure 8B yes Figure 8A Enlarged cross-sectional view of region AA'. Figure 8B This is an enlarged cross-sectional view of the curved portion of the third upper conductive pattern UC3'.

[0229] refer to Figure 8B The third upper conductive pattern UC3' may include multiple layers. More specifically, the third upper conductive pattern UC3' may include a third-first upper conductive pattern U31', a third-second upper conductive pattern U32', and a third-third upper conductive pattern U33'. The third-first upper conductive pattern to the third-third upper conductive pattern U31' to U33' may have a structure in which multiple layers comprising titanium, aluminum, and titanium, respectively, are sequentially stacked.

[0230] Figure 8B The illustration shows a peeling phenomenon occurring due to the step difference RH' of the third-third upper conductive pattern U33'; however, this is for ease of explanation. As an example, peeling may occur in the third-first upper conductive pattern U31' and the third-second upper conductive pattern U32', or in the first upper conductive pattern UC1' (see reference). Figure 8A ) and the second conductive pattern UC2' (reference) Figure 8A In one or more embodiments, reference is made to... Figure 8B The description of the peeling phenomenon provided can also be applied to the first upper conductive pattern UC1' (see reference). Figure 8A ) and the second conductive pattern UC2' (reference) Figure 8A ).

[0231] refer to Figure 8B Due to the step difference RH', peeling may occur in the third-third upper conductive pattern U33', and therefore, an isolation space SP may be formed or arranged between the third-second upper conductive pattern U32' and the third-third upper conductive pattern U33'.

[0232] In commonly available or frequently used electronic devices, the third upper conductive pattern UC3' may be oxidized by moisture / oxygen that has seeped into the isolation space SP. Correspondingly, the pad PD' (refer to...) Figure 8A The reliability of the combination may deteriorate.

[0233] Figure 9A This is an enlarged cross-sectional view of the pad area of ​​an electronic device according to one or more embodiments of the present disclosure. Figure 9B yes Figure 9A A magnified view of region BB'.

[0234] exist Figure 9A In the reference, the pad area can correspond to the area selected from the reference. Figure 5A At least one of the first pad region PA1 and the second pad region PA2 described.

[0235] refer to Figure 9A An electronic device according to one or more embodiments may include a substrate IBL, a first insulating pattern ILD1 disposed on the substrate IBL, a second insulating pattern ILD2 disposed on the first insulating pattern ILD1, and pads PD. The substrate IBL may be connected to the base layer BL (see reference BL). Figure 5B Formed or arranged by substantially the same process, and may include elements similar to the reference. Figure 5B The described basal layer BL (reference) Figure 5B The materials are basically the same.

[0236] However, for ease of explanation, the component disposed between the substrate IBL and the first lower conductive pattern LC1 may be omitted, and this disclosure should not be limited to... Figure 9A The electronic device ED shown in the figure may have one or more organic and / or inorganic layers disposed between the substrate IBL and the first lower conductive pattern LC1.

[0237] Reference Figure 8A and Figure 8B Compared to the described electronic device, the electronic device ED according to one or more embodiments of this disclosure may further include a second insulating pattern ILD2.

[0238] The pad PD according to one or more embodiments of the present disclosure may include a first lower conductive pattern LC1, a second lower conductive pattern LC2, a first upper conductive pattern UC1, a second upper conductive pattern UC2, and a third upper conductive pattern UC3. For example, with reference to... Figure 8A and Figure 8B Compared to the described pad PD', the pad PD according to one or more embodiments of this disclosure may further include a second lower conductive pattern LC2.

[0239] The first conductive pattern LC1 can be disposed on the substrate IBL. The first conductive pattern LC1 can be included with the pixel PX (reference). Figure 5A The transistor TR (reference) Figure 5B The gate G in ) (reference) Figure 5B They are formed or arranged using essentially the same process and can be included with pixels PX (reference). Figure 5A The gate G in the transistor TR of ) comprises essentially the same material.

[0240] A first insulating pattern ILD1 can be disposed on a substrate IBL. The first insulating pattern ILD1 can cover a first lower conductive pattern LC1. A contact hole CNT can be defined through the upper and lower surfaces of the first insulating pattern ILD1. The contact hole CNT can be defined by the side surface I1S of the first insulating pattern ILD1.

[0241] When viewed in a planar plane (e.g., in a planar diagram), the contact hole CNT may overlap with the first lower conductive pattern LC1. A portion of the first lower conductive pattern LC1 may be exposed through the contact hole CNT. Accordingly, the first lower conductive pattern LC1 may be connected to the second lower conductive pattern LC2.

[0242] The second lower conductive pattern LC2 can be disposed on the first insulating pattern ILD1 and the first lower conductive pattern LC1. The second lower conductive pattern LC2 can be included in pixel PX (reference). Figure 5AThe gate in another transistor of the same type is formed or arranged using substantially the same process, and can be included with the gate of the pixel PX (reference). Figure 5A The gate of another transistor in the same transistor uses essentially the same material.

[0243] The second conductive pattern LC2 may include a first portion PT1 and a second portion PT2. Figure 9A In the illustration, the first portion PT1 and the second portion PT2 are separated by a diagonal dashed line parallel to the direction between the second direction DR2 and the third direction DR3. However, this is for ease of explanation, and the first portion PT1 and the second portion PT2 can be provided as a substantially continuous single unit. The second portion PT2 can extend from the first portion PT1 and can be provided as an integral part of the first portion PT1.

[0244] The first portion PT1 may cover the first lower conductive pattern LC1 exposed through the contact hole CNT. The first portion PT1 may contact the first lower conductive pattern LC1. Accordingly, the second lower conductive pattern LC2 may be electrically connected to the first lower conductive pattern LC1.

[0245] The second part PT2 may cover the side surface I1S and the top surface I1U of the first insulating pattern ILD1. The second part PT2 may be exposed by the second insulating pattern ILD2 without being covered by it.

[0246] The second insulating pattern ILD2 may include a second-first insulating pattern ILD2-1 and a second-second insulating pattern ILD2-2.

[0247] A second-first insulating pattern ILD2-1 may be disposed on the first portion PT1. At least a portion of the second-first insulating pattern ILD2-1 may be disposed inside the contact hole CNT. When viewed in a plane (e.g., in a plan view), the second-first insulating pattern ILD2-1 may have a shape extending along a first direction DR1. The second-first insulating pattern ILD2-1 may prevent step differences in the first upper conductive pattern UC1 (or may reduce the degree or incidence of step differences in the first upper conductive pattern UC1). More specifically, the second-first insulating pattern ILD2-1 may have a selective thickness IH, and therefore may prevent step differences in the first upper conductive pattern UC1 (or may reduce the degree or incidence of step differences in the first upper conductive pattern UC1).

[0248] The first insulating pattern ILD1 and the second insulating pattern ILD2 can be compared with the reference. Figure 5B The described insulating layers 10 to 60 and reference Figure 6AOne or more of the described sensing insulating layers IS-IL1 to IS-IL3 are formed or arranged by substantially the same process and can be compared with the reference. Figure 5B The described insulating layers 10 to 60 and reference Figure 6A One or more of the described sensing insulating layers IS-IL1 to IS-IL3 comprise substantially the same material. However, the first insulating pattern ILD1 may be formed or arranged after the formation or arrangement of the first lower conductive pattern LC1, and the second insulating pattern ILD2 may be formed or arranged after the formation or arrangement of the second lower conductive pattern LC2. In one or more embodiments, the first insulating pattern ILD1 and the second insulating pattern ILD2 may be formed or arranged before the formation or arrangement of the first upper conductive pattern LC1.

[0249] The first upper conductive pattern UC1 can be arranged on the second - first insulating pattern ILD2-1.

[0250] The first upper conductive pattern UC1 may be separated from and / or isolated from the first lower conductive pattern LC1 (e.g., spaced apart or separated).

[0251] The first upper conductive pattern UC1 may not contact the first portion PT1. The first upper conductive pattern UC1 may be spaced apart from and / or separated from the first portion PT1 (e.g., spaced apart or separated), and the second-first insulating pattern ILD2-1 may be disposed between the first upper conductive pattern UC1 and the first portion PT1, and therefore, the first upper conductive pattern UC1 may not contact the first portion PT1. Accordingly, the first upper conductive pattern UC1 may not be disposed inside the contact hole CNT.

[0252] However, the first upper conductive pattern UC1 can contact the second portion PT2. For example, the second portion PT2, which is exposed but not covered by the second insulating pattern ILD2, can contact the first upper conductive pattern UC1. The upper surface of the second portion PT2 can contact the first upper conductive pattern UC1.

[0253] The first upper conductive pattern UC1 can be electrically connected to the first lower conductive pattern LC1 via the second lower conductive pattern LC2. For example, the step difference in the first upper conductive pattern UC1 can be compensated by the second-first insulating pattern ILD2-1. The first upper conductive pattern UC1 can be electrically connected to the first lower conductive pattern LC1.

[0254] The first upper conductive pattern UC1 may not be arranged inside the contact hole CNT and may not be in direct contact with the first lower conductive pattern LC1. However, the first upper conductive pattern UC1 can be electrically connected to the first lower conductive pattern LC1 through the second part PT2 on the first insulating pattern ILD1.

[0255] Therefore, bending due to step difference will not occur in the first upper conductive pattern UC1, or bending due to step difference can be reduced. Figure 9A The diagram is consistent with the reference. Figure 8A The first upper conductive pattern UC1' described is compared to the first upper conductive pattern UC1 with a significantly or substantially reduced curvature.

[0256] A second upper conductive pattern UC2 can be disposed on a first upper conductive pattern UC1. The second upper conductive pattern UC2 can cover the first upper conductive pattern UC1. The shape of the second upper conductive pattern UC2 can be indirectly determined by the shape of the first upper conductive pattern UC1. For example, when the curvature (e.g., the degree or rate of curvature) of the first upper conductive pattern UC1 decreases, the curvature (e.g., the degree or rate of curvature) of the second upper conductive pattern UC2 can also decrease.

[0257] The second upper conductive pattern UC2 can be in contact with the first upper conductive pattern UC1. When viewed in a plane (e.g., in a planar view), the second upper conductive pattern UC2 can have a larger area than the first upper conductive pattern UC1.

[0258] Each edge U1E in the second upper conductive pattern UC2 may be spaced apart from and / or separated from the edge of the first insulating pattern ILD1 (e.g., spaced apart or separated), and may be arranged between the edge of the first insulating pattern ILD1 and the edge of the second-first insulating pattern ILD2-1.

[0259] The distance L1 between the uppermost part L2T of the second lower conductive pattern LC2 and the upper surface of the first lower conductive pattern LC1 can be greater than the distance L2 between the upper surface L2U of the second-first insulating pattern ILD2-1 and the first lower conductive pattern LC1.

[0260] In one or more embodiments, the second insulating pattern ILD2 may further include a second-second insulating pattern ILD2-2. The second-second insulating pattern ILD2-2 may be disposed on the first insulating pattern ILD1 and may be spaced apart from and / or separated from the second-first insulating pattern ILD2-1 (e.g., spaced apart or separated). The second-second insulating pattern ILD2-2 may cover the second lower conductive pattern LC2.

[0261] However, embodiments of this disclosure are not limited thereto, and the second-second insulating pattern ILD2-2 may not be provided.

[0262] Each of the first upper conductive pattern UC1 and the second upper conductive pattern UC2 may include multiple layers of metallic material that are sequentially stacked in a direction away from the first lower conductive pattern LC1.

[0263] The first upper conductive pattern UC1 can be selected from signal line SGL (reference). Figure 5A ) and connecting electrodes CNE1 and CNE2 (reference) Figure 5B One of them is formed or arranged through essentially the same process, and can be selected from signal lines SGL (reference). Figure 5A ) and connecting electrodes CNE1 and CNE2 (reference) Figure 5B One of them contains essentially the same material.

[0264] The second conductive pattern UC2 can be selected from signal line SGL (reference). Figure 5A ), connecting electrodes CNE1 and CNE2 (reference) Figure 5B ) and the first electrode AE ​​(reference) Figure 5B One of them is formed or arranged through essentially the same process, and can be selected from signal lines SGL (reference). Figure 5A ), connecting electrodes CNE1 and CNE2 (reference) Figure 5B ) and the first electrode AE ​​(reference) Figure 5B One of them includes substantially the same material. However, the first upper conductive pattern UC1 and the second upper conductive pattern UC2 can be formed or arranged by different processes from each other, and the first upper conductive pattern UC1 can be formed or arranged before the second upper conductive pattern UC2 is formed.

[0265] In one or more embodiments, each of the first upper conductive pattern UC1 and the second upper conductive pattern UC2 may include a first layer containing titanium, a second layer containing aluminum, and a third layer containing titanium, wherein the first, second, and third layers are sequentially stacked on a third-direction DR3.

[0266] The third upper conductive pattern UC3 can be disposed on the second upper conductive pattern UC2. The shape of the third upper conductive pattern UC3 can be indirectly determined by the shape of the second upper conductive pattern UC2. For example, when the curvature (e.g., the degree or rate of curvature) of the first upper conductive pattern UC1 decreases, the curvature (e.g., the degree or rate of curvature) of the second upper conductive pattern UC2 and the third upper conductive pattern UC3 can also decrease. Each edge U2E of the edges U2E of the third upper conductive pattern UC3 can be spaced apart and / or separated from the edge U1E of the second upper conductive pattern UC2 (e.g., spaced apart or separated), and can be disposed between the edge U1E of the second upper conductive pattern UC2 and the edge of the second-first insulating pattern ILD2-1.

[0267] In one or more embodiments, the third upper conductive pattern UC3 may be connected to the second sensing conductive layer IS-CL2 (reference). Figure 6AThe third upper conductive pattern UC3 can be formed or arranged together in a single process and may comprise substantially the same material as the second sensing conductive layer IS-CL2; however, embodiments of this disclosure are not limited thereto. As an example, the third upper conductive pattern UC3 may be formed together with the first sensing conductive layer IS-CL1 (see reference UC3). Figure 6A They are formed or arranged together through a single process and may include substantially the same material as the first sensing conductive layer IS-CL1.

[0268] According to one or more embodiments, the third upper conductive pattern UC3 may include a first layer and a second layer disposed on the first layer. The first layer may be formed or disposed together with the first sensing conductive layer IS-CL1 in a single process, and may comprise substantially the same material as the first sensing conductive layer IS-CL1. The second layer may be formed or disposed together with the second sensing conductive layer IS-CL2 in a single process, and may comprise substantially the same material as the second sensing conductive layer IS-CL2.

[0269] Figure 9B yes Figure 9A A magnified cross-sectional view of region BB'. (Reference) Figure 9B The third upper conductive pattern UC3 may include multiple layers. More specifically, the third upper conductive pattern UC3 may include a third-first upper conductive pattern U31, a third-second upper conductive pattern U32, and a third-third upper conductive pattern U33. The third-first upper conductive pattern to the third-third upper conductive pattern U31 to U33 may have a structure in which multiple layers comprising titanium, aluminum, and titanium are sequentially stacked.

[0270] Figure 9B The illustration shows an example of a state where no peeling has occurred in the third-third upper conductive pattern U33. For example, compared with the reference... Figure 8B Compared to the step difference RH' in the described comparative example, the step difference RH in one or more embodiments of this disclosure can be reduced.

[0271] For example, in the electronic device according to this disclosure, the second insulating pattern ILD2 (reference) Figure 9A ) and the second lower conductive pattern LC2 (reference) Figure 9A This can prevent or reduce bending and peeling. Accordingly, the conductivity (e.g., electrical conductivity) of each layer can be maintained, and the bonding reliability can be maintained.

[0272] Figure 9C This is an enlarged plan view of the pad area according to one or more embodiments of the present disclosure.

[0273] In the following text, for ease of explanation, the area where the second upper conductive pattern UC2 is arranged can be defined as the second upper region U2A, the area where the first upper conductive pattern UC1 is arranged can be defined as the first upper region U1A, and the second-first insulating pattern ILD2-1 (see reference) is arranged. Figure 9A The region can be defined as the insulating region I2A.

[0274] refer to Figure 9C When viewed (e.g., in a plan view), the second upper region U2A may include the first upper region U1A, and the first upper region U1A may include the insulating region I2A.

[0275] Figure 9D This is a cross-sectional view illustrating the combined structure of an electronic device according to one or more embodiments of the present disclosure.

[0276] In the following description, the driver chip DC and the first bump BP1 will be used as examples of electronic components and bumps, respectively; however, the embodiments of this disclosure are not limited thereto. Except as otherwise provided... Figure 2A and Figure 2B Other electronic components besides the described driver chip DC can also be used as electronic components. In one or more embodiments, the description of the first bump BP1 can be applied in kind / similarly to the second bump BP2 (see reference). Figure 7 ) or substrate bump PB-BP (reference) Figure 7 ).

[0277] Figure 9D The diagram illustrates, as an example, the structure in which the first bump BP1 of the driver chip DC contacts the third upper conductive pattern UC3.

[0278] The first bump BP1 of the driver chip DC can contact the third upper conductive pattern UC3 due to bonding pressure after penetrating the first adhesive layer CF1. Although the step difference is reduced, the third upper conductive pattern UC3 may include a protrusion PR protruding on the third directional DR3.

[0279] For ease of explanation, in Figure 9D In the middle, the protruding part PR formed or arranged in the third upper conductive pattern UC3 is indicated by a dashed line.

[0280] In one or more embodiments, conductive (e.g., electrically conductive) balls included in the first adhesive layer CF1 may be arranged between the protrusion PR of the third upper conductive pattern UC3 and the first bump BP1. Therefore, the first bump BP1 can ensure an electrical connection path with the protrusion PR.

[0281] As described in one or more embodiments, the electronic device ED according to this disclosure can prevent or reduce the occurrence of conductive pattern peeling because it can compensate for step differences, and can maintain electrical contact between the conductive pattern and the bumps. Accordingly, the bonding reliability of the electronic device can be improved or enhanced, and the reliability of the electronic device can be improved or enhanced.

[0282] The first bump BP1, the first upper conductive pattern UC1, the second upper conductive pattern UC2, the third upper conductive pattern UC3, the first lower conductive pattern LC1, and the second lower conductive pattern LC2 can be electrically connected to each other.

[0283] Figure 10A This is an enlarged cross-sectional view of the pad area of ​​an electronic device according to one or more embodiments of the present disclosure. Figure 10B This is an enlarged plan view of the pad area of ​​an electronic device according to one or more embodiments of the present disclosure. Figure 10C This is a cross-sectional view of the combined structure of an electronic device according to one or more embodiments of the present disclosure.

[0284] In the following text, Figures 10A to 10C In the figures, the same / similar reference numerals indicate the same as... Figures 1 to 9D The components in the text are essentially the same, and therefore, it is not necessary to provide repeated descriptions of essentially the same / similar components.

[0285] refer to Figure 10A The electronic device ED-1 may include a substrate IBL, a first insulating pattern ILD1-1 disposed on the substrate IBL, a second insulating pattern ILD2-1' disposed on the first insulating pattern ILD1-1, and a pad PD-1.

[0286] In one or more embodiments, pad PD-1 may include a first lower conductive pattern LC1-1, a second lower conductive pattern LC2-1, a first upper conductive pattern UC1-1, a second upper conductive pattern UC2-1, and a third upper conductive pattern UC3-1.

[0287] Multiple contact holes CNTa and CNTb can be defined through the first insulating pattern ILD1-1. For example, with reference... Figure 9A The first insulating pattern ILD1 described (reference) Figure 9A Unlike other types of contact holes, multiple contact holes CNTa and CNTb can be defined by passing through the upper and lower surfaces of the first insulating pattern ILD1-1.

[0288] The first conductive pattern LC1-1 can be exposed through each of the contact holes CNTa and CNTb.

[0289] The second lower conductive pattern LC2-1 may include a first portion PT1 that contacts the first lower conductive pattern LC1-1 exposed through each of the contact holes CNTa and CNTb, and second portions PT2-1 and PT2-2 that cover the side and top surfaces of the first insulating pattern ILD1-1. The second portions PT2-1 and PT2-2 may include a second-first portion PT2-1 disposed between adjacent first portions PT1 and a second-second portion PT2-2 other than the second-first portion PT2-1.

[0290] In one or more embodiments, the second insulating pattern ILD2-1' can be provided as a plurality. For example, the number of second insulating patterns ILD2-1' can be substantially the same as the number of contact holes CNTa and CNTb. The second insulating patterns ILD2-1' can be arranged inside the contact holes CNTa and CNTb respectively to prevent step differences in the first upper conductive pattern UC1-1 (or reduce the degree or occurrence of step differences in the first upper conductive pattern UC1-1). When viewed in a plane (e.g., in a plan view), the second insulating pattern ILD2-1' can have a shape extending along the first direction DR1.

[0291] The second upper conductive pattern UC2-1 and the third upper conductive pattern UC3-1 can be arranged sequentially on the first upper conductive pattern UC1-1. The shape of the second upper conductive pattern UC2-1 can be indirectly determined by the shape of the first upper conductive pattern UC1-1, and the shape of the third upper conductive pattern UC3-1 can be indirectly determined by the shape of the second upper conductive pattern UC2-1.

[0292] Figure 10A The diagram is consistent with the reference. Figure 8A The first upper conductive pattern UC1' described is used as an example compared to the first upper conductive pattern UC1-1 which has a significantly reduced or obvious bend.

[0293] In the following text, for ease of explanation, the area where the second upper conductive pattern UC2-1 is arranged can be defined as the second upper region U2A-1, the area where the first upper conductive pattern UC1-1 is arranged can be defined as the first upper region U1A-1, and the area where the second insulating pattern ILD2-1' is arranged can be defined as the insulating regions I2Aa and I2Ab. Reference Figure 10B When viewed (e.g., in a plan view), the second upper region U2A-1 may include the first upper region U1A-1, and the first upper region U1A-1 may include insulating regions I2Aa and I2Ab.

[0294] Figure 10CThe illustration shows a driver chip DC as an electronic component. In one or more embodiments, conductive (e.g., electrically conductive) balls included in the first adhesive layer CF1 may be arranged between the first bump BP1 and the third upper conductive pattern UC3-1.

[0295] The first bump BP1 of the driver chip DC can contact the third upper conductive pattern UC3-1 due to bonding pressure after penetrating the first adhesive layer CF1. Although the step difference is reduced, the third upper conductive pattern UC3 may include a protrusion PR-1.

[0296] Figure 11 This is an enlarged cross-sectional view of the pad area of ​​an electronic device according to one or more embodiments of the present disclosure.

[0297] In the following text, Figure 11 In the figures, the same / similar reference numerals indicate the same as... Figures 1 to 10C The components in the text are essentially the same, and therefore, it is not necessary to provide repeated descriptions of essentially the same / similar components.

[0298] refer to Figure 11 The electronic device ED-2 may include a substrate IBL, a first insulating pattern ILD1 disposed on the substrate IBL, a second insulating pattern ILD2-2' disposed on the first insulating pattern ILD1, and a pad PD-2. In one or more embodiments, the pad PD-2 may include a first lower conductive pattern LC1-2, a second lower conductive pattern LC2-2, a first upper conductive pattern UC1-2, a second upper conductive pattern UC2-2, and a third upper conductive pattern UC3-2. The third upper conductive pattern UC3-2 may include a protrusion PR-2 protruding from a third-direction DR3.

[0299] The second insulating pattern ILD2-2' may include a second-first insulating pattern ILD2c and a second-second insulating pattern ILD2s.

[0300] Reference Figure 10A The second insulating pattern ILD2-1' described (reference) Figure 10A In contrast, the second insulating pattern ILD2-2' according to one or more embodiments of the present disclosure may further include a second-second insulating pattern ILD2s.

[0301] The second insulating pattern ILD2s can be arranged on the first insulating pattern ILD1. The second insulating pattern ILD2s can cover the second lower conductive pattern LC2-2.

[0302] The second-second insulating pattern ILD2s can be covered by one or more of the first upper conductive pattern UC1-2, the second upper conductive pattern UC2-2, and the third upper conductive pattern UC3-2. Figure 11 The diagram illustrates a structure in which the second-second insulating pattern ILD2s is covered by the first upper conductive pattern UC1-2 and the second upper conductive pattern UC2-2.

[0303] The second-second insulating pattern ILD2s can be exposed by the first upper conductive pattern UC1-2, the second upper conductive pattern UC2-2 and the third upper conductive pattern UC3-2.

[0304] The second-second insulating pattern ILD2s can prevent pad PD-2 from being electrically connected to another pad adjacent to pad PD-2 (or reduce the degree or occurrence of pad PD-2 being electrically connected to another pad adjacent to pad PD-2).

[0305] Figure 12 This is an enlarged cross-sectional view of the pad area of ​​an electronic device according to one or more embodiments of the present disclosure.

[0306] In the following text, Figure 12 In the figures, the same / similar reference numerals indicate the same as... Figures 1 to 10C The components in the text are essentially the same, and therefore, it is not necessary to provide repeated descriptions of essentially the same / similar components.

[0307] The electronic device ED-3 may include a substrate IBL, a first insulating pattern ILD1 disposed on the substrate IBL, a second insulating pattern ILD2-3 disposed on the first insulating pattern ILD1, and a pad PD-3.

[0308] The pad PD-3 may include a first lower conductive pattern LC1-3, a second lower conductive pattern LC2-3, a first upper conductive pattern UC1-3, a second upper conductive pattern UC2-3, and a third upper conductive pattern UC3-3.

[0309] The second insulating pattern ILD2-3 can be arranged on the first lower conductive pattern LC1-3.

[0310] The second insulating pattern ILD2-3 may include a second-first insulating portion IPT21 and a second-second insulating portion IPT22. (Refer to reference...) Figure 10A Compared to the described second insulating pattern ILD2-1', the second insulating pattern ILD2-3 according to one or more embodiments of the present disclosure may further include a second-second insulating portion IPT22.

[0311] exist Figure 12In the diagram, the second-first insulating portion IPT21 and the second-second insulating portion IPT22 are distinguished from each other by dashed lines, however, this is for ease of explanation. According to one or more embodiments, the second-first insulating portion IPT21 and the second-second insulating portion IPT22 can be provided as a substantially continuous single unit.

[0312] The second-first insulating portion IPT21 can be disposed on the second lower conductive pattern LC2-3. At least a portion of the second-first insulating portion IPT21 can be disposed inside the first contact hole CNTa and the second contact hole CNTb, respectively. The second-first insulating portion IPT21 can be in direct contact with the second lower conductive pattern LC2-3.

[0313] The second-second insulating portion IPT22 may be defined by the portion of the second insulating pattern ILD2-3 other than the second-first insulating portion IPT21. For example, the second-second insulating portion IPT22 may be a portion of the second insulating pattern ILD2-3 that extends from the second-first insulating portion IPT21 and protrudes beyond the upper surface of the second lower conductive pattern LC2-3.

[0314] The second insulating portion IPT22 can cover the upper surface of the second lower conductive pattern LC2-3. Figure 12 The illustration shows, for example, a second-second insulating portion IPT22 extending inward from the second-first insulating portion IPT21 relative to the pad PD-3 when viewed in a plane (e.g., in a plan view); however, embodiments of this disclosure are not limited thereto. As an example, the second-second insulating portion IPT22 may extend from the second-first insulating portion IPT21 in a direction outward relative to the pad PD-3.

[0315] refer to Figure 12 Because the protruding portion PR-3 overlaps with the second-second insulating portion IPT22, the protruding portion PR-3 can protrude beyond the thickness of the second-second insulating portion IPT22. For example, compared with the reference... Figure 10C Compared to the described protrusion PR-1, the protrusion PR-3 according to one or more embodiments of the present disclosure may protrude the thickness of the second-second insulating portion IPT22 onto the third-party DR3. Accordingly, the protrusion PR-3 according to one or more embodiments of the present disclosure relative to the first bump BP1 (see reference PR-1) may be improved or increased. Figure 9D The reliability of the combination.

[0316] The display device, electronic device, electronic device, means therefor, and / or any other related means or components according to one or more embodiments of this disclosure may be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuit), software, or a combination of software, firmware, and hardware (e.g., any suitable). For example, one or more components of the device may be provided on a single integrated circuit (IC) chip or multiple discrete IC chips. Further, one or more components of the device may be implemented on a flexible printed circuit film, a tape-on-a-package (TCP), and / or a printed circuit board (PCB), or provided on a substrate. Further, one or more components of the device may be a process or thread that runs on one or more processors in one or more computing devices, executes computer program instructions, and interacts with other system components to perform one or more functions described herein. The computer program instructions may be stored in a memory that may be implemented in a computing device using a standard memory device, such as random access memory (RAM). The computer program instructions may also be stored in other non-transitory computer-readable media, such as CD-ROMs and / or flash drives. Furthermore, those skilled in the art should recognize that the functions of one or more computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed across one or more other computing devices without departing from the scope of this disclosure.

[0317] Although one or more embodiments of this disclosure have been described, it should be understood that this disclosure is not intended to be limited to these embodiments, but rather that one or more suitable changes and modifications can be made by those skilled in the art within the spirit and scope of the claimed disclosure and its equivalents. Therefore, the subject matter disclosed should not be limited to any single embodiment described herein, and the scope of this disclosure should be determined by the claims and their equivalents.

Claims

1. An electronic device comprising: basal layer; Pixels located on the base layer; Signal lines electrically connected to the pixel; as well as The pads connected to the signal lines, each of the pads comprising: The first conductive pattern is located on the substrate layer; A first insulating pattern, a contact hole extending through the first insulating pattern to expose a portion of a first lower conductive pattern, the first insulating pattern covering the first lower conductive pattern; The second lower conductive pattern includes a first portion covering the first lower conductive pattern exposed through the contact hole and a second portion extending from the side surface of the first insulating pattern defining the contact hole, the second portion covering the upper surface of the first insulating pattern. The second-first insulating pattern is located on the first portion; A first conductive pattern is located on the second-first insulating pattern; and The second upper conductive pattern is located on the first upper conductive pattern and is in contact with the first upper conductive pattern.

2. The electronic device according to claim 1, wherein, The first upper conductive pattern does not contact the first portion, but contacts the second portion.

3. The electronic device according to claim 1, wherein, The contact hole overlaps with the first lower conductive pattern in the plan view.

4. The electronic device according to claim 1, wherein, The second upper conductive pattern has a larger area in the plan view than the first upper conductive pattern.

5. The electronic device according to claim 1, wherein, Each edge of the second upper conductive pattern is spaced apart from the edge of the first insulating pattern and is located between the edge of the first insulating pattern and the edge of the second-first insulating pattern.

6. The electronic device according to claim 1, wherein, The first upper conductive pattern is separated from the first lower conductive pattern.

7. The electronic device according to claim 1, wherein, At least a portion of the second-first insulating pattern is located inside the contact hole.

8. The electronic device according to claim 1, wherein, The distance between the uppermost part of the second lower conductive pattern and the first lower conductive pattern is greater than the distance between the upper surface of the second-first insulating pattern and the first lower conductive pattern.

9. The electronic device according to claim 1, further comprising: The second-second insulating pattern is located on the first insulating pattern and is spaced apart from the second-first insulating pattern.

10. The electronic device according to claim 9, wherein, The second insulating pattern covers the second lower conductive pattern.

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