Magnetic storage device, method of manufacturing the same, and storage apparatus including the same

Abstract

Magnetic storage devices, methods of manufacturing the same, and storage devices including the same are provided. A magnetic storage device includes a spin-orbit torque (SOT) generation layer configured to generate a SOT, a spin current transfer layer on a lower surface of the SOT generation layer, and a tunneling magnetoresistive layer on a lower surface of the spin current transfer layer and including a free layer, a tunnel barrier layer, and a pinned layer. The spin current transfer layer is configured to transfer the spin current generated from the SOT generation layer to the free layer.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2024-0177587 filed with the Korean Intellectual Property Office on December 3, 2024, and Korean Patent Application No. 10-2025-0126785 filed with the Korean Intellectual Property Office on September 5, 2025, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] Some exemplary embodiments of the present invention relate to magnetic storage devices including tunneling magnetoresistive layers, methods of manufacturing said magnetic storage devices, and / or storage devices including said magnetic storage devices. Background Technology

[0004] Magnetic storage devices, such as magnetic random access memory (MRAM), store data by using variations in the resistance of a magnetic tunnel junction device. The resistance of a magnetic tunnel junction device varies with the magnetization direction of the free layer. For example, when the magnetization direction of the free layer is the same as that of the pinned layer, the magnetic tunnel junction device can have a relatively low resistance, and when these magnetization directions are opposite to each other, the magnetic tunnel junction device can have a relatively high resistance. For instance, when using this characteristic in a storage device, a magnetic tunnel junction device can represent the data "0" with relatively low resistance, and it can represent the data "1" with relatively high resistance.

[0005] Such magnetic storage devices offer advantages such as non-volatility, relatively high-speed operation, and / or relatively high durability. For example, currently mass-produced spin-transfer torque magnetic RAM (STT-MRAM) can achieve operating speeds of approximately 50 to 100 nsec and can also provide improved data retention of 10 years or more. Furthermore, spin-orbit torque (SOT)-MRAM can achieve relatively very high operating speeds of less than or equal to 5 nsec, which is faster than STT-MRAM because the spin polarization direction is perpendicular to the magnetization direction. Moreover, because the paths for write and read currents are different from each other, SOT-MRAM can exhibit more stable characteristics. Summary of the Invention

[0006] Some example embodiments of this disclosure provide a magnetic storage device including a tunneling magnetoresistive layer and a storage device including the magnetic storage device.

[0007] Some example embodiments of this disclosure provide methods for manufacturing magnetic storage devices including tunneling magnetoresistive layers.

[0008] Other aspects will be set forth in part in the description which follows, and will be apparent in part from the description, or may be learned by practicing the exemplary embodiments presented in this disclosure.

[0009] According to an example embodiment, a method of manufacturing a magnetic storage device includes: sequentially forming a pinning layer material, a tunnel barrier layer material, a free layer material, and a spin current transfer layer material on an electrode material; forming a mask layer on the spin current transfer layer material; forming a first electrode, pinning layer, tunnel barrier layer, free layer, and spin current transfer layer by removing the spin current transfer layer material, free layer material, tunnel barrier layer material, pinning layer material, and electrode material exposed by a first etching process; forming an insulating layer to surround the side surfaces of the first electrode, pinning layer, tunnel barrier layer, free layer, and spin current transfer layer and to cover the side and top surfaces of the mask layer; performing a second etching process until the top surface of the spin current transfer layer is exposed; and forming a spin orbital moment (SOT) generation layer in contact with the top surface of the spin current transfer layer.

[0010] The method may also include forming a second electrode and a third electrode on the upper surface of the SOT generation layer, the second electrode and the third electrode being spaced apart from each other.

[0011] The SOT forming layer may include at least one material selected from iridium (Ir), manganese (Mn), vanadium (V), chromium (Cr), niobium (Nb), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), tungsten (W), titanium (Ti), rhenium (Re), platinum (Pt), tungsten (W) with a beta (β) phase, or alloys thereof.

[0012] The spin current transfer layer may include platinum (Pt).

[0013] The first etching process can be performed using ion beam etching (IOE).

[0014] The second etching process may include: planarizing the upper surface of the insulating layer until the mask layer is exposed; and removing the mask layer by reactive ion etching (RIE) and further planarizing the insulating layer.

[0015] According to an example embodiment, a magnetic storage device includes: a spin orbital moment (SOT) generation layer configured to generate SOT; a spin current transfer layer on a lower surface of the SOT generation layer; and a tunneling magnetoresistive layer on the lower surface of the spin current transfer layer, comprising a free layer, a tunneling barrier layer, and a pinning layer, wherein the spin current transfer layer is configured to transfer spin current generated from the SOT generation layer to the free layer, the SOT generation layer comprising at least one material selected from iridium (Ir), manganese (Mn), vanadium (V), chromium (Cr), niobium (Nb), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), tungsten (W), titanium (Ti), rhenium (Re), platinum (Pt), tungsten (W) having a beta (β) phase, or alloys thereof, and the spin current transfer layer comprising platinum (Pt).

[0016] The SOT generation layer may include an orbital Hall conductivity layer configured to provide an orbital Hall current due to the orbital Hall effect (OHE), and the orbital Hall conductivity layer may include at least one material selected from iridium (Ir), manganese (Mn), vanadium (V), chromium (Cr), niobium (Nb), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), tungsten (W), titanium (Ti), rhenium (Re), or alloys thereof.

[0017] The orbital Hall conductivity layer may include a first orbital Hall conductivity layer on a spin current transfer layer and a second orbital Hall conductivity layer on the first orbital Hall conductivity layer, and each of the first orbital Hall conductivity layer and the second orbital Hall conductivity layer includes at least one material different from each other, namely iridium (Ir), manganese (Mn), vanadium (V), chromium (Cr), niobium (Nb), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), tungsten (W), titanium (Ti), rhenium (Re), or alloys thereof.

[0018] The SOT generation layer may include a spin Hall conductivity layer configured to provide a spin Hall current due to the spin Hall effect (SHE), and the spin Hall conductivity layer may include platinum (Pt) or tungsten (W) having a beta (β) phase.

[0019] The thickness of the spin current transfer layer can be approximately 0.1 nm or more and approximately 10 nm or less.

[0020] The SOT generation layer may include: an orbital Hall conductivity layer on the spin current transfer layer and configured to provide an orbital Hall current due to OHE; and a spin Hall conductivity layer on the orbital Hall conductivity layer and configured to provide a spin Hall current through SHE.

[0021] The SOT generation layer may include: a spin Hall conductivity layer on the spin current transfer layer and configured to provide a spin Hall current due to SHE; and an orbital Hall conductivity layer on the spin Hall conductivity layer and configured to provide an orbital Hall current through OHE.

[0022] The magnetic storage device may further include an oxide layer between the free layer and the spin current transfer layer, and the oxide layer may include at least one of magnesium oxide (MgO), tantalum oxide (TaO), magnesium aluminum oxide (MgAlOx), aluminum oxide (AlOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), magnesium tantalum oxide (MgTaOx), titanium oxide (TiOx) or tungsten oxide (WOx).

[0023] The magnetic storage device may further include a diffusion barrier metal layer between the free layer and the spin current transfer layer, and the diffusion barrier metal layer may have a single-layer or multi-layer structure of at least one metal selected from tantalum (Ta), tungsten (W), iridium (Ir), titanium (Ti), rhenium (Re), cobalt (Co), or alloys thereof.

[0024] The pinning layer may include a first ferromagnetic layer, a second ferromagnetic layer, and an antiferromagnetic coupling layer between the first ferromagnetic layer and the second ferromagnetic layer, and the magnetization direction of the first ferromagnetic layer may be opposite to the magnetization direction of the second ferromagnetic layer.

[0025] The magnetic storage device may also include a first electrode electrically connected to the pinning layer, and a second and third electrode spaced apart from each other on the SOT generation layer.

[0026] Multiple tunneling magnetoresistive layers and multiple spin current transfer layers can correspond to a single SOT generation layer.

[0027] The SOT formation layer may include at least one material selected from platinum (Pt), iridium (Ir), ruthenium (Ru), or titanium (Ti).

[0028] The magnetic storage device may further include: a plurality of first electrodes electrically connected to corresponding pinning layers among a plurality of pinning layers of a plurality of tunneling magnetoresistive layers; and second and third electrodes spaced apart from each other on the SOT generation layer.

[0029] According to an example embodiment, a storage device includes a plurality of storage cells, each storage cell including a magnetic storage device and a switching device connected to the magnetic storage device. The magnetic storage device includes: a SOT generation layer configured to generate SOT; a spin current transfer layer on a lower surface of the SOT generation layer; and a tunneling magnetoresistive layer on the lower surface of the spin current transfer layer and including a free layer, a tunneling barrier layer, and a pinning layer. The spin current transfer layer is configured to transfer spin current generated from the SOT generation layer to the free layer. The SOT generation layer includes at least one material selected from iridium (Ir), manganese (Mn), vanadium (V), chromium (Cr), niobium (Nb), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), tungsten (W), titanium (Ti), rhenium (Re), platinum (Pt), tungsten (W) having a beta (β) phase, or alloys thereof. The spin current transfer layer includes platinum (Pt). Attached Figure Description

[0030] The above and other aspects, features, and advantages of certain exemplary embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, wherein:

[0031] Figure 1 This is a cross-sectional view illustrating a schematic configuration of a magnetic storage device according to an example embodiment;

[0032] Figure 2 It shows the arrangement in Figure 1 A cross-sectional view of the wiring structure in the lower part of the magnetic storage device shown;

[0033] Figure 3 This is a cross-sectional view illustrating a schematic configuration of a magnetic storage device according to another example embodiment;

[0034] Figures 4A to 4I It is a schematic representation of manufacturing. Figure 1 A cross-sectional view of the method for the magnetic storage device shown;

[0035] Figure 5 This is a cross-sectional view illustrating a schematic configuration of a magnetic storage device according to another example embodiment;

[0036] Figure 6 This is a cross-sectional view illustrating a schematic configuration of a magnetic storage device according to another example embodiment;

[0037] Figure 7 This is a cross-sectional view illustrating a schematic configuration of a magnetic storage device according to another example embodiment;

[0038] Figure 8 This is a cross-sectional view illustrating a schematic configuration of a magnetic storage device according to another example embodiment;

[0039] Figure 9This is a cross-sectional view illustrating a schematic configuration of a magnetic storage device according to another example embodiment;

[0040] Figure 10 This is a cross-sectional view illustrating a schematic configuration of a magnetic storage device according to another example embodiment;

[0041] Figure 11 This is a cross-sectional view illustrating a schematic configuration of a magnetic storage device according to another example embodiment;

[0042] Figure 12 The illustration schematically depicts a magnetic storage cell including a magnetic storage device according to an example embodiment;

[0043] Figure 13 It is schematically shown that includes Figure 12 A circuit diagram showing the configuration of a storage device with multiple storage cells;

[0044] Figure 14 This is a schematic cross-sectional view illustrating the configuration of a storage device according to another example embodiment; and

[0045] Figure 15 It is a conceptual diagram that schematically illustrates a device architecture applicable to electronic devices. Detailed Implementation

[0046] Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings, wherein the same reference numerals always denote the same elements. In this respect, these exemplary embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, these exemplary embodiments are described below only by reference to the accompanying drawings to explain various aspects. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. As used herein, expressions such as “one of…”, “one or more of…”, “any one of…”, “at least one of…”, “at least one of…”, and “selected from at least one of…” when preceding a list of elements modify the entire list of elements, without modifying the individual elements in the list. Thus, for example, “at least one of A, B, or C” and “at least one of A, B, and C” both mean A, B, C, or any combination thereof. Similarly, A and / or B means A, B, or A and B.

[0047] Although the term "identical" is used in the description of the example embodiments, it should be understood that some inaccuracies may exist. Therefore, when an element is referred to as being identical to another element, it should be understood that one element is identical to the other element within a range of expected manufacturing tolerances (e.g., ±10%).

[0048] When the terms “approximately” or “substantially” are used in conjunction with numerical values ​​in this specification, the numerical values ​​intended to be associated include manufacturing tolerances (e.g., ±10%) around said numerical values. Furthermore, when the terms “approximately” and “substantially” are used in conjunction with geometry, it is intended that the precision of the geometry is not required, but rather the tolerance of the shape within the scope of this disclosure. Moreover, regardless of whether numerical values ​​or shapes are modified to “approximately” or “substantially”, it should be understood that these values ​​and shapes should be interpreted as including manufacturing or operational tolerances (e.g., ±10%) around said numerical values ​​or shapes.

[0049] In the following description, with reference to the accompanying drawings, a magnetic storage device, a method of manufacturing a magnetic storage device, and a storage apparatus including a magnetic storage device will be described in detail. The same reference numerals always denote the same elements, and the dimensions of elements may be exaggerated in the drawings for clarity and ease of explanation. The exemplary embodiments described below are merely examples, and various modifications can be made from the exemplary embodiments.

[0050] In the layered structure described below, the expression "above / below" can include not only "directly above / below" in a contact manner, but also "above / below" in a non-contact manner. A singular expression covers a plural expression unless it has a distinctly different meaning in the context. It will be further understood that the terms "comprising" and / or "including" as used herein specify the presence of the stated feature or element, but do not preclude the presence or addition of one or more other features or elements.

[0051] The use of “the” and other similar indicator words can correspond to both the singular and plural forms. Unless explicitly mentioned or otherwise described, the order of operations according to the method of this disclosure may be performed in any appropriate order. This disclosure is not limited to the order in which the operations are mentioned.

[0052] In the example embodiments, terms such as “unit” or “module” are used to indicate a unit for processing at least one function or operation, and may be implemented in hardware or software, or a combination of hardware and software.

[0053] The connecting lines or connectors shown in the various accompanying figures are intended to represent functional relationships and / or physical or logical couplings between various components. It should be noted that many alternative or additional functional relationships, physical connections, or logical connections may exist in actual equipment.

[0054] Unless otherwise stated, any and all examples or language used herein are intended only to better illustrate this disclosure and do not constitute a limitation on the scope of this disclosure.

[0055] Figure 1 This is a cross-sectional view illustrating a schematic configuration of a magnetic storage device 100 according to an example embodiment. (Refer to...) Figure 1 The magnetic storage device 100 according to an example embodiment may include a tunneling magnetoresistive layer 120, a spin current transfer layer 131, and an orbital Hall conductivity layer 132 disposed on the spin current transfer layer 131. The tunneling magnetoresistive layer 120 and the orbital Hall conductivity layer 132 may face each other, and the spin current transfer layer 131 may be disposed between the tunneling magnetoresistive layer 120 and the orbital Hall conductivity layer 132.

[0056] The tunneling magnetoresistive layer 120 may include a pinned layer 121, a tunnel barrier layer 122 disposed on the pinned layer 121, and a free layer 123 disposed on the tunnel barrier layer 122. The pinned layer 121 and the free layer 123 may face each other, and the tunnel barrier layer 122 may be disposed between the pinned layer 121 and the free layer 123. A spin current transfer layer 131 may be disposed on the free layer 123. An orbital Hall conductivity layer 132 may be configured to face the free layer 123, and the spin current transfer layer 131 may be disposed between the orbital Hall conductivity layer 132 and the free layer 123.

[0057] When the configuration of the magnetic storage device 100 is described from top to bottom, the magnetic storage device 100 may include an orbital Hall conductivity layer 132, a spin current transfer layer 131 disposed on the lower surface of the orbital Hall conductivity layer 132, and a tunneling magnetoresistive layer 120 disposed on the lower surface of the spin current transfer layer 131. The tunneling magnetoresistive layer 120 may be configured to face the lower surface of the orbital Hall conductivity layer 132 from the bottom. The spin current transfer layer 131 may be disposed between the lower surface of the orbital Hall conductivity layer 132 and the upper surface of the tunneling magnetoresistive layer 120. The tunneling magnetoresistive layer 120 may include a free layer 123, a tunnel barrier layer 122, and a pinning layer 121 from top to bottom. The free layer 123 may be configured to face the lower surface of the orbital Hall conductivity layer 132 from the bottom. The spin current transfer layer 131 can be disposed between the lower surface of the orbital Hall conductivity layer 132 and the upper surface of the free layer 123. The free layer 123 can be in contact with the lower surface of the spin current transfer layer 131.

[0058] Pinned layer 121 and free layer 123 may each comprise a magnetic ferromagnetic metallic material. For example, pinned layer 121 and free layer 123 may each comprise at least one ferromagnetic material selected from iron (Fe), cobalt (Co), nickel (Ni), manganese (Mn), Fe-containing alloys, Co-containing alloys, Ni-containing alloys, Mn-containing alloys, or Heusler alloys. Pinned layer 121 and free layer 123 may comprise the same ferromagnetic material, but the exemplary embodiments are not limited thereto. Furthermore, free layer 123 may further comprise boron (B) to improve the wetting properties of free layer 123 during deposition on tunnel barrier layer 122. For example, free layer 123 may comprise CoFeB.

[0059] Furthermore, each of the pinned layer 121 and the free layer 123 can be configured to have high perpendicular magnetic anisotropy (PMA). In other words, the PMA energy of each of the pinned layer 121 and the free layer 123 can exceed the out-of-plane magnetization energy. In this case, the magnetic moment of each of the pinned layer 121 and the free layer 123 can be stable in the thickness direction (e.g., the Z direction) or in a direction perpendicular to the horizontal or planar direction (e.g., the X direction).

[0060] Pinned layer 121 can have a pinned magnetization direction. Once determined, the magnetization direction of pinned layer 121 can remain unchanged. On the other hand, free layer 123 can have a variable magnetization direction. Tunneling magnetoresistance layer 120 can have relatively low resistance when the magnetization directions of pinned layer 121 and free layer 123 are the same, and can have relatively high resistance when the magnetization directions of pinned layer 121 and free layer 123 are opposite. This phenomenon is called tunneling magnetoresistance (TMR).

[0061] The free layer 123 can have a relatively low saturation magnetization (Ms), allowing the magnetization direction to be easily changed. For this purpose, the free layer 123 can be doped with at least one nonmagnetic metal selected from, for example, Mg, Ru, Ir, Ti, Zn, Ga, Ta, Al, Mo, Zr, Sn, W, Sb, V, Nb, Cr, Ge, Si, Hf, Tb, Sc, Y, Rh, In, Ca, Sr, Ba, Be, Li, Cd, Pb, or Ga. The doping concentration of the nonmagnetic metal in the free layer 123 can be, for example, in the range of approximately 5 at% to approximately 50 at%.

[0062] The tunnel barrier layer 122 can be used as a tunnel barrier for a magnetic tunnel junction. The tunnel barrier layer 122 may include crystalline Mg oxide. For example, the tunnel barrier layer 122 may include MgO, MgAl2O4, or MgTiOx. The range of 'x' in MgTiOx may not be fixed to a specific single range, and various compounds may be formed depending on the range of 'x'.

[0063] When a current is applied to the orbital Hall conductance layer 132 in the horizontal direction (e.g., the X direction), the magnetization direction of the free layer 123 can be changed by the spin orbital moment (SOT) generated by the spin current generated in the vertical direction (e.g., the Z direction). In this regard, the magnetic storage device 100 can be applied to a SOT magnetic random access memory (MRAM). The orbital Hall conductance layer 132 can be referred to as the "SOT generation layer". The orbital Hall conductance layer 132 can switch the magnetization direction of the free layer 123 by providing a spin current to the tunneling magnetoresistive layer 120 (more specifically, the free layer 123) according to the current flowing through the orbital Hall conductance layer 132. For example, the free layer 123 can be magnetized in the +Z or -Z direction depending on the direction of the current applied to the orbital Hall conductance layer 132.

[0064] According to an example embodiment, the orbital Hall conductivity layer 132 may include an element or an alloy thereof having a relatively high orbital Hall conductivity (OHC) obtained through the orbital Hall effect (OHE). For example, the orbital Hall conductivity layer 132 may include at least one material selected from iridium (Ir), manganese (Mn), vanadium (V), chromium (Cr), niobium (Nb), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), tungsten (W), rhenium (Re), or an alloy thereof. For example, the alloy may include IrMn or PtMn. The thickness of the orbital Hall conductivity layer 132 may be, for example, about 1 nm or more to about 10 nm or less, or about 3 nm or more to about 7 nm or less, or about 4 nm or more to about 6 nm or less.

[0065] According to an example embodiment, when a current is applied to the orbital Hall conductivity layer 132 having a relatively large OHC, an orbital Hall current can be generated in the orbital Hall conductivity layer 132. The orbital Hall current can be converted into a spin Hall current via a spin current transfer layer 131. In this respect, the spin current transfer layer 131 can serve as a conversion layer for converting the orbital Hall current into a spin Hall current. Furthermore, because current flows in the spin current transfer layer 131, a spin Hall current can also be generated in the spin current transfer layer 131 itself via the spin Hall effect (SHE). Therefore, the spin current transfer layer 131 can transfer the spin current generated by the OHE and the spin current generated by the SHE to the free layer 123. Thus, a relatively large spin current can be generated by the combined action of the orbital Hall conductivity layer 132 and the spin current transfer layer 131. Then, even if the current applied to the orbital Hall conductance layer 132 is relatively small, a spin current sufficient to perform magnetic switching on the free layer 123 of the tunneling magnetoresistive layer 120 can be obtained, so the magnetic storage device 100 can have a relatively low operating current density.

[0066] The spin current transfer layer 131 may include a material capable of converting orbital Hall current into spin current and generating its own spin current due to the SHE. Furthermore, the spin current transfer layer 131 may include a material with a relatively high selectivity in the reactive ion etching (RIE) process described below. For example, the spin current transfer layer 131 may include platinum (Pt). The thickness of the spin current transfer layer 131 may be approximately 0.1 nm or greater and approximately 10 nm or less, approximately 0.1 nm or greater and approximately 5 nm or less, approximately 0.5 nm or greater and approximately 5 nm or less, approximately 0.5 nm or greater and approximately 4 nm or less, or approximately 1 nm or greater and approximately 3 nm or less.

[0067] The magnetic storage device 100 may further include a first electrode 111 for reading the resistance of the tunneling magnetoresistive layer 120, a second electrode 112 for applying current to the track Hall conductive layer 132, and a third electrode 113. The first electrode 111 may be electrically connected to the pinning layer 121. The second electrode 112 and the third electrode 113 may be positioned spaced apart from each other on the upper surface of the track Hall conductive layer 132. When a voltage is applied to each of the second electrode 112 and the third electrode 113, a track Hall current can be generated while current flows through the track Hall conductive layer 132.

[0068] Furthermore, the magnetic storage device 100 may also include an insulating layer 141 surrounding the side surfaces of the first electrode 111, the tunneling magnetoresistive layer 120, and the spin current transfer layer 131. Storage devices such as SOT MRAM may include a plurality of magnetic storage devices 100 arranged in a two-dimensional manner, and the plurality of magnetic storage devices 100 may be electrically isolated from each other through the insulating layer 141. An orbital Hall conductivity layer 132 may be disposed on the upper surface of the insulating layer 141 to contact the upper surface of the spin current transfer layer 131.

[0069] Figure 2 It shows the arrangement in Figure 1 The diagram shows a cross-sectional view of the wiring structure in the lower portion of the magnetic storage device 100. When the magnetic storage device 100 is used in a storage device such as SOT MRAM, various circuits such as output circuits and control circuits, as well as wiring that electrically connects the magnetic storage device 100 to the circuits, can be provided in the lower portion of the magnetic storage device 100. (Reference) Figure 2 The magnetic storage device 100 may further include: wiring 115 disposed in the lower portion of the first electrode 111; and a pass-through layer 114 electrically connecting the first electrode 111 to the wiring 115 between the first electrode 111 and the wiring 115. An insulating layer 141 may further extend downward to surround a side surface of the pass-through layer 114. The wiring 115 may be disposed on the lower surface of the insulating layer 141.

[0070] Figure 3 This is a cross-sectional view illustrating a schematic configuration of a magnetic storage device 100a according to another example embodiment. Figure 1 and Figure 2 The example shown illustrates a single-layer structure for the orbital Hall conductivity layer 132; however, this example embodiment is not limited to this, and the orbital Hall conductivity layer 132 can have a multi-layer structure in which different materials are stacked. (See reference...) Figure 3 The orbital Hall conductivity layer 132 of the magnetic storage device 100a may include a first orbital Hall conductivity layer 132a and a second orbital Hall conductivity layer 132b disposed on the first orbital Hall conductivity layer 132a. The first orbital Hall conductivity layer 132a may be disposed on the spin current transfer layer 131. In other words, the first orbital Hall conductivity layer 132a may be disposed between the spin current transfer layer 131 and the second orbital Hall conductivity layer 132b. The second electrode 112 and the third electrode 113 may be disposed spaced apart from each other on the upper surface of the second orbital Hall conductivity layer 132b. The first orbital Hall conductivity layer 132a and the second orbital Hall conductivity layer 132b may include one or more different materials selected from, for example, iridium (Ir), manganese (Mn), vanadium (V), chromium (Cr), niobium (Nb), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), tungsten (W), titanium (Ti), rhenium (Re), and their alloys. For example, the first orbital Hall conductivity layer 132a may include iridium (Ir), and the second orbital Hall conductivity layer 132b may include manganese (Mn), or the first orbital Hall conductivity layer 132a may include manganese (Mn), and the second orbital Hall conductivity layer 132b may include iridium (Ir).

[0071] As described above, because the magnetic storage devices 100 and 100a according to the above example embodiments perform magnetic switching of the free layer 123 using SOT, the magnetic storage devices 100 and 100a can have a faster operating speed than magnetic storage devices using spin-transfer torque (STT). For example, the magnetic storage devices 100 and 100a according to the above example embodiments can have a relatively fast operating speed of about 5 nsec or less or about 1 nsec or less. In addition, the magnetic storage devices 100 and 100a according to the above example embodiments can operate with a relatively high operating speed while having a relatively low current density, and therefore can have relatively low power consumption.

[0072] Figures 4A to 4I It is a schematic representation of manufacturing. Figure 1 A cross-sectional view of the method of the magnetic storage device 100 shown.

[0073] refer to Figure 4AElectrode material 111' can be formed first. When the magnetic storage device 100 is formed on the circuit layer of the storage device (e.g., SOT-MRAM), insulating layer 141 can be formed first on the circuit layer. Furthermore, after forming vias by etching a portion of insulating layer 141, vias can be formed by filling the vias with a conductive material to form via layer 114. Then, conductive electrode material 111' can be deposited on insulating layer 141. However, the example embodiment is not necessarily limited to this, and electrode material 111' can also be deposited on other substrates depending on the application. Electrode material 111' can include, for example, TiN or TaN.

[0074] refer to Figure 4B Pinning layer material 121', tunnel barrier layer material 122', free layer material 123', and spin current transfer layer material 131' can be sequentially formed on electrode material 111'. Although Figure 4B Not shown, but after a seed layer is first formed on the electrode material 111', a pinning layer material 121' can be formed on the seed layer. The ferromagnetic metal material used in the pinning layer 121 has a hexagonal close-packed (HCP) structure with a crystal orientation of (0001). The seed layer can improve the crystallinity of the pinning layer material 121', and thus can improve the PMA of the pinning layer 121. In addition, in the structure according to the example embodiment in which the pinning layer 121 is located below the tunnel barrier layer 122, the pinning layer material 121' is not formed on the tunnel barrier material 122', and therefore, the PMA of the pinning layer 121 can be further improved compared to the structure in which the pinning layer 121 is located on the tunnel barrier layer 122.

[0075] refer to Figure 4C The mask layer 150 can be formed on the upper surface of the spin current transfer layer material 131'. The mask layer 150 can be partially formed on the area to be left but not etched in the subsequent etching process.

[0076] refer to Figure 4DIn addition to the area covered by the mask layer 150, the spin current transfer layer material 131', free layer material 123', tunnel barrier layer material 122', pinning layer material 121', and electrode material 111' in the remaining areas not covered by the mask layer 150 (e.g., exposed by the mask layer 150) can be sequentially removed by an etching process. The etching process can be performed, for example, by ion beam etching (IOE). Thus, the first electrode 111, pinning layer 121, tunnel barrier layer 122, free layer 123, and spin current transfer layer 131 can be formed. Furthermore, a tunneling magnetoresistive layer 120 including the pinning layer 121, tunnel barrier layer 122, and free layer 123 can be formed. According to an example embodiment, the free layer 123 can be protected by the spin current transfer layer 131 disposed thereon, thereby reducing or preventing damage to the surface of the free layer 123 by the ion beam during the etching process. Thus, the PMA of the free layer 123 can be improved.

[0077] refer to Figure 4E The area removed by the etching process can be filled with an insulating layer 141. The insulating layer 141 can be formed to cover the upper surface of the mask layer 150. Then, the insulating layer 141 can completely surround the side surfaces of the first electrode 111, the pinning layer 121, the tunnel barrier layer 122, the free layer 123, and the spin current transfer layer 131. In addition, the insulating layer 141 can cover both the side surfaces and the upper surface of the mask layer 150.

[0078] refer to Figure 4F The upper surface of the insulating layer 141 can be planarized using a planarization process such as chemical mechanical plating (CMP). This planarization process can be performed until the mask layer 150 is exposed. In the planarization process, the mask layer 150 can protrude upward from the insulating layer 141 without being removed.

[0079] Reference Figure 4G The mask layer 150 can be removed by an etching process, and a planarization insulating layer 141 can be applied. The etching process can be performed, for example, by re-etching (RIE). The etching process can be performed until the upper surface of the spin current transfer layer 131 is exposed. The spin current transfer layer 131 can be used as an etch stop layer in the etching process. Because platinum (Pt), the material of the spin current transfer layer 131, has a relatively high selectivity relative to etching gases such as XeF, for example, 5 or greater, the spin current transfer layer 131 can be used as an etch stop layer. Furthermore, the spin current transfer layer 131 can protect other layers while performing RIE. Figure 4G In the additional planarization process shown, the upper portion of the spin current transfer layer 131 can be partially etched, and therefore the thickness of the spin current transfer layer 131 can be slightly reduced. Therefore, in Figure 4BIn the deposition process shown, the spin current transfer layer material 131' can be deposited to be slightly thicker than the target thickness of the final spin current transfer layer 131.

[0080] refer to Figure 4H Orbital Hall conductivity layer material 132' can be formed to cover the entire upper surface of insulating layer 141. Then, orbital Hall conductivity layer material 132' can also cover the upper surface of spin current transfer layer 131.

[0081] refer to Figure 4I The remaining portion of the orbital Hall conductivity layer material 132' can be removed by etching, leaving a portion of the orbital Hall conductivity layer material 132' in contact with the upper surface of the spin current transfer layer 131 and a portion of the insulating layer 141 surrounding the spin current transfer layer 131. Thus, an orbital Hall conductivity layer 132 in contact with the upper surface of the spin current transfer layer 131 can be formed. The width of the orbital Hall conductivity layer 132 can be greater than the width of the spin current transfer layer 131. Then, a portion of the orbital Hall conductivity layer 132 can be further extended upwards to the upper surface of the insulating layer 141. Subsequently, a second electrode 112 and a third electrode 113 spaced apart from each other can be formed on the upper surface of the orbital Hall conductivity layer 132. Then, the magnetic storage device 100 can be completed.

[0082] exist Figure 4G Following the additional planarization process shown, the spin current transfer layer 131 can be exposed to the outside until formation. Figure 4H The orbital Hall conductivity layer material 132' is shown. Because platinum (Pt), the material of the spin current transfer layer 131, has relatively high oxidation resistance, the surface of the spin current transfer layer 131 can be almost unoxidized before the orbital Hall conductivity layer material 132' is formed. Therefore, in the manufacturing method according to the example embodiment, almost no oxide is formed at the interface between the spin current transfer layer 131 and the orbital Hall conductivity layer 132, thus further improving the characteristics of the magnetic storage device 100.

[0083] For convenience, Figures 4A to 4I Only one mask layer 150 is shown, and for simplicity, only one magnetic storage device 100 is shown. However, multiple mask layers 150 arranged in a two-dimensional pattern can be formed on the spin current transfer layer material 131'. In this case, multiple magnetic storage devices 100 arranged in a two-dimensional pattern can be formed simultaneously. For example, multiple magnetic storage devices 100 arranged in a two-dimensional pattern can be formed. Figure 4D The etching process shown simultaneously forms multiple first electrodes 111, multiple pinning layers 121, multiple tunnel barrier layers 122, multiple free layers 123, and multiple spin current transfer layers 131, all separated from each other. Figure 4DIn the etching process shown, the insulating layer 141 or another substrate disposed below the first electrode 111 can be an etching stop layer. Therefore, in Figure 4D The etching process shown can be performed to a sufficient depth, and thus the yield of the magnetic storage device 100 can be improved. For example, electrical connections between some of the multiple magnetic storage devices 100 that are ultimately formed can be reduced or prevented.

[0084] When the magnetic storage device 100 is used in a storage device (e.g., SOT-RMAM) or other electronic device, additional wiring and circuitry can be formed on the magnetic storage device 100 using a back-end process (BEOL). According to an example embodiment, a pinning layer 121 is disposed in the lower portion of the magnetic storage device 100, and therefore, the heat transferred to the pinning layer 121 during subsequent BEOL processes can be reduced. Thus, the risk of damage to the pinning layer 121 due to high heat during subsequent BEOL processes can be reduced.

[0085] Figure 5 This is a cross-sectional view illustrating a schematic configuration of a magnetic storage device 100b according to another example embodiment. (Refer to...) Figure 5 The magnetic storage device 100b may include a spin Hall conductivity layer 133 instead of an orbital Hall conductivity layer 132 as a “SOT generation layer”. Figure 5 The remaining configuration of the magnetic storage device 100b shown can be consistent with... Figure 1 The magnetic storage device 100 shown has the same configuration. The spin Hall conductivity layer 133 may comprise an element or alloy thereof having a relatively high spin Hall conductivity (SHC) due to the spin Hall current (SHE). For example, the spin Hall conductivity layer 133 may comprise platinum (Pt) or tungsten (W) having a beta (β) phase (e.g., beta-tungsten (βW)). When a current is applied horizontally to the spin Hall conductivity layer 133, a spin Hall current can be generated due to the SHE. The spin current transfer layer 131 can transfer the spin Hall current generated in the spin Hall conductivity layer 133 to the free layer 123. The magnetization direction of the free layer 123 can be changed by the SOT generated due to the spin Hall current.

[0086] Can be used with Figures 4A to 4I The method for manufacturing the magnetic storage device 100 shown is the same as that used to manufacture it. Figure 5 The magnetic storage device 100b shown is, for example, capable of being stored in... Figure 4H and 4IThe magnetic storage device 100b is fabricated by forming a spin Hall conductivity layer 133 instead of an orbital Hall conductivity layer 132 in the illustrated process. According to the example embodiment, the spin Hall conductivity layer 133 is formed after an IOE process to form the tunneling magnetoresistive layer 120 and a RIE process to remove the mask layer 150 and planarize the insulating layer 141; therefore, the risk of the phase of the material of the spin Hall conductivity layer 133 changing during the etching process is minimal.

[0087] Figure 6 This is a cross-sectional view illustrating a schematic configuration of a magnetic storage device 100c according to another example embodiment. (Refer to...) Figure 6 The magnetic storage device 100c may further include an oxide layer 134 disposed between the free layer 123 and the spin current transfer layer 131. When the free layer 123 and the spin current transfer layer 131 are in direct contact with each other, platinum (Pt) from the spin current transfer layer 131 diffuses into the free layer 123, which may degrade the PMA of the free layer 123 and reduce the tunneling magnetoresistance of the tunneling magnetoresistance layer 120. The oxide layer 134 can serve as a diffusion prevention layer to prevent or reduce the diffusion of platinum (Pt) from the spin current transfer layer 131 into the free layer 123. The oxide layer 134 may include at least one material selected from, for example, magnesium oxide (MgO), tantalum oxide (TaO), magnesium aluminum oxide (MgAlOx), aluminum oxide (AlOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), magnesium tantalum oxide (MgTaOx), titanium oxide (TiOx), or tungsten oxide (WOx).

[0088] Figure 7 This is a cross-sectional view illustrating a schematic configuration of a magnetic storage device 100d according to another example embodiment. (Refer to...) Figure 7 The magnetic storage device 100d may further include a diffusion barrier metal layer 135 disposed between the free layer 123 and the spin current transfer layer 131. Figure 7 The magnetic storage device 100d shown is Figure 6 The magnetic storage device 100c shown differs from the magnetic storage device 100d in that it includes a diffusion barrier metal layer 135 instead of an oxide layer 134. The diffusion barrier metal layer 135 can perform the same function as the oxide layer 134 because it prevents or reduces the diffusion of platinum (Pt) from the spin current transfer layer 131 into the free layer 123, and unlike the oxide layer 134, it comprises a metal instead of an oxide. Furthermore, the diffusion barrier metal layer 135 can have superior or better thermal stability compared to the oxide layer 134. Therefore, the diffusion barrier metal layer 135 can thermally protect the pinned layer 121 from minimal deformation during subsequent BEOL processes.

[0089] The diffusion barrier metal layer 135 may include at least one metal selected from, for example, tantalum (Ta), tungsten (W), iridium (Ir), titanium (Ti), rhenium (Re), cobalt (Co), or alloys thereof. The diffusion barrier metal layer 135 may have a single-layer or multi-layer structure. For example, the diffusion barrier metal layer 135 may have a cobalt (Co) / iridium (Ir) / cobalt (Co) multi-layer structure. In addition to the cobalt (Co) / iridium (Ir) / cobalt (Co) multi-layer structure, the diffusion barrier metal layer 135 may be formed as a two-layer, four-layer, or more multi-layer structure, each layer comprising any one of the metals, or alloys thereof, of tantalum (Ta), tungsten (W), iridium (Ir), titanium (Ti), rhenium (Re), and cobalt (Co).

[0090] Each of the oxide layer 134 and the diffusion barrier metal layer 135 can have a relatively thin thickness to transfer spin current or SOT to the free layer 123 without allowing platinum (Pt) to pass through it. For example, the thickness of each of the oxide layer 134 and the diffusion barrier metal layer 135 can be selected in the range of about 0.5 nm or greater and about 2 nm or less, about 0.5 nm or greater and about 1 nm or less, or about 1 nm or greater and about 2 nm or less, depending on the physical properties of the oxide material or metal material actually used.

[0091] Figure 8 This is a cross-sectional view illustrating a schematic configuration of a magnetic storage device 100e according to another example embodiment. (Refer to...) Figure 8 The pinning layer 121 of the magnetic storage device 100e may have a synthetic antiferromagnetic structure. For example, the pinning layer 121 may include a first ferromagnetic layer 121a, an antiferromagnetic coupling layer 121c disposed on the first ferromagnetic layer 121a, and a second ferromagnetic layer 121b disposed on the antiferromagnetic coupling layer 121c. In other words, the first ferromagnetic layer 121a and the second ferromagnetic layer 121b are opposite to each other, and the antiferromagnetic coupling layer 121c may be disposed between the first ferromagnetic layer 121a and the second ferromagnetic layer 121b. The first ferromagnetic layer 121a may be disposed on the first electrode 111, and the tunnel barrier layer 122 may be disposed on the second ferromagnetic layer 121b.

[0092] Each of the first ferromagnetic layer 121a and the second ferromagnetic layer 121b may include a ferromagnetic metallic material. Each of the first ferromagnetic layer 121a and the second ferromagnetic layer 121b may include at least one ferromagnetic material selected from, for example, iron (Fe), cobalt (Co), nickel (Ni), manganese (Mn), Fe-containing alloys, Co-containing alloys, Ni-containing alloys, Mn-containing alloys, or Heusler alloys. The first ferromagnetic layer 121a and the second ferromagnetic layer 121b may include the same ferromagnetic material, but the exemplary embodiments are not limited thereto.

[0093] The antiferromagnetic coupling layer 121c may include a nonmagnetic metal that generates Dzyaloshinskii-Moriya interactions at the interface between the first ferromagnetic layer 121a and the second ferromagnetic layer 121b. For example, the antiferromagnetic coupling layer 121c may include at least one of ruthenium (Ru), iridium (Ir), tantalum (Ta), tungsten (W), palladium (Pd), zirconium (Zr), platinum (Pt), aluminum (Al), or alloys thereof. In this structure, the first ferromagnetic layer 121a and the second ferromagnetic layer 121b can form antiferromagnetism through the antiferromagnetic coupling layer 121c. In other words, the pinning layer 121 can have a stable state when the magnetization directions of the first ferromagnetic layer 121a and the second ferromagnetic layer 121b are opposite to each other.

[0094] According to an example embodiment, the thicknesses of the first ferromagnetic layer 121a and the second ferromagnetic layer 121b can be different from each other, allowing stray fields to be applied to the free layer 123. For example, the thickness of the first ferromagnetic layer 121a can be greater than the thickness of the second ferromagnetic layer 121b, or vice versa, allowing stray fields to be generated in the free layer 123. Magnetic switching can then be selectively performed on the free layer 123 without requiring a separate external magnetic field to be applied to the free layer 123.

[0095] Figure 9 This is a cross-sectional view illustrating a schematic configuration of a magnetic storage device 100f according to another example embodiment. (See reference...) Figure 9 The magnetic storage device 100f may include both an orbital Hall conductivity layer 132 and a spin Hall conductivity layer 133 as a "SOT generation layer". In other words, the magnetic storage device 100f includes an SOT generation layer, which comprises an orbital Hall conductivity layer 132 and a spin Hall conductivity layer 133. The orbital Hall conductivity layer 132 may be disposed on the spin current transfer layer 131, and the spin Hall conductivity layer 133 may be disposed on the orbital Hall conductivity layer 132. The second electrode 112 and the third electrode 113 may be spaced apart from each other on the upper surface of the spin Hall conductivity layer 133.

[0096] Figure 10 This is a cross-sectional view showing a schematic configuration of a magnetic storage device 100g according to another example embodiment. Figure 9 The illustration shows a spin Hall conductivity layer 133 disposed on an orbital Hall conductivity layer 132; however, the example embodiment is not limited to this, and the positions of the spin Hall conductivity layer 133 and the orbital Hall conductivity layer 132 may be interchanged. (See reference...) Figure 10The SOT generation layer of the magnetic storage device 100g may include a spin Hall conductivity layer 133 on the spin current transfer layer 131 and an orbital Hall conductivity layer 132 on the spin Hall conductivity layer 133. In this case, the second electrode 112 and the third electrode 113 may be arranged to be spaced apart from each other on the upper surface of the orbital Hall conductivity layer 132.

[0097] Figure 11 This is a cross-sectional view illustrating a schematic configuration of a magnetic storage device 100h according to another example embodiment. (Reference) Figure 11 The magnetic storage device 100h may include a plurality of tunneling magnetoresistive layers 120 connected to a track Hall conductance layer 132. For example, the magnetic storage device 100h may include a plurality of first electrodes 111, a plurality of tunneling magnetoresistive layers 120 respectively disposed on the plurality of first electrodes 111, a plurality of spin current transfer layers 131 respectively disposed on the plurality of tunneling magnetoresistive layers 120, a single track Hall conductance layer 132 disposed on the plurality of spin current transfer layers 131, and second electrodes 112 and third electrodes 113 spaced apart from each other on the upper surface of the track Hall conductance layer 132. The plurality of first electrodes 111 may be electrically connected to corresponding pinning layers in the plurality of pinning layers 121 of the plurality of tunneling magnetoresistive layers 120. Furthermore, the magnetic storage device 100h may further include a plurality of via layers 114 respectively electrically connected to the plurality of first electrodes 111, and a plurality of wirings 115 respectively electrically connected to the plurality of via layers 114. In addition, the magnetic storage device 100h may also include an insulating layer 141 disposed between the plurality of tunneling magnetoresistive layers 120 to electrically separate the plurality of tunneling magnetoresistive layers 120 from each other.

[0098] because Figure 11 The orbital Hall conductive layer 132 in the magnetic storage device 100h shown has a relatively long width and a relatively long distance between the second electrode 112 and the third electrode 113, so the orbital Hall conductive layer 132 can include a material with relatively high conductivity or a material with relatively low resistance. For example, the orbital Hall conductive layer 132 can include at least one material selected from iridium (Ir), ruthenium (Ru), or titanium (Ti). Figure 11 The magnetic storage device 100h is shown to include an orbital Hall conductivity layer 132 as an "SOT generation layer," but the magnetic storage device 100h may also include a spin Hall conductivity layer 133 as an "SOT generation layer." In this case, the spin Hall conductivity layer 133 may include platinum (Pt) as a material with relatively high conductivity and relatively low resistance.

[0099] according to Figure 11The illustrated example embodiment can increase the integration density of the multiple tunneling magnetoresistive layers 120. Furthermore, write and read operations can be selectively performed on the multiple tunneling magnetoresistive layers 120 via voltage-controlled magnetic anisotropy (VCMA). For example, while current is applied to the SOT generation layer, i.e., the orbital Hall conductivity layer 132 or the spin Hall conductivity layer 133, through the second electrode 112 and the third electrode 113, one or more specific tunneling magnetoresistive layers 120 can be selected based on the voltage applied to the first electrode 111.

[0100] Figure 12 A magnetic storage cell MC, including a magnetic storage device 100, is schematically shown according to an example embodiment. Reference Figure 12 The memory cell MC may include a magnetic storage device 100 and a switching device TR connected thereto. The switching device TR may be a thin-film transistor. The memory cell MC may be connected between a bit line BL and a word line WL. The bit line BL and the word line WL may be arranged to cross each other, and the memory cell MC may be located at the intersection of the bit line BL and the word line WL. The bit line BL may be electrically connected to the first electrode 111 of the magnetic storage device 100 via wiring 115 and a pass layer 114, and the word line WL may be connected to the gate of the switching device TR. In addition, the first source / drain electrode of the switching device TR may be electrically connected to the second electrode 112 of the magnetic storage device 100, and the second source / drain electrode may be electrically connected to the source line SL. Figure 12 The storage unit MC is shown to include Figure 1 and 2 The magnetic storage device 100 shown herein may vary, but the storage unit MC in other example embodiments may include Figure 3 and Figures 5 to 11 One of the magnetic storage devices 100a to 100h shown in the figure.

[0101] In this structure, the write current IW or read current IR can be applied to the memory cell MC through the word line WL, source line SL, and bit line BL. For example, when a voltage higher than the threshold voltage is applied to the word line WL and a current higher than the critical current is applied to the source line SL, the switching device TR can be turned on, and the write current IW can flow through the path between the second electrode 112 and the third electrode 113 of the magnetic storage device 100. At this time, the third electrode 113 of the magnetic storage device 100 can be grounded. Then, depending on the direction of the current applied to the track Hall conductance layer 132, the magnetization direction of the free layer 123 can be changed to the +Z direction or the -Z direction.

[0102] Simultaneously, the read current IR can flow from the second electrode 112 of the magnetic storage device 100 to the bit line BL through the first electrode 111. For example, when a voltage higher than the threshold voltage is applied to the word line WL and a current lower than the critical current is applied to the source line SL, the switching device TR can be turned on, and the read current IR can flow to the bit line BL through the second electrode 112 and the first electrode 111 of the magnetic storage device 100. At this time, the third electrode 113 of the magnetic storage device 100 can be in a floating state. Then, the resistance value of the magnetic storage device 100 can be read by measuring the current flowing through the bit line BL.

[0103] Figure 13 It is schematically shown that includes Figure 12 A circuit diagram showing the configuration of the storage device 200 with multiple storage cells MCs. (Refer to...) Figure 13 The storage device 200 may include multiple bit lines BL, multiple word lines WL, multiple source lines SL, multiple memory cells MC arranged at the intersections of the multiple bit lines BL and the multiple word lines WL, a bit line driver 201 that applies current to the multiple bit lines BL, a word line driver 202 that applies current to the multiple word lines WL, and a source line driver 203 that applies current to the multiple source lines SL. Each memory cell MC may have Figure 12 The configuration shown. Figure 13 The storage device 200 shown may be, for example, SOT MRAM and may be used in electronic devices that use non-volatile memory.

[0104] Figure 14 This is a schematic cross-sectional view illustrating the configuration of a storage device 200a according to another example embodiment. Reference Figure 14 The storage device 200a may have a structure in which two adjacent storage cells share a source line, a read bit line, and a track Hall conductivity layer 132. For example, the storage device 200a may include a first storage cell MC1 and a second storage cell MC2. The first storage cell MC1 and the second storage cell MC2 may be configured to share a source line 227, a read bit line 225, and a track Hall conductivity layer 132.

[0105] The first memory cell MC1 may include a track Hall conduction layer 132, a first spin current transfer layer 131a disposed on the lower surface of the track Hall conduction layer 132, a first tunneling magnetoresistive layer 120a disposed on the lower surface of the first spin current transfer layer 131a, a first electrode 111a disposed on the lower surface of the first tunneling magnetoresistive layer 120a, a second electrode 226 disposed on the lower surface of the track Hall conduction layer 132, a third electrode 227a disposed on the upper surface of the track Hall conduction layer 132, a first transistor TR1 electrically connected to the first electrode 111a, a read bit line 225 electrically connected to the first transistor TR1, a source line 227 electrically connected to the second electrode 226, and a first word line 228a electrically connected to the third electrode 227a. For example, the source line 227 may be disposed on the lower surface of the second electrode 226. The first word line 228a may be disposed on the upper surface of the third electrode 227a.

[0106] The first tunneling magnetoresistive layer 120a may include a free layer 123 disposed on the lower surface of the first spin current transfer layer 131a, a tunnel barrier layer 122 disposed on the lower surface of the free layer 123, and a pinning layer 121 disposed on the lower surface of the tunnel barrier layer 122. The first electrode 111a may be electrically connected to the pinning layer 121 of the first tunneling magnetoresistive layer 120a on the lower surface of the pinning layer 121 of the first tunneling magnetoresistive layer 120a.

[0107] The first transistor TR1 may include a first source / drain 214, a second source / drain 215, a first channel 211a between the first source / drain 214 and the second source / drain 215, a first gate insulating layer 212a on the first channel 211a, and a first read word line 213a on the first gate insulating layer 212a. The first source / drain 214 may face the first electrode 111a in the vertical direction and may be electrically connected to the first electrode 111a via a first wiring extending in the vertical direction. The first wiring may include, for example, a first conductive plug 221a, a first contact layer 222a, and a second conductive plug 223a, but the example embodiment is not limited thereto. The second source / drain 215 may face the read bit line 225 in the vertical direction and may be electrically connected to the read bit line 225 via a third conductive plug 224 extending in the vertical direction.

[0108] The second memory cell MC2 may include a track Hall conduction layer 132, a second spin current transfer layer 131b disposed on the lower surface of the track Hall conduction layer 132, a second tunneling magnetoresistive layer 120b disposed on the lower surface of the second spin current transfer layer 131b, a fourth electrode 111b disposed on the lower surface of the second tunneling magnetoresistive layer 120b, a second electrode 226 disposed on the lower surface of the track Hall conduction layer 132, a fifth electrode 227b disposed on the upper surface of the track Hall conduction layer 132, a second transistor TR2 electrically connected to the fourth electrode 111b, a read bit line 225 electrically connected to the second transistor TR2, a source line 227 electrically connected to the second electrode 226, and a second word line 228b electrically connected to the fifth electrode 227b. For example, the second word line 228b may be disposed on the upper surface of the fifth electrode 227b.

[0109] The second tunneling magnetoresistive layer 120b may include a free layer 123 disposed on the lower surface of the second spin current transfer layer 131b, a tunnel barrier layer 122 disposed on the lower surface of the free layer 123, and a pinning layer 121 disposed on the lower surface of the tunnel barrier layer 122. A fourth electrode 111b may be electrically connected to the pinning layer 121 of the second tunneling magnetoresistive layer 120b on the lower surface of the pinning layer 121.

[0110] The second transistor TR2 may include a second source / drain 215, a third source / drain 216, a second channel 211b between the second source / drain 215 and the third source / drain 216, a second gate insulating layer 212b on the second channel 211b, and a second read word line 213b on the second gate insulating layer 212b. The third source / drain 216 may face the fourth electrode 111b in the vertical direction and may be electrically connected to the fourth electrode 111b via a second wiring extending in the vertical direction. The second wiring may include, for example, a fourth conductive plug 221b, a second contact layer 222b, and a fifth conductive plug 223b, but the example embodiment is not limited thereto.

[0111] The first transistor TR1 and the second transistor TR2 may be disposed adjacent to each other in the horizontal direction on the substrate 210. The substrate 210 may include driving circuitry for controlling the storage device 200a. The first transistor TR1 and the second transistor TR2 may share a second source / drain 215. For example, the second source / drain 215 may be disposed between the first channel 211a and the second channel 211b.

[0112] The first storage cell MC1 and the second storage cell MC2 may also share the third conductive plug 224 and the second electrode 226. The track Hall conductive layer 132 shared by the first storage cell MC1 and the second storage cell MC2 may extend in the horizontal direction, and the first tunneling magnetoresistive layer 120a and the second tunneling magnetoresistive layer 120b may be adjacent to each other on the lower surface of the track Hall conductive layer 132. The third conductive plug 224, the read bit line 225, the second electrode 226, and the source line 227 shared by the first storage cell MC1 and the second storage cell MC2 may be disposed between the first tunneling magnetoresistive layer 120a and the second tunneling magnetoresistive layer 120b.

[0113] The third electrode 227a and the first word line 228a can be disposed on the track Hall conductive layer 132 to be spaced apart from the fifth electrode 227b and the second word line 228b. For example, the third electrode 227a and the first word line 228a can be disposed at a first side edge on the track Hall conductive layer 132, and the fifth electrode 227b and the second word line 228b can be disposed at a second side edge on the track Hall conductive layer 132 opposite to the first side edge. For example, a first tunneling magnetoresistive layer 120a can be disposed horizontally between the third electrode 227a and the second electrode 226. A second tunneling magnetoresistive layer 120b can be disposed horizontally between the fifth electrode 227b and the second electrode 226.

[0114] The storage device 200a may further include an insulating layer 220 that fills the space between the first transistor TR1 and the second transistor TR2 and the track Hall conductivity layer 132. The first tunneling magnetoresistive layer 120a, the second tunneling magnetoresistive layer 120b, the first electrode 111a, the first conductive plug 221a, the first contact layer 222a, the second conductive plug 223a, the fourth electrode 111b, the fourth conductive plug 221b, the second contact layer 222b, the fifth conductive plug 223b, the third conductive plug 224, the read bit line 225, the second electrode 226, and the source line 227 may be embedded in the insulating layer 220.

[0115] In a write operation to the first memory cell MC1, a voltage may not be applied to the second word line 228b, while a write voltage is applied to the first word line 228a. Then, when current flows from the first word line 228a to the source line 227, a write current can be applied to the first memory cell MC1, and a write current may not be applied to the second memory cell MC2. In a read operation to the first memory cell MC1, the first transistor TR1 can be turned on by applying a voltage higher than the threshold voltage of the first transistor TR1 to the first read word line 213a. A read voltage can be applied to the first word line 228a. Then, a read current can flow from the first word line 228a to the read bit line 225.

[0116] In a write operation to the second memory cell MC2, a voltage may not be applied to the first word line 228a, but a write voltage may be applied to the second word line 228b. Then, while current flows from the second word line 228b to the source line 227, a write current may be applied to the second memory cell MC2, and no write current may be applied to the first memory cell MC1. In a read operation to the second memory cell MC2, the second transistor TR2 can be turned on by applying a voltage higher than the threshold voltage of the second transistor TR2 to the second read word line 213b. A read voltage may be applied to the second word line 228b. Then, a read current may flow from the second word line 228b to the read bit line 225.

[0117] Figure 14 The first storage cell MC1 and the second storage cell MC2 are shown to include an orbital Hall conductivity layer 132 as a "SOT generation layer," but the first storage cell MC1 and the second storage cell MC2 may also include a spin Hall conductivity layer 133 as a "SOT generation layer." In this case, the spin Hall conductivity layer 133 as the "SOT generation layer" may include platinum (Pt) as a material with relatively high conductivity and relatively low resistance.

[0118] The aforementioned storage device 200 can be used for data storage in various electronic devices. Figure 15 This is a conceptual diagram schematically illustrating a device architecture applicable to electronic device 300. (Refer to...) Figure 15 Electronic device 300 may include main memory 310, secondary memory 320, central processing unit (CPU) 330, and input / output device 340. CPU 330 may include cache memory 331, arithmetic logic unit (ALU) 332, and control unit 333. Cache memory 331 may include static random access memory (SRAM). According to an example embodiment, main memory 310 may include a DRAM device, and secondary memory 320 may include storage device 200. In some example embodiments, cache memory 331, main memory 310, and secondary memory 320 may all include storage device 200 according to an example embodiment.

[0119] Any functional blocks shown in the accompanying drawings and described above can be implemented in processing circuitry, such as hardware including logic circuitry, hardware / software combinations (such as a processor executing software), or combinations thereof. For example, processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0120] The example implementations described above are summarized below.

[0121] (1) According to an example embodiment, a method of manufacturing a magnetic storage device may include: sequentially forming a pinning layer material, a tunnel barrier layer material, a free layer material, and a spin current transfer layer material on an electrode material; forming a mask layer on the spin current transfer layer material; forming a first electrode, a pinning layer, a tunnel barrier layer, a free layer, and a spin current transfer layer by removing the spin current transfer layer material, the free layer material, the tunnel barrier layer material, the pinning layer material, and the electrode material exposed by the mask layer via a first etching process; forming an insulating layer to surround the side surfaces of the first electrode, the pinning layer, the tunnel barrier layer, the free layer, and the spin current transfer layer and to cover the side surfaces and the top surface of the mask layer; performing a second etching process until the top surface of the spin current transfer layer is exposed; and forming an SOT generation layer in contact with the top surface of the spin current transfer layer.

[0122] (2) The method may also include forming a second electrode and a third electrode on the upper surface of the SOT generation layer, the second electrode and the third electrode being spaced apart from each other.

[0123] (3) The SOT formation layer may include at least one of the following materials: iridium (Ir), manganese (Mn), vanadium (V), chromium (Cr), niobium (Nb), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), tungsten (W), titanium (Ti), rhenium (Re), platinum (Pt), tungsten (W) with a beta (β) phase, or an alloy thereof.

[0124] (4) The spin current transfer layer may include platinum (Pt).

[0125] (5) The first etching process can be performed via IOE.

[0126] (6) The second etching process may include planarizing the upper surface of the insulating layer until the mask layer is exposed, removing the mask layer by RIE, and additionally planarizing the insulating layer.

[0127] (7) According to an example embodiment, a magnetic storage device may include: an SOT generation layer configured to generate SOT, a spin current transfer layer on the lower surface of the SOT generation layer, and a tunneling magnetoresistive layer on the lower surface of the spin current transfer layer, including a free layer, a tunneling barrier layer, and a pinning layer, wherein the spin current transfer layer is configured to transfer spin current generated from the SOT generation layer to the free layer, the SOT generation layer includes at least one material selected from iridium (Ir), manganese (Mn), vanadium (V), chromium (Cr), niobium (Nb), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), tungsten (W), titanium (Ti), rhenium (Re), platinum (Pt), tungsten (W) having a beta (β) phase, or an alloy thereof, and the spin current transfer layer includes platinum (Pt).

[0128] (8) The SOT generation layer may include an orbital Hall conductivity layer configured to provide an orbital Hall current due to OHE, and the orbital Hall conductivity layer may include at least one material selected from iridium (Ir), manganese (Mn), vanadium (V), chromium (Cr), niobium (Nb), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), tungsten (W), titanium (Ti), rhenium (Re) or alloys thereof.

[0129] (9) The orbital Hall conduction layer may include a first orbital Hall conduction layer on the spin current transfer layer and a second orbital Hall conduction layer on the first orbital Hall conduction layer.

[0130] (10) Each of the first orbital Hall conductivity layer and the second orbital Hall conductivity layer may include at least one material different from each other among iridium (Ir), manganese (Mn), vanadium (V), chromium (Cr), niobium (Nb), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), tungsten (W), titanium (Ti), rhenium (Re) and their alloys.

[0131] (11) The SOT generation layer may include a spin Hall conductivity layer configured to provide a spin Hall current due to the spin Hall effect (SHE), and the spin Hall conductivity layer may include platinum (Pt) or tungsten (βW) having a beta (β) phase.

[0132] (12) The thickness of the spin current transfer layer can be about 0.1 nm or more and about 10 nm or less.

[0133] (13) The SOT generation layer may include: an orbital Hall conductivity layer on the spin current transfer layer and configured to provide an orbital Hall current due to OHE; and a spin Hall conductivity layer on the orbital Hall conductivity layer and configured to provide a spin Hall current due to SHE.

[0134] (14) The SOT generation layer may include: a spin Hall conductivity layer on the spin current transfer layer and configured to provide a spin Hall current due to SHE; and an orbital Hall conductivity layer on the spin Hall conductivity layer and configured to provide an orbital Hall current due to OHE.

[0135] (15) The magnetic storage device may further include an oxide layer between the free layer and the spin current transfer layer, and the oxide layer may include at least one of magnesium oxide (MgO), tantalum oxide (TaO), magnesium aluminum oxide (MgAlOx), aluminum oxide (AlOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), magnesium tantalum oxide (MgTaOx), titanium oxide (TiOx) or tungsten oxide (WOx).

[0136] (16) The magnetic storage device may also include a diffusion barrier metal layer between the free layer and the spin current transfer layer.

[0137] (17) The diffusion barrier metal layer may have a single-layer or multi-layer structure of at least one metal selected from tantalum (Ta), tungsten (W), iridium (Ir), titanium (Ti), rhenium (Re), cobalt (Co) or alloys thereof.

[0138] (18) The pinning layer may include a first ferromagnetic layer, a second ferromagnetic layer and an antiferromagnetic coupling layer between the first ferromagnetic layer and the second ferromagnetic layer, and the magnetization direction of the first ferromagnetic layer may be opposite to the magnetization direction of the second ferromagnetic layer.

[0139] (19) The magnetic storage device may also include a first electrode electrically connected to the pinned layer and a second and third electrode spaced apart from each other on the SOT generation layer.

[0140] (20) Multiple tunneling magnetoresistive layers and multiple spin current transfer layers can correspond to one SOT generation layer.

[0141] (21) The SOT generation layer may include at least one material selected from platinum (Pt), iridium (Ir), ruthenium (Ru) or titanium (Ti).

[0142] (22) The magnetic storage device may further include a plurality of first electrodes that are electrically connected to a plurality of pinned layers of a plurality of tunneling magnetoresistive layers, and a second electrode and a third electrode that are spaced apart from each other on the SOT generation layer.

[0143] (23) According to an example embodiment, a storage device may include a plurality of storage cells, each storage cell including a magnetic storage device and a switching device connected to the magnetic storage device. The magnetic storage device may include: a SOT generation layer configured to generate SOT, a spin current transfer layer on the lower surface of the SOT generation layer, and a tunneling magnetoresistive layer on the lower surface of the spin current transfer layer including a free layer, a tunnel barrier layer and a pinning layer. The spin current transfer layer is configured to transfer spin current generated from the SOT generation layer to the free layer. The SOT generation layer includes at least one material selected from iridium (Ir), manganese (Mn), vanadium (V), chromium (Cr), niobium (Nb), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), tungsten (W), titanium (Ti), rhenium (Re), platinum (Pt), tungsten (βW) having a beta (β) phase, or an alloy thereof. The spin current transfer layer may include platinum (Pt).

[0144] The magnetic storage device including a tunneling magnetoresistive layer according to the example embodiment can have a relatively fast operating speed of about 5 nsec or less, or about 1 nsec or less. Furthermore, the magnetic storage device according to the example embodiment can operate at a relatively low current density while maintaining a high operating speed. Therefore, storage devices with relatively high operating speed and low power consumption, such as SOT-MRAM, can be realized.

[0145] Furthermore, because the pinning layer is located below the tunnel barrier layer, the PMA of the pinning layer can be easily ensured by forming the pinning layer before the tunnel barrier layer in the manufacturing process, and the risk of damage to the pinning layer due to the high heat in the subsequent BEOL process can be reduced.

[0146] Furthermore, because the SOT generation layer is formed after the etching process that forms the tunneling magnetoresistive layer in the manufacturing process, there is no risk that the phase of the SOT generation layer will be altered by the ion beam during the etching process that forms the tunneling magnetoresistive layer. Additionally, because the substrate or insulating layer disposed beneath the tunneling magnetoresistive layer is used as an etch stop layer during the etching process that forms the tunneling magnetoresistive layer, the tunneling magnetoresistive layer can be etched to a sufficient depth, thus improving yield.

[0147] It should be understood that the exemplary embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each exemplary embodiment should generally be considered applicable to other similar features or aspects in other exemplary embodiments. Although one or more exemplary embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

Claims

1. A method for manufacturing a magnetic storage device, the method comprising: Pinning layer material, tunnel barrier layer material, free layer material and spin current transfer layer material are sequentially formed on electrode material; A mask layer is formed on the spin current transfer layer material; A first electrode, a pinned layer, a tunnel barrier layer, a free layer, and a spin current transfer layer are formed by removing the spin current transfer layer material, the free layer material, the tunnel barrier layer material, the pinning layer material, and the electrode material exposed by the mask layer via a first etching process. An insulating layer is formed to surround the side surfaces of the first electrode, the pinning layer, the tunnel barrier layer, the free layer, and the spin current transfer layer, and to cover the side and top surfaces of the mask layer; Perform a second etching process until the upper surface of the spin current transfer layer is exposed; and A spin orbital moment (SOT) generation layer is formed in contact with the upper surface of the spin current transfer layer.

2. The method according to claim 1, further comprising: A second electrode and a third electrode are formed on the upper surface of the SOT generation layer, with the second electrode and the third electrode spaced apart from each other.

3. The method according to claim 1, wherein, The SOT formation layer comprises at least one material selected from iridium (Ir), manganese (Mn), vanadium (V), chromium (Cr), niobium (Nb), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), tungsten (W), titanium (Ti), rhenium (Re), platinum (Pt), tungsten (W) with a beta (β) phase, and alloys thereof. The spin current transfer layer comprises platinum (Pt).

4. The method according to claim 1, wherein, The first etching process is performed by ion beam etching.

5. The method according to claim 1, wherein, The second etching process includes: Planarize the upper surface of the insulating layer until the mask layer is exposed, and The mask layer is removed by reactive ion etching, and the insulating layer is further planarized.

6. A magnetic storage device, comprising: A spin orbit moment (SOT) generation layer is configured to generate SOTs; Spin current transfer layer on the lower surface of the SOT generation layer; and A tunneling magnetoresistive layer is formed on the lower surface of the spin current transfer layer. The tunneling magnetoresistive layer comprises a free layer, a tunneling barrier layer, and a pinning layer. The spin current transfer layer is configured to transfer the spin current generated from the SOT generation layer to the free layer. The SOT formation layer comprises at least one material selected from iridium (Ir), manganese (Mn), vanadium (V), chromium (Cr), niobium (Nb), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), tungsten (W), titanium (Ti), rhenium (Re), platinum (Pt), tungsten (W) with a beta (β) phase, and alloys thereof. The spin current transfer layer comprises platinum (Pt).

7. The magnetic storage device according to claim 6, wherein, The SOT generation layer includes an orbital Hall conductivity layer configured to provide an orbital Hall current due to the orbital Hall effect. The orbital Hall conductive layer comprises at least one material selected from iridium (Ir), manganese (Mn), vanadium (V), chromium (Cr), niobium (Nb), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), tungsten (W), titanium (Ti), rhenium (Re), and alloys thereof.

8. The magnetic storage device according to claim 7, wherein, The orbital Hall conductivity layer includes a first orbital Hall conductivity layer on the spin current transfer layer and a second orbital Hall conductivity layer on the first orbital Hall conductivity layer, and Each of the first orbital Hall conductive layer and the second orbital Hall conductive layer comprises at least one material different from each other selected from iridium (Ir), manganese (Mn), vanadium (V), chromium (Cr), niobium (Nb), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), tungsten (W), titanium (Ti), rhenium (Re) and alloys thereof.

9. The magnetic storage device according to claim 6, wherein, The SOT generation layer includes a spin Hall conductivity layer configured to provide a spin Hall current due to the spin Hall effect. The spin Hall conductive layer comprises platinum (Pt) or tungsten (W) with a beta (β) phase.

10. The magnetic storage device according to claim 6, wherein, The thickness of the spin current transfer layer is 0.1 nm or greater and 10 nm or less.

11. The magnetic storage device according to claim 6, wherein, The SOT generation layer includes: an orbital Hall conductivity layer on the spin current transfer layer and configured to provide an orbital Hall current due to the orbital Hall effect; and a spin Hall conductivity layer on the orbital Hall conductivity layer and configured to provide a spin Hall current due to the spin Hall effect.

12. The magnetic storage device according to claim 6, wherein, The SOT generation layer includes: a spin Hall conductivity layer on the spin current transfer layer and configured to provide a spin Hall current due to the spin Hall effect; and an orbital Hall conductivity layer on the spin Hall conductivity layer and configured to provide an orbital Hall current due to the orbital Hall effect.

13. The magnetic storage device according to claim 6, further comprising: An oxide layer is located between the free layer and the spin current transfer layer. The oxide layer includes magnesium oxide (MgO), tantalum oxide (TaO), and magnesium aluminum oxide (MgAlO). x ), aluminum oxide (AlO) x ), hafnium oxide (HfO) x ), zirconium oxide (ZrO x ), magnesium tantalum oxide (MgTaO) x Titanium oxide (TiO) x ) and tungsten oxide (WO) x At least one of the following.

14. The magnetic storage device according to claim 6, further comprising: A diffusion barrier metal layer is located between the free layer and the spin current transfer layer. The diffusion barrier metal layer has a single-layer or multi-layer structure comprising at least one metal selected from tantalum (Ta), tungsten (W), iridium (Ir), titanium (Ti), rhenium (Re), cobalt (Co), and their alloys.

15. The magnetic storage device according to claim 6, wherein, The pinning layer includes a first ferromagnetic layer, a second ferromagnetic layer, and an antiferromagnetic coupling layer between the first ferromagnetic layer and the second ferromagnetic layer. The magnetization direction of the first ferromagnetic layer is opposite to that of the second ferromagnetic layer.

16. The magnetic storage device according to claim 6, further comprising: The first electrode is electrically connected to the pinning layer; and The second and third electrodes are spaced apart from each other on the SOT generation layer.

17. The magnetic storage device according to claim 6, wherein, Multiple tunneling magnetoresistive layers and multiple spin current transfer layers correspond to a single SOT generation layer.

18. The magnetic storage device according to claim 17, wherein, The SOT formation layer comprises at least one material selected from platinum (Pt), iridium (Ir), ruthenium (Ru), and titanium (Ti).

19. The magnetic storage device according to claim 17, further comprising: Multiple first electrodes are electrically connected to corresponding pinning layers in the multiple pinning layers of the multiple tunneling magnetoresistive layers, respectively; and The second and third electrodes are spaced apart from each other on the SOT generation layer.

20. A storage device, comprising: Multiple storage units, each including a magnetic storage device and a switching device connected to the magnetic storage device, The magnetic storage device includes A spin orbit moment (SOT) generation layer is configured to generate SOTs; A spin current transfer layer is located on the lower surface of the SOT generation layer; and A tunneling magnetoresistive layer is formed on the lower surface of the spin current transfer layer. The tunneling magnetoresistive layer comprises a free layer, a tunneling barrier layer, and a pinning layer. The spin current transfer layer is configured to transfer the spin current generated from the SOT generation layer to the free layer. The SOT formation layer comprises at least one material selected from iridium (Ir), manganese (Mn), vanadium (V), chromium (Cr), niobium (Nb), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), tungsten (W), titanium (Ti), rhenium (Re), platinum (Pt), tungsten (W) with a beta (β) phase, and alloys thereof. The spin current transfer layer comprises platinum (Pt).

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