Semiconductor test device, semiconductor wafer, and mobility test method

Abstract

The application provides a semiconductor testing device, a semiconductor wafer and a mobility testing method. A first doped region includes a first sub-doped region, a second sub-doped region and a third sub-doped region. The third sub-doped region is connected to the first sub-doped region and the second sub-doped region which are arranged at intervals. A second doped region includes a fourth sub-doped region and a fifth sub-doped region. The fourth sub-doped region and the fifth sub-doped region are arranged in the first sub-doped region and the second sub-doped region respectively. A gate structure is arranged at least partially above the third sub-doped region and extends to above the fourth sub-doped region and the fifth sub-doped region. The gate structure is used for connecting an output end of a first voltage. A second conductive electrode is in ohmic contact with the fourth sub-doped region and is used for grounding. A third conductive electrode is in ohmic contact with the fifth sub-doped region and is used for connecting an input end of a second voltage. The structure makes the current path not pass through an epitaxial layer and a substrate, and achieves the purpose of accurately characterizing the mobility of the device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor testing device, a semiconductor wafer, and a mobility testing method. Background Technology

[0002] Miniaturizing the cell size and increasing the mobility of semiconductor devices (MOSFETs) is a simple way to further reduce the on-resistance of the devices.

[0003] Existing semiconductor devices, with their source and drain located on the top and bottom sides respectively, have a vertical structure that results in numerous parasitic resistances along the current path, such as contact resistance, N-type heavily doped layer resistance, drift layer resistance, and substrate resistance. The introduction of parasitic resistance, especially the presence of drift region resistance, reduces the actual current. Therefore, accurately characterizing device mobility is a challenge. Summary of the Invention

[0004] This application provides a semiconductor testing device, a semiconductor wafer, and a mobility testing method, which can accurately characterize the mobility of semiconductor devices.

[0005] To solve the above-mentioned technical problems, the first technical solution adopted in this application is: to provide a semiconductor testing device, comprising:

[0006] Substrate;

[0007] An epitaxial layer is disposed on the surface of the substrate, wherein the substrate and the epitaxial layer are of a first conductivity type;

[0008] A first doped region, including a first sub-doped region, a second sub-doped region, and a third sub-doped region, is disposed in the epitaxial layer and extends from the surface of the epitaxial layer away from the substrate along a first direction; the first direction is the direction of the epitaxial layer toward the substrate; the first doped region is of a second conductivity type; wherein, the first sub-doped region and the second sub-doped region are spaced apart along a second direction, and the third sub-doped region connects the first sub-doped region and the second sub-doped region; the first doped region is of a second conductivity type.

[0009] The second doped region includes a fourth sub-doped region and a fifth sub-doped region. The fourth sub-doped region is disposed within the first sub-doped region and has a first spacing distance from the edge of the first sub-doped region. The fifth sub-doped region is disposed within the second sub-doped region and has a second spacing distance from the edge of the second sub-doped region. The fourth and fifth sub-doped regions extend from the surface of the epitaxial layer away from the substrate along the first direction. The second doped region is of a first conductivity type. The first spacing distance is the same as the second spacing distance. The width of the third sub-doped region is greater than or equal to the first spacing distance and less than or equal to twice the first spacing distance. The width direction of the third sub-doped region is perpendicular to both the first and second directions.

[0010] A third doped region is disposed in the epitaxial layer and extends from the surface of the epitaxial layer away from the substrate along a first direction; the third doped region is disposed around the first doped region; the third doped region is of a second conductivity type.

[0011] A gate structure is at least partially disposed above the third sub-doped region and extends above the fourth sub-doped region and the fifth sub-doped region; wherein the gate structure includes a gate oxide layer and a first conductive electrode, the gate oxide layer is located between the first conductive electrode and the epitaxial layer, and the first conductive electrode is used to connect to the output terminal of a first voltage;

[0012] The second conductive electrode is ohmic contacted with the fourth sub-doped region, and the second conductive electrode is used for grounding;

[0013] The third conductive electrode is ohmicly connected to the fifth sub-doped region, and the third conductive electrode is used to connect to the input terminal of the second voltage.

[0014] To solve the above-mentioned technical problems, the second technical solution adopted in this application is: to provide a semiconductor wafer, said semiconductor wafer comprising:

[0015] Several semiconductor device regions, wherein the semiconductor devices in the semiconductor device regions are planar gate structure power devices;

[0016] Several monitoring areas are provided with at least one semiconductor test device for testing the channel mobility of the planar gate structure power device, the semiconductor test device comprising:

[0017] Substrate;

[0018] An epitaxial layer is disposed on the surface of the substrate, wherein the substrate and the epitaxial layer are of a first conductivity type;

[0019] A first doped region, including a first sub-doped region, a second sub-doped region, and a third sub-doped region, is disposed in the epitaxial layer and extends from the surface of the epitaxial layer away from the substrate along a first direction; the first direction is the direction of the epitaxial layer toward the substrate; the first doped region is of a second conductivity type; wherein, the first sub-doped region and the second sub-doped region are spaced apart along a second direction, and the third sub-doped region connects the first sub-doped region and the second sub-doped region; the first doped region is of a second conductivity type.

[0020] The second doped region includes a fourth sub-doped region and a fifth sub-doped region. The fourth sub-doped region is disposed within the first sub-doped region and has a first spacing distance from the edge of the first sub-doped region. The fifth sub-doped region is disposed within the second sub-doped region and has a second spacing distance from the edge of the second sub-doped region. The fourth and fifth sub-doped regions extend from the surface of the epitaxial layer away from the substrate along the first direction. The second doped region is of a first conductivity type. The first spacing distance is the same as the second spacing distance. The width of the third sub-doped region is greater than or equal to the first spacing distance and less than or equal to twice the first spacing distance. The width direction of the third sub-doped region is perpendicular to both the first and second directions.

[0021] A third doped region is disposed in the epitaxial layer and extends from the surface of the epitaxial layer away from the substrate along a first direction; the third doped region is disposed around the first doped region; the third doped region is of a second conductivity type.

[0022] A gate structure is at least partially disposed above the third sub-doped region and extends above the fourth sub-doped region and the fifth sub-doped region; wherein the gate structure includes a gate oxide layer and a first conductive electrode, the gate oxide layer is located between the first conductive electrode and the epitaxial layer, and the first conductive electrode is used to connect to the output terminal of a first voltage;

[0023] The second conductive electrode is ohmic contacted with the fourth sub-doped region, and the second conductive electrode is used for grounding;

[0024] The third conductive electrode is ohmicly connected to the fifth sub-doped region, and the third conductive electrode is used to connect to the input terminal of the second voltage.

[0025] To solve the above-mentioned technical problems, the third technical solution adopted in this application is: providing a mobility testing method applied to a semiconductor wafer, the semiconductor wafer comprising: a plurality of semiconductor device regions, wherein the semiconductor devices in the semiconductor device regions are planar gate structure power devices; a plurality of monitoring regions, wherein at least one semiconductor testing device is provided for testing the channel mobility of the planar gate structure power devices, the semiconductor testing device comprising: a substrate; an epitaxial layer disposed on the surface of the substrate, wherein the substrate and the epitaxial layer are of a first conductivity type; and a first doped region comprising a first sub-doped region, a second sub-doped region, and a third sub-doped region, all disposed on the substrate. In the epitaxial layer, a third sub-doped region extends along a first direction from the surface of the epitaxial layer away from the substrate; the first direction is the direction of the epitaxial layer toward the substrate; the first doped region is of a second conductivity type; wherein, the first sub-doped region and the second sub-doped region are spaced apart along the second direction, and the third sub-doped region connects the first sub-doped region and the second sub-doped region; the first doped region is of a second conductivity type; the second doped region includes a fourth sub-doped region and a fifth sub-doped region, the fourth sub-doped region being disposed in the first sub-doped region and having a first spacing distance from the edge of the first sub-doped region, and the fifth sub-doped region being disposed in the second doped region. The third sub-doped region is disposed in the epitaxial layer and has a second spacing distance from the edge of the second sub-doped region. The fourth and fifth sub-doped regions extend from the surface of the epitaxial layer away from the substrate along the first direction. The second doped region is of a first conductivity type. The first spacing distance is the same as the second spacing distance, and the width of the third sub-doped region is greater than or equal to the first spacing distance and less than or equal to twice the first spacing distance. The width direction of the third sub-doped region is perpendicular to both the first and second directions. The third doped region is disposed in the epitaxial layer and extends from the surface of the epitaxial layer away from the substrate along the first direction. The first doped region is surrounded by a third doped region of a second conductivity type. A gate structure is at least partially disposed above the third sub-doped region and extends above the fourth and fifth sub-doped regions. The gate structure includes a gate oxide layer and a first conductive electrode, the gate oxide layer being located between the first conductive electrode and the epitaxial layer. The first conductive electrode is used to connect to the output terminal of a first voltage. A second conductive electrode is ohmically connected to the fourth sub-doped region and is used to ground. A third conductive electrode is ohmically connected to the fifth sub-doped region and is used to connect to the input terminal of a second voltage.

[0026] The testing method includes:

[0027] The first conductive electrode in the semiconductor test device receives a first voltage V1 output from the output terminal of the first voltage, wherein the first voltage V1 is greater than the threshold voltage V of the gate structure. th ;

[0028] The third conductive electrode of the semiconductor test device receives the second voltage V2 output from the output terminal of the second voltage, wherein the second voltage V2 is greater than 0V;

[0029] Based on the second voltage V2, the test current I on the second conductive electrode and / or the third conductive electrode is detected;

[0030] Based on the first voltage V1 and the threshold voltage V th The channel mobility μ of the semiconductor test device is determined by the second voltage V2 and the test current I.

[0031] Based on the channel mobility μ of the semiconductor test device, the channel mobility of the planar gate structure power device in the semiconductor wafer is determined.

[0032] The beneficial effects of this application are that, unlike the prior art, the semiconductor testing device, semiconductor wafer, and mobility testing method provided in this application include a substrate, an epitaxial layer disposed on the substrate surface, a first doped region, a second doped region, a third doped region, a gate structure, a second conductive electrode, and a third conductive electrode; wherein, the first doped region includes a first sub-doped region, a second sub-doped region, and a third sub-doped region, all disposed in the epitaxial layer, the first sub-doped region and the second sub-doped region being spaced apart along a second direction, and the third sub-doped region connecting the first sub-doped region and the second sub-doped region; the first doped region is of a second conductivity type; the second doped region includes a fourth sub-doped region and a fifth sub-doped region, the fourth sub-doped region being disposed in the first sub-doped region and having a first spacing distance from the edge of the first sub-doped region, and the fifth sub-doped region being disposed in the second sub-doped region. The third sub-doped region is located in an epitaxial layer and has a second spacing distance from the edge of the second sub-doped region. The first spacing distance is the same as the second spacing distance, and the width of the third sub-doped region is greater than or equal to the first spacing distance and less than or equal to twice the first spacing distance. The third doped region is disposed in the epitaxial layer and surrounds the first doped region. A gate structure is at least partially disposed above the third sub-doped region and extends above the fourth and fifth sub-doped regions. The gate structure includes a gate oxide layer and a first conductive electrode. The gate oxide layer is located between the first conductive electrode and the epitaxial layer, and the first conductive electrode is used to connect to the output terminal of a first voltage. The second conductive electrode is ohmically connected to the fourth sub-doped region and is used for grounding. The third conductive electrode is ohmically connected to the fifth sub-doped region and is used to connect to the input terminal of a second voltage. Specifically, the structure of the semiconductor test device provided in this application enables the current path to flow from the fifth sub-doped region to the third sub-doped region and then to the fourth sub-doped region, eliminating the influence of parasitic resistances such as the drift region (i.e., epitaxial layer) resistance and substrate resistance below the first doped region on the mobility, thereby achieving the purpose of accurately characterizing the mobility of the semiconductor device. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0034] Figure 1 A schematic diagram illustrating the process of forming the channel of a power device using a self-aligned scheme in related technologies;

[0035] Figure 2 This is a schematic diagram of a planar gate structure power device in related technologies;

[0036] Figure 3 This is a schematic diagram of a test device used in related technologies to characterize the mobility of planar gate structure power devices;

[0037] Figure 4 A schematic diagram of the structure of an embodiment of the semiconductor wafer provided in this application;

[0038] Figure 5 for Figure 4 A structural block diagram of an embodiment of region A, magnified;

[0039] Figure 6 This is a schematic diagram of the structure of an embodiment of the semiconductor test device provided in this application;

[0040] Figure 7 An equivalent circuit diagram of an embodiment of the semiconductor test device provided in this application.

[0041] Figure 8 A schematic diagram of some intermediate products after the second step in the fabrication method of the semiconductor test device provided in this application;

[0042] Figure 9 This is a schematic diagram of the process for forming the channel of a semiconductor test device using a self-aligned scheme.

[0043] Figure 10 A schematic diagram of some intermediate products after the fourth step in the fabrication method of the semiconductor test device provided in this application;

[0044] Figure 11 A schematic diagram of some intermediate products after step six in the method for fabricating the semiconductor test device provided in this application;

[0045] Figure 12 A schematic diagram of some intermediate products after the ninth step in the fabrication method of the semiconductor test device provided in this application;

[0046] Figure 13 A schematic diagram of some intermediate products after step eleven in the method for fabricating the semiconductor test device provided in this application;

[0047] Figure 14 A schematic diagram of some intermediate products after step thirteen in the method for fabricating the semiconductor test device provided in this application.

[0048] Label Explanation:

[0049] Semiconductor wafers - 300; Planar gate power devices - 200; Semiconductor testing devices - 100;

[0050] Substrate-10; Epitaxial layer-20; First doped region-30; First sub-doped region-31; Second sub-doped region-32; Third sub-doped region-33; Second doped layer-40; Fourth sub-doped region-41; Fifth sub-doped region-42; Third doped layer-50; Gate structure-60; First conductive electrode-61; First metal connecting strip-71; First metal connecting plate-72; Second conductive electrode-70; Third conductive electrode-80; Second metal connecting strip-81; Second metal connecting plate-82; First through-hole H1; Second through-hole H2; Third through-hole H3;

[0051] Semiconductor device area A1; Monitoring area A2;

[0052] First direction - Z; Second direction - Y; Width direction - X. Detailed Implementation

[0053] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0054] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0055] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0056] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0057] Compared to traditional Si MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and Si IGBT (Insulated Gate Bipolar Transistor) power devices, SiC MOSFETs, at the same doping concentration, have a theoretical on-resistance two orders of magnitude lower than Si and a breakdown voltage 10 times higher, thus attracting widespread attention. However, because the oxide layer grown by thermal oxidation of SiC cannot effectively remove carbon impurities and defects, the channel mobility of SiC MOSFETs is much lower than that of Si MOSFETs, resulting in a significantly higher channel resistance. To further reduce the turn-on losses of power devices, it is necessary to reduce the on-resistance. The most important technical approach is to continuously shrink the size of the unit cell, especially the channel length, increasing the number of SiC MOSFET cells connected in parallel per unit area, thereby improving current density and reducing cost.

[0058] Therefore, the development path of SiC MOSFET power devices is similar to that of Si power devices, namely, optimizing each process step to reduce the cell size. However, the smallest power device currently achievable is 0.5µm. To achieve channel lengths below 0.5µm, one approach is to use lithography machines with higher exposure precision and resolution, while another is to use a self-aligned approach to achieve feature sizes that current lithography machines cannot achieve. For the first approach, the primary challenge is the high cost. The most advanced lithography machines currently cost over $100 million, and achieving small sizes requires a series of materials and equipment, including specific photoresists, thin masks, and high-selectivity etching techniques, resulting in costs far exceeding the profit margins of the power device market. Another problem, as mentioned above, is that achieving small sizes relies on thin mask technology. However, to achieve the required voltage withstand capability (generally above 650V), the injection energy of power devices is very high, especially for SiC MOSFETs, where the maximum injection voltage is generally above 400keV due to the high material hardness, making thin mask technology unsuitable. Therefore, the second self-alignment scheme is the most effective way to achieve channels below 0.5um. Moreover, the self-alignment of the channel achieved by the second scheme does not need to consider the overlay accuracy of the two photomasks, which greatly improves the process stability. Figure 1 This is a schematic diagram illustrating the process of forming the channel of a power device using a self-aligned scheme in related technologies. Figure 1 The technological principles of the second scheme were demonstrated.

[0059] In this diagram, dielectric mask 1 is a P-type substrate implantation mask. After implantation, the P-type substrate implantation mask is not removed, and dielectric mask 2 is grown directly. The thickness of dielectric mask 2 can be less than 0.5 μm. After etching, dielectric mask 1 and dielectric mask 2 located on its sidewall are retained, while dielectric mask 2 in other locations is removed. Then, N-type heavy doping implantation is performed. Channels are automatically formed in the un-implanted N-type heavy doped areas of the P-type substrate, achieving self-alignment between the P-type substrate and the N-type heavy doped implantation layer and realizing a channel scheme of less than 0.5 μm. This technology has been widely adopted in the power device industry and has successfully promoted the miniaturization of cell size.

[0060] However, this technology introduces another technical problem: it cannot effectively characterize the channel mobility of power devices.

[0061] The following explanation uses a planar gate structure power device as an example.

[0062] See Figure 2 , Figure 2 This is a schematic diagram of a planar gate structure power device in related technologies. Figure 2The power device shown is a VDMOSFET (Vertical Double-Diffused Metal-Oxide-Semiconductor Field-Effect Transistor). Because the source and drain are located on the top and bottom sides of the device, respectively, its vertical structure results in many parasitic resistances in the current path, such as contact resistance R. C N-type heavily doped layer resistor R N+ Drift region (epipolar layer) resistance R dri Substrate resistance R sub The introduction of parasitic resistance, especially the drift region resistance R... dri The presence of this leads to a reduction in the actual current.

[0063] As mentioned above, the presence of defects such as C clusters in the gate oxide causes the mobility of SiC MOSFETs to be much lower than the theoretical value (400 cm² * V⁻¹ s⁻¹), only about 30–50 cm² * V⁻¹ s⁻¹. Therefore, the channel resistance of SiC MOSFETs is much greater than that of Si MOSFETs. Accurately characterizing the mobility of SiC MOSFETs is an important technique for evaluating gate oxide processes and a necessary requirement for monitoring product stability. The channel mobility is generally characterized using the Id-Vgs formula, with the field-effect mobility used as a benchmark to assess the level of process technology. To eliminate the influence of other parasitic resistances on the current Id, accurate characterization of the device channel mobility requires ensuring that the resistance of the test device only includes the channel resistance, or that the channel resistance accounts for the majority of the resistance. Therefore, the test device used to characterize the mobility of power devices is generally an LDMOSFET (Laterally Diffused Metal-Oxide-Semiconductor Field-Effect Transistor) power device. Figure 3 As shown, Figure 3 This is a schematic diagram of a test device used in related technologies to characterize the mobility of planar gate power devices. In actual fabrication, the P-type substrate and heavily doped N-type layer in the LDMOSFET test device are identical to those in the VDMOSFET power device, ensuring process consistency and enabling accurate evaluation of the power device's channel mobility.

[0064] Specifically, according to formula (1):

[0065]

[0066] Where W is the gate width, L is the gate length, and V ds V is the drain-source voltage. gs C is the gate voltage.ox For a unit area of ​​gate dielectric (typically SiO2) capacitance, I ds For the channel current, g m For I ds For V gs The derivative is the derivative span.

[0067] This formula assumes a voltage V from the source to the drain. ds Both are determined by the channel resistance R ch However, the actual current path also includes the ohmic contact resistance R. C N-type heavily doped resistor R N+ Therefore, the obtained current I ds The channel current is smaller than the actual channel current, and the calculated channel mobility μ is also smaller than the actual mobility. Furthermore, with the gate voltage V... gs The increase of channel resistance R ch Further reduction of parasitic resistance on channel current I ds The impact increases, and the channel current I ds With gate voltage V gs Deviating from linear relationship, transconductance g m Therefore, when calculating the mobility, I is generally taken as... ds For V gs The maximum transconductance g m.max Solve for the problem. Therefore, the mobility of a planar gate MOSFET measured based on formula (1) will be much smaller than the actual value.

[0068] Combination Figure 1 and Figure 2 As the cell size of VDMOSFETs shrinks, the channel length needs to be continuously reduced. This requires a continuous reduction in the thickness of the dielectric mask 2. When the thickness of the dielectric mask 2 is less than 0.45µm, it cannot effectively block N-type heavy doping implantation, causing the P-type substrate to invert into an N-type layer. For VDMOSFETs, this problem is not a concern because their structure only needs to ensure that N-type impurities cannot be implanted at the sidewall dielectric mask 2 locations. The height of the dielectric mask 1 can be perfectly converted into the thickness of the dielectric mask 2 to block N-type heavy doping implantation. However, see [link to relevant documentation]. Figure 3 In LDMOSFETs, to accurately characterize channel mobility, the channel length (typically greater than 5µm, with a typical value of 100µm) is much greater than the channel length of 0.5µm. This results in the mask thickness of the dielectric mask 2 on most of the P-type substrates of LDMOSFETs being only the thickness of the dielectric mask 2 itself during actual manufacturing processes.

[0069] When the thickness is insufficient to effectively block N-type heavy doping implantation, most of the P-type substrate transforms into an N-type doped layer, exacerbating the short-channel effect (which leads to a higher measured mobility than the actual value), and may even transform into a depletion-mode device.

[0070] To achieve limited compatibility between the LDMOSFET process and the VDMOSFET channel self-alignment process, and to ensure that the N-type injection mask in the LDMOSFET can block N-type injection and accurately characterize the channel mobility of the power device, we propose a semiconductor test device in which the channel length can still be maintained above 100µm, thereby ensuring that the channel resistance accounts for the majority of the signal.

[0071] See Figure 4 and Figure 5 , Figure 4 A schematic diagram of the structure of an embodiment of the semiconductor wafer provided in this application; Figure 5 for Figure 4 A structural block diagram of an embodiment, magnified from region A. The semiconductor test device 100 proposed in this application for characterizing the mobility of a planar gate MOSFET can be integrated with the planar gate MOSFET on the same semiconductor wafer 300.

[0072] Specifically, the semiconductor wafer 300 includes several semiconductor device regions A1 and several monitoring regions A2. Semiconductor devices, specifically planar gate structure power devices 200, are disposed in semiconductor device regions A1. At least one semiconductor test device 100 for testing the channel mobility of the planar gate structure power device 200 is disposed in the monitoring regions A2.

[0073] in, Figure 5 The semiconductor device region A1 is illustrated by way of example only, showing a single semiconductor device, and the monitoring region A2 is illustrated by way of example only, showing a single semiconductor test device 100. In other embodiments, the semiconductor device region A1 may contain multiple semiconductor devices, and the monitoring region A2 may contain multiple semiconductor test devices 100.

[0074] Specifically, the semiconductor wafer 300 provided in this application characterizes the mobility of the planar gate structure power device 200 by detecting the channel mobility of the semiconductor test device 100.

[0075] In one embodiment, the planar gate structure power device 200 may have the same structure as the planar gate structure power device in the prior art, and will not be described in detail here. Exemplarily, the planar gate structure power device 200 may be... Figure 2 The power device shown is a planar gate structure.

[0076] It should be noted that although this application uses a planar gate MOSFET as an example, it can also be applied to other power devices with planar gate structures, including but not limited to planar gate MOSFETs, IGBTs, Super Junction MOSFETs, etc. The device material can be SiC, or Si, Ga2O3, GaN, diamond, etc.

[0077] Specifically, the wafer structure and manufacturing process of the semiconductor test device 100 provided in this application embodiment are compatible with the wafer structure and manufacturing process of the actual wafer fabrication. Therefore, it can be integrated into the process control and monitoring area of ​​the layout for online process monitoring, monitoring the actual process capability and the true mobility of semiconductor power devices.

[0078] See Figure 6 , Figure 7 as well as Figure 9 , Figure 6 This is a schematic diagram of the structure of an embodiment of the semiconductor test device provided in this application; Figure 7 An equivalent circuit diagram of an embodiment of the semiconductor test device provided in this application; Figure 9 This is a schematic diagram of the process for forming the channel of a semiconductor test device using a self-aligned scheme.

[0079] Specifically, the semiconductor test device 100 mainly includes the following features:

[0080] The semiconductor test device 100 includes a substrate 10 having a first conductivity type, an epitaxial layer 20, and a second doped region 40; it also includes a first doped region 30 and a third doped region 50 having a second conductivity type; and it includes an output gate structure 60 for connecting to a first voltage, a second conductive electrode 70 for grounding, and a third conductive electrode 80 for connecting to an output terminal of a second voltage.

[0081] In this embodiment, one of the first conductivity type and the second conductivity type is a P-type conductivity type, and the other is an N-type conductivity type. In this application, the N-type conductivity type is used as the first conductivity type, and the P-type conductivity type is used as the second conductivity type.

[0082] The ion doping concentration of the second doped region 40 is greater than that of the epitaxial layer 20. The second doped region can be understood as the aforementioned N-type heavily doped layer. The ion doping concentration of the third doped region 50 is greater than that of the first doped region 30. The first doped region 30 can be understood as the aforementioned P-type base region, and the third doped region 50 can be understood as the P-type heavily doped region.

[0083] The first doped region 30 includes a first sub-doped region 31, a second sub-doped region 32, and a third sub-doped region 33. The first sub-doped region 31, the second sub-doped region 32, and the third sub-doped region 33 are all disposed in the epitaxial layer 20 and extend from the surface of the epitaxial layer 20 away from the substrate 10 along a first direction Z. The first direction Z is the direction of the epitaxial layer 20 toward the substrate 10. The first sub-doped region 31 and the second sub-doped region 32 are disposed at intervals along a second direction Y, and the third sub-doped region 33 connects the first sub-doped region 31 and the second sub-doped region 32.

[0084] The second doped region 40 includes a fourth sub-doped region 41 and a fifth sub-doped region 42. The fourth sub-doped region 41 is disposed within the first sub-doped region 31 and has a first spacing distance from the edge of the first sub-doped region 31. The fifth sub-doped region 42 is disposed within the second sub-doped region 32 and has a second spacing distance from the edge of the second sub-doped region 32. The fourth sub-doped region 41 and the fifth sub-doped region 42 extend from the surface of the epitaxial layer 20 away from the substrate 10 along a first direction Z. The first spacing distance is the same as the second spacing distance, and the width of the third sub-doped region 33 is greater than or equal to the first spacing distance and less than or equal to twice the first spacing distance. The width direction X of the third sub-doped region 33 is perpendicular to the first direction Z and the second direction Y.

[0085] The third doped region 50 is disposed in the epitaxial layer 20 and extends from the surface of the epitaxial layer 20 away from the substrate 10 along the first direction Z; wherein the third doped region 50 is disposed around the first doped region 30.

[0086] The gate structure 60 is at least partially disposed above the third sub-doped region 33 and extends above the fourth sub-doped region 41 and the fifth sub-doped region 42. The gate structure 60 includes a gate oxide layer (not shown) and a first conductive electrode 61. The gate oxide layer is located between the first conductive electrode 61 and the epitaxial layer 20. The first conductive electrode 61 is used to connect to the output terminal of the first voltage.

[0087] The second conductive electrode 70 is connected to the fourth sub-doped region 41 by an ohm contact and is also used for grounding. The third conductive electrode 80 is connected to the fifth sub-doped region 42 by an ohm contact and is also used for connecting to the input terminal of the second voltage.

[0088] Under test conditions, a first voltage and a second voltage are configured to turn on the semiconductor test device 100, thereby calculating the mobility of the semiconductor test device 100 to characterize the mobility of the planar gate structure power device 200. The first voltage can be equivalent to the voltage V between the source and gate of a normal power device. gs The second voltage can be equivalent to the voltage V between the source and drain of a normal power device.ds .

[0089] In one embodiment, under test conditions, a first voltage is configured to be greater than the absolute value of a threshold voltage of the first conductive electrode 61, and a second voltage is configured to be greater than 0V, thereby enabling the semiconductor test device 100 to be in a conducting state based on the first and second voltages. It should be noted that the second voltage can be configured to be greater than 0V and less than 0.5V.

[0090] It should be noted that, under the test conditions, the absolute value of the first voltage is configured to be greater than the absolute value of the threshold voltage of the gate structure 60.

[0091] For details, please refer to Figure 7 Taking an N-type doped semiconductor as an example, point G represents the first conductive electrode 61, which is connected to the output terminal of the first voltage V1; point D represents the third conductive electrode 80, which is connected to the output terminal of the second voltage V2; and point S represents the second conductive electrode 70, which is grounded. Under test conditions, the first voltage V1 is configured to be greater than the threshold voltage of the gate structure 60, and the second voltage V2 is configured to be greater than 0V, so that the semiconductor test device 100 is in a conducting state based on the first voltage V1 and the second voltage V2. Based on the test current I obtained at point S, the mobility of the semiconductor test device 100 is calculated to characterize the mobility of the planar gate structure power device 200.

[0092] Specifically, the structure of the semiconductor test device 100 provided in this application embodiment is such that the gate structure 60 for the output terminal for accessing the first voltage is at least partially disposed above the third sub-doped region 33 and extends above the fourth sub-doped region 41 and the fifth sub-doped region 42; and the second conductive electrode 70 for grounding is ohmically connected to the fourth sub-doped region 41, and the third conductive electrode 80 for the input terminal for accessing the second voltage is ohmically connected to the fifth sub-doped region 42. This allows the current path to flow from the fifth sub-doped region 42 along the third sub-doped region 33 to the fourth sub-doped region 41, thus eliminating the current path from passing through the epitaxial layer 20 and the substrate 10, and eliminating the drift region (i.e., the resistance R of the epitaxial layer 20). dri Substrate 10 resistor R sub The influence of parasitic resistance on mobility is investigated to achieve the goal of accurately characterizing the mobility of the planar gate structure power device 200.

[0093] Furthermore, the current path of the semiconductor test device 100 provided in this application embodiment is parallel to the extension direction (second direction Y) of the gate structure 60, which allows the channel length of the test device to be increased arbitrarily in the second direction Y, thereby achieving accurate characterization of the channel mobility.

[0094] Furthermore, the first spacing distance is set to be the same as the second spacing distance, and the width of the third sub-doped region 33 is greater than or equal to the first spacing distance and less than or equal to twice the first spacing distance. Therefore, in combination with... Figure 9 When the self-aligned dielectric mask 2 used for doping the second doped region 40 is deposited, the dielectric mask 2 on both sides above the third sub-doped region 33 automatically closes. The thickness of the dielectric mask 2 over the entire channel region (part of the first sub-doped region 31, part of the second sub-doped region 32, and the third sub-doped region 33) becomes the height of the dielectric mask 1. This effectively blocks the N-type heavily doped implanted channel region, preventing the device from becoming a depletion-type device. Moreover, this scheme achieves perfect compatibility with the self-aligned process.

[0095] Furthermore, when the first spacing distance and the second spacing distance are less than 0.5um, the width of the third sub-doped region 33 (corresponding to the width of the channel region) is less than 1um. This structure is suitable for power devices of arbitrary size and solves the problem of incompatibility between the self-alignment process of VDMOSFET power devices and LDMOSFET test devices.

[0096] In some embodiments, the width of the third sub-doped region 33 is equal to the first spacing distance; or, the width of the third sub-doped region 33 is equal to 1.5 times the first spacing distance; or, the width of the third sub-doped region 33 is equal to twice the first spacing distance. The specific design can be tailored to the actual situation.

[0097] In one embodiment of this application, the width of the third sub-doped region 33 is set to be twice the first spacing distance. Thus, when the self-aligned dielectric mask 2 used for doping the second doped region 40 is deposited, the dielectric mask 2 on both sidewalls above the third sub-doped region 33 automatically closes, and the thickness of the dielectric mask 2 can be perfectly converted into the height of the dielectric mask 1 to block the N-type heavily doped implantation channel region.

[0098] In some embodiments, to optimize layout and improve space utilization, such as Figure 6 As shown, the first sub-doped region 31 and the second sub-doped region 32 can be symmetrically arranged so that the first doped region 30 forms an I-shaped or H-shaped structure.

[0099] Of course, in other embodiments, the first sub-doped region 31 may also be tilted relative to the second sub-doped region 32. This is not a limitation.

[0100] In some embodiments, see Figure 6 The outer contour of the third doped region 50 is rectangular.

[0101] In some embodiments, please continue to see Figure 6The gate structure 60 includes a first connection region 601, a second connection region 602, and a third connection region 603. The first connection region 601 is at least partially disposed above the third sub-doped region 33 and extends above the fourth sub-doped region 41 and the fifth sub-doped region 42. The second connection region 602 is disposed on the epitaxial layer 20 and located outside the third doped region 50. The third connection region 603 is at least partially disposed above the third doped region 50, and one end of the third connection region 603 is connected to the first connection region 601, while the other end extends toward the region outside the third doped region 50 and is connected to the second connection region 602.

[0102] Understandably, the first doped region 30 below the first connection region 601 is the channel region of the semiconductor test device 100. Furthermore, in this embodiment, the width of the first connection region 601 is greater than the width of the third sub-doped region 33, to ensure that the entire third sub-doped region 33 can serve as a channel region.

[0103] Furthermore, the semiconductor test device 100 also includes an insulating layer (not shown), which covers the surface of the epitaxial layer 20 and also covers the gate structure 60; and see also Figure 6 The insulating layer has a first through hole H1, a second through hole H2 and a third through hole H3 that are spaced apart.

[0104] The first through-hole H1 corresponds to the second connection region 602; the semiconductor test device 100 also includes a conductive metal layer 62, which is ohmically connected to the first conductive electrode 61 through the first through-hole H1. In one embodiment, as... Figure 6 As shown, the first conductive electrode 61 is polycrystalline silicon, and the conductive metal layer 62 is ohmically connected to the polycrystalline silicon through the first through hole H1. The conductive metal layer 62 serves as the gate metal plate of the semiconductor test device 100.

[0105] The second via H2 is configured to correspond to a portion of the first sub-doped region 31, a portion of the fourth sub-doped region 41, and a portion of the third doped region 50; the second conductive electrode 70 is disposed on the insulating layer and is ohmically connected to the fourth sub-doped region 41 through the second via H2. Figure 6 As shown, the second conductive electrode 70 includes a first metal connecting strip 71 and a first metal connecting plate 72 that are electrically connected. The first metal connecting strip 71 is ohmically connected to the fourth sub-doped region 41 through the second through hole H2. The first metal connecting plate 72 is used for grounding to serve as the source metal plate of the device.

[0106] The third through-hole H3 corresponds to the fifth sub-doped region 42; the third conductive electrode 80 is disposed on the insulating layer and is ohmicly connected to the fifth sub-doped region 42 through the third through-hole H3. Figure 6As shown, the third conductive electrode 80 includes a second metal connecting strip 81 and a second metal connecting plate 82 that are electrically connected. The second metal connecting strip 81 is ohmically connected to the fifth sub-doped region 42 through the third through hole H3. The second metal connecting plate 82 is used to connect to the input terminal of the second voltage to serve as the drain metal plate of the device.

[0107] And understandably, in order to achieve insulation between the electrodes of the test device, such as Figure 6 As shown, the second conductive electrode 70, the third conductive electrode 80, and the conductive metal layer 62 are spaced apart.

[0108] In some embodiments, the resistivity of the second conductive electrode 70, the third conductive electrode 80, and the conductive metal layer 62 is all less than 1e-5Ω*cm. 2 This reduces the impact of the resistance of the second conductive electrode 70, the third conductive electrode 80, and the conductive metal layer 62 on the mobility.

[0109] The materials of the second conductive electrode 70, the third conductive electrode 80, and the ohmic contact electrodes between the conductive metal layer 62 and the underlying semiconductor material include, but are not limited to, Ti, Ni, Ti / N, TiN / Ni, Ta / Ni, Ta / TiN / Ni, Ti / W, etc.

[0110] Unlike existing technologies, the semiconductor testing device 100 provided in this application embodiment has the following features:

[0111] (1) The substrate 10 is the same as the substrate required for actual fabrication (such as the planar gate structure power device 200 in this application), and there are no special requirements.

[0112] (2) The epitaxial layer 20 adopts the concentration and thickness required for the device withstand voltage, with no additional requirements.

[0113] (3) The current path does not pass through the epitaxial layer 20 and the substrate 10, thus eliminating the resistance R of the drift region (i.e., the epitaxial layer 20). dri Substrate 10 resistor R sub The influence of parasitic resistance on mobility is investigated to achieve the goal of accurately characterizing the mobility of the planar gate structure power device 200.

[0114] (4) The problem of incompatibility between the self-alignment process of VDMOSFET power devices and LDMOSFET test devices has been solved.

[0115] This application also provides a method for fabricating a semiconductor testing device 100, taking SiC MOSFET wafer fabrication as an example. Specific embodiments are as follows:

[0116] The first step is to grow a 1.5 μm dielectric mask 1 on the SiC epitaxial layer 20 for use as an injection mask for the P-type substrate (not shown).

[0117] The second step involves photolithography and etching processes to define an I-shaped P-type substrate implantation region on the dielectric mask 1. The upper and lower implantation regions (i.e., the first sub-doped region 31 and the second sub-doped region) are 100µm x 100µm squares, while the middle implantation region (i.e., the third sub-doped region 33) is 0.9µm x 50µm. Figure 8 As shown, Figure 8 A schematic diagram of some intermediate products after the second step in the fabrication method of the semiconductor test device provided in this application.

[0118] The third step involves implanting Al elements to form a P-type substrate, followed by depositing a 0.45µm dielectric mask 2 to form the channel (0.45µm) of the VDMOSFET power device. In the LDMOSFET mobility test device, the 0.9*50µm channel is completely closed, as shown... Figure 9 As shown.

[0119] The fourth step involves photolithography and etching to define the heavily doped N-type implantation regions. These regions are located within the upper and lower P-type substrates (i.e., the fourth sub-doped region 41 and the fifth sub-doped region 42), with their boundaries 0.45 μm from the P-type substrate. This is automatically defined by the self-aligned dielectric mask 2. The channels in the P-type implantation regions are shielded by the dielectric mask 2 and do not require etching. Figure 10 As shown, Figure 10 A schematic diagram of some intermediate products after the fourth step in the fabrication method of the semiconductor test device provided in this application.

[0120] Step 5: Remove dielectric mask 1 and dielectric mask 2, and regenerate dielectric mask 3 (not shown).

[0121] Step 6: The dielectric mask 3 undergoes photolithography and etching processes to define the P-type heavily doped implantation region (i.e., the third doped region 50). This region is a rectangle with a central cutout, the boundary of which completely overlaps with the P-type base layer implantation region, thus encapsulating the P-type base layer. The P-type heavily doped implantation area in the upper and lower H-shaped regions is 140um * 25um, resulting in a combined implantation area of ​​140um * 300um for the P-type base layer and the P-type heavily doped implantation region. Figure 11 As shown, Figure 11 A schematic diagram of some intermediate products after step six in the method for fabricating the semiconductor test device provided in this application.

[0122] The sixth step involves the electrical activation of impurities in each doped region after high-temperature treatment.

[0123] Step 7: After high-temperature oxidation, a 50nm layer of SiO2 is grown on the SiC surface as the gate oxide of the LDMOSFET (not shown).

[0124] Step 8: Deposit a layer of heavily doped N-type polysilicon on the gate oxide layer with a thickness of 5000 Å (not shown).

[0125] Step nine involves forming a polysilicon gate (i.e., gate structure 60, including a first conductive electrode 61 and a gate oxide layer) after photolithography and etching. This polysilicon covers the middle channel region of the I-shaped P-type substrate (corresponding to the first connection region 601 of the gate structure 60), with a size of 1.5um * 55um, and extends to the left along the horizontal line of the I-shape, connecting to the polysilicon region on the left (corresponding to the second connection region 602 of the gate structure 60). The extension strip is rectangular in shape (corresponding to the third connection region 603 of the gate structure 60), with an area of ​​170um * 30um. The polysilicon region on the left is square in shape, with an area of ​​200um * 200um. Figure 12 As shown, Figure 12 A schematic diagram of some intermediate products after the ninth step in the fabrication method of the semiconductor test device provided in this application.

[0126] Step 10: Grow an interlayer dielectric layer as an insulating layer to cover the entire area (not shown).

[0127] Step 11: After photolithography, the interlayer dielectric layer is etched to complete the openings (first via H1, second via H2, and third via H3) in the source ohmic contact region, drain ohmic contact region, and gate ohmic contact region. Figure 13 As shown, Figure 13 This is a schematic diagram of a portion of the intermediate products after step eleven of the fabrication method for the semiconductor test device provided in this application. Specifically: the source ohmic contact region is located above the I-shaped structure, with a bottom layer covered by a partially P-type heavily doped layer and an N-type heavily doped layer, and has an area of ​​80µm * 30µm; the drain ohmic contact region is located below the I-shaped structure, with a bottom layer covered by an N-type heavily doped layer, and has an area of ​​80µm * 30µm; the gate ohmic contact region is located at the center of the square polycrystalline silicon region on the left, and has an area of ​​80µm * 80µm.

[0128] Step 12: Sputter a 1000 Å thick layer of nickel metal. After annealing, Ni forms nickel-silicon alloys with the P-type heavily doped layer, the N-type heavily doped layer of SiC, and the polysilicon in the gate ohmic contact region. Then, Ni metal removal solution is used to remove the nickel that has not formed nickel-silicon alloys.

[0129] Step thirteen: Sputter a 4µm thick AlCu alloy layer. After photolithography and etching, the source metal (i.e., the second conductive electrode 70), drain metal (i.e., the second conductive electrode 70), and gate metal (i.e., the conductive metal layer 62) are formed. Figure 14 As shown, Figure 14This is a schematic diagram of the product after the thirteenth step of the fabrication method for the semiconductor test device provided in this application. The source metal covers the source ohmic contact area and consists of a 230um*50um source metal strip and a 100um*100um square source metal plate; the drain metal covers the source ohmic contact area and consists of a 230um*50um drain metal strip and a 100um*100um square drain metal plate; the gate metal covers the gate ohmic contact area, forming a 100um*100um square gate metal plate.

[0130] After the above steps, a semiconductor test device 100 is formed.

[0131] This application also provides a mobility testing method applied to a semiconductor wafer 300. The testing method includes:

[0132] The first conductive electrode 61 in the semiconductor test device 100 receives the first voltage V1 output from the first voltage output terminal.

[0133] In addition, the third conductive electrode 80 of the semiconductor test device 100 receives the second voltage V2 output from the output terminal of the second voltage.

[0134] Based on the second voltage V2, the test current I on the third conductive electrode 80 and / or the second conductive electrode 70 is detected.

[0135] Based on the first voltage V1 and the threshold voltage V th The channel mobility μ of the semiconductor test device 100 is determined by the second voltage V2 and the test current I.

[0136] Based on the channel mobility μ of the semiconductor test device 100, the channel mobility of the planar gate structure power device 200 in the semiconductor wafer 300 is determined.

[0137] Wherein, the first voltage V1 is greater than the threshold voltage V of the gate structure 60. th The second voltage V2 is greater than 0V. Specifically, under test conditions, the first voltage V1 and the second voltage V2 are configured to turn on the semiconductor test device 100.

[0138] Specifically, when the first conductivity type is an N-type doped semiconductor and the second conductivity type is a P-type semiconductor, the second conductive electrode 70 is grounded, and the third conductive electrode 80 is connected to the output terminal of the second voltage to receive the second voltage V2. Furthermore, when the semiconductor test device 100 is in the on-state, the test current I on the second conductive electrode 70 is detected. At this time, the first voltage is configured to be greater than the threshold voltage of the gate structure 60.

[0139] Specifically, when the first conductivity type is a P-type doped semiconductor and the second conductivity type is an N-type semiconductor, the second conductive electrode 70 is grounded, and the third conductive electrode 80 is connected to the output terminal of the second voltage to receive the second voltage V2. Furthermore, when the semiconductor test device 100 is in the on-state, the test current I on the third conductive electrode 80 is detected. At this time, the absolute value of the first voltage is configured to be greater than the absolute value of the threshold voltage of the gate structure 60.

[0140] In one embodiment, along the second direction X, the first doped region 30 between the fourth sub-doped region 41 and the fifth sub-doped region 42 is defined as the channel region, and the overlapping region of the projection region of the first conductive electrode 61 on the epitaxial layer 20 and the channel region is defined as the channel region.

[0141] The testing method also includes:

[0142] Determine the length L of the channel region along the second direction Y, and the width W of the channel region along the third direction X.

[0143] Among them, with Figure 6 For example, the length L of the channel region along the second direction Y is the distance between the fourth sub-doped region 41 and the fifth sub-doped region 42, and the width W of the channel region along the third direction X is the width of the third sub-doped region 33.

[0144] In one embodiment, based on a first voltage V1 and a threshold voltage V th The channel mobility μ of the semiconductor test device 100 is determined using the second voltage V2 and the test current I, including:

[0145] Based on the first voltage V1 and the threshold voltage V th The channel mobility μ of the semiconductor test device 100 is determined by the second voltage V2, the test current I, the length L, and the width W.

[0146] In one embodiment, the testing method further includes:

[0147] Determine the width T of the gate oxide layer along the first direction Z. ox .

[0148] Based on the thickness T of the gate oxide layer ox ,use The capacitance C per unit area of ​​the gate oxide layer was calculated. ox .

[0149] Where ε0 is the vacuum permittivity, ε ox T is the relative permittivity of SiO2. ox The width of the gate oxide layer along the first direction Z.

[0150] In this embodiment, based on the first voltage V1 and the threshold voltage V thThe channel mobility μ of the semiconductor test device 100 is determined by the second voltage V2, the test current I, the length L, and the width W, including:

[0151] Based on the first voltage V1 and the threshold voltage Vth, the second voltage V2 and the test current I, as well as the length L and the width W, and the capacitance C of the gate structure 60. ox Using the formula The channel mobility μ of the semiconductor test device 100 was calculated.

[0152] The channel mobility μ of the semiconductor test device 100 is used to characterize the channel mobility of the planar gate structure power device 200.

[0153] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A semiconductor testing device, characterized in that, include: Substrate; An epitaxial layer is disposed on the surface of the substrate, wherein the substrate and the epitaxial layer are of a first conductivity type; A first doped region, including a first sub-doped region, a second sub-doped region, and a third sub-doped region, is disposed in the epitaxial layer and extends from the surface of the epitaxial layer away from the substrate along a first direction; the first direction is the direction of the epitaxial layer toward the substrate; the first doped region is of a second conductivity type; wherein, the first sub-doped region and the second sub-doped region are spaced apart along a second direction, and the third sub-doped region connects the first sub-doped region and the second sub-doped region; the first doped region is of a second conductivity type. The second doped region includes a fourth sub-doped region and a fifth sub-doped region. The fourth sub-doped region is disposed within the first sub-doped region and has a first spacing distance from the edge of the first sub-doped region. The fifth sub-doped region is disposed within the second sub-doped region and has a second spacing distance from the edge of the second sub-doped region. The fourth and fifth sub-doped regions extend from the surface of the epitaxial layer away from the substrate along the first direction. The second doped region is of a first conductivity type. The first spacing distance is the same as the second spacing distance. The width of the third sub-doped region is greater than or equal to the first spacing distance and less than or equal to twice the first spacing distance. The width direction of the third sub-doped region is perpendicular to both the first and second directions. A third doped region is disposed in the epitaxial layer and extends from the surface of the epitaxial layer away from the substrate along a first direction; the third doped region is disposed around the first doped region; the third doped region is of a second conductivity type. A gate structure is at least partially disposed above the third sub-doped region and extends above the fourth sub-doped region and the fifth sub-doped region; wherein the gate structure includes a gate oxide layer and a first conductive electrode, the gate oxide layer is located between the first conductive electrode and the epitaxial layer, and the first conductive electrode is used to connect to the output terminal of a first voltage; The second conductive electrode is ohmic contacted with the fourth sub-doped region, and the second conductive electrode is used for grounding; The third conductive electrode is ohmicly connected to the fifth sub-doped region, and the third conductive electrode is used to connect to the input terminal of the second voltage.

2. The semiconductor testing device according to claim 1, characterized in that, Under the test conditions, the absolute value of the first voltage is configured to be greater than the absolute value of the threshold voltage of the first conductive electrode, and the second voltage is configured to be greater than 0V.

3. The semiconductor testing device according to claim 1, characterized in that, Under test conditions, the first voltage and the second voltage are configured to turn on the semiconductor test device.

4. The semiconductor testing device according to claim 1, characterized in that, The semiconductor test device is used to test the mobility of planar gate structure power devices.

5. The semiconductor testing device according to any one of claims 1-4, characterized in that, The width of the third sub-doped region is equal to twice the first spacing distance.

6. The semiconductor testing device according to any one of claims 1-4, characterized in that, The first sub-doped region and the second sub-doped region are symmetrically arranged.

7. The semiconductor testing device according to any one of claims 1-4, characterized in that, The outer contour of the third doped region is rectangular.

8. The semiconductor testing device according to any one of claims 1-4, characterized in that, The gate structure includes a first connection region, a second connection region, and a third connection region. The first connection region is at least partially disposed above the third sub-doped region and extends above the fourth and fifth sub-doped regions. The second connection region is disposed on the epitaxial layer and located outside the third doped region. The third connection region is at least partially disposed above the third doped region, and one end of the third connection region is connected to the first connection region, while the other end extends toward the region outside the third doped region and is connected to the second connection region.

9. The semiconductor testing device according to claim 8, characterized in that, The width of the first connection region is greater than the width of the third sub-doped region.

10. The semiconductor testing device according to claim 8, characterized in that, Also includes: An insulating layer covers the surface of the epitaxial layer and the gate structure; and the insulating layer has a first through-hole, a second through-hole, and a third through-hole spaced apart; wherein, the first through-hole corresponds to the second connection region; the second through-hole corresponds to a portion of the first sub-doped region, a portion of the fourth sub-doped region, and a portion of the third doped region; and the third through-hole corresponds to the second sub-doped region. The second conductive electrode is ohmically connected to the fourth sub-doped region through the second through-hole; the third conductive electrode is ohmically connected to the fifth sub-doped region through the third through-hole. Also includes: The conductive metal layer is electrically connected to the first conductive electrode through the first through hole.

11. A semiconductor wafer, characterized in that, The semiconductor wafer includes: Several semiconductor device regions, wherein the semiconductor devices in the semiconductor device regions are planar gate structure power devices; Several monitoring areas are provided with at least one semiconductor test device for testing the channel mobility of the planar gate structure power device, the semiconductor test device comprising: Substrate; An epitaxial layer is disposed on the surface of the substrate, wherein the substrate and the epitaxial layer are of a first conductivity type; A first doped region, including a first sub-doped region, a second sub-doped region, and a third sub-doped region, is disposed in the epitaxial layer and extends from the surface of the epitaxial layer away from the substrate along a first direction; the first direction is the direction of the epitaxial layer toward the substrate; the first doped region is of a second conductivity type; wherein, the first sub-doped region and the second sub-doped region are spaced apart along a second direction, and the third sub-doped region connects the first sub-doped region and the second sub-doped region; the first doped region is of a second conductivity type. The second doped region includes a fourth sub-doped region and a fifth sub-doped region. The fourth sub-doped region is disposed within the first sub-doped region and has a first spacing distance from the edge of the first sub-doped region. The fifth sub-doped region is disposed within the second sub-doped region and has a second spacing distance from the edge of the second sub-doped region. The fourth and fifth sub-doped regions extend from the surface of the epitaxial layer away from the substrate along the first direction. The second doped region is of a first conductivity type. The first spacing distance is the same as the second spacing distance. The width of the third sub-doped region is greater than or equal to the first spacing distance and less than or equal to twice the first spacing distance. The width direction of the third sub-doped region is perpendicular to both the first and second directions. A third doped region is disposed in the epitaxial layer and extends from the surface of the epitaxial layer away from the substrate along a first direction; the third doped region is disposed around the first doped region; the third doped region is of a second conductivity type. A gate structure is at least partially disposed above the third sub-doped region and extends above the fourth sub-doped region and the fifth sub-doped region; wherein the gate structure includes a gate oxide layer and a first conductive electrode, the gate oxide layer is located between the first conductive electrode and the epitaxial layer, and the first conductive electrode is used to connect to the output terminal of a first voltage; The second conductive electrode is ohmic contacted with the fourth sub-doped region, and the second conductive electrode is used for grounding; The third conductive electrode is ohmicly connected to the fifth sub-doped region, and the third conductive electrode is used to connect to the input terminal of the second voltage.

12. The semiconductor wafer according to claim 11, characterized in that, The width of the third sub-doped region is equal to twice the first spacing distance.

13. The semiconductor wafer according to claim 11, characterized in that, The first sub-doped region and the second sub-doped region are symmetrically arranged.

14. The semiconductor wafer according to claim 11, characterized in that, The outer contour of the third doped region is rectangular.

15. The semiconductor wafer according to claim 11, characterized in that, The gate structure includes a first connection region, a second connection region, and a third connection region. The first connection region is at least partially disposed above the third sub-doped region and extends above the fourth and fifth sub-doped regions. The second connection region is disposed on the epitaxial layer and located outside the third doped region. The third connection region is at least partially disposed above the third doped region, and one end of the third connection region is connected to the first connection region, while the other end extends toward the region outside the third doped region and is connected to the second connection region.

16. The semiconductor wafer according to claim 15, characterized in that, The width of the first connection region is greater than the width of the third sub-doped region.

17. The semiconductor wafer according to claim 15, characterized in that, The semiconductor testing device also includes: An insulating layer covers the surface of the epitaxial layer and the gate structure; and the insulating layer has a first through-hole, a second through-hole, and a third through-hole spaced apart; wherein, the first through-hole corresponds to the second connection region; the second through-hole corresponds to a portion of the first sub-doped region, a portion of the fourth sub-doped region, and a portion of the third doped region; and the third through-hole corresponds to the second sub-doped region. The second conductive electrode is ohmically connected to the fourth sub-doped region through the second through hole, and the second conductive electrode is used for grounding; the third conductive electrode is ohmically connected to the fifth sub-doped region through the third through hole, and the third conductive electrode is used for connecting to the input terminal of the second voltage; The semiconductor testing device also includes: The conductive metal layer is electrically connected to the first conductive electrode through the first through hole.

18. A mobility testing method, characterized in that, This invention is applied in a semiconductor wafer, the semiconductor wafer comprising: several semiconductor device regions, wherein the semiconductor devices in the semiconductor device regions are planar gate structure power devices; several monitoring regions, each having at least one semiconductor test device for testing the channel mobility of the planar gate structure power devices, the semiconductor test device comprising: a substrate; an epitaxial layer disposed on the surface of the substrate, the substrate and the epitaxial layer being of a first conductivity type; and a first doped region comprising a first sub-doped region, a second sub-doped region, and a third sub-doped region, all disposed in the epitaxial layer and extending from the surface of the epitaxial layer away from the substrate along a first direction. Extended; the first direction is the direction of the epitaxial layer toward the substrate; the first doped region is of the second conductivity type; wherein, the first sub-doped region and the second sub-doped region are spaced apart along the second direction, and the third sub-doped region connects the first sub-doped region and the second sub-doped region; the first doped region is of the second conductivity type; the second doped region includes a fourth sub-doped region and a fifth sub-doped region, the fourth sub-doped region is disposed in the first sub-doped region and has a first spacing distance from the edge of the first sub-doped region, and the fifth sub-doped region is disposed in the second sub-doped region and has a second spacing distance from the edge of the second sub-doped region. The first and second doped regions are spaced apart, and the fourth and fifth sub-doped regions extend from the surface of the epitaxial layer away from the substrate along the first direction; the second doped region is of a first conductivity type; wherein, the first spacing distance is the same as the second spacing distance, and the width of the third sub-doped region is greater than or equal to the first spacing distance and less than or equal to twice the first spacing distance; the width direction of the third sub-doped region is perpendicular to both the first and second directions; a third doped region is disposed in the epitaxial layer and extends from the surface of the epitaxial layer away from the substrate along the first direction; the third doped region surrounds the first doped region. The configuration includes: a third doped region of a second conductivity type; a gate structure, at least partially disposed above the third sub-doped region, extending above the fourth and fifth sub-doped regions; wherein the gate structure includes a gate oxide layer and a first conductive electrode, the gate oxide layer being located between the first conductive electrode and the epitaxial layer, the first conductive electrode being used to connect to the output terminal of a first voltage; a second conductive electrode, ohmically connected to the fourth sub-doped region, and the second conductive electrode being used to ground; and a third conductive electrode, ohmically connected to the fifth sub-doped region, and the third conductive electrode being used to connect to the input terminal of a second voltage. The testing method includes: The first conductive electrode in the semiconductor test device receives a first voltage V1 output from the output terminal of the first voltage, wherein the first voltage V1 is greater than the threshold voltage V of the gate structure. th ; The third conductive electrode of the semiconductor test device receives the second voltage V2 output from the output terminal of the second voltage, wherein the second voltage V2 is greater than 0V; Based on the second voltage V2, the test current I on the second conductive electrode and / or the third conductive electrode is detected; Based on the first voltage V1 and the threshold voltage V th The channel mobility μ of the semiconductor test device is determined by the second voltage V2 and the test current I. Based on the channel mobility μ of the semiconductor test device, the channel mobility of the planar gate structure power device in the semiconductor wafer is determined.

19. The method according to claim 18, characterized in that, Along the second direction, the first doped region between the fourth sub-doped region and the fifth sub-doped region is defined as the channel region, and the overlapping region of the projection region of the first conductive electrode in the epitaxial layer and the channel region is defined as the channel region. The method further includes: Determine the length L of the channel region along the second direction, and the width W of the channel region along the third direction; The first voltage V1 and the threshold voltage V th The second voltage V2 and the test current I are used to determine the channel mobility μ of the semiconductor test device, including: Based on the first voltage V1 and the threshold voltage V th The channel mobility μ of the semiconductor test device is determined by the second voltage V2, the test current I, the length L, and the width W.

20. The method according to claim 19, characterized in that, The method further includes: Determine the thickness T of the gate oxide layer along the first direction. ox ; Based on the thickness T of the gate oxide layer ox ,use The capacitance C per unit area of ​​the gate oxide layer was calculated. ox ; The first voltage V1 and the threshold voltage V th The second voltage V2, the test current I, the length L, and the width W are used to determine the channel mobility μ of the semiconductor test device, including: Based on the first voltage V1 and the threshold voltage V th The second voltage V2 and the test current I, as well as the length L and width W, and the capacitance C of the gate oxide layer. ox Using the formula The channel mobility μ of the semiconductor test device was calculated.

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