A semiconductor structure and a method of forming the same
By removing part of the first interlayer dielectric layer in a semiconductor structure and filling it with a barrier layer and an air gap, the problem of insufficient dielectric layer reliability is solved, and the breakdown strength of the dielectric layer and the stability of the metal interconnect are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SEMICON TECH INNOVATION CENT(BEIJING) CORP
- Filing Date
- 2024-12-02
- Publication Date
- 2026-06-05
AI Technical Summary
With the development of integrated circuits, metal interconnects are becoming longer and longer, which reduces the mechanical strength and inherent breakdown strength of the interlayer dielectric layer, leading to reliability issues of the dielectric layer, especially the insufficient reliability of the inter-metal dielectric after breakdown over time.
After filling the metal layer through the opening on the top surface of the first interlayer dielectric layer, a portion of the dielectric layer is removed to form a barrier layer. Then, the second interlayer dielectric layer is filled, and an air gap is formed in the dielectric layer to prevent the diffusion of metal cations and improve the breakdown strength of the dielectric layer.
This effectively avoids the breakdown effect of metal cations on the dielectric layer, enhances the reliability and breakdown strength of the dielectric layer, and improves the long-term stability of the semiconductor structure.
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Figure CN122161430A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology
[0002] With the development of integrated circuits and the miniaturization of critical dimensions, metal interconnects in back-end processes are becoming increasingly longer. In order to reduce parasitic capacitance in the back-end, materials with ultra-low dielectric constant (Ultra Low-K, ULK) are often used for interlayer dielectric layers. This leads to an increase in defects in the interlayer dielectric layers in the back-end processes, a decrease in the mechanical strength and inherent breakdown strength of the interlayer dielectric layers, and a reduction in the long-term reliability of the interlayer dielectric layers, especially the reliability of interlayer dielectric-time-dependent dielectric breakdown (IMD-TDDB).
[0003] Therefore, it is necessary to develop a method for forming semiconductor structures to improve the reliability of interlayer dielectric layers in subsequent processes. Summary of the Invention
[0004] The purpose of this application is to provide a semiconductor structure and a method for forming the same, so as to improve the reliability of the interlayer dielectric layer in the subsequent process.
[0005] In a first aspect, this application provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first interlayer dielectric layer; forming a plurality of openings in the first interlayer dielectric layer; forming a metal layer, the metal layer including a plurality of metal wires filling the plurality of openings; removing a portion of the first interlayer dielectric layer such that the top surface of the first interlayer dielectric layer is lower than the top surface of the metal layer; forming a barrier layer covering the surface of the metal wires; and forming a second interlayer dielectric layer, the second interlayer dielectric layer filling the gaps between adjacent metal wires in the metal layer.
[0006] In some embodiments, an air gap is formed in the second interlayer dielectric layer between some adjacent metal wires.
[0007] In some embodiments, the method of forming the air gap includes: forming a second interlayer dielectric layer in the gap by deposition, and controlling the deposition rate during the deposition of the second interlayer dielectric layer such that the ratio of the closing time of the top of the second interlayer dielectric layer to the total time to fill the gap is (0.3 to 0.8):1.
[0008] In some embodiments, the volume ratio of the air gap between adjacent metal wires to the total volume of the second interlayer dielectric layer is (0.1 to 0.8):1.
[0009] In some embodiments, the method for removing a portion of the first interlayer dielectric layer includes wet etching or dry etching.
[0010] In some embodiments, the ratio of the thickness of the first interlayer dielectric layer removal portion to the thickness of the metal layer is (0.1 to 0.5):1.
[0011] In some embodiments, the barrier layer is made of at least one of silicon nitride and polycrystalline silicon.
[0012] Secondly, this application also provides a semiconductor structure, comprising: a substrate, the substrate including a first interlayer dielectric layer, the first interlayer dielectric layer including a plurality of openings; a metal layer, the metal layer including a plurality of metal wires filling the plurality of openings, and the top surface of the metal wires being higher than the top surface of the first interlayer dielectric layer; a barrier layer, the barrier layer covering the top surface of the metal layer and the surface of the metal wires protruding from the first interlayer dielectric layer; and a second interlayer dielectric layer, the second interlayer dielectric layer filling the gaps between adjacent metal wires in the metal layer.
[0013] In some embodiments, an air gap is formed in the second interlayer dielectric layer between some adjacent metal wires.
[0014] In some embodiments, the volume ratio of the air gap between the adjacent metal wires to the total volume of the second interlayer dielectric layer is (0.1 to 0.8):1.
[0015] The beneficial effects of the semiconductor structure and its fabrication method provided in this application include, but are not limited to, the following:
[0016] This application removes a portion of the first interlayer dielectric layer located between adjacent metal wires in the metal layer after opening the top surface of the first interlayer dielectric layer and filling it with a metal layer. This removes the contaminated first interlayer dielectric layer with metal cations attached due to the chemical mechanical polishing of the metal layer. The portion of the first interlayer dielectric layer that has been removed is then filled with a second interlayer dielectric layer, thereby avoiding the impact of metal cations on the reliability of the dielectric layer after breakdown over time.
[0017] In addition, before filling the second interlayer dielectric layer, a barrier layer is formed covering the surface of the metal layer. The barrier layer can prevent metal cations generated by the ionization of the metal wires during TDDB testing from diffusing into the second interlayer dielectric layer and affecting the time-dependent breakdown reliability of the second interlayer dielectric layer.
[0018] Furthermore, an air gap is formed inside the second interlayer dielectric layer. Since air has a high breakdown voltage, forming an air gap in the second interlayer dielectric layer can enhance the breakdown strength of the second interlayer dielectric layer. Attached Figure Description
[0019] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale.
[0020] in:
[0021] Figures 1-12 This is a schematic diagram of the formation process of a semiconductor structure according to some embodiments of this application. Detailed Implementation
[0022] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.
[0023] In later-stage processes, the width or spacing of metal interconnects becomes increasingly smaller, and the introduction of ultra-low-K (ULK) materials leads to a continuous decrease in the voltage breakdown (Vbd) of interlayer dielectric layers. Furthermore, the application of double patterning technology in later-stage processes introduces early failure issues caused by misalignment during overlay. All of these factors affect the reliability of interlayer dielectric-time-dependent dielectric breakdown (IMD-TDDB).
[0024] Furthermore, during the later stages of the manufacturing process, the charge generated during chemical mechanical polishing of the copper metal layer can create a weak potential difference between adjacent copper lines within the same metal layer. This causes partial oxidation of the copper metal layer surface during chemical mechanical polishing, leading to the ionization of copper atoms and the formation of Cu. 2+ Furthermore, Cu is generated between adjacent copper wires under the influence of potential difference. 2+ Current degrades the reliability of interlayer dielectric layer breakdown over time. During TDDB testing, different voltages are applied to adjacent copper wires, causing some of the copper in the wires to ionize under stress, forming Cu.2+ It diffuses into the interlayer dielectric layer, further reducing the reliability of the interlayer dielectric layer after breakdown over time.
[0025] The main solution to optimize IMD-TDDB is to increase the minimum linewidth. However, increasing the minimum linewidth will have an adverse effect on the circuit and application, and it cannot improve the surface quality of the dielectric layer, nor can it prevent the diffusion of metal cations formed by the ionization of metal wires into the dielectric layer.
[0026] This application provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first interlayer dielectric layer; forming a plurality of openings in the first interlayer dielectric layer; forming a metal layer, the metal layer including a plurality of metal wires filling the plurality of openings; removing a portion of the first interlayer dielectric layer such that the top surface of the first interlayer dielectric layer is lower than the top surface of the metal layer; forming a barrier layer covering the surface of the metal wires; and forming a second interlayer dielectric layer, the second interlayer dielectric layer filling the gaps between adjacent metal wires in the metal layer.
[0027] During the formation of the metal layer, a chemical mechanical polishing (CMP) process is used to make the top surface of the metal layer coplanar with the top surface of the first interlayer dielectric layer. During CMP, the metal wires are ionized to produce metal cations, which adhere to the top surface of the first interlayer dielectric layer. By removing part of the first interlayer dielectric layer and then filling it with a second interlayer dielectric layer to replace the removed first interlayer dielectric layer, that is, the contaminated first interlayer dielectric layer with attached metal cations is removed, and the removed part of the first interlayer dielectric layer is filled with the second interlayer dielectric layer, thereby avoiding the impact of metal cations on the reliability of the dielectric layer after breakdown over time.
[0028] In addition, before filling the second interlayer dielectric layer, a barrier layer is formed covering the surface of the metal layer. The barrier layer can prevent metal cations generated by the ionization of the metal wires during TDDB testing from diffusing into the second interlayer dielectric layer and affecting the time-dependent breakdown reliability of the second interlayer dielectric layer.
[0029] The method for forming the semiconductor structure provided in this application will be described in detail below with reference to specific embodiments and accompanying drawings.
[0030] It should be noted that this application describes various operations sequentially as multiple discrete operations in a manner most conducive to understanding this application; however, the order of description should not be interpreted as implying that these operations must depend on the order. More specifically, these operations do not need to be performed in the order described.
[0031] refer to Figure 1 A substrate is provided, the substrate including a first interlayer dielectric layer 200.
[0032] In some embodiments, the substrate further includes a first metal layer 100, wherein the first interlayer dielectric layer 200 covers the top surface of the first metal layer 100.
[0033] In some embodiments, the substrate further includes a semiconductor substrate (not shown), and the first metal layer 100 covers the top surface of the semiconductor substrate. In some embodiments, the material of the semiconductor substrate includes (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or gallium indium phosphide; or silicon on insulator (SOI) or (iv) a combination thereof.
[0034] The first metal layer 100 is any metal layer of the metal interconnect structure in the subsequent process (except for the last metal layer).
[0035] In some embodiments, the material of the first metal layer 100 includes copper.
[0036] In some embodiments, the material of the first interlayer dielectric layer 200 is a material having an ultra-low dielectric constant K (ULK), such as SiOC, SiCOH, or a combination thereof with a dielectric constant of 2.2 to 2.4.
[0037] refer to Figures 2-4 A plurality of openings 300 are formed in the first interlayer dielectric layer 200.
[0038] Specifically, in some embodiments, the method of forming the plurality of openings 300 includes: stacking a hard mask layer 210 and a photolithography layer 220 sequentially on the top surface of the first interlayer dielectric layer 200; forming an opening 230 in the hard mask layer 210 by photolithography; and continuing to etch along the opening 230 to form the opening 300 in the first interlayer dielectric layer 200.
[0039] In some embodiments, the hard mask layer 210 includes a first hard mask layer 211 and a second hard mask layer 212 sequentially stacked on the top surface of the first interlayer dielectric layer 200. In some embodiments, the material of the first hard mask layer 211 includes TiN; the material of the second hard mask layer 212 includes SiOC.
[0040] In some embodiments, the photolithography layer 220 includes an organic carbon layer (ODL) 221, a Si-containing antireflective coating (SiARC) 222, and a photoresist layer (PR) 223, which are sequentially stacked on the top surface of the hard mask layer 210.
[0041] In some embodiments, the method for forming the opening 300 is anisotropic etching. The direction of anisotropic etching is perpendicular to the surface of the first interlayer dielectric layer 200 and downwards. The etching speed is faster only in the vertical direction, and slower in other directions. Therefore, the shape of the opening 300 in the first interlayer dielectric layer 200 is an inverted trapezoid, that is, the width of the opening 300 gradually decreases along the direction from the top surface of the first interlayer dielectric layer 200 to the bottom surface of the first interlayer dielectric layer 200.
[0042] Continue to refer to Figure 5 A second metal layer 400 is formed, the second metal layer 400 including a plurality of metal wires 410 filling the opening 300 and covering the top surface of the first interlayer dielectric layer 200.
[0043] In some embodiments, the method for forming the second metal layer 400 includes, but is not limited to, electroplating, chemical vapor deposition, atomic layer deposition, physical vapor deposition, and sputtering.
[0044] In some embodiments, the material of the second metal layer 400 includes copper.
[0045] In some embodiments, a diffusion barrier layer (not shown) is further formed between the second metal layer 400 and the first interlayer dielectric layer 200. In some embodiments, the material of the diffusion barrier layer includes tantalum nitride (TaN).
[0046] In some embodiments, a seed layer (not shown) is further formed on the surface of the diffusion barrier layer facing the second metal layer 400. The material of the seed layer includes copper.
[0047] In some embodiments, reference Figure 6 After forming the second metal layer 400, the method further includes: planarizing the second metal layer 400 so that the top surface of the second metal layer 400 is flush with the top surface of the first interlayer dielectric layer 200.
[0048] In some embodiments, the method of planarizing the second metal layer 400 includes chemical mechanical polishing.
[0049] refer to Figure 7 or Figure 8 A portion of the first interlayer dielectric layer 200 is removed, so that the top surface of the first interlayer dielectric layer 200 is lower than the top surface of the second metal layer 400.
[0050] During chemical mechanical polishing, the metal wire 410 is ionized into metal cations. These metal cations adhere to the top surface of the first interlayer dielectric layer 200, affecting the reliability of the first interlayer dielectric layer 200 over time. By removing a portion of the first interlayer dielectric layer 200, the metal cations attached to the top surface of the first interlayer dielectric layer 200 can be removed.
[0051] In some embodiments, the ratio of the thickness of the removed portion of the first interlayer dielectric layer 200 to the thickness of the second metal layer 400 is (0.1 to 0.5):1, for example, 0.1:1, 0.2:1, 0.3:1, 0.4:1, or 0.5:1. Generally, the metal cations generated during chemical mechanical polishing not only adhere to the top surface of the first interlayer dielectric layer 200 but also partially penetrate into the interior of the first interlayer dielectric layer 200. If the thickness of the removed portion of the first interlayer dielectric layer 200 is too low, the metal cations penetrating into the interior of the first interlayer dielectric layer 200 cannot be removed. If the thickness of the removed portion of the first interlayer dielectric layer 200 is too high, the metal wires 410 in the second metal layer 400 may shift or even detach from the first interlayer dielectric layer 200 due to lack of support.
[0052] refer to Figure 7 In some embodiments, the method for removing a portion of the first interlayer dielectric layer 200 includes dry etching.
[0053] Part of the first interlayer dielectric layer 200 is removed by dry etching. In dry etching, the etched surface is relatively smooth, which is beneficial for controlling the subsequent deposition process.
[0054] refer to Figure 8 In some embodiments, the method for removing the first interlayer dielectric layer 200 includes wet etching.
[0055] Part of the first interlayer dielectric layer 200 is removed by wet etching. During wet etching, the metal cations located in the first interlayer dielectric layer 200 are removed from the gap along with the etching waste liquid, thus avoiding the residue of metal cations.
[0056] The subsequent processes for removing a portion of the first interlayer dielectric layer 200 using wet etching are the same as or similar to those for removing a portion of the first interlayer dielectric layer 200 using dry etching. Details of the process after removing a portion of the first interlayer dielectric layer 200 will be provided later. Figure 7 The following explanation uses the example of a semiconductor structure in which the first interlayer dielectric layer 200 is partially removed by dry etching.
[0057] Figures 9-11 for Figure 7The diagram shows a semiconductor structure for subsequent processes of dry etching to remove part of the first interlayer dielectric layer 200. Figure 12 for Figure 8 The diagram shows a semiconductor structure for subsequent processes of wet etching to remove a portion of the first interlayer dielectric layer 200.
[0058] refer to Figure 9 This forms a barrier layer 500 covering the surface of the metal wire 410.
[0059] During TDDB testing, different voltages are applied to adjacent metal wires; for example, a positive voltage is applied to one metal wire and a negative voltage is applied to the other. This causes the metal in the metal wires to ionize, forming metal cations that enter the interlayer dielectric layer. In this embodiment, the barrier layer 500 is formed on the surface of the second metal layer 400 to block the diffusion of metal cations generated by the ionization of the metal wire 410 during the TDDB process.
[0060] The surface of the metal conductor 410 covered by the barrier layer 500 includes the top surface of the metal conductor 410 and the side surface of the metal conductor 410 exposed after part of the first interlayer dielectric layer 200 has been removed.
[0061] The metal wires 410 are inverted trapezoidal, and the bottoms of adjacent metal wires 410 are far apart. Even if the bottom of the metal wires 410 is not covered by the barrier layer 500, allowing metal cations to diffuse into the first interlayer dielectric layer 200, it is difficult for the metal cations to form a current between adjacent metal wires 410, causing the first interlayer dielectric layer 200 to fail. Although the top regions of adjacent metal wires 410 are close together, the metal cations generated by the ionization of the metal wires 410 cannot pass through the barrier layer 500 due to the obstruction of the barrier layer 500, thus preventing the formation of a current between adjacent metal wires 410.
[0062] In some embodiments, the method for forming the barrier layer 500 includes, but is not limited to, processes such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, and sputtering.
[0063] In some embodiments, the barrier layer 500 is made of at least one of silicon oxide and polycrystalline silicon.
[0064] refer to Figure 10 A second interlayer dielectric layer 600 is formed, which fills the gap between adjacent metal wires 410 in the second metal layer 400.
[0065] In some embodiments, the second interlayer dielectric layer 600 completely fills the gap between adjacent metal wires 410.
[0066] In other embodiments, reference is made to Figure 10 An air gap 610 is formed in the second interlayer dielectric layer 600 between some adjacent metal conductors 410. Since air has a high breakdown voltage, forming an air gap 610 in the second interlayer dielectric layer 600 can enhance the breakdown strength of the second interlayer dielectric layer 600.
[0067] In some embodiments, the method of forming an air gap 610 in the second interlayer dielectric layer 600 includes: forming the second interlayer dielectric layer 600 in the gap by deposition, and controlling the deposition rate during the deposition of the second interlayer dielectric layer 600 such that the ratio of the closing time of the top of the second interlayer dielectric layer 600 to the total time to fill the gap is (0.3 to 0.8):1, for example, 0.3:1, 0.4:1, 0.5:1, 0.6:1, 0.7:1 or 0.8:1.
[0068] In some embodiments, the volume ratio of the air gap 610 between adjacent metal conductors 410 to the total volume of the second interlayer dielectric layer 600 is (0.1 to 0.8):1, for example, 0.1:1, 0.2:1, 0.3:1, 0.4:1, 0.5:1, 0.6:1, 0.7:1, or 0.8:1. It should be noted that the total volume of the second interlayer dielectric layer 600 between adjacent metal conductors 410 includes the volume of the second interlayer node layer between adjacent metal conductors 410 and the volume of the air gap 610.
[0069] If the proportion of the air gap 610 is too high, the mechanical properties of the second interlayer dielectric layer 600 will decrease, making it more prone to collapse or deformation. If the proportion of the air gap is too low, it will not effectively enhance the breakdown strength of the second interlayer dielectric layer 600.
[0070] In some embodiments, the material of the second interlayer dielectric layer 600 is a material having an ultra-low dielectric constant K, such as SiOC, SiCOH, or a combination thereof with a dielectric constant of 2.2 to 2.4.
[0071] In some embodiments, after the second interlayer dielectric layer 600, the top surface of the second interlayer dielectric layer 600 is further planarized so that the top surface of the interlayer dielectric layer is flush with the top surface of the barrier layer 500 located on top of the metal conductor 410.
[0072] In some embodiments, the method of planarizing the second interlayer dielectric layer 600 includes chemical mechanical polishing.
[0073] In some embodiments, reference Figure 11A dielectric barrier layer 700 is formed, which covers the top surface of the second interlayer dielectric layer 600 and the barrier layer 500.
[0074] In some embodiments, the method for forming the dielectric barrier layer 700 includes, but is not limited to, processes such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, and sputtering. In some embodiments, the material of the dielectric barrier layer 700 includes nitro-doped silicon carbide (NDC).
[0075] This application also provides a semiconductor structure, referenced... Figure 11 or Figure 12 The semiconductor structure includes a substrate, the substrate including a first metal layer 100 and a first interlayer dielectric layer 200 covering the top surface of the first metal layer 100, the first interlayer dielectric layer 200 including a plurality of openings 300; a second metal layer 400, the second metal layer 400 including a plurality of metal wires 410 filling the openings 300, and the top surface of the metal wires 410 being higher than the top surface of the first interlayer dielectric layer 200; a barrier layer 500 covering the top surface of the first metal layer 100 and the surface of the metal wires 410 protruding from the first interlayer dielectric layer; and a second interlayer dielectric layer 600 filling the gaps between adjacent metal wires 410 in the second metal layer 400.
[0076] In some embodiments, an air gap 610 is formed in the second interlayer dielectric layer 600 between adjacent metal wires 410.
[0077] In some embodiments, the volume ratio of the air gap 610 between the adjacent metal conductors 410 to the total volume of the second interlayer dielectric layer 600 is (0.1 to 0.8):1, for example, 0.1:1, 0.2:1, 0.3:1, 0.4:1, 0.5:1, 0.6:1, 0.7:1 or 0.8:1.
[0078] The semiconductor structure and embodiments of this application provide Figures 1-3 The semiconductor structures shown are the same or similar, and will not be described in detail here for the sake of brevity in the specification.
[0079] The beneficial effects of the semiconductor structure and its fabrication method provided in this application include, but are not limited to, the following:
[0080] This application removes a portion of the first interlayer dielectric layer located between adjacent metal wires in the metal layer after opening the top surface of the first interlayer dielectric layer and filling it with a metal layer. This removes the contaminated first interlayer dielectric layer with metal cations attached due to the chemical mechanical polishing of the metal layer. The portion of the first interlayer dielectric layer that has been removed is then filled with a second interlayer dielectric layer, thereby avoiding the impact of metal cations on the reliability of the dielectric layer after breakdown over time.
[0081] In addition, before filling the second interlayer dielectric layer, a barrier layer is formed covering the surface of the metal layer. The barrier layer can prevent metal cations generated by the ionization of the metal wires during TDDB testing from diffusing into the second interlayer dielectric layer and affecting the time-dependent breakdown reliability of the second interlayer dielectric layer.
[0082] Furthermore, an air gap is formed within the second interlayer dielectric layer. Since air has a high breakdown voltage, forming an air gap in the second interlayer dielectric layer enhances its breakdown strength. In summary, after reading this application, those skilled in the art will understand that the foregoing content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.
[0083] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.
[0084] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.
[0085] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.
[0086] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a first interlayer dielectric layer; Several openings are formed in the first interlayer dielectric layer; A metal layer is formed, the metal layer comprising a plurality of metal wires filling the plurality of openings; Remove part of the first interlayer dielectric layer so that the top surface of the first interlayer dielectric layer is lower than the top surface of the metal layer; A barrier layer is formed covering the surface of the metal wire; as well as A second interlayer dielectric layer is formed, which fills the gaps between adjacent metal wires in the metal layer.
2. The method for forming a semiconductor structure according to claim 1, characterized in that, An air gap is formed in the second interlayer dielectric layer between some adjacent metal wires.
3. The method for forming a semiconductor structure according to claim 2, characterized in that, The method for forming the air gap includes: forming a second interlayer dielectric layer in the gap by deposition, and controlling the deposition rate during the deposition of the second interlayer dielectric layer such that the ratio of the closing time of the top of the second interlayer dielectric layer to the total time to fill the gap is (0.3 to 0.8):
1.
4. The method for forming a semiconductor structure according to claim 2, characterized in that, Between adjacent metal wires, the volume of the air gap is in the ratio of the total volume of the second interlayer dielectric layer to (0.1-0.8):
1.
5. The method for forming a semiconductor structure according to claim 1, characterized in that, Methods for removing part of the first interlayer dielectric layer include wet etching or dry etching.
6. The method for forming a semiconductor structure according to claim 1, characterized in that, The ratio of the thickness of the portion of the first interlayer dielectric layer removed to the thickness of the metal layer is (0.1~0.5):
1.
7. The method for forming a semiconductor structure according to claim 1, characterized in that, The barrier layer is made of at least one of silicon nitride and polycrystalline silicon.
8. A semiconductor structure, characterized in that, include: A substrate, the substrate including a first interlayer dielectric layer, the first interlayer dielectric layer including a plurality of openings; A metal layer comprising a plurality of metal wires filling the plurality of openings, wherein the top surface of the metal wires is higher than the top surface of the first interlayer dielectric layer; A barrier layer that covers the top surface of the metal layer and the surface of the metal wire protruding from the first interlayer dielectric layer; as well as The second interlayer dielectric layer fills the gaps between adjacent metal wires in the metal layer.
9. The semiconductor structure according to claim 8, characterized in that, An air gap is formed in the second interlayer dielectric layer between some adjacent metal wires.
10. The semiconductor structure according to claim 9, characterized in that, Between the adjacent metal wires, the volume of the air gap is in the ratio of the total volume of the second interlayer dielectric layer to (0.1-0.8):1.