Semiconductor element and method for forming the same
By setting a hard mask and dielectric layers of different materials above the conductive layer to form a shielding wall, the leakage problem caused by the reduction in spacing in semiconductor devices is solved, thereby improving the performance and reliability of the devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NAN YA TECH
- Filing Date
- 2026-03-23
- Publication Date
- 2026-06-05
AI Technical Summary
As semiconductor structure dimensions shrink and component spacing becomes closer, leakage current is more likely to occur, a problem that existing technologies struggle to solve effectively.
A hard mask is formed above the conductive layer, and a first interlayer dielectric layer is formed around and above it. By selecting dielectric layers composed of different materials, etching selectivity is improved, and a shielding wall is formed to avoid leakage.
This effectively reduces leakage current between adjacent conductive layers, improving the performance and reliability of semiconductor devices.
Smart Images
Figure CN122161433A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a semiconductor device and a method for forming the same, and more particularly to a semiconductor device and a method for forming the same that can reduce leakage current between contacting and spaced conductive layers. Background Technology
[0002] With the rapid development of the electronics industry, integrated circuits (ICs) capable of providing very high performance in extremely small packages have been developed. Technological advancements in IC materials and design have led to generations of ICs, each generation being smaller and more complex than the last.
[0003] As semiconductor structure dimensions shrink, in addition to increasing the difficulty of manufacturing processes, components in semiconductor structures are also prone to leakage due to their close proximity.
[0004] Therefore, how to propose a semiconductor device and its formation method that can solve the above problems is one of the problems that the industry is currently eager to invest research and development resources to solve. Summary of the Invention
[0005] In view of this, one object of the present invention is to provide a semiconductor device and a method for forming the same that can solve the above problems.
[0006] To achieve the above objectives, according to one embodiment of the present invention, a semiconductor device forming method includes forming a hard mask over a conductive layer; forming a first interlayer dielectric layer around the hard mask and the conductive layer; forming a second interlayer dielectric layer over the hard mask and the first interlayer dielectric layer; forming an opening in the second interlayer dielectric layer and the hard mask to expose the conductive layer; and forming a contact in the opening.
[0007] In one or more embodiments of the present invention, the hard mask and the second interlayer dielectric layer are composed of the same material.
[0008] In one or more embodiments of the present invention, the dielectric layer between the hard mask and the second layer comprises an oxide.
[0009] In one or more embodiments of the present invention, the hard mask and the first interlayer dielectric layer are composed of different materials.
[0010] In one or more embodiments of the present invention, the hard mask is an oxide. The first interlayer dielectric layer is a nitride.
[0011] In one or more embodiments of the present invention, the semiconductor device formation method further includes performing planarization on the first interlayer dielectric layer before forming the second interlayer dielectric layer.
[0012] In one or more embodiments of the present invention, forming the opening further includes forming a photoresist over the second interlayer dielectric layer. The photoresist has an opening. At least one portion of the photoresist has an opening that overlaps with the first interlayer dielectric layer in the vertical direction.
[0013] In one or more embodiments of the present invention, forming the opening includes performing an etching process. The etching rate on the second interlayer dielectric layer and the hard mask is higher than the etching rate on the first interlayer dielectric layer.
[0014] In one or more embodiments of the present invention, the remaining portion of the hard shield after the opening is formed is in contact with the contact.
[0015] In one or more embodiments of the present invention, the bottom surface of the contact is lower than the top surface of the first interlayer dielectric layer.
[0016] To achieve the above objectives, according to one embodiment of the present invention, a semiconductor device includes a substrate, a conductive feature, a hard mask, a first interlayer dielectric layer, a second interlayer dielectric layer, and a contact. The conductive feature is located above the substrate. The hard mask is located above the conductive feature. The first interlayer dielectric layer is located above the substrate and surrounds the conductive feature. The hard mask is laterally adjacent to the first interlayer dielectric layer. The second interlayer dielectric layer is located above the first interlayer dielectric layer. The contact is located between the second interlayer dielectric layer and the first interlayer dielectric layer and is electrically coupled to the conductive feature.
[0017] In one or more embodiments of the present invention, the hard mask and the second interlayer dielectric layer are composed of the same material.
[0018] In one or more embodiments of the present invention, the dielectric layer between the hard mask and the second layer comprises an oxide.
[0019] In one or more embodiments of the present invention, the hard mask and the first interlayer dielectric layer are composed of different materials.
[0020] In one or more embodiments of the present invention, the hard mask is an oxide. The first interlayer dielectric layer is a nitride.
[0021] In one or more embodiments of the present invention, the bottom surface of the contact is lower than the top surface of the first interlayer dielectric layer.
[0022] In one or more embodiments of the present invention, the top surface of the hard mask is substantially flush with the top surface of the first interlayer dielectric layer.
[0023] In one or more embodiments of the present invention, the hard mask and the contact are in contact with each other.
[0024] In one or more embodiments of the present invention, the contact has a portion that is higher in the vertical direction than the first interlayer dielectric layer.
[0025] In one or more embodiments of the present invention, the first interlayer dielectric layer forms an arc-shaped interface with the contact.
[0026] In summary, in the semiconductor device and its formation method of the present invention, by first placing a hard mask above the conductive layer and then placing a first interlayer dielectric layer above the hard mask and around the conductive layer, the top surface of the first interlayer dielectric layer can be made higher than the top surface of the conductive layer after the planarization process. By using a first interlayer dielectric layer composed of different materials than the hard mask and the first interlayer dielectric layer, the structural integrity of the first interlayer dielectric layer can be preserved after the etching process, thus serving as a shielding wall between adjacent conductive layers to prevent leakage.
[0027] The above description is only used to illustrate the problem to be solved by the present invention, the technical means to solve the problem, and the effects produced, etc. The specific details of the present invention will be described in detail in the following embodiments and related drawings. Attached Figure Description
[0028] To make the above and other objects, features, advantages and embodiments of the present invention more apparent and understandable, the accompanying drawings are described below: Figures 1 to 6 To illustrate a method for forming a semiconductor device at different stages according to an embodiment of the present invention.
[0029] Figures 7 to 10 To illustrate semiconductor elements according to other embodiments of the present invention. Detailed Implementation
[0030] The following describes several embodiments of the present invention with reference to the accompanying drawings. For clarity, many practical details will be described in the following description. However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not essential. Furthermore, for the sake of simplicity, some conventional structures and elements will be shown in the drawings in a simple schematic manner.
[0031] To help readers better understand the interrelationships and orientations of the various components, the accompanying diagram indicates the coordinate axes X as the first direction, Y as the second direction, and Z as the third direction. Furthermore, the first direction X, the second direction Y, and the third direction Z are perpendicular to each other.
[0032] Please refer to Figures 1 to 6 This illustrates a method for forming a semiconductor element 100 at different stages according to an embodiment of the present invention. Figure 1As shown, in this embodiment, the method for forming the semiconductor element 100 includes forming a hard mask 130 over the conductive layer 120. The conductive layer 120 may be disposed on a base layer 110 (e.g., a substrate). Specifically, the hard mask 130 has a higher etch selectivity and plasma resistance than the conductive layer 120, thereby allowing the pattern of the conductive layer 120 to be precisely formed. In this embodiment, the conductive layer 120 is a metal line, but the invention is not limited thereto. In some embodiments, the conductive layer 120 may be other conductive features with conductive properties. In this embodiment, the hard mask 130 may comprise oxides, such as silicon dioxide (SiO2), aluminum oxide (Al2O3), high-k oxides, low-k oxides, titanium dioxide (TiO2), or other composite oxides.
[0033] like Figure 2 As shown, in this embodiment, the method of forming the semiconductor element 100 further includes forming a first interlayer dielectric layer 140 around the hard mask 130 and the conductive layer 120. Specifically, the first interlayer dielectric layer 140 can be deposited towards the substrate 110 (i.e., in the opposite direction of the Z-axis) by a deposition process, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). In this embodiment, the first interlayer dielectric layer 140 and the hard mask 130 can be composed of different materials. Specifically, the first interlayer dielectric layer 140 can contain nitrides, such as silicon nitride (SiN), aluminum nitride (AlN), or other composite nitrides. In this embodiment, the first interlayer dielectric layer 140 can electrically isolate adjacent conductive layers 120 on the substrate 110 to prevent leakage between adjacent conductive layers 120. In other words, the first interlayer dielectric layer 140 can serve as a barrier layer to prevent metal atoms from migrating between adjacent conductive layers 120.
[0034] like Figure 3 and Figure 4As shown, in this embodiment, the method of forming the semiconductor device 100 further includes forming a second interlayer dielectric layer 150 above the hard mask 130 and the first interlayer dielectric layer 140. Specifically, the method of forming the semiconductor device 100 further includes performing a planarization process, such as chemical mechanical polishing (CMP), on the first interlayer dielectric layer 140 before forming the second interlayer dielectric layer 150. In this embodiment, the planarization process can polish the hard mask 130 and the first interlayer dielectric layer 140 to a substantially flush height. In other words, the top surface 130a of the hard mask 130 is substantially at the same height as the top surface 140a of the first interlayer dielectric layer 140. Through the planarization process, the second interlayer dielectric layer 150 can be more uniformly distributed above the hard mask 130 and the first interlayer dielectric layer 140. In this embodiment, the second interlayer dielectric layer 150 and the hard mask 130 can be composed of the same material. Specifically, the second interlayer dielectric layer 150 may also contain oxides, such as silicon dioxide (SiO2), aluminum oxide (Al2O3), high-k oxides, low-k oxides, titanium dioxide (TiO2), or other composite oxides.
[0035] like Figure 4 and Figure 5 As shown, in this embodiment, the method of forming the semiconductor element 100 further includes forming an opening 170 in the second interlayer dielectric layer 150 and the hard mask 130 to expose the conductive layer 120. Specifically, forming the opening 170 further includes forming a photoresist 160 above the second interlayer dielectric layer 150 and performing an etching process. In this embodiment, the photoresist 160 has an opening 160a, and at least one portion of the opening 160a overlaps with the first interlayer dielectric layer 140 in the vertical direction (i.e., the third direction Z). In other words, the opening 170 formed through the opening 160a can not only expose the conductive layer 120, but also further expose the first interlayer dielectric layer 140 that overlaps with the opening 170 in the vertical direction. In this embodiment, since the second interlayer dielectric layer 150 and the hard mask 130 are composed of the same material, but this material is different from the material constituting the first interlayer dielectric layer 140, the etchant forming the opening 170 can be appropriately selected so that the etch rate of the etchant on the second interlayer dielectric layer 150 and the hard mask 130 is higher than the etch rate on the first interlayer dielectric layer 140. In this way, the first interlayer dielectric layer 140 can serve as an etch stop layer in the etching process, and therefore the amount of material consumed by the first interlayer dielectric layer 140 in the etching process is very small or negligible. In some embodiments, due to the etching process, the exposed first interlayer dielectric layer 140 may include a curved surface.
[0036] like Figure 5 and Figure 6 As shown, in this embodiment, the method of forming the semiconductor element 100 further includes forming a contact 180 in the opening 170. Specifically, after the opening 170 is formed, a conductive material, such as tungsten (W), cobalt (Co), copper (Cu), a multilayer structure, or other types of conductive material, can be deposited on the opening 170 to fill the opening 170. Then, a planarization process is performed to remove excess conductive material until the second interlayer dielectric layer 150 is exposed. In this embodiment, after the contact 180 is formed, the remaining portion 131 of the hard mask 130 can contact the contact 180. In this embodiment, since the first interlayer dielectric layer 140 has high etch resistance, the bottom surface 180a of the contact 180 is lower than the top surface 140a of the first interlayer dielectric layer 140, and the portion of the contact 180 is higher than the first interlayer dielectric layer 140 in the vertical direction (i.e., the third direction Z).
[0037] In this embodiment, the first interlayer dielectric layer 140 can serve as an etch stop layer when forming contact openings (e.g., opening 170). When the first interlayer dielectric layer 140 does not possess sufficient etch resistance to the etch process forming the contact opening, the contact 180 may undesirably extend into the first interlayer dielectric layer 140, forming a potential leakage path to the adjacent conductive layer 120. In embodiments of the present invention, the material of the first interlayer dielectric layer 140 has sufficient etch selectivity for the etch process, which can solve the aforementioned leakage problem and thereby improve device performance.
[0038] Please refer to Figures 7 to 10 This is an illustration of semiconductor elements 100A to 100D according to other embodiments of the present invention. For example... Figure 7 As shown, and in conjunction with reference Figure 5 In this embodiment, the difference between semiconductor element 100A and semiconductor element 100 is that the contact 180 of semiconductor element 100A substantially overlaps the conductive feature 120 in the vertical direction (i.e., the third direction Z). Specifically, during the etching process, since the opening 160a of the photoresist 160 on the second interlayer dielectric layer 150 is nearly directly positioned above the conductive feature 120, the second interlayer dielectric layer 150 and the hard mask 130, which overlap the conductive feature 120 in the vertical direction, will be primarily etched during the etching process. At this time, the first interlayer dielectric layer 140, since it is not aligned with the opening 160a of the photoresist 160 in the vertical direction, can retain the integrity of the structure (for example, there may be no arc interface between it and the contact 180).
[0039] like Figure 8 and Figure 9 As shown, and in conjunction with reference Figure 5In this embodiment, the difference between semiconductor elements 100B and 100C and semiconductor element 100 is that the width of the contact 180 of semiconductor element 100B in the first direction X is greater than the width of the conductive feature 120 in the first direction X, while the width of the contact 180 of semiconductor element 100C in the first direction X is smaller than the width of the conductive feature 120 in the first direction X. In this embodiment, the contact 180 of semiconductor element 100B can be simultaneously located above the first interlayer dielectric layer 140 on both sides of the conductive feature 120. At this time, the hard mask 130 can be etched almost completely. It should be particularly noted that although... Figure 8 The illustration shows the interface between contact 180 and the first interlayer dielectric layer 140 as an unetched state, but the present invention is not limited thereto. In some embodiments, the interface between contact 180 and the first interlayer dielectric layer 140 may be an arc-shaped interface. In this embodiment, the contact 180 of the semiconductor element 100C is located only above the conductive feature 120 and not above the first interlayer dielectric layer 140. In this case, the remaining portion 131 of the hard mask 130 will exist above the conductive feature 120.
[0040] like Figure 10 As shown, in this embodiment, the semiconductor device 100D differs from the semiconductor device 100 in that the substrate 110 of the semiconductor device 100D includes a substrate 111 and an interlayer dielectric layer 112. The gate structure includes a gate dielectric layer 1121 and a gate electrode 1122 disposed on the substrate 111. Source / drain regions 1111 are disposed in the substrate 111 and located on opposite sides of the gate structure. The gate structure and the source / drain regions 1111 can together form a transistor. The interlayer dielectric layer 112 surrounds the gate structure and covers the source / drain regions 1111. A source / drain contact 1123 is disposed in the interlayer dielectric layer 112 and electrically coupled to one of the source / drain regions 1111. The conductive layer 120 is electrically coupled to the source / drain contact 1123.
[0041] From the detailed description of the specific embodiments of the present invention above, it is clear that in the semiconductor device and its formation method of the present invention, by first setting a hard mask above the conductive layer and then setting a first interlayer dielectric layer above the hard mask and around the conductive layer, the top surface of the first interlayer dielectric layer can be made higher than the top surface of the conductive layer after performing the planarization process. By using a first interlayer dielectric layer composed of different materials than the hard mask and the first interlayer dielectric layer, the structural integrity of the first interlayer dielectric layer can be preserved after the etching process, so as to act as a shielding wall between adjacent conductive layers to prevent leakage.
[0042] The above description is only used to illustrate the problem to be solved by the present invention, the technical means to solve the problem, and the effects produced, etc. The specific details of the present invention will be described in detail in the following embodiments and related drawings.
[0043] [Symbol Explanation] 100, 100A, 100B, 100C, 100D: Semiconductor components 110: Grassroots 111: Substrate 1111: Source / Drain Region 112: Interlayer dielectric layer 1121: Gate dielectric layer 1122: Gate electrode 1123: Source / Drain Contact 120: Conductive layer / Conductive characteristics 130: Hard Mask 130a, 140a: Top surface 131: Remaining parts 140: First interlayer dielectric layer 150: Second interlayer dielectric layer 160: Optical Resist 160a, 170: Opening 180: Contact 180a: Bottom surface X: First direction Y: Second direction Z: Third-party.
Claims
1. A method for forming a semiconductor device, characterized in that, Include: A hard mask is formed above the conductive layer; A first interlayer dielectric layer is formed around the hard shield and the conductive layer; A second interlayer dielectric layer is formed above the hard shield and the first interlayer dielectric layer; An opening is formed in the second interlayer dielectric layer and the hard mask to expose the conductive layer; and Contact is formed in the opening.
2. The method according to claim 1, characterized in that, The hard mask and the dielectric layer between the second layer are made of the same material.
3. The method according to claim 2, characterized in that, The dielectric layer between the hard mask and the second layer contains oxide.
4. The method according to claim 1, characterized in that, The hard mask and the dielectric layer between the first layer are composed of different materials.
5. The method according to claim 4, characterized in that, The hard mask is an oxide, and the first interlayer dielectric layer is a nitride.
6. The method according to claim 1, characterized in that, This further includes performing planarization on the first interlayer dielectric layer before forming the second interlayer dielectric layer.
7. The method according to claim 1, characterized in that, The formation of the opening further includes forming a photoresist above the second interlayer dielectric layer, the photoresist having an opening, at least one portion of which overlaps with the first interlayer dielectric layer in the vertical direction.
8. The method according to claim 1, characterized in that, Forming the opening involves performing an etching process, wherein the etching rate on the second interlayer dielectric layer and the hard mask is higher than the etching rate on the first interlayer dielectric layer.
9. The method according to claim 1, characterized in that, After the opening is formed, the remaining portion of the hard shield comes into contact with the contact.
10. The method according to claim 1, characterized in that, The bottom surface of the contact is lower than the top surface of the first interlayer dielectric layer.
11. A semiconductor element, characterized in that, Include: Substrate; The conductive feature is located above the substrate; A hard shield is positioned above the conductive feature; A first interlayer dielectric layer is located above the substrate and surrounds the conductive feature, wherein the hard mask is laterally adjacent to the first interlayer dielectric layer. The second interlayer dielectric layer is located above the first interlayer dielectric layer; as well as The contact is located between the second interlayer dielectric layer and the first interlayer dielectric layer and is electrically coupled to the conductive feature.
12. The semiconductor device according to claim 11, characterized in that, The hard mask and the dielectric layer between the second layer are made of the same material.
13. The semiconductor element according to claim 12, characterized in that, The dielectric layer between the hard mask and the second layer contains oxide.
14. The semiconductor element according to claim 11, characterized in that, The hard mask and the dielectric layer between the first layer are composed of different materials.
15. The semiconductor element according to claim 14, characterized in that, The hard mask is an oxide, and the first interlayer dielectric layer is a nitride.
16. The semiconductor element according to claim 11, characterized in that, The bottom surface of the contact is lower than the top surface of the first interlayer dielectric layer.
17. The semiconductor element according to claim 16, characterized in that, The top surface of the hard mask is substantially flush with the top surface of the first interlayer dielectric layer.
18. The semiconductor element according to claim 11, characterized in that, The hard mask contacts the contact.
19. The semiconductor element according to claim 11, characterized in that, The contact has a portion that is higher in the vertical direction than the first interlayer dielectric layer.
20. The semiconductor device according to claim 11, characterized in that, The first interlayer dielectric layer forms an arc-shaped interface with the contact.