System on chip and method of manufacturing the same

Abstract

A system on a chip (SoC) and a method of manufacturing the SoC are disclosed. The SoC includes segmented interposers and computer chips such as high bandwidth memory (HBM) chips. Each computer chip is on one segmented interposer. The SoC also includes a second interposer that connects the segmented interposers together. At least some of the second interposer extends across a gap between adjacent segmented interposers. The SoC also includes an organic substrate coupled to each segmented interposer.

Description

Technical Field

[0001] This disclosure relates to segmented intermediary layers for three-dimensional (3D) chips. Background Technology

[0002] An interposer is a thin substrate used in semiconductors and integrated circuits to connect two or more chips or dies. Interposers are typically connected via microbump bonding and provide a high-speed communication interface that allows the chips to communicate with each other. Interposers can provide signal routing, power distribution, and thermal management. Furthermore, interposers are commonly used in 2.5D chip packaging and 3D chip packaging. In 2.5D chip packaging, multiple dies are stacked horizontally on an interposer, while in 3D chip packaging, the interposer vertically connects multiple dies.

[0003] However, the interposer in related technologies is designed to accommodate multiple dies, and is prone to extensive warping due to the different coefficients of thermal expansion (CTE) between the different dies on the interposer. For example, Figures 1A to 1C A device 100 of the related technology is illustrated, which includes sixteen high-bandwidth memory (HBM) chips 101 arranged in a 4×4 grid on a single interposer (e.g., a silicon interposer) 102. Furthermore, as... Figures 1A to 1C As shown, an epoxy molding compound (EMC) layer 103 is provided on each HBM chip 101 to increase heat dissipation. Figures 1A to 1C The illustrated related technology's interposer 102 has dimensions of approximately 52 mm × 68 mm and a thickness of approximately 160 μm. As shown in 1D, the related technology's interposer 102 exhibits a maximum warpage of approximately 819 μm at a temperature of approximately 250°C. This extensive warpage of the related technology's interposer 102 makes assembly impossible (or at least difficult) and / or results in lower manufacturing yields.

[0004] The information disclosed in this background section is only for enhancing the understanding of the background of the present invention, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0005] The purpose of this disclosure is to provide a segmented interposer layer for three-dimensional stacked chips with improved performance.

[0006] This disclosure relates to various embodiments of a system-on-a-chip (SoC). In one embodiment, the SoC includes segmented interposers and computer chips. Each computer chip is on one segmented interposer. The SoC also includes a second interposer connecting the segmented interposers together. At least some of the second interposers extend across gaps between adjacent segmented interposers. The SoC also includes an organic substrate coupled to each segmented interposer.

[0007] The second interlayer can be located between the segmented interlayer and the organic substrate.

[0008] The second interposer layer can be connected to the lower surface of the segmented interposer layer using microbumps.

[0009] The second interposer can be attached to the upper surface of the organic substrate using microbumps.

[0010] The second interposer can be attached to the upper surface of the organic substrate using controlled collapse chip connection (C4) bumps.

[0011] The second intermediary layer can be placed on the upper surface of the segmented intermediary layer.

[0012] The second intermediary layer can have a height that is substantially the same as the height of the computer chip.

[0013] The second intermediary layer can be connected to the upper surface of the segmented intermediary layer using microbumps.

[0014] Some of the second intermediary layers may not extend across the gaps between adjacent segmented intermediary layers.

[0015] Computer chips can include high-bandwidth memory (HBM) chips.

[0016] This disclosure also relates to various embodiments of a method for manufacturing a system-on-a-chip (SoC). In one embodiment, the method includes attaching computer chips to segmented interposers, such that each computer chip is on one segmented interposer. The method also includes attaching the segmented interposers to a second interposer and attaching the segmented interposers to an organic substrate.

[0017] Connecting the segmented interposer layer to the second interposer layer may include: using microbumps to attach the second interposer layer to the lower surface of the segmented interposer layer.

[0018] Connecting the segmented interposer layer to the second interposer layer can include: using microbumps to attach the second interposer layer to the upper surface of the segmented interposer layer.

[0019] Connecting a segmented interposer to an organic substrate may include: directly bonding the segmented interposer to the upper surface of the organic substrate using controlled collapse chip connection (C4) bumps.

[0020] Connecting a segmented interposer to an organic substrate may include bonding a second interposer to the upper surface of the organic substrate.

[0021] The second interposer can be bonded to the upper surface of the organic substrate using controlled collapse chip connection (C4) bumps.

[0022] Microbumps can be used to bond the second interposer to the upper surface of the organic substrate.

[0023] Connecting the segmented intermediary layer to the second intermediary layer may include: attaching the second intermediary layer to the segmented intermediary layer with microbumps, such that at least some extensions of the second intermediary layer cross the gap between adjacent segmented intermediary layers.

[0024] The second intermediary layer can have a height that is substantially the same as the height of the computer chip.

[0025] Computer chips can include high-bandwidth memory (HBM) chips.

[0026] This summary is provided to introduce some concepts that will be further described below in the detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. One or more of the described features may be combined with one or more other described features to provide a working device.

[0027] Beneficial effects of the present invention

[0028] Embodiments of this disclosure provide segmented interposer layers for three-dimensionally stacked chips, which have improved performance by each supporting a single computer chip.

[0029] Specifically, by providing computer chips on separate segmented interposers, the warping of the segmented interposers at high temperatures is reduced. Attached Figure Description

[0030] This patent or application document contains at least one color drawing.

[0031] The features and advantages of embodiments of this disclosure will be better understood when considered in conjunction with the accompanying drawings and by referring to the following detailed description. Throughout the drawings, the same reference numerals are used to refer to the same features and components. The drawings are not necessarily drawn to scale.

[0032] Figures 1A to 1C These are perspective, side, and top views of an apparatus for related technologies that includes multiple chips on a single intermediary layer.

[0033] Figure 1D It is a thermal map showing the warpage of the intermediate layer of the relevant technology at a temperature of approximately 250°C;

[0034] Figures 2A to 2B These are perspective and side views of an apparatus including multiple segmented intermediary layers according to embodiments of the present disclosure;

[0035] Figure 3 This is a side view of an apparatus including multiple segmented intermediary layers according to an embodiment of the present disclosure;

[0036] Figure 4This is a side view of an apparatus including multiple segmented intermediary layers according to an embodiment of the present disclosure;

[0037] Figure 5 This is a side view of an apparatus including multiple segmented intermediary layers according to an embodiment of the present disclosure;

[0038] Figure 6 It is a graph comparing the warpage of the segmented interposer layer according to the embodiments of this disclosure with the warpage of interposers in related technologies; and

[0039] Figure 7 This is a flowchart illustrating the task of a method for manufacturing an apparatus according to an embodiment of the present disclosure. Detailed Implementation

[0040] This disclosure relates to various implementations of segmented interposers (e.g., segmented silicon interposers) for three-dimensional (3D) chips (e.g., system-on-a-chip (SoC)). In one or more implementations, each segmented interposer may support a single computer chip (e.g., a single high-bandwidth memory (HBM) chip) configured to reduce warpage at high temperatures compared to an interposer (e.g., a silicon interposer) of a related technology supporting multiple computer chips (e.g., multiple HBM chips). Furthermore, in one or more implementations, because the computer chip is provided on separate segmented interposers to reduce warpage at high temperatures, an epoxy molding compound (EMC) layer may not be provided on the computer chip, which is consistent with... Figures 1A to 1C The devices depicted in the related technologies differ from those in the technology, which utilize an EMC layer on the HBM chip to reduce warping of the interposer caused by the difference in the coefficient of thermal expansion (CTE) between the HBM chip and the interposer.

[0041] In the following description, exemplary embodiments will be illustrated in more detail with reference to the accompanying drawings, in which the same reference numerals consistently denote the same elements. However, the invention can be embodied in various different forms and should not be construed as being limited to the embodiments shown herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey to those skilled in the art aspects and features of the invention. Therefore, processes, elements, and techniques unnecessary for those skilled in the art to fully understand the aspects and features of the invention are not described. Unless otherwise stated, the same reference numerals denote the same elements throughout the drawings and written description, and therefore their description is not repeated.

[0042] In the accompanying drawings, for clarity, the relative dimensions of elements, layers, and regions may be exaggerated and / or simplified. For ease of illustration, spatial relational terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., may be used herein to describe the relationship of one element or feature to other elements or features as shown in the figures. It will be understood that, in addition to the orientations depicted in the figures, the spatial relational terms are also intended to cover different orientations of the device in use or operation. For example, if the device in the figures is flipped, an element described as “below” or “below” or “below” other elements or features will be oriented “above” said other elements or features. Thus, the example terms “below” and “below” can cover both above and below orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relational descriptions used herein should be interpreted accordingly.

[0043] It will be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Therefore, the first element, component, region, layer, or section described below may be referred to as the second element, component, region, layer, or section without departing from the spirit and scope of the invention.

[0044] It will be understood that when an element or layer is referred to as being "on" another element or layer, "connected" to another element or layer, or "attached" to another element or layer, it can be directly on, directly connected to, or directly attached to the other element or layer, or there can be one or more intervening elements or layers. Furthermore, it will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there can be one or more intervening elements or layers.

[0045] The terminology used herein is for the purpose of describing particular embodiments and is not intended to limit the invention. As used herein, the singular form “a” is also intended to include the plural form unless the context clearly indicates otherwise. It will also be understood that, when used herein, the terms “comprising,” “including,” “containing,” and “comprising…” indicate the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more associated listed items. Expressions such as “at least one of”, when following a list of elements, modify the entire list of elements, not individual elements of the list.

[0046] As used herein, the terms “substantially,” “about,” and similar terms are used as approximations rather than terms of degree and are intended to describe the inherent variations in measured or calculated values ​​that will be recognized by those skilled in the art. Furthermore, when describing embodiments of the invention, the use of “may” means “one or more embodiments of the invention.” As used herein, the terms “use,” “using…,” and “being used” can be considered synonymous with the terms “utilize,” “using…,” and “being exploited,” respectively. Additionally, the term “exemplary” is intended to refer to an example or illustration.

[0047] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that terms (such as those defined in common dictionaries) shall be interpreted as having the same meaning as they have in the context of the relevant field and / or the context of this specification, and shall not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0048] Figures 2A to 2B An apparatus 200 (e.g., a system-on-a-chip (SoC)) according to an embodiment of the present disclosure is illustrated, which includes an organic substrate 201, a plurality of segmented interposers (e.g., segmented silicon interposers) 202 connected to the organic substrate 201, a plurality of computer chips (e.g., high bandwidth memory (HBM) chips) 203 supported on the plurality of segmented interposers 202, and a plurality of second interposers (e.g., second silicon interposers) 204 connecting adjacent segmented interposers 202 together.

[0049] In the illustrated embodiment, each second interposer 204 extends across the gap 205 between adjacent segmented interposers 202 (e.g., each second interposer 204 bridges the gap 205 between adjacent segmented interposers 202). Furthermore, in the illustrated embodiment, the second interposer 204 is located between the segmented interposers 202 and the organic substrate 201. In the illustrated embodiment, the second interposer 204 is connected to the lower surface 206 of the segmented interposers 202 by a first set of microbumps 207 and to the upper surface 208 of the organic substrate 201 by a second set of microbumps 209. Additionally, in one or more embodiments, each second interposer 204 may include a redistribution layer (RDL) (i.e., copper interconnect) to electrically connect computer chips (e.g., HBM chips) 203 to each other and / or to the organic substrate 201.

[0050] In the illustrated embodiment, the segmented interposer layer 202 is directly connected to the upper surface 208 of the organic substrate 201 using a plurality of controlled collapse chip connection (C4) bumps 210. Furthermore, in the illustrated embodiment, a plurality of solder balls 211 are provided on the lower surface 212 of the organic substrate 201 for attaching the device 200 to other components.

[0051] In one or more embodiments, each computer chip (e.g., an HBM chip) 203 is coupled to the upper surface 213 of one of the segmented interposers 202 using microbumps 214. In the illustrated embodiment, each segmented interposer 202 supports a single computer chip (e.g., an HBM chip) 203. Therefore, in one or more embodiments, the number of segmented interposers 202 is equal to the number of computer chips (e.g., HBM chips) 203. As described in more detail below, providing a single computer chip (e.g., an HBM chip) 203 on each segmented interposer 202 is configured to reduce warpage of the segmented interposers 202 compared to a single interposer (e.g., a silicon interposer) supporting all computer chips (e.g., HBM chips) 203. Furthermore, in one or more embodiments, because the computer chip (e.g., an HBM chip) 203 is provided on the separated segmented interposer 202 to reduce warpage of the segmented interposer 202 at high temperatures, an epoxy molding compound (EMC) layer may not be provided on the computer chip (e.g., an HBM chip) 203. This is consistent with... Figures 1A to 1C The apparatus shown differs from that of the related technologies, which utilize an EMC layer on the HBM chip to reduce warping of the interposer caused by the difference in the coefficient of thermal expansion (CTE) between the HBM chip and the interposer.

[0052] In one or more embodiments, the device 200 may also include a stiffener and / or a top metal plate configured to improve the rigidity and reliability of the device 200.

[0053] Figure 3 An apparatus 300 according to an embodiment of the present disclosure is illustrated. In the illustrated embodiment, the apparatus 300 includes an organic substrate 301, a plurality of segmented interposers (e.g., segmented silicon interposers) 302 connected to the organic substrate 301, a plurality of computer chips (e.g., high bandwidth memory (HBM) chips) 303 supported on the plurality of segmented interposers 302, and a plurality of second interposers (e.g., second silicon interposers) 304 connecting adjacent segmented interposers 302 together.

[0054] In the illustrated embodiment, each second interposer 304 extends across a gap 305 between adjacent segmented interposers 302 (e.g., each second interposer 304 traverses the gap 305 between adjacent segmented interposers 302). Furthermore, in the illustrated embodiment, the second interposer 304 is located between the segmented interposers 302 and the organic substrate 301. In the illustrated embodiment, the second interposer 304 is connected to the lower surface 306 of the segmented interposers 302 by a plurality of microbumps 307 and to the upper surface 308 of the organic substrate 301 by a plurality of controlled-collapse chip connection (C4) bumps 309. Additionally, in one or more embodiments, each second interposer 304 may include a redistribution layer (RDL) (i.e., copper interconnect) to electrically connect computer chips (e.g., HBM chips) 303 to each other and / or to the organic substrate 301.

[0055] Furthermore, in the illustrated embodiment, the size of the second intermediary layer 304 is equal to (or substantially equal to) the combined size of the plurality of segmented intermediary layers 302 (e.g., the width of the second intermediary layer 304 is substantially equal to the combined width of the plurality of segmented intermediary layers 302, and the length of the second intermediary layer 304 is substantially equal to the combined length of the plurality of segmented intermediary layers 302). Therefore, in the illustrated embodiment, with... Figure 2A and Figure 2B In a different embodiment, the segmented interposer 302 is indirectly connected to the organic substrate 301 via a second interposer 304. Furthermore, in the illustrated embodiment, a plurality of solder balls 310 are provided on the lower surface 311 of the organic substrate 301 for attaching the device 300 to other components.

[0056] In one or more embodiments, each computer chip (e.g., an HBM chip) 303 is connected to the upper surface 312 of one of the segmented interposers 302 using microbumps 313. In the illustrated embodiment, each segmented interposer 302 supports a single computer chip (e.g., an HBM chip) 303. Therefore, in one or more embodiments, the number of segmented interposers 302 is equal to the number of computer chips (e.g., HBM chips) 303. As described in more detail below, providing a single computer chip (e.g., an HBM chip) 303 on each segmented interposer 302 is configured to reduce warpage of the segmented interposers 302 compared to a single interposer (e.g., a silicon interposer) supporting all computer chips (e.g., HBM chips) 303. Furthermore, in one or more embodiments, because the computer chip (e.g., an HBM chip) 303 is provided on the separated segmented interposer 302 to reduce warpage of the segmented interposer 302 at high temperatures, an epoxy molding compound (EMC) layer may not be provided on the computer chip (e.g., an HBM chip) 303. This is consistent with... Figures 1A to 1C The apparatus shown differs from that of the related technologies, which utilize an EMC layer on the HBM chip to reduce warping of the interposer caused by the difference in the coefficient of thermal expansion (CTE) between the HBM chip and the interposer.

[0057] In one or more embodiments, the device 300 may further include a stiffener and / or a top metal plate configured to improve the rigidity and reliability of the device 300.

[0058] Figure 4 An apparatus 400 according to an embodiment of the present disclosure is illustrated, which includes an organic substrate 401, a plurality of segmented interposers (e.g., segmented silicon interposers) 402 connected to the organic substrate 401, a plurality of computer chips (e.g., high bandwidth memory (HBM) chips) 403 supported on the plurality of segmented interposers 402, and a plurality of second interposers (e.g., second silicon interposers) 404 connecting adjacent segmented interposers 402 together.

[0059] In the illustrated embodiment, each second interposer 404 extends across a gap 405 between adjacent segmented interposers 402 (e.g., each second interposer 404 spans the gap 405 between adjacent segmented interposers 402). Furthermore, in the illustrated embodiment, the second interposer 404 is supported on the segmented interposers 402 such that the segmented interposers 402 are between the second interposer 404 and the organic substrate 401. In one or more embodiments, the height of the second interposer 404 may be equal to (or substantially equal to) the height of the computer chip (e.g., an HBM chip) 403 (e.g., the upper and lower surfaces of the second interposer 404 may be coplanar or substantially coplanar with the upper and lower surfaces of the computer chip 403, respectively). In the illustrated embodiment, the second interposer 404 is connected to the upper surface 406 of the segmented interposer 402 by microbumps 407. In addition, in one or more embodiments, each second interposer layer 404 may include a redistribution layer (RDL) (i.e., copper metal interconnect) to electrically connect computer chips (e.g., HBM chips) 403 to each other.

[0060] In the illustrated embodiment, the segmented interposer layer 402 is directly connected to the upper surface 408 of the organic substrate 401 using a plurality of controlled collapse chip connection (C4) bumps 409. Furthermore, in the illustrated embodiment, a plurality of solder balls 410 are provided on the lower surface 411 of the organic substrate 401 for attaching the device 400 to other components.

[0061] In one or more embodiments, each computer chip (e.g., an HBM chip) 403 is connected to the upper surface 406 of one of the segmented interposers 402 using microbumps 412. In the illustrated embodiments, each segmented interposer 402 supports a single computer chip (e.g., an HBM chip) 403. Therefore, in one or more embodiments, the number of segmented interposers 402 is equal to the number of computer chips (e.g., HBM chips) 403. As described in more detail below, providing a single computer chip (e.g., an HBM chip) 403 on each segmented interposer 402 is configured to reduce warpage of the segmented interposers 402 compared to a single interposer (e.g., a silicon interposer) supporting all computer chips (e.g., HBM chips) 403. Furthermore, in one or more embodiments, because the computer chips (e.g., HBM chips) 403 are provided on separate segmented interposers 402 to reduce warpage of the segmented interposers 402 at high temperatures, an epoxy molding compound (EMC) layer may not be provided on the HBM chip 403, which is consistent with... Figures 1A to 1C The apparatus depicted differs from that of related technologies, which utilize an EMC layer on the HBM chip to reduce warping of the interposer caused by the difference in coefficient of thermal expansion (CTE) between the HBM chip and the interposer. Furthermore, a second interposer 404 serves as a dummy silicon for heat reduction.

[0062] In one or more embodiments, the device 400 may also include a stiffener and / or a top metal plate configured to improve the rigidity and reliability of the device 400.

[0063] Figure 5 An apparatus 500 according to an embodiment of the present disclosure is illustrated, which includes an organic substrate 501, a plurality of segmented interposers (e.g., segmented silicon interposers) 502 connected to the organic substrate 501, a plurality of computer chips (e.g., high bandwidth memory (HBM) chips) 503 supported on the plurality of segmented interposers 502, and a plurality of second interposers (e.g., second silicon interposers) 504 connecting adjacent segmented interposers 502 together and connecting the segmented interposers 502 to the organic substrate 501.

[0064] In the illustrated embodiment, some of the second interposers 504 extend across the gaps 505 between adjacent segmented interposers 502 (e.g., some of the second interposers 504 traverse the gaps 505 between adjacent segmented interposers 502). The remaining second interposers 504 do not extend across the gaps 505 between adjacent segmented interposers 502. Furthermore, in the illustrated embodiment, the second interposers 504 are located between the segmented interposers 502 and the organic substrate 501. In the illustrated embodiment, the second interposers 504 are connected to the lower surface 506 of the segmented interposers 502 by a plurality of microbumps 507 and to the upper surface 508 of the organic substrate 501 by a plurality of controlled-collapse chip connection (C4) bumps 509. Therefore, in the illustrated embodiment, the segmented interposers 502 are indirectly connected to the organic substrate 501 via the second interposers 504. Furthermore, in the illustrated embodiment, a plurality of solder balls 510 are provided on the lower surface 511 of the organic substrate 501 for attaching the device 500 to other components. Additionally, in one or more embodiments, each second interposer layer 504 may include a redistribution layer (RDL) (i.e., copper interconnect) to electrically connect and / or connect computer chips (e.g., HBM chips) 503 to each other and / or to the organic substrate 501.

[0065] In one or more embodiments, each HBM chip 503 is connected to the upper surface 512 of one of the segmented interposers 502 by microbumps 513. In the illustrated embodiments, each segmented interposer 502 supports a single computer chip (e.g., an HBM chip) 503. Therefore, in one or more embodiments, the number of segmented interposers 502 is equal to the number of computer chips (e.g., HBM chips) 503. As described in more detail below, providing a single computer chip (e.g., an HBM chip) 503 on each segmented interposer 502 is configured to reduce warpage of the segmented interposers 502 compared to a single interposer (e.g., a silicon interposer) supporting all computer chips (e.g., HBM chips) 503. Furthermore, in one or more embodiments, because the computer chips (e.g., HBM chips) 503 are provided on separate segmented interposers 502 to reduce warpage of the segmented interposers 502 at high temperatures, an epoxy molding compound (EMC) layer may not be provided on the computer chips (e.g., HBM chips) 503, which is consistent with... Figures 1A to 1C The devices depicted in the related technologies differ from those in the technology, which utilize an EMC layer on the HBM chip to reduce warping of the interposer caused by the difference in the coefficient of thermal expansion (CTE) between the HBM chip and the interposer.

[0066] In one or more embodiments, the device 500 may also include a stiffener and / or a top metal plate configured to improve the rigidity and reliability of the device 500.

[0067] Figure 6 This is a graph comparing the warpage of a segmented interposer layer according to an embodiment of this disclosure with the warpage of an interposer layer in related technologies. For example... Figure 6 As shown, regardless of the number of computer chips (e.g., HBM chips), the device according to this disclosure exhibits only about 100 μm of warpage at high temperatures, while devices of related technologies exhibit significantly higher warpage, increasing with the number of computer chips (e.g., HBM chips). For example, Figure 6 Devices with two computer chips (e.g., HBM chips) (e.g., computer chips with a 2×2 grid on a single silicon interposer) along the length of a single interposer exhibit warpage of approximately 240 μm at high temperatures; devices with three computer chips (e.g., HBM chips) (e.g., computer chips with a 3×3 grid on a single silicon interposer) along the length of a single interposer exhibit warpage of approximately 460 μm at high temperatures; and devices with four computer chips (e.g., HBM chips) (e.g., computer chips with a 4×4 grid on a single silicon interposer) along the length of a single interposer exhibit warpage of approximately 860 μm at high temperatures.

[0068] Figure 7 This is a flowchart illustrating the tasks of a method 600 of a manufacturing apparatus according to an embodiment of the present disclosure. In the illustrated embodiment, method 600 includes task 610 of attaching a plurality of computer chips (e.g., high-bandwidth memory (HBM) chips) to a plurality of segmented interposers (e.g., segmented silicon interposers). In one or more embodiments, in task 610, each computer chip (e.g., an HBM chip) is attached to a different segmented interposer (i.e., the computer chips are provided on separate, individual segmented interposers such that each segmented interposer supports one computer chip). In one or more embodiments, task 610 includes bonding the computer chips (e.g., HBM chips) to the segmented interposers using microbumps.

[0069] In the illustrated embodiment, method 600 further includes a task 620 of connecting segmented interposers together. In one embodiment, task 620 includes bonding at least one second interposer (e.g., a second silicon interposer) to the segmented interposers. In one or more embodiments, task 620 includes bonding the second interposers to the segmented interposers using microbumps. Furthermore, in one or more embodiments, in task 620, the second interposers may be connected to an upper surface or a lower surface of the segmented interposers. Additionally, in one or more embodiments, in task 620, at least some of the second interposers extend across the gap between adjacent segmented interposers (i.e., across the gap). In one or more embodiments, after task 620, the second interposers may be connected to the lower surface of the segmented interposers, such as... Figures 2A to 2B Implementation methods Figure 3 Implementation methods or Figure 5 As shown in the implementation method. In one or more implementations, after task 620, the second intermediary layer can be connected to the upper surface of the segmented intermediary layer, as shown. Figure 4 The implementation method is shown below.

[0070] In the illustrated embodiment, method 600 further includes a task 630 of attaching a segmented interposer, a computer chip (e.g., an HBM chip) supported on the segmented interposer, and a second interposer to an organic substrate. In one or more embodiments where the second interposer is attached to the lower surface of the segmented interposer, task 630 may include bonding the second interposer to the upper surface of the organic substrate using microbumps, and bonding the segmented interposer to the upper surface of the organic substrate using controlled-collapse chip connection (C4) bumps. In one or more embodiments where the second interposer is attached to the lower surface of the segmented interposer, task 630 may include bonding the second interposer to the upper surface of the organic substrate using C4 bumps, and indirectly attaching the segmented interposer to the organic substrate via the second interposer. In one or more embodiments where the second interposer is attached to the upper surface of the segmented interposer, task 630 may include directly bonding the segmented interposer to the upper surface of the organic substrate using C4 bumps.

[0071] Compared to related technologies in which a single interposer (e.g., a silicon interposer) supports multiple computer chips (e.g., HBM chips) with different coefficients of thermal expansion (CTE), the device manufactured according to method 600 is configured to exhibit reduced warpage at high temperatures.

[0072] Although the invention has been described in detail with reference to specific embodiments thereof, the embodiments described herein are not intended to be exhaustive or to limit the scope of the invention to the exact forms disclosed. Those skilled in the art will understand that modifications and alterations to the described structures, assembly, and methods of operation can be practiced without materially departing from the principles, spirit, and scope of the invention. While some embodiments of this disclosure are disclosed herein, the disclosure is not limited thereto, and its scope is defined by the appended claims and their equivalents.

Claims

1. A system-on-a-chip, comprising: Multiple segmented intermediary layers; Multiple computer chips, each of the multiple computer chips being on one of the multiple segmented intermediary layers; A plurality of second intermediary layers connect the plurality of segmented intermediary layers together, and at least some of the plurality of second intermediary layers extend across the gaps between adjacent segmented intermediary layers in the plurality of segmented intermediary layers. as well as An organic substrate is attached to each of the plurality of segmented interposer layers.

2. The system-on-a-chip according to claim 1, wherein, The plurality of second interposers are located between the plurality of segmented interposers and the organic substrate.

3. The system-on-a-chip according to claim 2, wherein, The plurality of second intermediary layers are connected to the lower surface of the plurality of segmented intermediary layers by microbumps.

4. The system-on-a-chip according to claim 2, wherein, The plurality of second interposers are connected to the upper surface of the organic substrate by microbumps.

5. The system-on-a-chip according to claim 2, wherein, The plurality of second interposers are connected to the upper surface of the organic substrate using controlled collapse chip connection bumps.

6. The system-on-a-chip according to claim 1, wherein, The plurality of second intermediary layers are on the upper surface of the plurality of segmented intermediary layers.

7. The system-on-a-chip according to claim 6, wherein, The plurality of second intermediary layers have a height substantially equal to the height of the plurality of computer chips.

8. The system-on-a-chip according to claim 6, wherein, The plurality of second intermediary layers are connected to the upper surface of the plurality of segmented intermediary layers by microbumps.

9. The system-on-a-chip according to claim 1, wherein, Some of the plurality of second intermediary layers do not extend across the gaps between adjacent segmented intermediary layers.

10. The system-on-a-chip according to claim 1, wherein, The plurality of computer chips includes a plurality of high-bandwidth memory chips.

11. A method for manufacturing a system-on-a-chip, the method comprising: Multiple computer chips are connected to multiple segmented intermediary layers, wherein each of the multiple computer chips is on one of the multiple segmented intermediary layers; Connect the plurality of segmented intermediary layers together with the plurality of second intermediary layers; and The multiple segmented interposers are connected to the organic substrate.

12. The method according to claim 11, wherein, Connecting the plurality of segmented intermediary layers together with the plurality of second intermediary layers includes: attaching the plurality of second intermediary layers to the lower surface of the plurality of segmented intermediary layers using microbumps.

13. The method according to claim 11, wherein, Connecting the plurality of segmented intermediary layers together with the plurality of second intermediary layers includes: attaching the plurality of second intermediary layers to the upper surface of the plurality of segmented intermediary layers using microbumps.

14. The method according to claim 11, wherein, Connecting the plurality of segmented interposers to the organic substrate includes: directly bonding the plurality of segmented interposers to the upper surface of the organic substrate using controlled collapse chip connection bumps.

15. The method according to claim 11, wherein, Connecting the plurality of segmented interposers to the organic substrate includes: bonding the plurality of second interposers to the upper surface of the organic substrate.

16. The method according to claim 15, wherein, The plurality of second interposers are bonded to the upper surface of the organic substrate using controlled collapse chip connection bumps.

17. The method according to claim 15, wherein, The plurality of second interposers are bonded to the upper surface of the organic substrate using microbumps.

18. The method according to claim 11, wherein, Connecting the plurality of segmented intermediary layers to the plurality of second intermediary layers includes: attaching the plurality of second intermediary layers to the plurality of segmented intermediary layers with microbumps, such that at least some of the plurality of second intermediary layers extend across the gap between adjacent segmented intermediary layers in the plurality of segmented intermediary layers.

19. The method according to claim 13, wherein, The plurality of second intermediary layers have a height substantially equal to the height of the plurality of computer chips.

20. The method according to claim 11, wherein, The plurality of computer chips includes a plurality of high-bandwidth memory chips.

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