Package structure and method of manufacturing the same

By constructing a chip housing cavity defined by a carrier board and a dam in a 2.5D packaging structure and forming a metal shielding layer, the problem of electromagnetic interference between chips is solved, and signal integrity and performance are improved.

CN122161468APending Publication Date: 2026-06-05JCET MICROELECTRONICS (JIANGYIN) CO LTD
View PDF 0 Cites 0 Cited by

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
JCET MICROELECTRONICS (JIANGYIN) CO LTD
Filing Date
2026-03-06
Publication Date
2026-06-05

AI Technical Summary

Technical Problem

In 2.5D packaging structures, electromagnetic interference issues exist between densely integrated chips, affecting signal integrity and packaging performance.

Method used

The chip housing cavity is defined by a carrier plate and a cofferdam, and a continuous metal shielding layer is formed at the bottom and sidewalls of the cavity to construct a quasi-Faraday cage shielding structure. This structure reflects external electromagnetic waves and absorbs internal electromagnetic radiation, blocking the electromagnetic energy propagation path between chips, while retaining the vertical power supply and signal transmission channels of the conductive pillars.

Benefits of technology

Effectively suppresses electromagnetic interference between chips in complex electromagnetic environments, ensuring signal integrity and improving the quality and performance of the packaging structure.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN122161468A_ABST
    Figure CN122161468A_ABST
Patent Text Reader

Abstract

The embodiment of the present application provides a packaging structure and a manufacturing method thereof, the packaging structure comprising: a carrier plate having a first surface and a second surface, and having a plurality of conductive columns penetrating through the thickness direction thereof; a cofferdam located on the first surface of the carrier plate, the cofferdam and the carrier plate jointly defining a chip accommodating cavity; and a metal shielding layer conformally covering the bottom and the sidewall of the chip accommodating cavity, and exposing the top surface of the conductive column. By using the above technical scheme, the signal integrity of the packaging structure can be ensured in a complex electromagnetic environment, and the quality and performance of the packaging structure are improved.
Need to check novelty before this filing date? Find Prior Art