A chip advanced packaging bonding system and method based on pad / bump feature targeting

By combining visual acquisition of pad/bump features with a dynamic correction control unit, the problems of unstable alignment and deviation accumulation during chip-substrate bonding are solved, achieving high-precision bonding results suitable for advanced packaging with high density and fine pitch.

CN122161475APending Publication Date: 2026-06-05常乐

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
常乐
Filing Date
2026-03-23
Publication Date
2026-06-05

AI Technical Summary

Technical Problem

Existing technologies cannot achieve high-precision alignment during the bonding process between chips and substrates. Especially in high-density interconnect scenarios, there are problems such as poor alignment stability, thermal drift, and cumulative deviation caused by mechanical deformation. Furthermore, there is a lack of dynamic correction mechanisms, making it difficult to meet the precision requirements of advanced packaging.

Method used

An integrated hardware architecture is constructed by employing a pad/bump feature visual acquisition unit, an array feature targeted solution unit, and a dynamic correction control unit to achieve in-situ synchronization between vision and bonding coaxiality. By using the pad/bump array features as the sole targeting reference and combining them with a dynamic correction algorithm, dynamic closed-loop correction is achieved throughout the bonding process.

Benefits of technology

It achieves high-precision chip-substrate bonding with an alignment accuracy of less than 0.5μm, meeting the advanced packaging requirements of high density and fine pitch, and improving bonding stability and yield.

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Abstract

The present application relates to the chip advanced packaging and precision bonding technical field, specifically discloses a kind of chip advanced packaging bonding system and method based on pad / bump feature targeting.The present application uses the geometric barycenter, edge profile, array spacing of pad, bump (including copper column bump, micro bump) on chip and substrate as the only targeting feature, completely get rid of the dependence on special alignment mark (Mark point), for 2.5D / 3D packaging, flip welding, copper copper bonding and other advanced packaging scenarios, innovative use "visual-bonding axis in position + array feature targeting solution + whole-process dynamic closed-loop correction" architecture, through the clear correction algorithm and trigger mechanism, real-time dynamic correction bonding coordinate in the whole bonding process, compensate the alignment deviation caused by thermal deformation, mechanical drift, patch pressure deformation, realize bonding alignment accuracy≤0.5 μm.The present application is different from the existing conventional bump alignment technology, the core innovation lies in the deep integration of array feature targeting solution and dynamic closed-loop correction, solve the industry pain point of traditional bonding "pre-alignment deviation accumulation", can greatly improve advanced packaging yield and reliability, have unavoidable underlying technical barriers.
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Description

Technical Field

[0001] This invention relates to the fields of advanced chip packaging, precision bonding, flip-chip packaging, and micro-bump interconnect technology. Specifically, it relates to an advanced chip packaging bonding system and method based on pad / bump feature targeting, which is applicable to advanced packaging bonding processes such as 2.5D / 3D packaging, WLP, FO-WLP, CoWoS, and CoP, and is especially suitable for high-precision bonding scenarios with high-density bumps and fine-pitch pads. Background Technology

[0002] In advanced packaging processes, the bonding and alignment accuracy between the chip and the substrate directly determines the yield and performance. Existing technologies have significant shortcomings that are difficult to overcome: 1. Traditional bonding relies on dedicated alignment marks (mark points) for alignment. Once the marks are contaminated, worn, or missing, the equipment cannot bond properly. In addition, the marks occupy package space, which restricts the development of high-density interconnects. 2. Although existing technologies use visual alignment of bumps / pads, they are only "single pre-alignment" and do not use the pad / bump array features as the only targeting reference. Furthermore, they do not achieve dynamic correction throughout the bonding process and cannot offset the micro-displacement caused by thermal drift, mechanical deformation, and placement pressure during bonding. The accumulated deviations cannot meet the precision requirements of advanced packaging. 3. Existing bump alignment methods mostly use single bump feature recognition without combining the pad / bump array spacing and arrangement rules for targeted calculation. This results in poor alignment stability and susceptibility to defects in a single bump (such as oxidation or breakage). 4. Visual acquisition and bonding execution are on different axes and asynchronous. Most of them are offline pre-alignment followed by moving bonding, which has coordinate transformation error. Moreover, the specific algorithm and triggering mechanism for dynamic correction are not disclosed, the technical solution is vague and difficult to reproduce. 5. Multi-chip stacking and 3D packaging have extremely high requirements for real-time alignment and dynamic compensation. Traditional open-loop alignment methods are difficult to meet the micron-level or even sub-micron-level accuracy requirements, becoming a bottleneck for advanced packaging yield.

[0003] Currently, there is no advanced packaging bonding solution that uses pad / bump array features as the sole targeting reference, adopts a vision-bond coaxial in-situ structure, discloses dynamic correction algorithms and triggering mechanisms, and achieves dynamic closed-loop correction throughout the bonding process. This invention addresses this pain point by forming a complete technical system, which is different from existing conventional bump alignment technology and has significant inventiveness. Summary of the Invention

[0004] (I) System Composition This system consists of a pad / bump feature visual acquisition unit, an array feature targeted calculation unit, a dynamic correction control unit, and a precision bonding execution unit. It adopts an integrated hardware architecture of "vision-bonding coaxial presence, co-motion platform, and unified clock synchronization" to ensure real-time synchronization between feature acquisition and bonding execution. The core emphasis is on the feasibility and uniqueness of dynamic correction.

[0005] 1. Pad / Bump Feature Visual Acquisition Unit The in-situ detection structure adopts coaxial incident vision + side auxiliary vision, and is arranged coaxially with the bonding head on the same platform, so that real-time feature acquisition can be completed without offline movement; The visual acquisition unit and the bonding head share the same vacuum adsorption platform, ensuring that the acquisition field of view is completely aligned with the bonding station without any coordinate offset. The extracted target features are clearly defined as: the geometric centroid, edge gradient, roundness, array spacing, and arrangement pattern of the pads / bumps (copper pillar bumps, micro bumps). No mark points or calibration boards are required; alignment is completed solely based on the features of the pads / bumps themselves. The visual acquisition frequency is ≥2kHz to ensure the real-time performance of dynamic correction; the pixel size is ≤1μm; and with the sub-pixel subdivision algorithm, the feature extraction accuracy is ≤0.1μm.

[0006] 2. Array Feature Targeting Solving Unit (Core, Enhancing Creativity) It uses pad / bump array features as the sole targeting reference, unlike existing single-bump alignment techniques: • The "global array feature calculation + local calibration of individual bumps" mode is adopted. First, global target positioning is completed by the spacing and arrangement of pad / bump arrays, and then local deviation correction is performed by the centroid of individual bumps. • Built-in array feature matching algorithm: compares the real-time acquired pad / bump array with the preset array template (only records the array pattern and does not participate in the positioning reference) to eliminate abnormal bumps that are damaged or oxidized, and ensures the stability of the target positioning; • Define the calculation logic: calculate the translational deviation (X / Y direction), rotational deviation (θ direction), tilt deviation (Z direction), and array spacing deviation of the corresponding pad / bump pairs on the chip side and the substrate side, with a calculation delay ≤0.5ms.

[0007] 3. Dynamic correction control unit (core innovation, supplementing publicly available information) The specific implementation of "dynamic closed-loop correction throughout the bonding process" is clearly defined, thus completely resolving the issue of insufficient disclosure. • Correction covers the entire process (with clearly defined triggering conditions): 1. Pre-press-down calibration: The trigger condition is that the chip and the substrate are initially aligned. Calibration is performed once to eliminate the initial offset. 2. Downward pressure correction: The trigger condition is that the pressure reaches 50% of the target pressure, and the displacement caused by pressure deformation is corrected in real time; 3. Correction during hot pressing: The trigger condition is that the temperature reaches 150℃ (the critical temperature for advanced packaging bonding), and correction is performed once every 1ms to compensate for thermal drift; 4. Correction before bonding completion: The triggering condition is that the pressure and temperature reach the target values. A final correction is performed to ensure that the bonding offset is ≤0.5μm. • Correction frequency: ≥1kHz during hot pressing, ≥500Hz for other stages; • Correction algorithm (explicitly disclosed and reproducible): The algorithm adopts "feedforward + PID + iterative learning control algorithm". Thermal drift compensation adopts linear fitting modeling (model: ΔX=k×ΔT, k is the temperature coefficient, with a value of 0.001μm / ℃). Pressure deformation compensation adopts polynomial fitting (model: ΔY=a×F²+b×F, a and b are fitting coefficients). • Correction logic: The dynamic correction control unit receives deviation data from the array feature calculation unit in real time and synchronously outputs correction commands to the precision bonding execution unit, forming a closed-loop control of "acquisition-calculation-correction-feedback".

[0008] 4. Precision bonding execution unit The system shares a motion platform with the vision acquisition unit and dynamic correction control unit, and uses a unified clock for synchronization to ensure real-time coordinate reuse. It includes a high-precision motion platform (resolution ≤0.1μm, following error ≤0.2μm), a hot press head, a vacuum nozzle, and a pressure-temperature dual feedback module; It supports advanced packaging and bonding processes such as flip-chip bonding, thermo-press bonding, laser-assisted bonding, and direct copper-copper bonding. It can receive dynamically corrected coordinates and perform high-precision bonding. Pressure feedback accuracy ≤0.1N, temperature control accuracy ≤±1℃, to avoid damage to pads / bumps caused by excessive pressure or temperature.

[0009] (II) Working Methods 1. The vision acquisition unit (coaxial in-situ) acquires images of the pads / bumps of the chip and the substrate, extracts their geometric centroid, edge contours, array spacing and other target features, and the acquisition frequency is ≥2kHz; 2. The array feature targeting calculation unit uses the pad / bump array features as the sole targeting reference. Through "global array calculation + local bump calibration", it calculates the alignment deviation between the chip and the substrate, with a calculation delay of ≤0.5ms. 3. After bonding begins, the dynamic correction control unit uses a feedforward + PID + iterative learning algorithm according to preset trigger conditions to dynamically correct the bonding coordinates in real time throughout the entire bonding process. The correction frequency is ≥1kHz during hot pressing. 4. The precision bonding execution unit performs advanced packaging bonding under pressure and temperature dual feedback control based on the calibrated coordinates; 5. After bonding is completed, the vision acquisition unit acquires the features of the bonded pads / bumps again to verify that the bonding offset is ≤0.5μm, thus completing the entire bonding process.

[0010] (III) Beneficial Effects 1. Clearly define the target features as array features and single features of pads / bumps (including copper pillar bumps and microbumps), lock in advanced packaging bonding scenarios, distinguish it from existing conventional bump alignment, and enhance creativity; 2. The triggering conditions, frequency, and algorithm for dynamic correction are supplemented to address the issue of insufficient disclosure, and can be fully reproduced by those skilled in the art; 3. Adopting a "vision-key coaxial alignment in place, common platform" structure eliminates coordinate transformation errors and prevents competitors from circumventing infringement through "offline pre-alignment"; 4. Using the pad / bump array features as the sole targeting reference, the logic is self-consistent, resolving the contradiction between "single targeting" and "array pairing", resulting in stronger stability; 5. Dynamic closed-loop correction completely solves the problem of deviation accumulation caused by thermal drift and pressure deformation, with bonding alignment accuracy ≤0.5μm, adapting to the high-density and fine-pitch requirements of advanced packaging; 6. The underlying principle cannot be avoided: As long as "pad / bump bonding" is performed, "pad / bump feature positioning" must be used. However, this invention focuses on "array feature targeting + dynamic closed-loop correction", forming a unique technical barrier. Detailed Implementation

[0011] Application scenario: 2.5D / 3D advanced packaging copper pillar bump bonding (fine pitch 0.8μm) Targeting features: centroid of copper pillar bumps, edge contour, array spacing (100μm×100μm) System Configuration: • Visual acquisition unit: coaxial incident camera (pixel size 0.8μm) + side auxiliary camera, acquisition frequency 2.5kHz; • Array feature resolution unit: FPGA heterogeneous acceleration, resolution latency of 0.3ms, and abnormal bump removal accuracy ≥99.9%; • Dynamic correction control unit: feedforward + PID + iterative learning algorithm, hot pressing process correction frequency 1.2kHz, temperature coefficient k=0.001μm / ℃; • Precision bonding actuator: 0.1μm-level motion platform, pressure feedback accuracy of 0.05N, and temperature control accuracy of ±0.5℃.

[0012] Accuracy verification method (complete, to meet competitor challenges): Using standard bumped wafer samples (bump size 5μm, array spacing 100μm), the test was repeated 100 times at 25℃±2℃. The standard deviation of bonding offset was ≤0.5μm, and the maximum single offset was ≤0.45μm, verifying the effectiveness of dynamic correction.

[0013] Test results: • Pad / bump feature extraction accuracy ≥ 99.8% • Bonding alignment accuracy ≤ 0.5 μm (average 0.38 μm) • Dynamic correction response delay ≤ 0.5ms • Bonding yield ≥ 99.6% • Suitable for advanced packaging and bonding scenarios with fine pitch ≥0.8μm.

Claims

1. An advanced chip packaging bonding system based on pad / bump feature targeting, characterized in that, It includes a pad / bump feature visual acquisition unit, an array feature targeted calculation unit, a dynamic correction control unit, and a precision bonding execution unit. The four units adopt an integrated architecture with coaxial in-situ, shared motion platform, and unified clock synchronization. The visual acquisition unit is an in-situ detection structure, coaxially arranged with the bonding head, used to extract the geometric centroid, edge contour, and array spacing features of pads and bumps (including copper pillar bumps and micro bumps) on the chip and substrate, without the need for additional alignment marks; The array feature targeting calculation unit uses the pad / bump array features as the sole targeting reference and adopts the "global array feature calculation + local calibration of a single bump" mode to calculate the alignment deviation between the chip and the substrate, with a calculation delay of ≤0.5ms. The dynamic correction control unit adopts a "feedforward + PID + iterative learning control algorithm" to dynamically correct the bonding coordinates in real time according to preset conditions throughout the entire bonding process. The correction frequency is ≥1kHz during hot pressing. The thermal drift compensation adopts a linear fitting model, and the pressure deformation compensation adopts a polynomial fitting model. The precision bonding execution unit completes advanced packaging bonding based on the corrected coordinates, with a bonding alignment accuracy of ≤0.5μm.

2. The system according to claim 1, characterized in that, The visual acquisition unit has an acquisition frequency of ≥2kHz and a pixel size of ≤1μm. With the help of the subpixel subdivision algorithm, the feature extraction accuracy is ≤0.1μm. It shares the same vacuum adsorption platform with the bonding head, and the field of view is completely overlapped with the bonding station.

3. The system according to claim 1, characterized in that, The triggering conditions for the dynamic correction include: before pressing, during pressing (pressure reaches 50% of the target pressure), during hot pressing (temperature reaches 150℃), and before bonding is completed, forming a closed-loop correction.

4. The system according to claim 1, characterized in that, The array feature targeting calculation unit has built-in abnormal bump rejection logic, which can reject damaged or oxidized abnormal pads / bumps to ensure the stability of targeting positioning.

5. The system according to claim 1, characterized in that, Suitable for advanced packaging scenarios such as 2.5D / 3D packaging, flip-chip bonding, micro-bump bonding, and copper-copper bonding, and adaptable to high-density bonding requirements with fine pitch ≥0.8μm.

6. The system according to claim 1, characterized in that, The bonding alignment accuracy is ≤0.5μm. The verification method is to repeat the test 100 times on a standard bump wafer sample, and the coordinate standard deviation is ≤0.5μm.

7. A chip advanced packaging bonding method based on pad / bump feature targeting, characterized in that, Includes the following steps: 1) Acquire images of the pads / bumps of the chip and substrate using a coaxial in-situ vision acquisition unit, and extract their geometric centroid, edge contours, and array spacing features at an acquisition frequency ≥2kHz. 2) Using the pad / bump array features as the sole target reference, the "global calculation of array features + local calibration of individual bumps" mode is adopted to calculate the alignment deviation, with a calculation delay ≤0.5ms; 3) The feedforward + PID + iterative learning control algorithm is adopted to dynamically correct the bonding coordinates in real time according to the preset trigger conditions throughout the bonding process, and the correction frequency is ≥1kHz during hot pressing. 4) Drive the precision bonding execution unit to complete advanced packaging bonding according to the corrected coordinates, ensuring bonding alignment accuracy ≤0.5μm; 5) After bonding is completed, the bonding offset is verified by the visual acquisition unit to form a complete closed loop.

8. The method according to claim 7, characterized in that, It achieves targeted positioning and dynamic correction without relying on any alignment marks, calibration boards, or reference templates, but solely on the array features and individual features of the pads / bumps themselves.

9. The system according to claim 1 or the method according to claim 7, characterized in that, Thermal drift compensation uses a linear fitting model ΔX=k×ΔT (k=0.001μm / ℃), and pressure deformation compensation uses a polynomial fitting model ΔY=a×F²+b×F.