Semiconductor chip bonding method
By attaching bonding material to the back of the target circuit chip and selecting known good chips for wafer-level bonding, the problem of insufficient bonding efficiency and yield in the prior art is solved, and efficient and reliable chip bonding is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- PEKING UNIV
- Filing Date
- 2026-05-07
- Publication Date
- 2026-06-05
Smart Images
Figure CN122161489A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor packaging technology, and in particular to a semiconductor chip bonding method. Background Technology
[0002] As Moore's Law gradually slows down, three-dimensional heterogeneous integration and hybrid bonding technology have become the core path to improve chip integration and system performance. High-density, high-yield and high-efficiency chip bonding processes have become a necessity for the development of advanced packaging.
[0003] Currently, mainstream chip bonding solutions in the industry are divided into two categories: die-to-wafer (D2W) hybrid bonding and wafer-to-wafer (W2W) hybrid bonding. The D2W solution uses individual chip pick-and-place, resulting in low throughput and thermal budget overruns due to multiple thermal cycles. The W2W solution uses direct bonding of the entire wafer, which improves bonding efficiency and allows for thermal budget control, but suffers from issues such as poor die matching leading to a significant drop in composite yield, high bonding costs, and poor design flexibility.
[0004] Therefore, how to balance bonding efficiency and yield gains in chip bonding has become a problem that needs to be solved. Summary of the Invention
[0005] To address the aforementioned issues, this application provides a semiconductor chip bonding method that can balance bonding efficiency and yield gains in chip bonding.
[0006] The embodiments of this application disclose the following technical solutions: This application provides a semiconductor chip bonding method, the method comprising: Bonding material is attached to the back of the target circuit chip with a bonding structure; Known good chips are selected from the chips contained in the target circuit chip; Multiple known good chips are bonded one-to-one into multiple pre-formed grooves in the target wafer to obtain a reconstructed wafer; the bonding material is in contact with the bottom surface of the groove; The reconstructed wafer is bonded using a wafer-to-wafer hybrid bonding process.
[0007] Optionally, the step of bonding multiple known good chips one-to-one into multiple pre-formed grooves in the target wafer to obtain a reconstructed wafer includes: The target wafer is etched to form a groove with a length and width greater than that of the chip and a depth less than that of the chip; Multiple known good chips are bonded one-to-one into multiple grooves to obtain a reconstructed wafer.
[0008] Optionally, the step of bonding multiple known good chips one-to-one into multiple grooves to obtain a reconstructed wafer includes: Multiple known good chips are bonded one-to-one into multiple grooves; The gap between the known good chip and the groove is filled with an insulating medium; The insulating dielectric on the top of the known good chip is removed by chemical mechanical polishing, exposing the pads of the known good chip, to obtain a reconstructed wafer.
[0009] Optionally, filling the gap between the known good chip and the recess with an insulating medium includes: Deposit parylene to fill the gap between the known good chip and the groove; Alternatively, an electronic-grade resin-based dry film may be pressed into the gap between the known good chip and the groove.
[0010] Optionally, the difference between the length of the groove and the length of the chip is selected from 12μm to 20μm; the difference between the width of the groove and the width of the chip is selected from 12μm to 20μm.
[0011] Optionally, the difference between the height of the chip and the depth of the groove is selected from 1μm to 5μm.
[0012] Optionally, attaching bonding material to the back of the target circuit chip having a bonding structure includes: Backside thinning is performed on target circuit chips with bonding structures; Bonding material is attached to the back of the thinned target circuit chip.
[0013] Optionally, the back-side thinning of the target circuit chip with the bonding structure includes: The back side of the target circuit chip with bonding structure is thinned to 50μm~100μm.
[0014] Optionally, attaching bonding material to the back of the thinned target circuit chip includes: A chip mounting film is attached to the back of the thinned target circuit chip.
[0015] Optionally, selecting known good chips from the chips included in the target circuit chip includes: The target circuit chip with bonding material attached is diced to obtain multiple chips; A known good chip is selected from multiple chips by using a probe station test.
[0016] Compared with the prior art, this application has the following advantages: This application provides a semiconductor chip bonding method. In this method, firstly, bonding material is attached to the back of a target circuit chip having a bonding structure; then, known good chips are selected from the chips included in the target circuit chip; subsequently, multiple known good chips are bonded one-to-one to multiple pre-formed grooves in a target wafer to obtain a reconstructed wafer; the bonding material is in contact with the bottom surface of the grooves; finally, the reconstructed wafer is bonded using a wafer-to-wafer hybrid bonding process.
[0017] Therefore, by selecting known good chips and reconstructing wafers, the traditional D2W serial chip mounting is transformed into wafer-level integral bonding. On the one hand, this significantly improves equipment throughput and production efficiency, meeting the needs of large-scale mass production, and requires only one overall heat treatment throughout the process, eliminating the accumulation of thermal stress caused by repeated thermal cycles and improving chip bonding reliability. On the other hand, it enables bonding of good chips to good chips, reduces the matching of bad chips, significantly improves the composite yield after bonding, reduces packaging costs, and achieves the integration of the advantages of D2W and W2W. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 A flowchart of a semiconductor chip bonding method provided in this application embodiment; Figure 2 A schematic diagram of a target circuit chip provided in an embodiment of this application; Figure 3 A schematic diagram of a target wafer provided in an embodiment of this application; Figure 4 This application provides a schematic diagram of a known good chip bonding result in an embodiment of the present application. Figure 5 This is a schematic diagram of an insulating medium filling result provided in an embodiment of this application; Figure 6 This is a schematic diagram of a reconstructed wafer provided in an embodiment of this application; Figure 7 This is a schematic diagram of wafer-to-wafer bonding provided in an embodiment of this application. Detailed Implementation
[0020] The semiconductor chip bonding method provided in this application can be used in the field of semiconductor packaging. The above is only an example and does not limit the application field of the semiconductor chip bonding method provided in this application.
[0021] The terms "first," "second," "third," and "fourth," etc., used in this application specification, claims, and drawings are used to distinguish different objects, not to limit a specific order.
[0022] In the embodiments of this application, the terms "as an example" or "for example" are used to indicate that they are examples, illustrations, or explanations. Any embodiment or design that is described as "as an example" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design options. Specifically, the use of terms such as "as an example" or "for example" is intended to present the relevant concepts in a specific manner.
[0023] The terminology used in the implementation section of this application is for the purpose of explaining specific embodiments of this application only, and is not intended to limit this application.
[0024] As mentioned earlier, the mainstream chip bonding solutions in the industry are currently divided into two categories: chip-to-wafer (D2W) hybrid bonding and wafer-to-wafer (W2W) hybrid bonding.
[0025] In traditional D2W hybrid bonding processes, high-precision equipment is required to pick up, align, and attach individual chips one by one onto the target wafer. With the increasing demand for high-density integration, this serial operation mode results in extremely low equipment throughput, which severely restricts large-scale mass production.
[0026] On the other hand, hybrid bonding, especially Cu-Cu interconnects, typically requires a high-temperature annealing process. In D2W multi-chip sequential bonding scenarios, the first chip bonded must repeatedly endure the repetitive thermal cycles from each subsequent bond. This severe thermal budget overrun not only leads to significant thermal stress accumulation within the wafer, causing microscopic delamination and alignment misalignment at the bonding interface, but also results in irreversible degradation of the electrical performance of the underlying bonded devices.
[0027] In addition, during the dicing and multiple mechanical gripping processes, a single chip is highly susceptible to particulate contamination and physical damage, which further reduces the reliability of the bonding interface after D2W bonding.
[0028] While W2W hybrid bonding achieves extremely high production efficiency and ensures a single thermal cycle through one-time alignment and bonding, it faces a severe yield waste problem. Specifically, any wafer inevitably contains a certain percentage of known bad dies after manufacturing. During direct W2W hard-match bonding, the bad dies on the top wafer will be bonded directly to the good dies on the bottom wafer, and vice versa. This blind bonding of good dies to bad dies leads to the scrapping of high-value chips that were originally in good working order. As the number of stacked layers increases, the composite yield of the final packaged product will decrease exponentially, resulting in significant cost waste. W2W bonding is therefore unsuitable for high-yield, high-end heterogeneous integrated products.
[0029] In view of this, in order to balance bonding efficiency and yield gains in chip bonding, this application provides a semiconductor chip bonding method. In this method, firstly, bonding material is attached to the back of a target circuit chip with a bonding structure; then, known good chips are selected from the chips contained in the target circuit chip; subsequently, multiple known good chips are bonded one-to-one to multiple pre-formed grooves in the target wafer to obtain a reconstructed wafer; the bonding material is in contact with the bottom surface of the grooves; finally, the reconstructed wafer is bonded using a wafer-to-wafer hybrid bonding process.
[0030] Therefore, by selecting known good chips and reconstructing wafers, the traditional D2W serial chip mounting is transformed into wafer-level integral bonding. On the one hand, this significantly improves equipment throughput and production efficiency, meeting the needs of large-scale mass production, and requires only one overall heat treatment throughout the process, eliminating the accumulation of thermal stress caused by repeated thermal cycles and improving chip bonding reliability. On the other hand, it enables bonding of good chips to good chips, reduces the matching of bad chips, significantly improves the composite yield after bonding, reduces packaging costs, and achieves the integration of the advantages of D2W and W2W.
[0031] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.
[0032] See Figure 1 The figure is a flowchart of a semiconductor chip bonding method provided in an embodiment of this application. The method includes: S101: Bonding material is attached to the back of the target circuit chip with a bonding structure.
[0033] For example, such as Figure 2As shown, the target circuit chip 100 with bonding structure can be thinned on the back first; then, bonding material 200 is attached to the back of the thinned target circuit chip 100.
[0034] The target circuit chip 100 is a circuit chip that has completed the previous process and has a surface with mixed bonding pads and dielectric layers.
[0035] In one example, a wafer thinning device can first be used to mechanically rough grind the unbonded surface of the target circuit chip 100, i.e., the back side of the target circuit chip 100, to remove most of the substrate thickness. For example, the back side of the target circuit chip 100 can be thinned to the range of 100μm to 150μm. Then, the rough-ground back side is finely ground. For example, chemical mechanical polishing (CMP) can be used to remove the mechanical damage layer on the back side of the target circuit chip 100, and the back side of the target circuit chip 100 can be further thinned to the target thickness range, such as 50μm to 100μm, to meet the low stress requirements of subsequent steps such as dicing, picking, and embedding grooves.
[0036] In one example, a die attach film (DAF) can be used as the bonding material 200. The bonding surface of the thinned target circuit chip 100, i.e., the front side of the target circuit chip 100, can be fixed on a chuck to protect the bonding structure. The DAF is then centered and placed over the back side of the target circuit chip 100. The chip is then thermo-pressed under vacuum conditions to ensure that the DAF is completely bonded to the back side of the target circuit chip 100.
[0037] As an example, the DAF hot-press bonding process can be carried out under low temperature and low pressure conditions, such as a temperature range of 80℃ to 120℃ and a pressure range of 0.3MPa to 0.8MPa, so that the introduced thermal stress and interface defects are kept at a low level, reducing the damage to the front hybrid bonding structure of the target circuit chip 100 during the bonding process.
[0038] After attaching DAF to the back of the target circuit chip 100, excess DAF can be removed by cutting along the wafer outline of the target circuit chip 100 to align the DAF edge with the wafer edge, so as to facilitate subsequent steps such as dicing and probe testing.
[0039] Alternatively, any one of the following materials may be selected as the bonding material 200: die attach film (DFD), liquid adhesive film (LAM), UV-release film, and liquid die attach epoxy.
[0040] S102: Select known good chips from the chips contained in the target circuit chip.
[0041] For example, the target circuit chip 100 with bonding material 200 attached can be diced to obtain multiple chips 110; then, a known good chip 111 can be selected from the multiple chips 110 by probe station testing.
[0042] In one example, the target circuit chip 100 can be fixed face up on a dicing ring and an adhesive film such as a blue film or a UV film, and the bonding material 200 on the back of the target circuit chip 100 can be bonded to the film. The target circuit chip 100 can be diced at the wafer level using equipment such as a fully automatic laser dicing machine or a blade dicing machine, dividing the entire wafer into individual chips 110.
[0043] The chip 110, held on the film after dicing, is fed into a fully automated probe station. Electrical functional tests, including but not limited to functional logic tests, DC parameter tests, hybrid bonding pad continuity / insulation tests, and tests for key parameters such as leakage current, withstand voltage, and speed, can be performed on the chip 110. If all electrical parameters of the chip 110 are qualified, there are no functional failures, no open or short circuit abnormalities, no leakage abnormalities, and the bonding pads are intact, the chip 110 can be marked as a Known Good Die (KGD) 111, and its coordinates recorded for high-precision picking. Chips 110 that fail the tests are marked as defective and do not proceed to the next process.
[0044] Therefore, only known good chips 111 enter the subsequent process, eliminating the possibility of matching defective chips from the source.
[0045] S103: Bond multiple known good chips one-to-one into multiple pre-formed grooves in the target wafer to obtain a reconstructed wafer.
[0046] For example, such as Figure 3 As shown, the target wafer 300 can be pre-etched to form grooves with a length and width greater than the chip and a depth less than the chip; then, multiple known good chips 111 are bonded one-to-one into the multiple grooves, as shown. Figure 4 As shown, a reconstructed wafer is obtained. The bonding material 200 is in contact with the bottom surface of the groove.
[0047] In one example, a single-layer polished silicon wafer can be used as the target wafer 300, and a groove array can be defined on the surface of the target wafer 300 using photolithography. The length and width of the grooves can be increased by 12μm to 20μm based on the chip 110 to ensure that the known good chip 111 can be successfully embedded in the grooves; the depth of the grooves can be less than the height of the chip 110, for example, 1μm to 5μm lower than the chip 110, so that after the known good chip 111 is bonded into the groove, the bonding surface is slightly higher than the surface of the target wafer 300, so as to facilitate subsequent chip bonding.
[0048] Alternatively, grooves can be formed on the surface of the target wafer 300 using methods such as deep silicon etching or plasma dry etching.
[0049] In one example, the selected known good chip 111 can be placed on a submicron bonding device and automatically aligned visually, with the front of the known good chip 111 facing up and the back bonding material 200 facing down, and accurately placed into the corresponding groove, so that the bonding material 200 on the back of the known good chip 111 is in direct contact with the bottom of the groove; then, methods such as low temperature hot pressing can be used to reliably bond the known good chip 111 to the groove.
[0050] By embedding all the known good chips 111 into different grooves one by one, a reconstructed wafer 01 can be formed.
[0051] In this embodiment, the groove size is slightly larger than the chip 110 size. After the known good chip 111 is bonded to the target wafer 300, a gap will exist between the groove and the known good chip 111. Therefore, the gap between the known good chip 111 and the groove can be filled with an insulating medium 400, such as... Figure 5 As shown.
[0052] For example, polymers such as parylene can be deposited to fill the gap between a known good chip and a recess, or electronic-grade resin-based dry films, such as ABF (Ajinomoto Build-up Film), can be pressed into the gap between a known good chip and a recess.
[0053] In one example, a target wafer 300 with a known good chip 111 bonded to it can be placed in a vacuum deposition chamber for parylene deposition, so that parylene covers the top of the known good chip 111 and conformally covers the known good chip 111 along the sidewalls of the groove, completely filling the gap between the known good chip 111 and the groove.
[0054] In another example, ABF can be applied to the surface of a target wafer 300 to which a known good chip 111 is bonded, and then placed in a vacuum laminator where it is thermally cured to allow the ABF to flow completely into the gap between the known good chip 111 and the groove and harden.
[0055] Furthermore, the insulating dielectric 400 on top of the known good chip 111 can be removed by chemical mechanical polishing (CMP), exposing the pads of the known good chip 111, thus obtaining the reconstructed wafer 01, as shown below. Figure 6 As shown.
[0056] For example, a chemical mechanical polishing (CMP) device can be used with a neutral or weakly alkaline polishing slurry that allows for a controllable selection ratio between the insulating medium 400 and the pads. First, a rough polishing is performed to quickly remove most of the insulating medium on the top of the known good chip 111. The polishing rate can be controlled between 1 μm / min and 3 μm / min, rapidly reducing the surface height of the wafer to near the pad plane of the known good chip 111. Then, a low-pressure, low-rate fine polishing is performed to expose the pads of the known good chip 111, resulting in a reconstructed wafer 01.
[0057] After polishing, the insulating dielectric 400 and the pad are coplanar and flat, completing the surface flattening treatment. The flatness meets the requirements of W2W hybrid bonding, and the reconstructed wafer 01 can directly enter the wafer-level hybrid bonding.
[0058] S104: Reconstructing wafers by bonding using a wafer-to-wafer hybrid bonding process.
[0059] For example, such as Figure 7 As shown, the reconstructed wafer 01 with its surface planarized and hybrid bonding pads exposed can be aligned at the wafer level with another wafer 02 to be bonded. Room temperature prebonding is then performed in a vacuum environment to allow the two wafers to initially bond together. Subsequently, the prebonded stacked structure is placed in a high-temperature annealing furnace and subjected to a one-time high-temperature annealing treatment in an inert or reducing atmosphere to achieve dielectric bonding and Cu-Cu metal interconnect at the hybrid bonding interface, thus completing a permanent and reliable W2W hybrid bonding between the two wafers.
[0060] The other wafer 02 to be bonded can be a reconstructed wafer obtained through steps S101 to S103, or it can be an unreconstructed wafer.
[0061] In this embodiment, firstly, bonding material 200 is attached to the back of the target circuit chip 100 with a bonding structure; then, known good chips 111 are selected from the chips 110 included in the target circuit chip 100; subsequently, multiple known good chips 111 are bonded one-to-one to multiple pre-formed grooves in the target wafer 300 to obtain a reconstructed wafer 01; the bonding material 200 is in contact with the bottom surface of the groove; finally, the reconstructed wafer 01 is bonded using a wafer-to-wafer hybrid bonding process. Thus, by selecting known good chips and reconstructing the wafer, the traditional serial chip-to-wafer bonding (D2W) process is transformed into wafer-level integral bonding. On the one hand, this significantly improves equipment throughput and production efficiency, meeting the needs of large-scale mass production, and requires only one overall heat treatment throughout the process, eliminating the accumulation of thermal stress caused by repeated thermal cycles and improving chip bonding reliability; on the other hand, it achieves good-to-good chip bonding, reduces bad chip matching, significantly improves the composite yield after bonding, reduces packaging costs, and realizes the integration of the advantages of D2W and W2W.
[0062] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. The embodiments described above are merely illustrative, and some or all of the modules can be selected to achieve the purpose of this embodiment solution according to actual needs. Those skilled in the art can understand and implement this without creative effort.
[0063] The above description is merely one specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A semiconductor chip bonding method, characterized in that, The method includes: Bonding material is attached to the back of the target circuit chip with a bonding structure; A known good chip is selected from the chips contained in the target circuit chip; Multiple known good chips are bonded one-to-one into multiple pre-formed grooves in the target wafer to obtain a reconstructed wafer; the bonding material is in contact with the bottom surface of the groove; The reconstructed wafer is bonded using a wafer-to-wafer hybrid bonding process.
2. The method according to claim 1, characterized in that, The step of bonding multiple known good chips one-to-one into multiple pre-formed grooves in the target wafer to obtain a reconstructed wafer includes: The target wafer is etched to form a groove with a length and width greater than that of the chip and a depth less than that of the chip; Multiple known good chips are bonded one-to-one into multiple grooves to obtain a reconstructed wafer.
3. The method according to claim 2, characterized in that, The step of bonding multiple known good chips one-to-one into multiple grooves to obtain a reconstructed wafer includes: Multiple known good chips are bonded one-to-one into multiple grooves; The gap between the known good chip and the groove is filled with an insulating medium; The insulating dielectric on the top of the known good chip is removed by chemical mechanical polishing, exposing the pads of the known good chip, to obtain a reconstructed wafer.
4. The method according to claim 3, characterized in that, The process of filling the gap between the known good chip and the groove with an insulating medium includes: Deposit parylene to fill the gap between the known good chip and the groove; Alternatively, an electronic-grade resin-based dry film may be pressed into the gap between the known good chip and the groove.
5. The method according to claim 2, characterized in that, The difference between the length of the groove and the length of the chip is selected from 12μm to 20μm; the difference between the width of the groove and the width of the chip is selected from 12μm to 20μm.
6. The method according to claim 2, characterized in that, The difference between the height of the chip and the depth of the groove is selected from 1μm to 5μm.
7. The method according to claim 1, characterized in that, The process of attaching bonding material to the back of a target circuit chip with a bonding structure includes: Backside thinning is performed on target circuit chips with bonding structures; Bonding material is attached to the back of the thinned target circuit chip.
8. The method according to claim 7, characterized in that, The back-side thinning of the target circuit chip with bonding structure includes: The back side of the target circuit chip with bonding structure is thinned to 50μm~100μm.
9. The method according to claim 7, characterized in that, The process of attaching bonding material to the back of the thinned target circuit chip includes: A chip mounting film is attached to the back of the thinned target circuit chip.
10. The method according to claim 1, characterized in that, The step of selecting known good chips from the chips contained in the target circuit chip includes: The target circuit chip with bonding material attached is diced to obtain multiple chips; A known good chip is selected from multiple chips by using a probe station test.