Test pattern generation

Abstract

A method and data processing system for extracting a path having a longest delay time through an integrated circuit are provided. The method includes obtaining a data set for the integrated circuit, the data set including a maximum arrival time and a maximum propagation delay; selecting a logic cell in the integrated circuit; based on the data set, identifying a longest arrival path from a start point in the integrated circuit to an output pin O of the selected logic cell; identifying a longest propagation path from an input pin I of the selected logic cell to an end point in the integrated circuit; and based on the identified longest arrival path and longest propagation path, extracting a longest path through the selected logic cell.

Description

Technical Field

[0001] This disclosure relates to methods and systems for testing integrated circuits. Various aspects of the invention can be used for cell library characterization and test pattern generation. Background Technology

[0002] In recent years, the semiconductor industry has increasingly focused on the devastating impact of silent data errors (SDEs) (also known as silent data corruption (SDCs)) in data centers. SDEs are elusive and difficult to detect until they affect a specific application. Detection may not occur until days or months after integrated circuits (ICs) have been deployed in the field. Furthermore, most of these devices have been observed to fail in the very early stages of their deployment, raising questions about the reliability and quality of manufacturing testing.

[0003] While the causes of SDEs can be multifaceted, ranging from test omissions and design margins to design errors, there is an industry-wide consensus: they are typically traced back to timing delay issues. Depending on the software workload and different operating and environmental conditions (known as the process, voltage, and temperature (PVT) corner), transistor performance can vary, causing certain defective behaviors to be captured only under specific conditions. Defective behaviors can also occur later in the chip's lifespan. In this case, silicon degradation due to aging effects manifests as additional delay-related failures. For example, aging effects caused by negative bias temperature instability (NBTI) and hot carrier injection (HCI) degrade circuit performance and introduce reliability issues. Furthermore, the effects of aging on transistors are not uniform, making SDE screening even more difficult.

[0004] Investigating the root causes of SDEs (such as isolating defective cores and reverse engineering) is complex and costly. Therefore, there is an urgent need for improved test generation and design-for-testability (DFT) techniques to detect timing-related defects causing SDEs before defective chips are shipped and deployed. During test generation, the impact of varying environmental conditions and lifetime degradation on cell propagation delays should also be considered.

[0005] Timing-related defects can be targeted in at least two ways. The first type of test generation process detects small-latency defects by propagating transitions through the defect location using the longest possible path. For example, the Timing-Aware Module-Aware Test (TA CAT) Automated Test Pattern Generation (ATPG) generates tests for small-latency defects by propagating transitions through long paths with minimal relaxation. The second type of test generation process uses various criteria to directly select a subset of longest-path delay defects as the target for test generation. Summary of the Invention

[0006] The purpose of this invention is to provide a method for generating test patterns.

[0007] The above and other objectives are achieved through the features of the independent claim. Other implementations are apparent from the dependent claims, description, and drawings.

[0008] According to a first aspect, a method is provided for extracting a path having the longest delay time through an integrated circuit. The method includes: a) obtaining a dataset for the integrated circuit, the dataset including the maximum arrival time and maximum propagation delay for each pin in the integrated circuit; b) selecting a logic cell in the integrated circuit; c) based on the dataset, identifying the longest arrival path from a starting point in the integrated circuit to an output pin O of the selected logic cell; d) identifying the longest propagation path from an input pin I of the selected logic cell to an endpoint in the integrated circuit; and e) based on the identified longest arrival path and longest propagation path, extracting the longest path through the selected logic cell. For each logic cell, the maximum arrival time and maximum propagation delay for each pin of the logic cell are determined based on an evaluation of the logic cell for each two-cycle stimulus in a two-cycle stimulus set.

[0009] The method according to the first aspect enables the identification of the longest path through a cell in an integrated circuit based on data considering both single-input switching excitation and multi-input switching excitation.

[0010] In the first implementation, the method includes repeating steps c) to e) for each input and output pin of the selected logic unit.

[0011] In a second implementation, the method includes: selecting one or more additional logic units, and repeating steps c) through e) for each input and output pin of each of the additionally selected logic units.

[0012] In the third implementation, identifying the longest reach path from output pin O includes: identifying the path from output pin O to input pin I1 of the selected logic unit, which makes the magnitude... Maximize, where It is an input pin. I 1 Maximum arrival time From I 1 The maximum propagation delay to O.

[0013] In the fifth implementation, identifying the longest reach path from the starting point to the output pin of the selected logic unit includes iteratively: a) identifying the output O i and the previous input pin I on the drive path i-1 The logic unit, and b) the subsequent input pin I of the identified logic unit.i The subsequent input pin I i Make the quantity value Maximize, where It is an input pin. I i Maximum arrival time From I i To O i The maximum propagation delay.

[0014] In the sixth implementation, identifying the longest propagation path from input pin I includes: identifying the path from input pin I to the output pin O1 of the selected logic unit, which makes the magnitude... Maximize, where It is an input pin. I Maximum propagation time From I The maximum propagation delay to O1.

[0015] In the seventh implementation, identifying the longest propagation path from input pin I includes iteratively: a) identifying input pin I i and the previous output pin O on the path i-1 The driven logic unit, and b) the subsequent output pin O of the identified logic unit. i The subsequent output pin O i Make the quantity value Maximize, where It is an input pin. I i The maximum propagation time; and From I i arrive O i The maximum propagation delay.

[0016] These and other aspects of the invention will become apparent from the embodiments described below. Attached Figure Description

[0017] To gain a more complete understanding of this disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, wherein:

[0018] Figure 1 A schematic diagram of the circuit based on the example is shown.

[0019] Figure 2 A flowchart of a method 200 for determining propagation delay in a logic unit, based on an example, is shown.

[0020] Figure 3 A schematic diagram of the circuit based on the example is shown.

[0021] Figure 4 A flowchart is shown, based on an example, of a method for generating a database of combinations for a unit library.

[0022] Figure 5 A flowchart is shown, based on an example, for extracting the method with the longest delay path through an integrated circuit.

[0023] Figure 6 A flowchart of a method for generating timing verification tests, based on an example, is shown.

[0024] Figure 7 A schematic diagram of the circuit based on the example is shown.

[0025] Figure 8 A flowchart of a method for generating automated test patterns, based on an example, is shown.

[0026] Figure 9 This is a schematic representation of a data processing system suitable for implementing embodiments of the present invention. Detailed Implementation

[0027] Example embodiments are described below in sufficient detail to enable those skilled in the art to implement and carry out the systems and processes described herein. It is important to understand that embodiments may be provided in many alternative forms and should not be construed as limited to the examples set forth herein.

[0028] Therefore, while embodiments may be modified in various ways and take various alternative forms, specific embodiments thereof are shown in the accompanying drawings and described in detail below as examples. There is no intention to limit oneself to the particular forms disclosed. Rather, all modifications, equivalents, and substitutions falling within the scope of the appended claims should be included. Where appropriate, elements of the exemplary embodiments are consistently designated by the same reference numerals throughout the drawings and detailed description.

[0029] The terminology used herein to describe embodiments is not intended to limit the scope. The articles “a,” “an,” and “the” are singular forms because they refer to a single object, but their use in this document should not preclude the existence of more than one object of reference. In other words, the number of elements referenced in the singular form can be one or more, unless the context explicitly indicates otherwise. It will be further understood that the term “comprises / comprising / includes / including” as used herein specifies the presence of the stated features, items, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, items, steps, operations, elements, components, and / or groups thereof.

[0030] The term "design" in this document encompasses data describing microdevices, such as integrated circuit devices or system-on-a-chip (SoC) devices. However, "design" can also refer to, for example, a single layer or a portion of a layer of an integrated circuit device. The term "cell" or "logic cell" in this document refers to the logic circuitry within a design. "Input mode" or "excitation" includes the input signal to a cell, where the signal includes the input value for each input pin of the cell. The term "cell library" refers to a collection of logic cells used in a design. "Cell instance" refers to a specific instance of a logic cell in an actual integrated circuit. "Propagation delay" is a measurement of the time it takes for a change in the input value at a target input pin of a cell to propagate to a target output pin of the cell.

[0031] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall be interpreted in accordance with the conventions of the field. It will be further understood that commonly used terms should also be interpreted in accordance with the conventions of the relevant field, rather than in an idealized or overly formal sense, unless explicitly defined herein.

[0032] The method and system described in this paper provide a approach to test generation for timing-related defects, termed Timing Verification Test Generation. Timing Verification Test Generation offers versatility, allowing the ATPG tool to target delay defects via the longest path, considering cell and interconnect delays at different PVT corners and aging effects (collectively referred to herein as PVTA combinations) under single-input switching (SIS) or multiple-input switching (MIS) conditions. This versatility ensures that the timing of the critical path is tested under all conditions.

[0033] The timing verification test generation has several components. Characterization is performed on the library cells used for the design under different operating conditions and aging effects. For each cell, the cell characterization process exhaustively analyzes all two-cycle input stimuli to find the stimuli that can propagate the transition through the cell and their propagation delays. This ensures that timing information is available to support test generation with the maximum path delay.

[0034] The library characterizes the database and combines it with timing information obtained from a second timing information source, such as a Standard Delay Format (SDF) file. An SDF file is a data file that includes timing information specific to the design. The SDF file provides the timing behavior of cell instances used in the design, as well as interconnect delays. In an SDF, two instances of the same cell can have different timing information, depending on design characteristics such as load capacitance. However, an SDF only considers single-input switching when characterizing delays. It does not consider the case where multiple inputs of a cell switch together within the same clock cycle.

[0035] Users who generate timing verification tests have the freedom to obtain one or more SDF files suitable for their applications. SDF files can be generated corresponding to each PVT corner. The process for generating timing verification tests enhances the SDF data by utilizing timing information obtained through performing cell-level delay characterization against the standard cell library used in the design. The combined database includes timing information for cases where multiple inputs switch simultaneously, as well as the effects of operating conditions and aging.

[0036] In timing verification test generation, latency calculations are applied using a combined timing database to extract the path with the maximum latency. The path extraction process begins with two-cycle cell-aware defects (referred to as cell-aware test dual-timeframes or CAT-2TF defects). The CAT-2TF defect model is a model of latency defects occurring in silicon, based on actual defects occurring inside transistors within a standard cell. For each CAT-2TF defect, the longest path is obtained, through which the CAT-2TF defect can be detected. This creates a superset of path latency faults, from which a subset including the longest path is selected for test generation.

[0037] Given the longest path associated with a CAT-2TF defect, a test cube is first generated using a conventional test generation process to satisfy the basic propagation conditions for path-delay faults. The test cube includes a partially specified input vector, where the specified values ​​are sufficient to detect a particular fault or set of faults. Then, the test cube is expanded into one or more tests that maximize the path delay under different conditions using a time-series database. This is an optimization process involving satisfying additional propagation conditions for the cells along the path. The process prioritizes the cells that contribute the most to the path delay and their input stimuli.

[0038] The method described in this paper can be used to apply tests generated by the timing verification ATPG in addition to the conventional two-cycle mode. This enables the evaluation of the impact of timing verification testing on the detection of additional timing-related defects that may be missed from other manufacturing tests.

[0039] Unit library representation

[0040] Based on the example described herein, library characterization is performed on each cell in the cell library to determine the propagation delay. In the first step, all valid two-cycle stimuli are identified for the target input / output pins of the cell. Two-cycle stimuli consist of two input modes to the cell. A stimulus is considered valid if it satisfies both of the following conditions with respect to the target input and output pins: • Observation conditions: There must be a change at the target output pin. • Propagation condition: A transition from the target input pin must propagate to the output pin without being masked by transitions from any other input value.

[0041] In this paper, the target input pin is referred to as the on-path input, and other input pins are referred to as the off-path input.

[0042] Effective stimuli are classified into two types: Single-Input Switching (SIS) and Multiple-Input Switching (MIS). • SIS (Single-Input Switching): Only inputs on the path carry the transition. Inputs outside the path retain a constant logic value. For single-path and primitive gate types (such as AND / NAND gates, OR / NOR gates), the constant logic value is the same as its non-controllable value. For complex units (such as AND-OR-NOT gates or XOR / XNOR gates), there is no fixed non-controllable value, and the constant logic value changes with the stimulus. • MIS (Multiple Input Switching): Inputs outside the path also carry transitions while satisfying the propagation condition. To check if the propagation condition is satisfied, inputs on the path retain their initial values, while other inputs are allowed to transition. If the output does not transition until the inputs on the path change, the propagation condition is satisfied.

[0043] Figure 1 This is a circuit diagram showing a logic unit 100 according to an example. Unit 100 is an AND gate with three input pins 110, 120, and 130 and a single output pin 140. An input pattern including the input value of each of the input pins 110, 120, and 130 can be applied to unit 100, and an output signal can be observed at the output pin 140. Figure 1 In the example shown, input pin 110 is an input on the path, and output pin 140 is an output on the path. Input pins 120 and 130 are external inputs.

[0044] Table I below illustrates the effective two-cycle MIS excitation for cell 100. In Table I, the first row shows the values ​​in the first cycle (referred to herein as the start-up cycle), and the third row shows the values ​​in the second cycle (referred to herein as the capture cycle). The second row shows the values ​​when the external inputs 120 and 130 have changed but the input 110 on the path has not yet changed. A rising transition at the input 110 on the path completes the transition at the output 140. In other words, rising transitions at the external inputs 120 and 130 do not affect the propagation path from the input 110 on the path to the output 140. Table I

[0045] exist Figure 1In the example shown, the propagation condition will not be satisfied when the input signals to inputs 110, 120, and 130 undergo a descent transition. In this case, after inputs 120 and 130 change, output 140 transitions, and the change in input 110 along the path will not propagate to output 140.

[0046] Figure 2 A flowchart of a method 200 for determining propagation delay in a cell is shown. Method 200 can be repeated for each input / output pin pair, treating each pair as an input and output on a path. Method 200 can be implemented in conjunction with other methods and systems described herein.

[0047] In block 210, method 200 includes identifying input pins and output pins as inputs and outputs on a path. In block 220, the method includes evaluating a model of a logic unit for each pair of input patterns from a set including input pattern pairs. The model may be a circuit representation as an analog circuit simulation model. Each input pattern includes an input value for each input pin. The evaluation includes: evaluating the logic unit based on a first input pattern in a first cycle of two cycles; and evaluating the logic unit based on a second input pattern in the pair of input patterns in a second cycle of two cycles.

[0048] In box 230, the method includes identifying a subset of the input pattern set. For each pair in this subset, the output value for the output on the path transitions from a first value at the start of the first cycle to a second value at the end of the second cycle, the second value being different from the first value, thus satisfying the observation condition. Furthermore, for each pair in this subset, the transition of the input value for the input on the path from the first value to a second value different from the first value is propagated to the output on the path during either the first or second cycle, such that the output value at the end of the second cycle depends on the transition of that input value. Therefore, for each pair in the identified subset, the propagation condition is satisfied.

[0049] In box 240, the method includes determining a propagation delay for each pair of input patterns in a subset. The propagation delay can be calculated using SPICE software or similar software. Method 200 can be repeated for both rising and falling transitions of the inputs along the path.

[0050] The maximum propagation delay of the effective two-cycle excitation for a cell can be determined by calculating the propagation delay according to method 200. This method can be applied to each cell in the cell library to obtain a complete library characterization.

[0051] Figure 3 A circuit diagram of logic unit 300 according to the example is shown. Figure 3The illustrated unit 300 is an AND-OR-NOT gate, comprising two two-input AND gates 310 and 320, followed by a NOR gate 330. Figure 3 In the diagram, the input on the path is input pin 340 of AND gate 310. The remaining input pins 350, 360, and 370 are inputs outside the path, and a single output pin 380 is the output on the path.

[0052] Table II below shows all activators with a descent transition propagating from input 340 to output 380 on the path, sorted from maximum to minimum propagation delay. In Table II, the propagation delay is normalized based on the minimum delay. Each activation in the second column of Table II is formatted as follows: <abcd>This indicates that each of A, B, C, and D corresponds to input pins 340, 350, 360, and 370, and each of A, B, C, and D is F for a falling transition and R or a constant 0 / 1 value for a rising transition. Table II

[0053] MIS Incentives <f1rf>The maximum propagation delay introduced and SIS incentives <f100>The minimum case is 40% longer. Different SIS stimuli also show significant differences in latency; for example, the fourth-ranked SIS stimuli... <f101>This can introduce approximately 35% more delay than the minimum delay. The results indicate that timing information associated with MIS excitation should not be ignored, and relying on SIS information may not result in the maximum path delay.

[0054] In further testing, the maximum propagation delay d for any stimulus was measured for all NOR elements, all AND-OR-NOT elements, and all AND-OR elements in a commercially available library of cells. max With minimum propagation delay d for any stimulus min percentage difference between p diff Considering all possible stimuli and the inputs and outputs along the path, in the NOR element, it is observed that the MIS stimulus causes the maximum propagation delay in 80% of cases, and for the NOR element, the maximum... p diff The value is 5%. In AND-OR-NOT and AND-OR elements, the MIS excitation causes the maximum propagation delay in 81% of cases, and the maximum... p diff The figure is 60%. In addition, in AND-OR-NOT and AND-OR-NOT cells, approximately 30% of the MIS excitations cause propagation delays that are 10% or more longer than the minimum delay.

[0055] Considering all library characterization results, two trends were observed: First, the maximum delay difference is larger for more complex cells. Second, in most cases, MIS excitation leads to the maximum propagation delay.

[0056] Method 200 can be repeated for each cell in the cell library to obtain a library characterization. However, the timing information is the same for each instance of a cell in the actual design. The SDF file provides timing information for cell instances in the design. Instances of the same cell library may have different timing information in the SDF file based on characteristics that vary from instance to instance (such as load capacitance and drive strength). However, the SDF file used for the design has equal delays for different SIS excitations associated with the inputs and outputs on the same path as the instance. Furthermore, as mentioned earlier, the SDF file does not include MIS excitations.

[0057] Figure 4 This is a block diagram illustrating method 400 for generating a combined database. The combined database utilizes both instance-dependent information from SDF files and extensive data provided by the cell library representation. For each instance, all stimuli from both sources are considered. Method 400 can be used in conjunction with other methods described herein, particularly method 200.

[0058] In box 410, method 400 includes accessing a cell library comprising multiple cells for a design. In box 420, method 400 includes determining a propagation delay for each pair of input and output pins for each cell in the cell library. According to the example, the propagation delay can be determined using the previously described method 200. In box 430, method 400 includes accessing a Standard Delay Format (SDF) file comprising timing information for each instance of each cell. In box 440, method 400 includes combining the timing information from the SDF and the propagation delay for the cell to obtain a combined database. According to the example, combining the timing information and the propagation delay includes adjusting the propagation delay based on the timing information to obtain the propagation delay for the cell instance.

[0059] In some examples, a timing information value from the timing information values ​​in the SDF file can be used as a baseline, and the propagation delay from the library characterization is adjusted to the SDF baseline. When multiple SDF files are provided to cover different PVTA combinations, the adjustment can be repeated for each combination. This will work in cases where there is no aging effect. In cases where there is an aging effect in the PVT combination, the SDF file corresponding to that PVT corner can be used, and the cell characterization data for the PVTA combination can be combined with the data from the SDF file.

[0060] As in the example, the inputs and outputs on each path of the cell are considered separately for tuning. Considering the propagation delays obtained from the cell characterization, all SIS and MIS stimuli are sorted from maximum to minimum propagation delays: d 0 , d 1 , d 2 ... d n-1 Let the minimum SIS delay be... d i Considering the SDF file, let the corresponding delay for the same SIS stimulus be... r 0 When the minimum SIS stimulus is added to the SDF data, its latency is reduced. r 0 / d i And thus, adjustments are made. The same adjustments can be applied to all stimuli. Therefore, d j Replaced with d j r 0 / d i .

[0061] Table III below illustrates the requirements for three-input AND units (such as...) Figure 1 The adjustment shown is for unit 100, with input 110 and output 140 on the path. The first column of Table III is an index for the different stimuli considered. The second column indicates the stimuli. The third column indicates the stimuli type, SIS or MIS. The fourth column provides the propagation delay (in arbitrary units) from the library representation. The fifth column includes the adjusted delay. Table III

[0062] The third stimulus is the only SIS stimulus and is selected as the baseline SIS stimulus for performing delay adjustment. The timing information for the SIS stimulus obtained from the SDF file is... r 0 .against 1 ≤ j ≤ 4 , No. j The adjusted delay of the incentive is d j r 0 / d i The adjusted delay of the third incentive equals r 0 (Values ​​from the SDF file), and all other delays are adjusted based on the delay ratio.

[0063] Longest path extraction

[0064] Figure 5 A block diagram of a method 500 for extracting a path with the longest delay time through an integrated circuit is shown. Method 500 can be used in conjunction with other methods and systems described herein.

[0065] In box 510, method 500 includes obtaining a dataset for the integrated circuit. This dataset includes the maximum arrival time and maximum propagation delay for each pin in the integrated circuit, and is generated based on static path delay calculations using data from a combined database (i.e., maximum propagation delay data for each cell obtained from evaluations of two-cycle input stimuli for each cell). The static path delay can be determined by adding the maximum propagation delay for each cell in the design to the interconnect delay for the lines along the path. This calculation does not attempt to justify any value. Using the combined database, it uses stimuli with the maximum propagation delay for each cell without checking whether these stimuli can be justified.

[0066] In block 520, method 500 includes selecting a logic cell in an integrated circuit. In block 530, method 500 includes identifying the longest reach path from a starting point in the integrated circuit to the output pin O of the selected logic cell based on a dataset. The starting point can be a main input or a scan cell of the integrated circuit.

[0067] In the example, identifying the longest reach path from output pin O includes: identifying the path from output pin O to input pin I1 of the selected logic unit, which a) makes the value Maximize, where It is the maximum propagation time of the input pin I. From I 1 The maximum propagation delay to O, and b) are associated with the transition on output O. After selecting an input pin, the output pin that drives it is identified, and the process is repeated for the logic cell associated with that output pin. This is repeated until the scan cell or main input is reached.

[0068] In block 540, method 500 includes identifying the longest propagation path from the input pin I of the selected logic cell to an endpoint in the integrated circuit. The endpoint may be the main output or a scan cell of the integrated circuit.

[0069] In the example, identifying the longest propagation path from input pin I includes: identifying the path from input pin I to the output pin O1 of the selected logic unit, which a) makes the magnitude Maximize, where It is an input pin. I Maximum propagation time From I The maximum propagation delay to O1, and b) the output O1 is associated with the transition on input I. After identifying the output pins that meet these conditions, repeat the process until the scan cell or main output is reached. Depending on the cell type of the instance, both rising and falling transitions can be considered for the output to maximize the propagation delay.

[0070] In box 550, the longest path through the selected logical unit is extracted based on the identified longest arrival path and longest propagation path.

[0071] Timing verification test generation

[0072] Figure 6 This is a block diagram of a method for generating timing verification tests based on an example. Method 600 can be implemented in conjunction with other methods and systems described herein. Method 600 depicts the generation of timing verification tests for a single PVTA combination. In block 610, method 600 includes obtaining a design for an integrated circuit. In block 620, method 600 includes obtaining a database of combinations of propagation delays for each instance of each cell in a cell library for the design, for example using method 400 previously described. In block 630, based on the database of combinations, the static path delay for each pin in the design is determined from the maximum arrival time of the pin and the propagation delay from the pin. In block 640, CAT-2TF defects with a relaxation amount below a user-defined threshold are identified and stored in a list. The relaxation amount refers to the difference between the actual clock cycle and the path propagation delay. In block 650, for example using method 500 previously described, the longest path through each CAT-2TF defect in the list is extracted. In some cases, two different CAT-2TF defects in the list may result in the same longest path. To avoid duplicate paths in the extracted path set, each newly extracted path can be compared with previously extracted paths, and the path can be checked to determine if it has already been extracted. This check can be accelerated by associating each path with a unique numerical identifier. In box 660, timing verification ATPG is applied to each extracted path for the CAT-2TF defect.

[0073] The temporal verification ATPG can be applied to each extracted path for the CAT-2TF defect. Given a path... p The path delay ATPG framework is derived by targeting p The assignments required for the strong non-robust test begin. These assignments include transitions at the path source and non-control values ​​on the inputs outside each path during the second clock cycle of the test. p The assignment set is represented as A(p) Using path-delayed ATPG to generate [something] that satisfies [the desired outcome]. A(p) Assignment p The test cube is generated. Once the test cube is generated, arrival time analysis can be performed for inputs on and off the path to determine whether only SIS stimulation is needed for each cell, or both SIS and MIS stimulation are required. An optimization process is then applied to maximize the path delay. Based on the path... p Use the unit to specify additional values, path p Inputs outside the path have unspecified values.

[0074] For each unit, find the match A(p) The assignments in the list are consistent with the stimuli from the combined time-series database. The stimuli are sorted in descending order of their contribution to path delay. Considering the stimuli in this order, the stimuli at the top of the list are added to the list. A (p) And the test generation attempt is based on A(p) Generate a new test cube.

[0075] Figure 7 The path through circuit 700 according to the example is depicted. p Circuit 700 includes a two-input OR gate 710, a two-input NAND gate 720, and a two-three-input AND gate 730. Path p Indicated by the arrow. Figure 7 The path was described p The transition at the source and the non-control values ​​on the inputs outside the path during each of the second clock cycles. Satisfying these assignments leaves unspecified values ​​on the inputs outside the paths of OR gate 710 and AND gate 730, such as Figure 7 The variable X indicates this. This determines the path. p Possible assignment set A (p) With assignment set A(p) The cell excitations with consistent assignments are depicted in Table IV below. For each cell, the excitations in Table IV are shown in descending order of delay in the fourth column. Table IV

[0076] Even if the unspecified value is filled in randomly, cell 730 will still have a delay of 6 units— A(p) Consistent minimum delay. In Table IV, the fifth column indicates the minimum delay for each cell. A(p) Additional delays beyond the consistent minimum delay. Table V below shows the results of reordering Table IV based on the additional delays indicated in column 5 of Table IV. Table V

[0077] During test generation, stimuli are sorted according to the order in Table V. Therefore, additional adjustments first consider inputs outside the path of unit 730 for possible MIS stimuli. <rrr>Then consider incentives. <ff>or cell 710.

[0078] As new test cubes are computed and A(p) updated, stimuli consistent with A(p) are found and sorted. Backtracking limits are used for each stimulus and each cell to limit the running time. When the list of stimuli consistent with A(p) is empty and has not been considered, test generation terminates.

[0079] Figure 8 FIG. depicts a method 800 for timing verification ATPG according to an example. Method 800 can be used in combination with other methods and systems described herein. At block 810, method 800 includes deriving an assignment set for performing a strong non-robust test for a path p . At block 820, method 800 includes generating a test cube for A(p) . If a test cube for A(p) cannot be generated, method 800 terminates. Let A(p) represent the set of stimuli consistent with S . At block 830, method 800 includes identifying, for each cell, the stimulus A(p) in S with the minimum delay s 0 , and for each stimulus S for that cell in s i , determining the difference s i between the stimulus s 0 and x i . At block 840, method 800 includes sorting the stimuli in S based on the determined differences. At block 850, method 800 includes repeating until the set S is empty: a) selecting the stimulus S at the top of s i and removing S from s i , b) adding s i to A(p) , and c) generating a new test cube for A(p) . If a new test cube is generated, all stimuli conflicting with S are removed from A(p) . Otherwise, A(p) is removed from s i . When method 800 ends, the resulting test cube is for the path p The new test cube.

[0080] Figures 6 to 8 The timing verification test generation process described herein can be repeated for multiple PVTA combinations of the design to create a superset of timing verification test patterns, thereby enabling more comprehensive testing of the design. Each PVTA combination requires a separate SDF file and a library representation executed for that combination. Some patterns can be shared between different PVTA combinations. When the DUT (Device Under Test) is subjected to a specific PVTA combination on the ATE (Automatic Test Equipment), the corresponding subset of timing verification test patterns is applied to detect defects that may have been missed from other PVTA combinations.

[0081] The method described in this paper can be combined with other manufacturing tests and unit-aware tests. Defects detected by timing verification tests are unique and cannot be detected by other tests. Units that fail timing verification tests can be analyzed for diagnostic purposes to determine the cause of failure.

[0082] Figure 9 An example of a data processing system that can implement embodiments of the present disclosure is illustrated, such as a method for performing embodiments of the invention described herein. The data processing system 900 includes a processor 910 connected to a local system bus 920. The local system bus connects the processor to main memory 930 and a graphics display adapter 940, which can be connected to a display 950. The data processing system can communicate with other systems via a wireless user interface adapter connected to the local system bus 920 or via a wired network (e.g., connection to a local area network). Additional memory 960 may also be connected via the local system bus 920.

[0083] Appropriate adapters for other peripheral devices (such as the wireless user interface adapter 970), such as the keyboard 980 and mouse 990, or other pointing devices, allow the user to provide input to the data processing system. Other peripheral devices may include one or more I / O controllers, such as U... S B controller, Bluetooth controller, and / or dedicated audio controller (connected to speakers and / or microphones). It should also be understood that various peripheral devices can be connected to the U... S B controller (via various U) S Port B includes input devices (such as keyboards, mice, touchscreens, trackballs, cameras, microphones, scanners), output devices (such as printers, speakers), or any other type of device operable to provide input or receive output from a data processing system.

[0084] Furthermore, it should be understood that many devices referred to as input or output devices can both provide input and receive output for communication with the data processing system. Additionally, it should be understood that other peripheral hardware connected to the I / O controller can include any type of device, machine, or component configured to communicate with the data processing system.

[0085] The operating system included in the data processing system enables the output from the system to be displayed to the user on a monitor and allows the user to interact with the system. Examples of operating systems that can be used in a data processing system include Microsoft Windows™, Linux™, UNIX™, iOS™, and Android™ operating systems.

[0086] Furthermore, it should be understood that the data processing system 900 can be implemented in a network environment, a distributed system environment, a virtual machine in a virtual machine architecture, and / or a cloud environment. For example, the processor and associated components may correspond to a virtual machine executing in a virtual machine environment on one or more servers. Examples of virtual machine architectures include VMware ESCi, Microsoft Hyper-V, Xen, and KVM.

[0087] Those skilled in the art will understand that the hardware depicted for the data processing system 900 can vary for particular implementations. For example, the data processing system 900 in this example may correspond to a computer, workstation, and / or server. However, it should be understood that the data processing system of alternative embodiments may be configured with corresponding or alternative components, such as a mobile phone, tablet computer, controller board, or any other system operable to process data and perform the functions and features discussed herein associated with the operation of the data processing system, computer, processor, and / or controller. The examples depicted are provided for illustrative purposes only and are not intended to imply any architectural limitations with respect to this disclosure.

[0088] Data processing system 900 may be connected to a network (not part of data processing system 900), which may be any public or private data processing system network or combination of networks, including the Internet, as known to those skilled in the art. Data processing system 900 may communicate with one or more other data processing systems (such as servers, also not part of data processing system 900) via the network. However, alternative data processing systems may correspond to multiple data processing systems implemented as part of a distributed system, wherein processors associated with multiple data processing systems may communicate via one or more network connections and may collectively perform tasks described as being performed by a single data processing system. Therefore, it should be understood that, when referring to a data processing system, such a system may be implemented across multiple data processing systems organized in a distributed system that communicates with each other via a network.

[0089] The data processing system 900 is adapted to perform methods according to the embodiments described herein. For example, a keyboard 980 and a mouse 990 may be used as user input devices for receiving information from a user, a processor 910 may be adapted to perform the steps of the method, and a display 950 may be adapted to display a specific view to the user. Computer products including instructions may be provided that, when run on a computer such as the data processing system 900, cause the computer to perform the steps of the methods of the embodiments of the present invention described above.

[0090] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus, and systems as examples of those described herein. Although the flowcharts above illustrate a specific order of execution, the order of execution may differ from the order depicted. Boxes described in one flowchart may be combined with boxes from another flowchart. In some examples, some boxes in the flowcharts may not be necessary, and / or additional boxes may be added.

[0091] This invention can be embodied in other specific devices and / or methods. The described embodiments should be considered illustrative rather than restrictive in all respects. In particular, the scope of the invention is indicated by the appended claims rather than by the description and drawings herein. All variations falling within the meaning and scope of equivalents of the claims should be included within their scope.< / ff> < / rrr> < / abcd>

Claims

1. A computer-implemented method for extracting a path having the longest delay time through an integrated circuit, the method comprising: a) Obtain a dataset for the integrated circuit, the dataset including the maximum arrival time and maximum propagation delay for each pin in the integrated circuit; b) Select the logic unit in the integrated circuit; c) Based on the dataset, identify the longest reach path from the starting point in the integrated circuit to the output pin O of the selected logic unit; d) Identify the longest propagation path from the input pin I of the selected logic unit to the endpoint in the integrated circuit; and e) Based on the identified longest arrival path and longest propagation path, extract the longest path through the selected logical unit. Wherein, for each logic unit, the maximum arrival time and maximum propagation delay for each pin of the logic unit are determined based on an evaluation of the logic unit for each two-cycle stimulus in a two-cycle stimulus set.

2. The method according to claim 1, comprising: For each input and output pin of the selected logic unit, repeat steps c) through e).

3. The method according to claim 1, comprising: Select one or more additional logic units, and repeat steps c) through e) for each input and output pin of each of the additionally selected logic units.

4. The method of claim 1, wherein identifying the longest reach path from the output pin O comprises: Identify the path from the output pin O to the input pin I1 of the selected logic unit, the path causing the value... Maximize, where It is the input pin I 1 The maximum arrival time, From I 1 The maximum propagation delay to O.

5. The method of claim 4, wherein identifying the longest reach path from the starting point to the output pin of the selected logic unit comprises iteratively: a) Identification Output O i and drive the previous input pin I on the path t-1 The logical units, and b) Identify the subsequent input pins of the identified logic unit. I i The subsequent input pin I i Make the quantity value Maximize, where It is the input pin I i The maximum arrival time, From I i To O i The maximum propagation delay.

6. The method of claim 1, wherein identifying the longest propagation path from the input pin I comprises: Identify the path from the input pin I to the output pin O1 of the selected logic unit, the path being a magnitude Maximize, where It is the input pin I The maximum propagation time, From I The maximum propagation delay to O1.

7. The method of claim 6, wherein identifying the longest propagation path from the input pin I comprises iteratively: a) Identify input pins I i and the previous output pin on the path O i-1 The driven logic unit, and b) Identify the subsequent output pins of the identified logic unit. O i The subsequent output pin O i Make the quantity value Maximize, where It is the input pin I i The maximum propagation time; and From I i arrive O i The maximum propagation delay.

8. The method of claim 1, wherein obtaining the dataset comprises: Access the cell library that includes the logic cells of the integrated circuit. Based on the evaluation of the excitation for two-cycle single-input switching and multi-input switching, the propagation delay for each pair of input pins and output pins of each logic cell in the cell library is determined.

9. The method of claim 8, comprising: Access a stored data file, the data file including interconnect delay information and timing information for instances of logic cells in the integrated circuit; as well as Based on the timing information, the propagation delay of each input pin and output pin of the logic unit is adjusted to obtain the propagation delay of each input pin and output pin of the instance.

10. The method of claim 1, wherein determining the maximum propagation delay and arrival time for each pin comprises: Determine the static path delay for each path through the pin.

11. A computer-implemented method, comprising: Obtain the design for the integrated circuit; Identify one or more CAT-2TF defects with a relaxation amount below a predefined threshold; as well as For each identified CAT-2TF defect, the method according to claim 1 is applied to extract one or more longest paths through the CAT-2TF defect.

12. The method of claim 11, comprising: For each of the one or more identified CAT-2TF defects, a test cube is generated based on the one or more longest paths extracted through the CAT-2TF defect.

13. The method of claim 12, wherein generating the test cube comprises: Determine what is used for targeting p Assignment set for performing strong non-robust tests A(p) ; Generate targeting A(p) The initial test cube; Logo and A(p) Consistent incentive set S ; For the path p Each cell on the array identifies the excitation with the minimum delay. s 0 ; For each excitation of the unit s i Determine incentives s i and s 0 The differences between them; as well as Based on the determined differences, the set S Sort them.

14. The method of claim 13, further comprising: Based on the incentive set S The sorting identifies the incentive with the greatest difference. s ; From the stimulus set S Remove the incentive s ; The incentive s Add to the assignment set A(p) middle; as well as Generate targeting A(p) The modified test cube.

15. A data processing system comprising a processor and a memory, the memory including instructions that, when executed by the processor, cause the processor to perform the method according to any one of claims 1 to 14.

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