Improving management of memory module buffers by coordinating cpu caches

Abstract

In some examples, a method for regulating operations between a central processing unit (CPU) cache and a buffer of a memory module of a device includes the memory module placing a memory block including a plurality of cache lines for the device in a buffer of the memory module, the memory module querying the CPU cache for a plurality of modified cache lines associated with the memory block, and updating the plurality of cache lines in the memory block based on the obtained plurality of modified cache lines, wherein the querying occurs prior to evicting the memory block from the buffer of the memory module of the device and / or writing back the memory block.

Description

Technical Field

[0001] This disclosure generally relates to the operation between the central processing unit (CPU) cache and the memory module buffers of a device. Various aspects of this disclosure relate to improving the management of memory module buffers by coordinating the CPU cache. Background Technology

[0002] Modern computers are characterized by multiple memory modules, which are typically based on different media (e.g., DRAM, PCM, 3D XPoint, MRAM, ReRAM). These memory modules are either directly attached to the CPU's memory controller or provided as separate devices and connected to the computer via a fast interconnect (e.g., based on the Compute Fast Interconnect (CXL) standard). Access to memory is performed through memory read and write operations issued by the CPU's memory controller. Data moves between memory and the CPU's cache in blocks called cache lines, which are typically 64 bits (B) in size.

[0003] Some computer memory modules feature fast onboard buffers (or caches) to speed up access to the media (which can be much slower than dynamic random access memory (DRAM)). For example, the 3DXPoint-based Intel® Optane™ DC persistent memory module (PMM) features a 16 kilobyte (kB) buffer for each memory module (Dual In-line Memory Module, DIMM). These buffers are managed by a separate memory controller (called MMC) located on the memory module itself and are transparent to the computer's CPU and its cache controller.

[0004] Fast buffers located on the memory module help reduce memory access latency because computer programs often exhibit temporal and spatial locality in memory access patterns. Therefore, the cost of accessing slow memory media can be amortized over multiple read operations. Similarly, multiple write operations can be combined into a buffer, thus avoiding a costly write operation to the media for every write operation issued by the CPU memory controller to the memory module.

[0005] Due to technical reasons, access to memory media is sometimes performed in blocks (called Error Correcting Code (ECC) blocks), which are larger than a single cache line. For example, the Intel® Optane™ DC PMM internally uses 256-byte blocks, which are four times the size of a typical cache line. Some future memory expansion cards from various manufacturers (such as Samsung, Panasonic, and HP) will also internally use ECC blocks larger than 64 bytes (e.g., 128-byte, 256-byte, 512-byte, etc.). In such cases, a buffer located on the memory module helps the MMC handle smaller, cache-line-sized read and write operations. For this purpose, the buffer stores the entire ECC block but allows the MMC to read and write portions of the ECC block, corresponding to a single cache line.

[0006] The overall cost of memory access (e.g., expressed in terms of latency and bandwidth) depends heavily on the relative speed of read / write operations to the buffer and memory medium, the size of the buffer, the buffer eviction policy (i.e., which ECC blocks should be evicted from the memory medium to make room in the buffer for the ECC blocks needed to serve the upcoming read or write operation), and the memory access pattern (which is typically application-dependent).

[0007] Specifically, random memory access patterns involving reads and writes spread across very different memory locations are problematic because they cause high read and write amplification on the memory medium: To serve a read of a single cache line, the entire ECC block needs to be read from the memory medium and placed in the buffer. To handle writes to a single cache line, the entire ECC block needs to be read from memory, placed in a buffer, and partially modified according to the write operation. Each ECC block in the buffer is rarely reused to serve later read / write operations.

[0008] High read and write amplification not only significantly reduces available memory bandwidth but also increases memory access latency. In the case of some storage media with lower write endurance compared to DRAM (such as phase-change memory (PCM)), high write amplification leads to increased wear of the memory media and thus shortens the lifespan of the memory module. Summary of the Invention

[0009] The purpose of this disclosure is to improve the management of memory module buffers by coordinating the CPU cache.

[0010] The above and other objectives are achieved through the features of the independent claims.

[0011] Other implementations are obvious from the dependent claims, the specification and the drawings.

[0012] A first aspect of this disclosure provides a method for regulating operations between a central processing unit (CPU) cache and a buffer of a memory module of a device, the method comprising: the memory module placing a memory block comprising a plurality of cache lines for the device in the buffer of the memory module; the memory module querying the CPU cache to obtain a plurality of modified cache lines associated with the memory block; and updating the plurality of cache lines in the memory block based on the obtained plurality of modified cache lines, wherein the query occurs before the memory block is evicted from the buffer of the memory module of the device and / or written back to the memory block.

[0013] Importantly, it can improve the utilization of memory read / write bandwidth, thereby improving performance. Furthermore, by reducing the number of operations, it can reduce memory media wear, as memory media wear is closely related to the memory write bandwidth utilized. Finally, this invention provides a way to reduce the latency of evicting certain cache lines from the CPU, thereby further improving application performance.

[0014] The method may further include: performing operations on multiple cache lines in the CPU cache using the CPU cache to obtain the multiple modified cache lines, wherein the multiple cache lines in the CPU cache are associated with the memory block.

[0015] In response to performing the operation on the plurality of cache lines in the CPU cache using the CPU cache, the method may further include: the CPU cache changing the state of the plurality of cache lines in the CPU cache to indicate that the plurality of cache lines in the CPU cache have been modified.

[0016] In response to the memory module detecting a change in the state of the plurality of cache lines in the CPU cache, the method may further include: the memory module issuing a request to retrieve the plurality of modified cache lines from the CPU cache.

[0017] The method may further include: the memory module assigning a unique state to a portion of the plurality of cache lines included in the memory block in the memory module's buffer, wherein the unique state is used only by the memory module and not by the CPU cache, wherein the unique state indicates that the state of a portion of the plurality of cache lines is unknown to the memory module; communicating with the CPU cache to determine the current state of each of the plurality of modified cache lines in the CPU cache; and the memory module changing the corresponding state of those cache lines corresponding to the plurality of modified cache lines from the unique state based on the current state of each of the plurality of modified cache lines.

[0018] The method may further include: before evicting the memory block from the buffer of the memory module and / or writing back the memory block, the memory module queries the CPU cache to determine the current state of those cache lines whose state has not changed from the unique state.

[0019] A second aspect of this disclosure provides an apparatus comprising: a memory module including a buffer and a plurality of memory blocks; and a central processing unit (CPU) cache, wherein the memory module is arranged to: place the memory blocks, including a plurality of cache lines for the apparatus, in the buffer of the memory module; query the CPU cache to obtain a plurality of modified cache lines associated with the memory blocks; and update the plurality of cache lines in the memory blocks based on the obtained plurality of modified cache lines, wherein the query occurs before the memory blocks are evicted from the buffer of the memory module of the apparatus and / or written back to the memory blocks.

[0020] The CPU cache can also be configured to perform operations on multiple cache lines in the CPU cache to obtain the multiple modified cache lines, wherein the multiple cache lines in the CPU cache are associated with the memory block.

[0021] The CPU cache may also be configured to: in response to performing the operation on the plurality of cache lines in the CPU cache, change the state of the plurality of cache lines to indicate that the plurality of cache lines have been modified.

[0022] The memory module can also be configured to: detect changes in the state of the plurality of cache lines in the CPU cache, and issue a request to retrieve the plurality of modified cache lines from the CPU cache.

[0023] The memory module may also be configured to: allocate a unique state to a subset of cache lines among the plurality of cache lines included in the memory block within the memory module's buffer, wherein the unique state is used only by the memory module and not by the CPU cache, wherein the unique state indicates that the state of a subset of cache lines among the plurality of cache lines is unknown to the memory module; communicate with the CPU cache to determine the current state of each of the plurality of modified cache lines in the CPU cache; and, based on the current state of each of the plurality of modified cache lines, change the corresponding state of those cache lines among the plurality of cache lines that correspond to the plurality of modified cache lines from the unique state.

[0024] The memory module may also be configured to: query the CPU cache to determine the current state of those cache lines whose state has not changed from the unique state before evicting the memory block from the buffer of the memory module and / or writing back the memory block.

[0025] A third aspect of this disclosure provides a computer-readable storage medium including computer program code accessible by a device including a processor to provide instructions and / or data to the device, the computer program code being configured to cause the device, via the processor, to: place a memory block comprising a plurality of cache lines for the device in a buffer of the memory module; query the CPU cache via the memory module to obtain a plurality of modified cache lines associated with the memory block; and update the plurality of cache lines in the memory block based on the obtained plurality of modified cache lines, wherein the query occurs before the memory block is evicted from the buffer of the memory module of the device and / or written back to the memory block.

[0026] The computer-readable storage medium may further include computer program code for causing the device, via the processor, to: perform operations on a plurality of cache lines in the CPU cache using the CPU cache, thereby obtaining the plurality of modified cache lines, wherein the plurality of cache lines in the CPU cache are associated with the memory block.

[0027] The computer-readable storage medium may further include computer program code for causing the device, via the processor, to: perform the operation on the plurality of cache lines in the CPU cache using the CPU cache, thereby changing the state of the plurality of cache lines in the CPU cache to indicate that the plurality of cache lines in the CPU cache have been modified.

[0028] The above and other aspects of the invention will become apparent from the embodiments described below. Attached Figure Description

[0029] To make the invention easier to understand, embodiments of the invention will now be described by way of example with reference to the accompanying drawings, in which: Figures 1a to 1m It is a step-by-step description of the read-modify-write operation based on existing technology; Figure 2 It is a flowchart of a method for adjusting the operation between the CPU cache and the buffer of the memory module of the device, based on an example; Figures 3a to 3g It is a step-by-step description based on the example's read-modify-write operations; Figure 4 It is a schematic depiction of example communication between the CPU and memory modules; Figure 5 It is a schematic depiction of example communication between the CPU and memory module, based on another example; Figure 6 It is a schematic depiction of example communication between the CPU and memory module, based on yet another example; and Figure 7 It is a schematic depiction of the apparatus based on the example. Detailed Implementation

[0030] The exemplary embodiments are described below in sufficient detail to enable those skilled in the art to implement and carry out the systems and processes described herein. It is important to understand that the embodiments may be provided in many alternative forms and should not be construed as being limited to the examples set forth herein.

[0031] Therefore, while embodiments may be modified in various ways and take various alternative forms, specific embodiments thereof are shown in the accompanying drawings and described in detail below as examples. It is not intended to limit one to the specific forms disclosed. Rather, all modifications, equivalents, and alternatives falling within the scope of the appended claims should be included. Where appropriate, elements of the exemplary embodiments are consistently denoted by the same reference numerals throughout all drawings and detailed embodiments.

[0032] The terminology used herein to describe embodiments is not intended to be limiting. The quantifiers “a,” “an,” and “the” are singular because they refer to a single object; however, the use of the singular form in this document should not preclude the existence of more than one object. In other words, unless the context explicitly indicates otherwise, elements mentioned in the singular form may be one or more in number. It will also be understood that when the terms “comprising,” “including,” “containing,” and / or “having” are used herein, these terms specify the presence of the stated feature, item, step, operation, element, and / or component, but do not preclude the presence or addition of one or more other features, items, steps, operations, elements, components, and / or groups thereof.

[0033] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall be interpreted as their customary usage in the field. It should also be understood that, unless explicitly defined herein, terms in common usage shall also be interpreted as their customary usage in the relevant field, and not as having an idealized or overly formal meaning.

[0034] Typically, CPU caches greatly help reduce required memory bandwidth and memory access latency. Unfortunately, in some cases, the way data is managed in the CPU cache can lead to reduced available memory bandwidth, increased memory access latency, and a shortened memory module lifespan. Specifically, problems can arise due to a lack of synchronization between the CPU cache and the memory module's buffer, resulting in the aforementioned issues. More precisely, each cache line in the CPU cache is considered independent and is therefore fetched and evicted as needed by the CPU cache controller by issuing read and write operations that typically involve the entire cache line. There is no additional coordination between the CPU cache controller and the MMC in prefetching ECC blocks into the buffer and later evicting them from the memory medium. In contrast, the multi-level CPU caches of modern computers are always tightly coordinated. In principle, random memory accesses involving objects occupying at most one cache line will cause read / write amplification, which directly corresponds to the ratio of the ECC block size on the memory module to the size of a single cache line. However, even for objects occupying multiple (i.e., contiguous) cache lines, or for objects allocated adjacent to each other in memory and frequently accessed simultaneously or rapidly (because applications typically exhibit temporal and spatial locality), read-write amplification remains high. This is because the CPU cache controller treats all cache lines as independent, even if they may belong to the same ECC block and be modified together during computation. Furthermore, the CPU cache is typically much larger than the buffer size on the memory module (tens of MB vs. tens of kB). Therefore, ECC blocks are usually evicted from the memory module's buffer before cache lines that are part of an ECC block are evicted from the CPU cache. This further increases read-write amplification.

[0035] Figures 1a to 1m It is a step-by-step description of the read-modify-write operation based on existing technology. Figure 1a In this context, memory block #42 (e.g., an ECC block) already exists in buffer 130 of memory module 120 (i.e., it has been fetched from memory module 140, which includes multiple memory blocks), and cache lines #42a and #42c already exist in CPU cache 111 of CPU 110. CPU 110 performs a read-modify-write operation in random access mode, simultaneously or rapidly and sequentially modifying the two cache lines #42c and #42a existing in CPU cache 111. Specifically, in Figure 1a In the image, CPU 110 reads (described as an arrow pointing from the cache line) cache lines #42c and #42a from its cache 111. Figure 1bIn the diagram, the CPU modifies a previously read cache line and writes the modified cache lines #42c and #42a (depicted as arrows pointing to the cache lines) to its cache 111. In the diagram, the modified cache lines are depicted with a shaded background.

[0036] exist Figure 1c In this process, memory block #42 (containing cache lines #42a and #42c) is evicted from buffer 130 of memory module 120. Memory block #42 was initially placed in buffer 130 to serve read operations performed by CPU 110. Memory block #42 was evicted from buffer 130 early because buffer 130 is much smaller than CPU cache 111. Figure 1d In this process, the CPU evicts the modified cache line #42c from its cache 111 and writes the modified cache line #42c to memory module 120. However, evicting each of the modified cache lines #42a and #42c from the CPU cache 111 requires fetching memory block #42 into buffer 130 again. Therefore, in Figure 1e In the process, memory block #42 is retrieved again from memory 140 and placed into buffer 130 so that the modified cache line #42c can be written into it. Figure 1f In the middle, the modified cache line #42c is updated in buffer 130. Figure 1g The modified cache line #42c is shown in memory block #42, which now exists in buffer 130. Figure 1h In the middle, memory block #42 was evicted from buffer 130 again and replaced by some other memory blocks. Figure 1i In this process, CPU 110 evicts the remaining modified cache line #42a from its cache 111 and writes the modified cache line #42a to memory module 120. Figure 1j In, with steps Figure 1e Similarly, memory block #42 was again retrieved into buffer 130. Figure 1k In the middle, the modified cache line #42a is written to buffer 130. Figure 11 The modified cache line #42a is shown in memory block #42, which now exists in buffer 130. Finally, Figure 1m In the middle, memory block #42c was evicted from buffer 130 again.

[0037] In other words, even if modifications to two cache lines (64B each) belonging to the same memory block (256B) occur simultaneously or rapidly in succession, two additional reads from the storage medium are required, thus requiring an additional 512B of read bandwidth (totaling 768B, including the initial read, for simplicity...). Figures 1a to 1m(omitted). Furthermore, two write operations are required to the memory medium, necessitating 512 bytes of bandwidth.

[0038] According to one example, a mechanism is provided to reduce the number of read / write operations performed on or to the memory medium, particularly in random memory access modes. Aspects of the invention relate to allowing for faster and more efficient evicting of cached data from the CPU cache. This increases the available read / write bandwidth of the memory module, reduces memory medium wear, and makes CPU cache management more efficient. Furthermore, the improved memory read / write bandwidth utilization enables the use of larger ECC blocks to store data in the memory medium without performance degradation. This, in turn, increases the effective capacity of the memory module.

[0039] This invention relates to computer systems characterized by memory modules with onboard buffers. The memory modules can be based on different media (e.g., DRAM, PCM, 3D XPoint, MRAM, ReRAM) and can be directly attached to the CPU's memory controller, or provided as a separate device and connected to the computer via a fast interconnect (e.g., based on the Compute Fast Interconnect (EXL) standard). Specifically, this invention affects both the memory module controller on the memory module and the CPU cache controller.

[0040] The examples in this disclosure can be provided as methods, systems, or machine-readable instructions, such as any combination of software, hardware, or firmware. Such machine-readable instructions can be contained in or on a computer-readable storage medium (including, but not limited to, disk memory, CD-ROM, optical memory, etc.) having computer-readable program code thereon.

[0041] This disclosure is described using flowcharts and / or block diagrams of methods, apparatus, and systems provided in conjunction with examples. While the flowcharts above illustrate a specific order of execution, the order may differ from what is described. A block described in one flowchart may be combined with a block described in another flowchart. In some examples, some blocks in these flowcharts may not be necessary and / or additional blocks may be added. It should be understood that each flowchart and / or block in a flowchart and / or block diagram, and combinations of flowcharts and / or diagrams in a flowchart and / or block diagram, can be implemented using machine-readable instructions.

[0042] For example, machine-readable instructions can be executed by a processor of a machine such as a general-purpose computer, a user device such as a smart device (e.g., a smartphone), a special-purpose computer, an embedded processor, or other programmable data processing device to implement the functions described in the specification and figures. Specifically, a processor or processing device can execute the machine-readable instructions. Therefore, modules of the device (e.g., modules implementing comparator units, firewall structures, etc.) can be implemented by a processor that executes machine-readable instructions stored in memory, or by a processor that operates according to instructions embedded in logic circuitry. The term "processor" will be interpreted broadly to include CPUs, processing units, ASICs, logic units, or programmable gate groups, etc. These methods and modules can be executed by a single processor or can be distributed among multiple processors.

[0043] Such machine-readable instructions can also be stored in a computer-readable storage device that can instruct a computer or other programmable data processing device to operate in a specific mode. For example, the instructions can be provided in a non-transient computer-readable storage medium using instruction encoding, and the instructions can be executed by a processor.

[0044] Figure 2 This is a flowchart illustrating an example of a method for adjusting operations between a CPU cache and a buffer of a memory module in a device. The method includes: in block 201, the memory module placing a memory block comprising multiple cache lines for the device in its buffer. In block 202, the memory module queries the CPU cache to obtain multiple modified cache lines associated with the memory block. To obtain the multiple modified cache lines associated with the memory block in the buffer of the memory module, the CPU may perform operations on the multiple cache lines in its cache. For example, the CPU may modify a cache line by writing to it, thereby creating a modified cache line. The modified cache line may then need to be written to the buffer of the memory module so that the memory module can store its value in its memory.

[0045] Advantageously, the memory module can retrieve the modified cache line from the CPU cache before evicting the ECC block containing the cache line from the memory module's buffer, thereby avoiding Figures 1a to 1m The multiple eviction scenarios depicted in the diagram. In block 203, the method includes: updating the plurality of cache lines in the memory block based on the obtained plurality of modified cache lines, wherein the query occurs before the memory block is evicted from the buffer of the memory module of the device and / or written back to the memory block.

[0046] To illustrate this better, please see Figures 3a to 3g , Figures 3a to 3g It is a step-by-step description of the read-modify-write operation based on the example. Figure 3a and Figure 3b Corresponding to Figure 1a and Figure 1b There is no change to the behavior of the CPU / memory module. Figures 1a to 1m and Figures 3a to 3g The same elements in the figures are represented by the same reference numerals and have the same function.

[0047] exist Figure 3a In this context, memory block #42 (e.g., an ECC block) already exists in buffer 130 of memory module 120, and cache lines #42a and #42c already exist in CPU cache 111 of CPU 110. CPU 110 performs a read-modify-write operation in random access mode, simultaneously or rapidly and sequentially modifying the two cache lines #42c and #42a existing in CPU cache 111. Specifically, in Figure 3a In the image, CPU 110 reads (described as an arrow pointing from the cache line) cache lines #42c and #42a from its cache 111. Figure 3b In this process, the CPU modifies a previously read cache line and writes the modified cache lines #42c and #42a (described as arrows pointing to cache lines) into its cache 111. Figure 3c In the process of evicting memory block #42 from memory, memory module 120 queries CPU cache 111 for all cache lines belonging to memory block #42 that have not yet been written back to that memory. Figure 3d In the process, the modified cache lines #42a and #42c are written to buffer 130. Figure 3e In the process, the CPU cache marks the modified cache lines #42a and #42c as written back to the memory module. Figure 3e Different shades of gray are used to depict it. Figure 3f In the middle, memory block #42 is evicted from the buffer and replaced by some other memory blocks. Finally, in Figure 3g In this system, whenever the cache controller decides to evict modified cache lines #42a and #42c from the CPU cache 111 to make room for other cache lines, it can easily do so because these modified cache lines have already been written back to the memory module 120. The eviction of each cache line in question can be performed independently for each of #42a and #42c. In other words, compared to existing solutions, the number of read / write operations to the memory module can be reduced.

[0048] In order to select fast paths during cache line eviction, the CPU should know which cache lines have been written back to memory. This capability can be achieved through the CPU cache controller and a cache coherence protocol (e.g., MESI), which maintains a consistent state of all cache lines across all CPU caches. For example, using MESI: - A cache line (at a given address) just fetched from memory can be marked in the CPU cache. alone occupy (E). CPU write and read requests for this cache line can be processed without additional pre-synchronization with other CPU caches; - When some other CPUs want to read the cache line at the same address, they can be placed in the cache... exclusive The cache line containing the state is copied to the local CPU cache and then used to process CPU requests. Both copies of the cache line can now be marked as... shared (S); When the CPU modifies a cache line, that cache line can be marked as... Edited (M). Simultaneously, all cache lines at the same address in other CPU caches can be invalidated (i.e., marked as...). invalid (I)); -Responding to the situation invalid When a cache line in a given state is read, it may be necessary to update the local copy of the cache line. This can be achieved by copying the latest value of the cache line in question from some other CPU cache. The two copies of the cache line can now be marked as such in the CPU cache. shared (S).

[0049] If a cache line is marked as such in any CPU cache exclusive or shared This means that memory holds the latest (most recent) value of that cache line.

[0050] When the CPU cache controller begins using cache lines originating from memory modules, it can monitor cache line consistency. If any cache line is marked as [unclear] in any CPU cache... Edited This may indicate that the memory module does not have the latest version of this cache line. Before evicting a memory block from its buffer, the memory module can make a special request to the CPU cache controller to obtain all cache lines belonging to the memory block to be evicted. Specifically, the memory module can obtain all modified cache lines belonging to the memory block to be evicted (i.e., those not marked as such). exclusive or shared (Cache lines).

[0051] Figure 4 The process is illustrated. Figure 4 This is a schematic depiction of example communication between the CPU and memory modules. Figure 4 In the example, the CPU performs a read operation on cache line #42c. The CPU can check if cache line #42c exists in the CPU cache. If cache line #42c is not in the local cache, the CPU cache can indicate that the requested cache line does not exist and attempt to read cache line #42c from a buffer in a memory module. Since the buffer may initially be empty, the requested cache line may not exist in the buffer. In response, the buffer can acquire the memory block associated with the requested cache line (e.g., memory block #42 for cache line #42c) into the buffer. The buffer can then send the requested cache line #42c to the CPU cache. The CPU cache (e.g., the CPU cache controller) may find that the state of cache line #42c is... exclusive That is, the cache line has been newly fetched from the memory module. The CPU can then modify the cache line (e.g., by performing a write operation), after which the state of the cache line will be changed. Edited Then, the CPU can perform a read operation on cache line #42a, which is associated with memory block #42, the same as cache line #42c. Similarly, the CPU can attempt to read cache line #42a from its cache, and in response to cache line #42a not existing in the CPU cache, the CPU cache can attempt to read cache line #42a from the memory module's buffer. Since memory block #42 has been placed in the buffer as part of the operation performed on cache line #42c, cache line #42a can be retrieved from the memory module's buffer into the CPU cache, marked as... exclusive Before evicting memory block #42 from its buffer, the memory module can make a special request to the CPU cache to retrieve all modified cache lines belonging to memory block #42. Since the state of cache line #42a is... exclusive Therefore, it will not be retrieved into the buffer, unlike the one marked as... Edited The opposite of line #42c. The CPU cache can write cache line #42c to the buffer of the memory module and change the state of cache line #42c to... sharedAfter cache line #42c has been updated in the buffer, memory block #42 can then be written to memory. That is, advantageously, since cache line #42c has already been written back, its eviction can be performed quickly without having to fetch the memory block #42 associated with that cache line back into the memory module's buffer as in prior art solutions.

[0052] In one embodiment, memory modules (including buffers) may be included in the CPU cache coherency domain. This is in Figure 5 The example shows, Figure 5 It is a schematic depiction of example communication between the CPU and memory module, based on another example. Figure 5 The operations shown are largely related to combination Figure 4 The described operations are similar. As discussed above, under normal circumstances, cache lines retrieved from the memory medium and placed in the buffer will be marked as... exclusive However, if a cache line at the same address already exists in some other CPU caches, the cache line fetched from memory must have a different allocated state to maintain cache coherence. Therefore, it may be necessary to query the cache line status in the CPU cache. An earlier request to read cache line #42c (i.e., BusRd(S) #42c in the diagram) can indicate that there is no copy of #42c in any of the CPU caches. Once the CPU modifies cache line #42c, the state of the copy of cache line #42c in the CPU cache can be changed to... Edited At the same time, the state of the copy of cache line #42c existing in the buffer can be changed to invalid To maintain CPU cache consistency. When a memory module wants to update something that exists in its buffer and is marked as such... invalid The cache line (i.e., in) Figure 5 In the example of cache line #42c, the memory module can use the cache coherence protocol and issue a read request (BusRd(s)) for cache line #42c, as depicted in the figure. Therefore, the latest value of cache line #42c can be copied from some other CPU cache to the buffer, and both copies of cache line #42c can be marked as... shared For cache lines belonging to the same memory block, the memory module can discover their status in the CPU cache (or retrieve their status from the CPU cache) by issuing individual requests for each cache line or by issuing a batch request for all cache lines.

[0053] Figure 6This is a schematic depiction of example communication between the CPU and memory module, based on yet another example. Here, with... Figure 5 In contrast, optimizations were introduced to avoid queries to the cache line status that occur when loading memory blocks into the buffer. As mentioned above... Figure 5 The earlier request to read cache line #42c (i.e., BusRd(S) #42c) discussed here could indicate that there is no copy of #42c in either of the CPU's caches. However, advantageously, the discovery of the consistent state of the remaining cache lines associated with the same memory block as #42c (i.e., the cache line associated with memory block #42) can be postponed to a later date, i.e., before the memory block is evicted from the memory module's buffer.

[0054] To achieve this, a new, unique state can be introduced that is used only by the memory module and not by the CPU cache (that is, the CPU cache will not assign this state to any cache line). Figure 6 In this context, a unique state is called... unknown (?), but those skilled in the art will understand that only any unique state that the memory module wishes to use may be used. Occasionally, the memory module will learn the state of certain cache lines associated with a memory block in its buffer during normal operation. For example, as discussed earlier, a request to read cache line #42a could indicate that there is no copy of #42a in either of the CPU's caches, thus instructing the memory module that it has an exclusive copy of cache line #42a in its own buffer. Subsequently, once the cache line is copied to the CPU cache, the memory module can degrade the state of #42a to shared .

[0055] Finally, before evicting memory block #42 from the buffer, the memory module can attempt to retrieve the associated, tagged memory block from the CPU cache. invalid Or the state in the buffer is unknown All cache lines. As before, no response for some cache lines can indicate that the buffer holds an exclusive copy of the cache line.

[0056] Figure 7This is a schematic depiction of an example apparatus. The apparatus 700 includes a memory module 720, which includes a buffer 730 and a plurality of memory blocks. The apparatus 700 also includes a central processing unit (CPU) 710, which includes a CPU cache 711. The memory module 720 is used to place memory blocks from the plurality of memory blocks into its buffer 730. The memory module 720 may further include memory 740, which stores the plurality of memory blocks. The memory blocks include a plurality of cache lines for the apparatus 700. The memory module 720 is further configured to: query the CPU cache 711 to obtain a plurality of modified cache lines in the buffer 730 associated with the memory blocks; and update the plurality of cache lines in the memory blocks according to the plurality of modified cache lines, wherein the query occurs before evicting the memory block from the buffer 730 of the memory module 720 of the apparatus 700 and / or writing back the memory block.

[0057] According to one example, machine-readable instructions can be loaded onto a computer or other programmable data processing device to cause the computer or other programmable data processing device to perform a series of operations to produce a computer-implemented process. Thus, the instructions that execute on the computer or other programmable device provide operations for implementing the processes in the flowchart and / or the functions specified by the boxes in the block diagram.

[0058] Furthermore, the teachings herein can be implemented in the form of a computer or software product, such as a non-transient machine-readable storage medium, in which the computer software or product is stored, and includes a plurality of instructions, such as machine-readable instructions, for causing a computer device to perform the methods described in the examples of this disclosure.

[0059] In some examples, certain methods can be executed in a cloud computing or web-based environment. Cloud computing environments provide a variety of services and applications over the internet. These cloud-based services (e.g., Software as a Service, Platform as a Service, Infrastructure as a Service, etc.) can be accessed, for example, through a web browser or other remote interface on a user's device. The various functionalities described herein can be provided through a remote desktop environment or any other cloud-based computing environment.

[0060] While various embodiments have been described and / or illustrated herein in the context of a full-featured computer system, one or more of these exemplary embodiments may be distributed as a program product in various forms, regardless of the specific type of computer-readable storage medium used to actually perform the distribution. The embodiments disclosed herein may also be implemented using software modules that perform specific tasks. These software modules may include scripts, batch files, or other executable files that may be stored on a computer-readable storage medium or in a computing system. In some embodiments, these software modules may configure a computing system to perform one or more exemplary embodiments disclosed herein. Furthermore, one or more modules described herein can transform the form of data, physical devices, and / or representations of physical devices from one form to another.

[0061] The above description is provided to enable those skilled in the art to best utilize various aspects of the exemplary embodiments disclosed herein. This exemplary description is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Various modifications and variations can be made without departing from the spirit and scope of the invention. The embodiments disclosed herein should be considered illustrative in all respects, not restrictive. In determining the scope of the invention, reference should be made to the appended claims and their equivalents.

Claims

1. A method for regulating the operation between the central processing unit (CPU) cache and the buffer of the memory module of a device, characterized in that, The method includes: The memory module places a memory block, including multiple cache lines for the device, in the buffer of the memory module (201). The memory module queries the CPU cache to obtain multiple modified cache lines (202) associated with the memory block; and The multiple cache lines in the memory block are updated based on the obtained multiple modified cache lines (203), wherein the query occurs before the memory block is evicted from the buffer of the memory module of the device and / or written back to the memory block.

2. The method according to claim 1, characterized in that, Also includes: The CPU cache is used to perform operations on multiple cache lines in the CPU cache to obtain the multiple modified cache lines, wherein the multiple cache lines in the CPU cache are associated with the memory block.

3. The method according to claim 2, characterized in that, Also includes: In response to performing the operation on the plurality of cache lines in the CPU cache using the CPU cache, the CPU cache changes the state of the plurality of cache lines in the CPU cache to indicate that the plurality of cache lines in the CPU cache have been modified.

4. The method according to claim 3, characterized in that, Also includes: In response to the memory module detecting a change in the state of the plurality of cache lines in the CPU cache, the memory module issues a request to retrieve the plurality of modified cache lines from the CPU cache.

5. The method according to claim 3 or 4, characterized in that, Also includes: The memory module allocates a unique state to a portion of the plurality of cache lines included in the memory block in the buffer of the memory module, wherein the unique state is used only by the memory module and not by the CPU cache, and wherein the unique state indicates that the state of the portion of the plurality of cache lines is unknown to the memory module. Communicating with the CPU cache to determine the current state of each of the plurality of modified cache lines in the CPU cache; and The memory module changes the state of the corresponding cache lines that correspond to the plurality of modified cache lines from the unique state based on the current state of each of the plurality of modified cache lines.

6. The method according to claim 5, characterized in that, Also includes: Before evicting the memory block from the buffer of the memory module and / or writing it back, the memory module queries the CPU cache to determine the current state of those cache lines whose state has not changed from the unique state.

7. An apparatus (700), characterized in that, include: A memory module (720) includes a buffer (730) and multiple memory blocks; as well as Central Processing Unit (CPU) Cache (711). The memory module (720) is arranged as follows: A memory block comprising multiple cache lines for the device is placed in the buffer (730) of the memory module (720); Query the CPU cache (711) to obtain multiple modified cache lines associated with the memory block; and The multiple cache lines in the memory block are updated based on the multiple modified cache lines obtained, wherein the query occurs before the memory block is evicted from the buffer (730) of the memory module (720) of the device and / or written back to the memory block.

8. The apparatus (700) according to claim 7, characterized in that, The CPU cache (711) is also arranged as follows: An operation is performed on a plurality of cache lines in the CPU cache (711) to obtain the plurality of modified cache lines, wherein the plurality of cache lines in the CPU cache are associated with the memory block.

9. The apparatus (700) according to claim 8, characterized in that, The CPU cache (711) is also arranged as follows: In response to performing the operation on the plurality of cache lines in the CPU cache (711), the state of the plurality of cache lines is changed to indicate that the plurality of cache lines have been modified.

10. The apparatus (700) according to claim 9, characterized in that, The memory module (720) is also arranged as follows: The system detects changes in the state of the plurality of cache lines in the CPU cache (711) and issues a request to retrieve the plurality of modified cache lines from the CPU cache (711).

11. The apparatus (700) according to claim 9 or 10, characterized in that, The memory module (720) is also arranged as follows: Assign a unique state to a portion of the plurality of cache lines included in the memory block in the buffer (730) of the memory module (720), wherein the unique state is used only by the memory module (720) and not by the CPU cache (711), wherein the unique state indicates that the state of the portion of the plurality of cache lines is unknown to the memory module (720); Communicating with the CPU cache (711) to determine the current state of each of the plurality of modified cache lines in the CPU cache (711); and Based on the current state of each of the plurality of modified cache lines, the states of those cache lines corresponding to the plurality of modified cache lines are changed from the unique state.

12. The apparatus according to claim 11, characterized in that, The memory module (720) is also arranged as follows: Before evicting the memory block from the buffer (730) of the memory module and / or writing back the memory block, the CPU cache (711) is queried to determine the current state of those cache lines whose state has not changed from the unique state.

13. A computer-readable storage medium including computer program code, said computer program code being accessible by a device including a processor to provide instructions and / or data to said device, said computer program code being configured to cause the device, via said processor, to: The memory module places a memory block, comprising multiple cache lines for the device, into the buffer of the memory module. The CPU cache is queried through the memory module to obtain multiple modified cache lines associated with the memory block; as well as The plurality of cache lines in the memory block are updated based on the plurality of modified cache lines obtained, wherein the query occurs before the memory block is evicted from the buffer of the memory module of the device and / or written back to the memory block.

14. The computer-readable storage medium according to claim 13, characterized in that, It also includes computer program code for causing the device via the processor: The CPU cache is used to perform operations on multiple cache lines in the CPU cache to obtain the multiple modified cache lines, wherein the multiple cache lines in the CPU cache are associated with the memory block.

15. The computer-readable storage medium according to claim 14, characterized in that, It also includes computer program code for causing the device via the processor: In response to performing the operation on the plurality of cache lines in the CPU cache using the CPU cache, the state of the plurality of cache lines in the CPU cache is changed by the CPU cache to indicate that the plurality of cache lines in the CPU cache have been modified.

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