Multiple bank memory supporting multiple reads and multiple writes per cycle

Abstract

In a memory system having a plurality of memory banks, a plurality of memory access requests having a first priority level and a plurality of memory access requests having a different second priority level are received. A first set of memory banks performs the plurality of memory access requests having the first priority level during a first clock cycle. The memory system determines one or more second memory banks that did not perform a memory access request having the first priority level during the first clock cycle. In response to determining the one or more second memory banks that did not perform a memory access request having the first priority level during the first clock cycle, the one or more second memory banks perform one or more memory access requests having the second priority level during the first clock cycle.

Description

Cross-reference to related applications

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 538,488, filed September 14, 2023, entitled “Opportunity Memory Reading,” the disclosure of which is expressly incorporated herein by reference for various purposes. Technical Field

[0002] This disclosure generally relates to communication networks, and more specifically to simultaneous operations in the memory of a network device. Background Technology

[0003] Traditional single-port memory devices are configured so that only a single memory operation (such as a read operation) can be performed by the memory device during any given clock cycle. In the context of some networking or switching applications, various data used for packet processing (such as control tables, forwarding tables, etc.) are shared between multiple switching devices or the switching core of a single device. These multiple devices and cores collectively provide the ability to switch between numerous ports. However, limitations in the ability of multiple devices and cores to quickly access data stored in shared memory can lead to a decrease in switching capacity. One alternative is to use multi-port memory devices, which are configured to serve multiple memory access requests during a single clock cycle. However, multi-port memory devices are significantly more expensive than single-port memory devices. Additionally, the number of memory access requests that a multi-port memory device can serve during a single clock cycle is also limited. As another alternative, each switching device / core of the network equipment has its own memory device; however, increasing the number of memory devices increases costs, not only in terms of the direct cost of additional memory but also in terms of the circuitry resources required to keep information in different memories synchronized. As yet another alternative, memory systems can simulate multi-port memory by using multiple single-port memory banks. For example, one memory bank (parity bank) stores parity data about data stored in other memory banks (data banks). If two read requests for the first data bank are received simultaneously, one read request is served by the first data bank, and the other read request is served by reconstructing the data stored in the first data bank using an error correction algorithm (applied to data read from one or more second data banks and the parity data from the parity bank). Summary of the Invention

[0004] In one embodiment, a memory system includes: a plurality of memory banks; and circuitry configured to: receive a plurality of memory access requests having a first priority level; receive a plurality of memory access requests having a second priority level different from the first priority level; forward the plurality of memory access requests having the first priority level to a group of first memory banks for execution by the group of first memory banks during a first clock cycle; determine one or more second memory banks that did not execute the memory access requests having the first priority level during the first clock cycle; and in response to determining that one or more second memory banks did not execute the memory access requests having the first priority level during the first clock cycle, forward one or more memory access requests to one or more second memory banks for execution by the one or more second memory banks during the first clock cycle.

[0005] In another embodiment, a method is to execute memory access requests through a memory system having a plurality of memory banks. The method includes: receiving a plurality of memory access requests having a first priority level; receiving a plurality of memory access requests having a second priority level different from the first priority level; executing the plurality of memory access requests having the first priority level by a group of first memory banks during a first clock cycle; determining, through the memory system, one or more second memory banks that did not execute memory access requests having the first priority level during the first clock cycle; and, in response to determining that the one or more second memory banks did not execute memory access requests having the first priority level during the first clock cycle, executing one or more memory access requests having the second priority level by the one or more second memory banks during the first clock cycle. Attached Figure Description

[0006] Figure 1 This is a simplified block diagram of an example network device according to an embodiment, the network device including a memory system configured to execute guaranteed memory access requests and best-effort memory access requests within a single clock cycle.

[0007] Figure 2 The illustration schematically depicts a memory system (such as...) according to an embodiment. Figure 1 A simplified diagram of an example configuration of memory storage in a memory system.

[0008] Figure 3 According to the embodiments and Figure 1A simplified block diagram of the circuit associated with the memory bank of the memory system, which is configured to cache a best-effort memory access request when a guaranteed memory access request is received during the same clock cycle, and to enable the memory bank to execute the best-effort memory access request in a subsequent clock cycle.

[0009] Figure 4 This is a flowchart of an example method for executing guaranteed memory access requests and best-effort memory access requests within a single clock cycle, according to an embodiment. Detailed Implementation

[0010] In the following embodiments, the network device's memory system includes multiple memory banks. When a memory bank does not execute a guaranteed memory access request during a clock cycle, the memory system can instruct the memory bank to execute a best-effort memory access request during that clock cycle. According to embodiments, a guaranteed memory access request is a memory access request that the memory system is configured to execute during a specific clock cycle; and a best-effort memory access request is a memory access request that the memory system can execute during a specific clock cycle but can also defer to a subsequent clock cycle. For example, according to an embodiment, when the memory bank corresponding to a best-effort memory access request is busy during the current clock cycle in which the guaranteed memory access request is executed, the memory system defers the execution of the best-effort memory access request to a subsequent clock cycle.

[0011] In the following embodiments, the memory system is configured to execute a maximum number of guaranteed memory access requests during a single clock cycle, wherein the guaranteed memory access requests occupy a subset of memory banks among a plurality of memory banks. Additionally, according to some embodiments, the memory system is configured to issue one or more best-effort memory access requests to one or more memory banks (which are not occupied by the guaranteed memory access requests during that single clock cycle) during a single clock cycle. Therefore, at least in some embodiments, the memory system is configured to execute more memory access requests during a single clock cycle than a previous memory system (which was capable of executing a maximum number of guaranteed memory access requests during a single clock cycle), thus providing higher throughput.

[0012] Figure 1 This is a simplified block diagram of an example network device 100 according to an embodiment, which includes a memory system 104 configured to execute guaranteed memory access requests and best-effort memory access requests within a single clock cycle. In the embodiment, the example network device 100 includes network switches, routers, bridges, etc., which receive, process, and forward packets in a communication network.

[0013] Network device 100 includes a plurality of network interfaces 108 configured to communicatively couple to a plurality of network links for sending and receiving packets. Network device 100 also includes a packet processor 112 configured to analyze the headers of packets received via the plurality of network interfaces 108 to determine the network interface 108 to be used for forwarding packets. Packet processor 112 includes a plurality of circuits 116 configured to write to and / or read from memory system 104; therefore, circuits 116 are referred herein as “clients” of memory system 104 and / or “client 116”. Client 116 includes a variety of processing circuitry or processing elements (sometimes referred to as “processing engines”). In some embodiments, at least some clients of client 116 correspond to processing elements of a packet processing pipeline. In other embodiments, at least some clients of client 116 correspond to a completion processor. More generally, client 116 includes any suitable circuitry means for writing data to and / or reading data from memory system 104.

[0014] The memory system 104 includes a plurality of memory cells 132 (referred to herein as memory banks 132), a controller 136, and a mapping table 140 that stores the associations (e.g., logical-to-physical mappings) between logical addresses and physical addresses corresponding to the memory banks 132. More specifically, the mapping table 140 maps logical addresses (as specified in read and write commands issued by the client 116) to physical addresses (physical storage locations within the memory banks 132). The controller 136 (also referred to herein as control logic) manages the storage of data in the memory banks 132 and communicates with the client 116.

[0015] Figure 1 The memory bank 132 shown is logically arranged as an n×p 2D array, where n and p are suitable positive integers. In other embodiments, the memory bank 132 is logically arranged in another suitable manner, such as a 1D array (e.g., where n equals one), a 3D array, a 4D array, etc.

[0016] Typically, in embodiments, each memory bank 132 includes a single-port memory, meaning that it can execute a single memory access request, such as a read request or a write request, within each memory access cycle (typically corresponding to a clock cycle). The clock cycle referred to is the clock cycle of a clock signal that times the memory bank 132. In the present context, the clock cycle is also referred to herein as a memory access cycle, and the two terms are used interchangeably herein. In this example, each memory bank 132 includes a single-port static random access memory (SRAM). However, alternatively, the memory bank 132 may be implemented using any other suitable type of memory, such as dynamic random access memory (DRAM), solid-state memory, register memory, etc.

[0017] Although each memory bank 132 is capable of executing only a single memory access request per clock cycle, according to an embodiment, the entire memory system 104 is configured (as described in more detail below) to execute up to J memory access requests with a first priority level per clock cycle, where the first priority level is derived from multiple priority levels associated with the memory access request. In the embodiment, memory access requests with the first priority level are referred to herein as “guaranteed” memory access requests, while memory access requests with a second priority level derived from multiple priority levels are referred to herein as “best-effort” memory access requests. In the embodiment, the memory system 104 is configured to execute not only J guaranteed memory access requests but also one or more best-effort memory access requests per clock cycle. In the embodiment, the J guaranteed memory access requests are executed by a first subset of memory banks during the clock cycle, and one or more best-effort memory access requests are executed by a second subset of memory banks during the clock cycle, which is different from the first subset of memory access requests.

[0018] In an embodiment, the entire memory system 104 is configured (as will be described in more detail below) to execute up to K guaranteed read requests and up to L guaranteed write requests, where K and L are corresponding predefined integers, and where K + L = J.

[0019] According to an embodiment, during each clock cycle in at least some clock cycles, the controller 136 sends i) up to J guaranteed memory access requests and optionally ii) one or more best-effort memory requests to the memory bank 132. In an embodiment, the controller 136 is configured to forward both guaranteed memory access requests and best-effort memory access requests to the memory bank 132 during the same clock cycle. In an embodiment, each memory bank 132 includes or is otherwise associated with corresponding circuitry configured to store a best-effort memory access request in a corresponding buffer in response to receiving both a best-effort memory access request and a guaranteed memory access request during the same clock cycle; and the corresponding circuitry is configured to provide the best-effort memory access request to the corresponding memory bank for execution during a subsequent clock cycle in which the memory bank does not execute the guaranteed memory access request. In an embodiment, circuitry included in or otherwise associated with the corresponding memory bank 132 is configured to cause the corresponding memory bank to selectively execute a best-effort memory access request during a clock cycle, depending on whether the memory bank 132 executes a guaranteed memory access request during the clock cycle. For example, according to an embodiment, when the corresponding memory bank 132 executes a guaranteed memory access request during a clock cycle, the associated circuitry does not prompt the corresponding memory bank 132 to execute a best-effort memory access request during the clock cycle, but instead stores the best-effort memory access request in a buffer for execution during a subsequent clock cycle; and when the corresponding memory bank 132 does not execute a guaranteed memory access request during a clock cycle, the associated circuitry prompts the corresponding memory bank 132 to execute a best-effort memory access request during the clock cycle (or a previously received best-effort memory access request from the buffer).

[0020] In another embodiment, during each clock cycle of at least some clock cycles, the controller 136 sends to the memory bank 132 i) up to J guaranteed memory access requests for a first subset of memory bank 132 and optionally ii) one or more best-effort memory requests for a second subset of memory bank 132, which is different from the first subset of memory bank 132. For example, during each clock cycle of at least some clock cycles, the controller 136 selectively sends best-effort memory access requests to a particular memory bank 132 depending on whether the controller 136 is sending guaranteed memory access requests to that particular memory bank 132. For example, according to an embodiment, when the controller 136 sends a guaranteed memory access request to a specific memory bank 132 during a clock cycle, the controller 136 does not send a best-effort memory access request to the specific memory bank 132 during that clock cycle, but instead stores the best-effort memory access request in a buffer to send to the specific memory bank 132 in a subsequent clock cycle; and when the controller 136 does not send a guaranteed memory access request to the specific memory bank 132 during a clock cycle, the controller 136 sends a best-effort memory access request to the specific memory card 132 during the clock cycle.

[0021] Different components of network device 100 and memory system 104 are typically implemented using dedicated hardware circuitry. Alternatively, some elements of network device 100 and / or memory system 104, such as controller 136 (also referred to as control logic) or portions thereof, may be implemented using a processor that executes machine-readable instructions (e.g., software instructions and / or firmware instructions) or using a combination of dedicated hardware circuitry and machine-readable instructions executed by the processor.

[0022] Figure 2 This is a simplified diagram, schematically illustrating a memory system (such as...) according to an embodiment. Figure 1 An example configuration 200 of the memory storage in the memory system 104), and Figure 2 It is a reference Figure 1 Described. In Figure 2 In the illustrative example, n = 1 and p = 5, and memory banks 132 are labeled BANK #1, BANK #2...BANK #5. Figure 2 In the example, according to the embodiment, the memory system 104 is a one-dimensional array and is configured to execute one read request and one write request during each clock cycle. As described above, the memory system 104 includes a multi-dimensional array of memory banks 132, with parameters K, L, and J having other suitable values.

[0023] exist Figure 2In the illustrative example, each memory bank 136 includes multiple entries 204. In the embodiment, each entry 204 stores a data word or other basic data unit. Each group of p corresponding entries in the P corresponding memory banks is referred to as a stripe 208. In other words, the x-th entry of BANK #1, the x-th entry of BANK #2, the x-th entry of BANK #3, the x-th entry of BANK #4, and the x-th entry of BANK #5 are collectively referred to as the x-th stripe.

[0024] In this example, where K = 1, controller 136 designates one entry in each stripe 208 to serve as redundant entry 212. In general, where memory system 104 is designed to perform K write requests per clock cycle, controller 136 designates K entries in each stripe 208 to serve as redundant entries 212. As described below, according to an embodiment, the position of the redundant entries in the stripe is not fixed but varies over time.

[0025] In some embodiments, each entry 204 is identified by a corresponding physical address. The set of physical addresses is referred to as the physical memory space of the memory system 104. The size of the logical memory space of the memory system 104 (i.e., the memory space exposed to the client 116) corresponds to the total number of non-redundant entries 204. Therefore, in an embodiment, the logical memory space of the memory system 104 is smaller than the physical memory space. In an embodiment, the size of the logical memory space corresponds to the total amount of data that can be stored in the memory system 136. In an embodiment, the size difference between the logical memory space and the physical memory space corresponds to a plurality of redundant entries 212.

[0026] Typically, client 116 issues write and read requests to specified logical addresses without knowing the physical addresses where the data is actually stored. Logical-to-physical mapping table 124 maintains the current mapping between each logical address and its corresponding physical address. Control unit 40 uses table 44 to translate between logical and physical addresses when executing write and read commands. Typically, mapping table 124 also indicates the location of redundant entries 212 (or multiple redundant entries, for K>1) for each stripe 208.

[0027] As will now be described in detail, the use of redundancy entry 212 enables the controller 136 to execute multiple guaranteed memory access requests (e.g., one guaranteed read request and K guaranteed write requests) during each clock cycle, even when the memory bank 132 is a single-port memory.

[0028] Reference Figure 2Consider guaranteed read requests and guaranteed write requests to be executed within the same clock cycle. If the guaranteed read request and guaranteed write request access entries 204 reside in different memory banks 132, the controller 136 can execute the guaranteed read request and guaranteed write request in a simple manner. For example, the controller 136 forwards the guaranteed read request and guaranteed write request to the corresponding memory banks 132, which execute the guaranteed read request and guaranteed write request issued by the controller in parallel.

[0029] If, on the other hand, guaranteed read request and guaranteed write request access entries 204 happen to reside in the same memory bank 132 (referred to herein as a "conflict"), this conflict must be resolved because memory bank 132 can only execute one memory access command per clock cycle. In this case, controller 136 executes the guaranteed read request received from client 116, i.e., reads data from the logical address of entry 204 specified in the guaranteed read request. However, the guaranteed write request is not executed at the logical address of entry 204 specified in the guaranteed write request, but rather in a redundant entry 212 of the same band 208 corresponding to the logical address of entry 204 specified in the guaranteed write request. Controller 136 then updates the logical-to-physical mapping table 121 accordingly.

[0030] Since each stripe 204 has redundant entries 212 for K = 1, a conflict between a guaranteed read request and a guaranteed write request will always be successfully resolved. In general, each stripe includes K redundant entries 212. Therefore, even in the worst-case scenario where a guaranteed read request conflicts with K guaranteed write requests (which occurs when all K+1 guaranteed memory access requests access the same memory bank 132), this conflict will still be resolved.

[0031] exist Figure 2 In the illustrative example, entries 204-1-6 of Bank #1 and 204-2-5 of Bank #2 relate to corresponding guaranteed memory access requests during a clock cycle. Therefore, Bank #1 and Bank #2 cannot be used to execute any best-effort memory access requests during a clock cycle. On the other hand, Bank #4 does not execute guaranteed memory access requests during a clock cycle, therefore Bank #4 can be used to execute the best-effort memory access request associated with entry 204-4-3.

[0032] Figure 3This is a simplified block diagram of a circuit arrangement 300 associated with memory bank 304 according to an embodiment. This circuit is configured to cache a best-effort memory access request when a guaranteed memory access request is received during the same clock cycle, and to prompt memory bank 304 to execute the best-effort memory access request in a subsequent clock cycle. In the embodiment, memory system 104 ( Figure 1 This includes corresponding examples of circuit arrangements 300 (or similar circuit arrangements) for each of at least some of the memory banks in memory bank 132, and for ease of illustration, Figure 3 It is a reference Figure 1 The description is as follows. For example, memory storage unit 304 ( Figure 3 ) corresponds to the corresponding memory storage unit 132 ( Figure 1 In other embodiments, the circuit device 300 includes components connected to... Figure 1 In another suitable network device, network device 100 differs from network device 300. In other embodiments, network device 100 includes other suitable circuitry different from circuitry 300, which is configured to cache best-effort memory access requests when guaranteed memory access requests are also received during the same clock cycle, and to prompt memory bank 132 to execute the best-effort memory access request during a subsequent clock cycle.

[0033] Circuit arrangement 300 includes a first-in, first-out (FIFO) buffer 308 configured to store some best-effort read requests from client 116, such as best-effort read requests received within the same clock cycle (during which guaranteed read requests are also received). Circuit arrangement 300 also includes a selection circuit arrangement 312 (also referred to herein as “selector 312”) configured to: i) transmit guaranteed read requests to the corresponding memory bank 304 for execution, and ii) selectively transmit best-effort read requests to the corresponding memory bank 304 for execution, and iii) selectively transmit best-effort read requests to FIFO 308.

[0034] In one embodiment, selector 312 is configured to store a received best-effort read request in FIFO 308 in response to receiving both a best-effort read request and a guaranteed read request during the same clock cycle. In another embodiment, selector 312 is configured to store a received best-effort read request in FIFO 308 in response to determining that FIFO 308 is not empty. In yet another embodiment, selector 312 is configured to store a best-effort read request in FIFO 308 in response to at least one of the following: i) receiving both a best-effort read request and a guaranteed read request within the same clock cycle and ii) determining that FIFO 308 is not empty.

[0035] In an embodiment, selector 312 is configured to retrieve a best-effort read request from FIFO 308 and transmit the retrieved best-effort read request to memory bank 304 in response to determining i) no guaranteed read request received within a clock cycle and ii) FIFO 308 is not empty.

[0036] In an embodiment, selector 312 is configured to transmit the received best-effort read request to memory bank 304 in response to determining i) that no guaranteed read request was received in the same clock cycle in which the best-effort read request was received and ii) that FIFO 308 is empty.

[0037] The circuit device 300 includes a delay line 320 that receives attribute information about a read request provided to the memory bank 304. In an embodiment, the attribute information includes information indicating whether the corresponding read request is a best-effort read request. According to an embodiment, the delay line 320 is configured to output the attribute information about the read request while the memory bank 304 outputs the result of executing the read request.

[0038] FIFO buffer 324 is configured to store the result of executing a best-effort read request. The input of demultiplexer 328 is coupled to the output of memory bank 304. A first output of demultiplexer 328 corresponds to the result of executing a guaranteed read request, and a second output of demultiplexer 328 corresponds to the result of executing a best-effort read request. The control input of demultiplexer 328 is coupled to the output of delay line 320. Demultiplexer 328 is configured to selectively store the result of executing a read request in FIFO 324. For example, according to an embodiment, demultiplexer 328 is configured to select a first output to output the result of executing a read request when attribute information corresponding to the read request (e.g., output by delay line 320) indicates that the read request is a guaranteed read request; and demultiplexer 328 is configured to select a second output to output the result of executing a read request (and also store the result in FIFO 324) when attribute information corresponding to the read request (e.g., output by delay line 320) indicates that the read request is a best-effort read request.

[0039] The output of FIFO 324 is coupled to arbitration circuit 340. Arbitration circuit 340 is coupled to the outputs of multiple FIFOs 324 corresponding to multiple different memory banks 304 / 132, and is configured to retrieve the result of a best-effort read request from the multiple FIFOs 324 according to an arbitration algorithm (such as polling) or another suitable arbitration algorithm. In an embodiment, the best-effort read request output by arbitration circuit 340 is provided to a suitable client among clients 116.

[0040] In an embodiment, FIFO 324 is configured to output multiple results of multiple best-effort read requests during a single clock cycle (e.g., two results of two best-effort read requests, or another suitable number greater than two) to facilitate faster emptying of FIFO 324 compared to an embodiment in which FIFO 324 outputs a single result of a single best-effort read request during a single clock cycle.

[0041] In some embodiments, circuitry 300 is configured to further selectively forward a best-effort read request to memory bank 304 during a clock cycle based on whether a guaranteed write request is received during that clock cycle. For example, in one embodiment, if both a best-effort read request and a guaranteed write request are received during the same clock cycle, circuitry 300 stores the best-effort read request in FIFO 308 and transmits the guaranteed write request to memory bank 304 for execution. As another example, in one embodiment, if a guaranteed write request is received during a clock cycle and FIFO 308 is not empty, circuitry 300 will not retrieve the best-effort read request from FIFO 308.

[0042] In operation, in response to receiving both a best-effort memory access request and a guaranteed memory access request during the same clock cycle, circuitry 300 stores the best-effort memory access request in FIFO 308; and selector 312 provides the best-effort memory access request to memory bank 304 for execution during subsequent clock cycles in which memory bank 304 does not execute the guaranteed memory access request. In an embodiment, circuitry 300 causes memory bank 304 to selectively execute the best-effort memory access request during a clock cycle, depending on whether memory bank 304 executes the guaranteed memory access request during that clock cycle. For example, according to an embodiment, when the corresponding memory bank 304 executes a guaranteed memory access request during a clock cycle, the selector 312 does not prompt the memory bank 304 to execute a best-effort memory access request during the clock cycle, but instead stores the best-effort memory access request in the FIFO 308 for execution during a subsequent clock cycle; and when the memory bank 304 does not execute a guaranteed memory access request during a clock cycle, the selector 312 prompts the memory bank 304 to execute a best-effort memory access request (or a previously received best-effort memory access request from the FIFO 308) during the clock cycle.

[0043] Figure 4 This is a flowchart of an example method 400 for executing a memory access request by a memory system including multiple memory banks according to an embodiment. Method 400 is performed by an example memory system according to an embodiment (such as those described above). Figures 1 to 3The described memory system is implemented, and for ease of illustration, method 400 is referred to Figures 1 to 3 The method described above is used in other embodiments. Figures 1 to 3 Another suitable memory system implementation different from the described memory system and / or in conjunction with Figure 1 The network device 100 is implemented in another suitable device. In other embodiments, the memory system (such as those mentioned above) Figures 1 to 3 The described memory system) implementation and Figure 4 There are 400 different suitable methods.

[0044] In block 404, the memory system receives multiple memory access requests with a first priority level, and in block 408, the memory system receives multiple memory access requests with a second priority level different from the first priority level. For example, memory system 104 receives memory access requests with the first priority level and memory access requests with the second priority level.

[0045] In block 412, a first set of memory banks, among a plurality of memory banks, executes multiple memory access requests with a first priority level during a first clock cycle. For example, a set of memory banks 132 executes multiple guaranteed memory access requests during the first clock cycle. Figure 2 In the example, Bank #1 and Bank #2 execute guaranteed memory access requests during the first clock cycle.

[0046] In block 416, the memory system identifies one or more second memory banks that did not execute memory access requests with a first priority level during the first clock cycle. For example, circuitry 300 associated with each of at least some of the memory banks 132 determines whether the corresponding memory bank 132 / 304 is to execute a guaranteed memory access request during the clock cycle.

[0047] In block 420, in response to determining in block 416 that one or more second memory banks (which did not execute memory access requests with a first priority level during the first clock cycle), the one or more second memory banks execute one or more memory access requests with a second priority level during the first clock cycle. For example, when a memory bank does not execute a guaranteed memory access request during a clock cycle, the circuitry 300 associated with each of at least some of the memory banks in memory bank 132 will execute a best-effort memory access request during that clock cycle in response to receiving a best-effort memory access request.

[0048] In an embodiment, method 400 further includes: for each of one or more first memory banks in a set of first memory banks: in response to receiving a first memory access request having a first priority level and a second memory access request having a second priority level at a corresponding first circuit device associated with the first memory bank within the same clock cycle, storing the second memory access request in a corresponding buffer associated with the first memory bank for execution by the first memory bank during a subsequent clock cycle.

[0049] In an embodiment, method 400 further includes: during a first clock cycle, receiving a memory access request with a first priority level at a first circuit device associated with a memory bank of the first memory bank; during the first clock cycle, receiving a memory access request with a second priority level at the first circuit device; in response to the first circuit device determining that a first memory access request with the first priority level has been received during the first clock cycle, storing a second memory access request with the second priority level in a buffer of the first circuit device; and in response to the first circuit device determining that no memory access request with the first priority level has been received during a second clock cycle following the first clock cycle, executing a second memory access request with the second priority level by a first memory bank during the second clock cycle.

[0050] In another embodiment, method 400 further includes: in response to a first circuit device determining that no memory access request with a first priority level has been received during a third clock cycle between a first clock cycle and a second clock cycle: retrieving another memory access request with a second priority level from a buffer of the first circuit device during the third clock cycle, the other memory access request with the second priority level having been received prior to the receipt of the third memory access request; and executing the other memory access request with the second priority level by a first memory bank during the third clock cycle.

[0051] In another embodiment, method 400 further includes: during a first clock cycle, receiving a memory access request having a second priority level at a first circuit device associated with each of the second memory banks; wherein executing one or more memory access requests having a second priority level in block 420 includes: during the first clock cycle, executing a memory access request having a second priority level by a second memory bank.

[0052] In another embodiment, executing a memory access request (with a second priority level) received during a first clock cycle is at least in response to the first circuit device determining that the first circuit device did not receive a memory access request with a first priority level during the first clock cycle.

[0053] In another embodiment, method 400 further includes: during a second clock cycle prior to the first clock cycle, receiving a memory access request having a second priority level at a first circuit device associated with one of the second memory banks; storing a memory access request (having a second priority level) received during the second clock cycle in a buffer of the first circuit device; and retrieving a memory access request (having a second priority level) received during the second clock cycle from the buffer during the first clock cycle; wherein executing one or more memory access requests having a second priority level in block 420 includes: executing a memory access request (having a second priority level) retrieved from the buffer via a second memory bank.

[0054] In another embodiment, method 400 further includes: for each of at least some of the plurality of memory banks: in response to a memory access request having a second priority level being executed by the memory bank, storing data read from the memory bank in a corresponding buffer associated with the second memory bank; and selecting, by means of the memory system, the order in which data is output from the corresponding buffers of the at least some memory banks according to an arbitration algorithm.

[0055] In another embodiment, for each of at least some of the multiple memory banks, method 400 further includes: at a circuit associated with the memory bank, determining whether to store the data read from the memory bank in a buffer based on whether the data is in response to a memory access request having a second priority level.

[0056] In another embodiment, executing multiple memory access requests with a first priority level in block 412 includes: executing one or more read requests at one or more corresponding first memory stores in a first subset of the first memory stores during a first clock cycle; and executing one or more write requests at one or more corresponding first memory stores in a second subset of the first memory stores during the first clock cycle.

[0057] In another embodiment, executing one or more memory access requests with a second priority level in block 420 includes executing one or more read requests by one or more corresponding second memory banks.

[0058] Some of the frameworks, operations, and techniques described above can be implemented using hardware, a processor executing firmware instructions, a processor executing software instructions, or any suitable combination thereof. When implemented using a processor executing software or firmware instructions, the software or firmware instructions can be stored in any suitable computer-readable storage medium. The software or firmware instructions may include machine-readable instructions that, when executed by one or more processors, cause one or more processors to perform the various actions described above.

[0059] When implemented in hardware, the hardware may include one or more of the following: discrete components, integrated circuits, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), etc.

[0060] Although the present invention has been described with reference to specific examples (which are intended to be illustrative only and not to limit the invention), changes, additions and / or deletions may be made to the disclosed embodiments without departing from the scope of the invention.

Claims

1. A memory system, comprising: Multiple memory banks; as well as The circuit device is configured as follows: Receive multiple memory access requests with the first priority level. Receive multiple memory access requests with a second priority level, which is different from the first priority level. Multiple memory access requests with the first priority level are forwarded to a first set of memory banks for execution by the first set of memory banks during a first clock cycle. One or more second memory banks are identified, which did not execute a memory access request with the first priority level during the first clock cycle, and In response to determining that one or more second memory banks did not execute a memory access request with the first priority level during the first clock cycle, one or more memory access requests are forwarded to the one or more second memory banks for execution by the one or more second memory banks during the first clock cycle.

2. The memory system of claim 1, wherein the circuitry includes a corresponding first circuitry associated with each of the one or more first memory banks, each first circuitry including a buffer configured to store a memory access request having the second priority level for later execution, the first circuitry being configured to: In response to receiving a first memory access request with the first priority level and a second memory access request with the second priority level during the same clock cycle, the second memory access request is stored in the buffer for execution by the first memory bank during a subsequent clock cycle.

3. The memory system of claim 1, wherein the circuitry includes a first circuitry associated with a first memory bank, the first circuitry including a buffer configured to store memory access requests having a second priority level for later execution, the first circuitry being configured to: During the first clock cycle, receive one of the memory access requests having the first priority level; During the first clock cycle, receive one of the memory access requests having the second priority level; In response to the first circuit device determining that a first memory access request having the first priority level is received during the first clock cycle, a second memory access request having the second priority level is stored in the buffer; as well as In response to the first circuit device determining that no memory access request with the first priority level is received during a second clock cycle following the first clock cycle, the second memory access request with the second priority level is forwarded to a first memory bank during the second clock cycle for execution by the first memory bank.

4. The memory system of claim 3, wherein the first circuitry is further configured to respond to the first circuitry determining that no memory access request having the first priority level is received during a third clock cycle between the first clock cycle and the second clock cycle: During the third clock cycle, another memory access request with the second priority level is retrieved from the buffer, the other memory access request with the second priority level having been received prior to the receipt of the third memory access request; and During the third clock cycle, the other memory access request with the second priority level is forwarded to the first memory bank for execution by the first memory bank.

5. The memory system of claim 1, wherein the circuit means includes a first circuit means associated with one of the second memory banks, the first circuit means being configured to: During the first clock cycle, receive one of the memory access requests having the second priority level; During the first clock cycle, the memory access request with the second priority level is forwarded to a second memory bank for execution by the second memory bank.

6. The memory system of claim 5, wherein the first circuitry is configured to forward the memory access request having the second priority level to the second memory bank at least in response to the first circuitry determining that no memory access request having the first priority level has been received by the first circuitry during the first clock cycle.

7. The memory system of claim 1, wherein the circuitry includes a first circuitry associated with a second memory bank, the first circuitry including a buffer configured to store a memory access request having the second priority level for later execution, the first circuitry being configured to: During a second clock cycle preceding the first clock cycle, one of the memory access requests having the second priority level is received; The memory access request with the second priority level received during the second clock cycle is stored in the buffer; as well as During the first clock cycle, the memory access request with the second priority level received during the second clock cycle is retrieved from the buffer; During the first clock cycle, the memory access request with the second priority level retrieved from the buffer is forwarded to the second memory bank.

8. The memory system of claim 1, wherein the circuitry comprises: A corresponding buffer is associated with each of at least some of the plurality of memory banks, the buffer being configured to store data read from the memory bank in response to a memory access request having the second priority level executed by the memory bank; as well as The selection circuitry is configured to select the order in which data is output from the respective buffers of the at least some memory stores according to an arbitration algorithm.

9. The memory system of claim 8, further comprising, for each of the at least some of the memory banks of the plurality of memory banks: The corresponding demultiplexer circuitry is configured to select whether to store the data read from the memory bank in the buffer based on whether the data is in response to a memory access request having the second priority level.

10. The memory system of claim 1, wherein the memory system is configured to: During the first clock cycle, one or more read requests are executed at one or more corresponding first memory banks in a first subset of the first memory banks; as well as During the first clock cycle, one or more write requests are executed at one or more corresponding first memory banks in a second subset of the first memory banks; as well as One or more read requests are executed through one or more corresponding second memory banks.

11. The memory system of claim 10, further comprising: A control circuit is configured to prioritize a read request and direct the read request to the first memory bank when i) a read request having the first priority level and corresponding to a first memory bank among the plurality of memory banks and ii) a write request having the first priority level and corresponding to the first memory bank are received during the same clock cycle.

12. The memory system of claim 11, wherein the control circuitry is further configured to, when i) a read request having the first priority level and corresponding to the first memory bank and ii) a write request having the first priority level and corresponding to the first memory bank are received during the same clock cycle: The write request is directed to another memory bank that acts as a redundant memory bank.

13. A method for executing a memory access request through a memory system comprising a plurality of memory banks, comprising: Receive multiple memory access requests with the first priority level; Receive multiple memory access requests with a second priority level that is different from the first priority level; During the first clock cycle, multiple memory access requests with the first priority level are executed through a set of first memory banks; The memory system determines one or more second memory banks that did not execute a memory access request with the first priority level during the first clock cycle. as well as In response to determining that one or more second memory banks did not execute a memory access request with the first priority level during the first clock cycle, one or more memory access requests with the second priority level are executed through the one or more second memory banks during the first clock cycle.

14. The method for executing a memory access request according to claim 13, further comprising, for each of the one or more first memory banks: In response to receiving a first memory access request having the first priority level and a second memory access request having the second priority level at a corresponding first circuit device associated with the first memory bank during the same clock cycle, the second memory access request is stored in a corresponding buffer associated with the first memory bank for execution by the first memory bank during a subsequent clock cycle.

15. The method for executing a memory access request according to claim 1132, further comprising: During the first clock cycle, a memory access request having the first priority level is received at a first circuit device associated with a first memory bank of the first memory bank; During the first clock cycle, a memory access request with the second priority level is received at the first circuit device. In response to the first circuit device determining that a first memory access request having the first priority level is received during the first clock cycle, a second memory access request having the second priority level is stored in the buffer of the first circuit device; as well as In response to the first circuit device determining that no memory access request with the first priority level is received during a second clock cycle following the first clock cycle, the second memory access request with the second priority level is executed by the first memory bank during the second clock cycle.

16. The method for executing a memory access request according to claim 15, further comprising responding to the first circuit means determining that no memory access request having the first priority level has been received during a third clock cycle between the first clock cycle and the second clock cycle: During the third clock cycle, another memory access request having the second priority level is retrieved from the buffer of the first circuit device, the other memory access request having the second priority level having been received before the third memory access request was received; and During the third clock cycle, the other memory access request with the second priority level is executed by the first memory bank.

17. The method for executing a memory access request according to claim 13, further comprising: During the first clock cycle, a memory access request having the second priority level is received at a first circuit device associated with one of the second memory stores in the second memory stores; Executing one or more memory access requests with the second priority level during the first clock cycle includes: executing a memory access request with the second priority level received during the first clock cycle by the second memory bank.

18. The method of claim 17 for executing a memory access request, wherein executing the memory access request having the second priority level received during the first clock cycle is at least in response to the first circuit device determining that no memory access request having the first priority level was received by the first circuit device during the first clock cycle.

19. The method for executing a memory access request according to claim 13, further comprising: During a second clock cycle preceding the first clock cycle, a memory access request having the second priority level is received at a first circuit device associated with a second memory bank in the second memory bank; The memory access request with the second priority level received during the second clock cycle is stored in the buffer of the first circuit device; as well as During the first clock cycle, the memory access request with the second priority level received during the second clock cycle is retrieved from the buffer; Executing the one or more memory access requests with the second priority level during the first clock cycle includes: executing the memory access request with the second priority level retrieved from the buffer by the second memory bank.

20. The method for executing a memory access request according to claim 13, further comprising: For each of at least some of the plurality of memory banks: in response to a memory access request with the second priority level being executed by the memory bank, data read from the memory bank is stored in a corresponding buffer associated with the memory bank; as well as The memory system selects the order in which data is output from the corresponding buffers of the at least some memory stores according to an arbitration algorithm.

21. The method for executing a memory access request according to claim 20, further comprising, for each of the at least some of the memory banks of the plurality of memory banks: At the circuitry associated with the memory bank, it is determined whether the data read from the memory bank is stored in the buffer based on whether the data is in response to a memory access request having the second priority level.

22. The method of claim 13 for executing memory access requests, wherein executing the plurality of memory access requests having the first priority level during the first clock cycle comprises: During the first clock cycle, one or more read requests are executed at one or more corresponding first memory stores in a first subset of the first memory stores; as well as During the first clock cycle, one or more write requests are executed at one or more corresponding first memory stores in a second subset of the first memory stores.

23. The method for executing a memory access request according to claim 22, wherein: Executing one or more memory access requests with the second priority level during the first clock cycle includes: executing one or more read requests by one or more corresponding second memory banks.

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