Display substrate and display device

Abstract

A display substrate and a display device. The display substrate comprises a plurality of circuit units, each of the circuit units comprising a pixel driving circuit, the pixel driving circuit comprising at least a first capacitor (10), a second capacitor (20), a third capacitor (30), a first connection electrode (51), a second connection electrode (52), and a third connection electrode (53), a first terminal of the second capacitor (20) and a first terminal of the third capacitor (30) being connected to the first connection electrode (51), a second terminal of the first capacitor (10) and a second terminal of the second capacitor (20) being connected to the second connection electrode (52), and a first terminal of the first capacitor (10) and a second terminal of the third capacitor (30) being connected to the third connection electrode (53); in a direction perpendicular to the display substrate, the display substrate comprises at least a first conductive layer, a second conductive layer, and a semiconductor layer, one capacitor plate of the third capacitor (30) being arranged in the semiconductor layer.

Description

Display substrate and display device TECHNICAL FIELD

[0001] The present document relates to, but is not limited to, the technical field of display, in particular to a display substrate and a display device. BACKGROUND

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, lightness, flexibility, low cost, etc. With the continuous development of display technology, flexible display devices with OLED or QLED as light-emitting devices and controlled by Thin Film Transistor (TFT) have become the mainstream products in the current display field.

[0003] SUMMARY

[0004] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0005] In one aspect, the present disclosure provides a display substrate, comprising a plurality of circuit units, at least one circuit unit comprising a pixel driving circuit, the pixel driving circuit comprising at least a first capacitor, a second capacitor, a third capacitor, a first connection electrode having a first node potential, a second connection electrode having a second node potential, and a third connection electrode having a third node potential, the first end of the second capacitor and the first end of the third capacitor are connected with the first connection electrode, the second end of the first capacitor and the second end of the second capacitor are connected with the second connection electrode, the first end of the first capacitor and the second end of the third capacitor are connected with the third connection electrode, the first capacitor, the second capacitor and the third capacitor each comprise at least two capacitor plates stacked; in a direction perpendicular to the display substrate, the display substrate comprises at least a first conductive layer disposed on a substrate, a second conductive layer disposed on a side of the first conductive layer away from the substrate, and a semiconductor layer disposed on a side of the second conductive layer away from the substrate; in at least one circuit unit, one capacitor plate of the third capacitor is disposed in the semiconductor layer.

[0006] In an exemplary embodiment, the display substrate further comprises a third conductive layer disposed on the side of the semiconductor layer away from the base and a fourth conductive layer disposed on the side of the third conductive layer away from the base, another capacitor plate of the third capacitor is disposed in at least one of the conductive layers and is shared with one of the capacitor plates of the first capacitor or one of the capacitor plates of the second capacitor.

[0007] In an exemplary embodiment, the first capacitor comprises at least a first plate as a second end of the first capacitor and a second plate as a first end of the first capacitor, the second capacitor comprises at least a third plate as a second end of the second capacitor and a fourth plate as a first end of the second capacitor, the first plate and the third plate are disposed in the first conductive layer, the second plate and the fourth plate are disposed in the second conductive layer, the orthographic projection of the second plate on the base at least partially overlaps the orthographic projection of the first plate on the base, the orthographic projection of the fourth plate on the base at least partially overlaps the orthographic projection of the third plate on the base; in at least one circuit unit, the first plate is connected with the third plate, the third plate is connected with the second connection electrode, the second plate is connected with the third connection electrode, and the fourth plate is connected with the first connection electrode.

[0008] In an exemplary embodiment, the pixel driving circuit further comprises a first transistor as a first reset transistor, a second transistor as a second reset transistor, and a third transistor as a driving transistor, the first electrode of the first transistor and the first electrode of the second transistor are connected with a first initial signal line; in at least one circuit unit, the first end of the first connection electrode is connected with the second electrode of the first transistor, the second end of the first connection electrode is connected with the gate electrode of the third transistor, and the gate electrode of the third transistor is connected with the fourth plate through a plate connection strip and a sixth connection electrode.

[0009] In an exemplary embodiment, in at least one circuit unit, the first end of the sixth connection electrode is connected with the fourth plate, the second end of the sixth connection electrode is connected with the plate connection strip, and the plate connection strip is connected with the gate electrode of the third transistor.

[0010] In an exemplary embodiment, the display substrate further comprises a third conductive layer disposed on the side of the semiconductor layer away from the base; in at least one circuit unit, the gate electrode of the third transistor and the plate connection strip are disposed in the third conductive layer and are an integrated structure connected with each other.

[0011] In an exemplary embodiment, in at least one circuit unit, a first end of the second connection electrode is connected with the second electrode of the second transistor, and a second end of the second connection electrode is connected with the third plate.

[0012] In an exemplary embodiment, in at least one circuit unit, a first end of the third connection electrode is connected with the second electrode of the third transistor, and a second end of the third connection electrode is connected with the second plate.

[0013] In an exemplary embodiment, the third capacitor includes the fourth plate as a first end of the third capacitor and a fifth plate as a second end of the third capacitor; in at least one circuit unit, the fifth plate is arranged in the semiconductor layer, a normal projection of the fifth plate on the substrate at least partially overlaps a normal projection of the fourth plate on the substrate, and the fifth plate is connected with the third connection electrode.

[0014] In an exemplary embodiment, the pixel driving circuit further includes a fifth transistor as a first light-emitting control transistor and a sixth transistor as a second light-emitting control transistor, a first electrode of the third transistor is connected with a second electrode of the fifth transistor, and a second electrode of the third transistor is connected with a first electrode of the sixth transistor; in at least one circuit unit, a first end of the third connection electrode is connected with the second electrode of the third transistor and the first electrode of the sixth transistor, a second end of the third connection electrode is connected with the second plate, and the fifth plate is connected with the first electrode of the sixth transistor.

[0015] In an exemplary embodiment, the sixth transistor at least includes a sixth active layer, and the fifth plate and the sixth active layer are an integrated structure connected with each other.

[0016] In an exemplary embodiment, the display substrate further comprises a third conductive layer disposed on a side of the semiconductor layer distal to the base; the third capacitor comprises a first sub-capacitor and a second sub-capacitor in a parallel structure, the first sub-capacitor comprises the fourth plate as a first terminal of the first sub-capacitor and the fifth plate as a second terminal of the first sub-capacitor, the second sub-capacitor comprises the sixth plate as a first terminal of the second sub-capacitor and the fifth plate as a second terminal of the second sub-capacitor; the fifth plate is disposed in the semiconductor layer, a footprint of the fifth plate on the base at least partially overlaps a footprint of the fourth plate on the base, the fifth plate is connected to the third connection electrode; in at least one circuit unit, the sixth plate is disposed in the third conductive layer, a footprint of the sixth plate on the base at least partially overlaps a footprint of the fifth plate on the base, the sixth plate is connected to the fourth plate through a plate connection strip and a sixth connection electrode.

[0017] In an exemplary embodiment, in at least one circuit unit, a first terminal of the sixth connection electrode is connected to the fourth plate, a second terminal of the sixth connection electrode is connected to the plate connection strip, the sixth plate and the plate connection strip are an integrated structure connected to each other.

[0018] In an exemplary embodiment, in at least one circuit unit, a footprint of the sixth plate on the base is within a range of a footprint of the fifth plate on the base.

[0019] In an exemplary embodiment, the display substrate further comprises a third conductive layer disposed on a side of the semiconductor layer distal to the base; the first capacitor at least comprises the second plate as a first terminal of the first capacitor and the seventh plate as a second terminal of the first capacitor, the second capacitor at least comprises the fourth plate as a first terminal of the second capacitor and the seventh plate as a second terminal of the second capacitor, the third capacitor at least comprises the fourth plate as a first terminal of the third capacitor and the fifth plate as a second terminal of the third capacitor; the second plate is disposed in the first conductive layer, the seventh plate is disposed in the second conductive layer, the fifth plate is disposed in the semiconductor layer, the fourth plate is disposed in the third conductive layer; the seventh plate having the second node potential and the second plate having the third node potential form the first capacitor, the seventh plate having the second node potential and the fourth plate having the first node potential form the second capacitor, the fourth plate having the first node potential and the fifth plate having the third node potential form the third capacitor.

[0020] In an example embodiment, the display substrate further comprises a third conductive layer disposed on a side of the semiconductor layer distal to the base; the first capacitor comprises at least a second plate as a first terminal of the first capacitor and a seventh plate as a second terminal of the first capacitor, the second capacitor comprises at least a fourth plate as a first terminal of the second capacitor and the seventh plate as a second terminal of the second capacitor, the third capacitor comprises a third sub-capacitor and a fourth sub-capacitor, the third sub-capacitor comprises at least the fourth plate as a first terminal of the third sub-capacitor and a fifth plate as a second terminal of the third sub-capacitor, the fourth sub-capacitor comprises at least the fourth plate as a first terminal of the fourth sub-capacitor and the second plate as a second terminal of the third sub-capacitor; the second plate is disposed in the first conductive layer, the seventh plate is disposed in the second conductive layer, the fifth plate is disposed in the semiconductor layer, and the fourth plate is disposed in the third conductive layer; the seventh plate having the second node potential and the second plate having the third node potential form the first capacitor, the seventh plate having the second node potential and the fourth plate having the first node potential form the second capacitor, the fourth plate having the first node potential and the fifth plate having the third node potential form the third sub-capacitor, the fourth plate having the first node potential and the second plate having the third node potential form the fourth sub-capacitor, and the third sub-capacitor and the fourth sub-capacitor in parallel form the third capacitor.

[0021] In an exemplary embodiment, the display substrate further comprises a third conductive layer disposed on a side of the semiconductor layer distal to the substrate, and a fourth conductive layer disposed on a side of the third conductive layer distal to the substrate; the first capacitor comprises at least a second plate as a first terminal of the first capacitor and a seventh plate as a second terminal of the first capacitor, the second capacitor comprises at least a fifth sub-capacitor and a sixth sub-capacitor, the fifth sub-capacitor comprises a fourth plate as a first terminal of the fifth sub-capacitor and the seventh plate as a second terminal of the fifth sub-capacitor, the sixth sub-capacitor comprises the fourth plate as a first terminal of the sixth sub-capacitor and an eighth plate as a second terminal of the sixth sub-capacitor, and the third capacitor comprises at least the fourth plate as a first terminal of the third capacitor and a fifth plate as a second terminal of the third capacitor; the second plate is disposed in the first conductive layer, the seventh plate is disposed in the second conductive layer, the fifth plate is disposed in the semiconductor layer, the fourth plate is disposed in the third conductive layer, the eighth plate is disposed in the fourth conductive layer and is connected to the seventh plate; the seventh plate having the second node potential and the second plate having the third node potential form the first capacitor, the seventh plate having the second node potential and the fourth plate having the first node potential form the fifth sub-capacitor, the eighth plate having the second node potential and the fourth plate having the first node potential form the sixth sub-capacitor, the fifth sub-capacitor and the sixth sub-capacitor in parallel structure constitute the second capacitor, and the fourth plate having the first node potential and the fifth plate having the third node potential form the third capacitor.

[0022] In an exemplary embodiment, the display substrate further comprises a third conductive layer disposed on a side of the semiconductor layer distal to the substrate and a fourth conductive layer disposed on a side of the third conductive layer distal to the substrate; the first capacitor comprises at least a second plate as a first terminal of the first capacitor and a seventh plate as a second terminal of the first capacitor, the second capacitor comprises at least a fifth sub-capacitor and a sixth sub-capacitor, the fifth sub-capacitor comprises a fourth plate as a first terminal of the fifth sub-capacitor and the seventh plate as a second terminal of the fifth sub-capacitor, the sixth sub-capacitor comprises the fourth plate as a first terminal of the sixth sub-capacitor and an eighth plate as a second terminal of the sixth sub-capacitor, the third capacitor comprises a third sub-capacitor and a fourth sub-capacitor, the third sub-capacitor comprises at least the fourth plate as a first terminal of the third sub-capacitor and a fifth plate as a second terminal of the third sub-capacitor, the fourth sub-capacitor comprises at least the fourth plate as a first terminal of the fourth sub-capacitor and the second plate as a second terminal of the third sub-capacitor; the second plate is disposed in the first conductive layer, the seventh plate is disposed in the second conductive layer, the fifth plate is disposed in the semiconductor layer, the fourth plate is disposed in the third conductive layer, the eighth plate is disposed in the fourth conductive layer and connected to the seventh plate; the seventh plate having the second node potential and the second plate having the third node potential form the first capacitor, the seventh plate having the second node potential and the fourth plate having the first node potential form the fifth sub-capacitor, the eighth plate having the second node potential and the fourth plate having the first node potential form the sixth sub-capacitor, the fifth sub-capacitor and the sixth sub-capacitor in parallel form the second capacitor, the fourth plate having the first node potential and the fifth plate having the third node potential form the third sub-capacitor, the fourth plate having the first node potential and the second plate having the third node potential form the fourth sub-capacitor, and the third sub-capacitor and the fourth sub-capacitor in parallel form the third capacitor.

[0023] In another aspect, the present disclosure also provides a display substrate, comprising a plurality of circuit units, at least one of which comprises a pixel driving circuit, the pixel driving circuit comprising at least a first capacitor, a second capacitor, a third capacitor, a first transistor as a first reset transistor, a second transistor as a second reset transistor, and a third transistor as a driving transistor, a first end of the second capacitor and a first end of the third capacitor being connected to a second electrode of the first transistor and a gate electrode of the third transistor, a second end of the first capacitor and a second end of the second capacitor being connected to a second electrode of the second transistor, a first end of the first capacitor and a second end of the third capacitor being connected to a second electrode of the third transistor, a first electrode of the first transistor and a first electrode of the second transistor being connected to a first initial signal line.

[0024] In another aspect, the present disclosure also provides a display device comprising the aforementioned display substrate.

[0025] Other aspects can become apparent from a review of the drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0026] The accompanying drawings are included to provide a further understanding of the present disclosure, and constitute a part of this specification that is included to illustrate the technical solutions of the present disclosure, and together with the embodiments of the present disclosure, serve to explain the technical solutions of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure.

[0027] FIG. 1 is a structural schematic diagram of a display device;

[0028] FIG. 2 is a planar structural schematic diagram of a display substrate;

[0029] FIG. 3 is a cross-sectional structural schematic diagram of a display substrate;

[0030] FIG. 4 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0031] FIG. 5 is a driving timing diagram of the pixel driving circuit shown in FIG. 4;

[0032] FIG. 6 is a structural schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0033] FIG. 7 is a schematic diagram of a capacitor structure according to an exemplary embodiment of the present disclosure;

[0034] FIG. 8 is a cross-sectional view along A-A in FIG. 6;

[0035] FIG. 9 is a schematic diagram of a display substrate after forming a first conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0036] FIGS. 10A and 10B are schematic diagrams of a display substrate after forming a second conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0037] FIGS. 11A and 11B are schematic diagrams of a display substrate after forming a semiconductor layer pattern according to an embodiment of the present disclosure;

[0038] FIGS. 12A and 12B are schematic diagrams of a display substrate after forming a third conductive layer pattern according to an embodiment of the present disclosure;

[0039] FIG. 13 is a schematic diagram of a display substrate after forming a fourth insulating layer pattern according to an embodiment of the present disclosure;

[0040] FIGS. 14A and 14B are schematic diagrams of a display substrate after forming a fourth conductive layer pattern according to an embodiment of the present disclosure;

[0041] FIG. 15 is a schematic diagram of a display substrate after forming a fifth insulating layer and a first planarization layer pattern according to an embodiment of the present disclosure;

[0042] FIGS. 16A and 16B are schematic diagrams of a display substrate after forming a fifth conductive layer pattern according to an embodiment of the present disclosure;

[0043] FIG. 17 is a schematic diagram of a meshed interconnection structure according to an embodiment of the present disclosure;

[0044] FIG. 18 is a schematic diagram of another display substrate according to an embodiment of the present disclosure;

[0045] FIG. 19 is a schematic diagram of another capacitor structure according to an embodiment of the present disclosure;

[0046] FIG. 20 is a sectional view taken along line B-B of FIG. 18;

[0047] FIGS. 21A and 21B are schematic diagrams of a display substrate after forming a third conductive layer pattern according to another embodiment of the present disclosure;

[0048] FIG. 22 is a schematic diagram of another capacitor structure according to an embodiment of the present disclosure;

[0049] FIG. 23 is a schematic diagram of another capacitor structure according to an embodiment of the present disclosure;

[0050] FIG. 24 is a schematic diagram of another capacitor structure according to an embodiment of the present disclosure;

[0051] FIG. 25 is a schematic diagram of another capacitor structure according to an embodiment of the present disclosure.

[0052] Explanation of Reference Numerals:

[0053] 10 - first capacitor; 11 - first plate; 12 - second plate;

[0054] 13 - third plate; 14 - fourth plate; 15 - fifth plate;

[0055] 16 - sixth plate; 17 - seventh plate; 18 - eighth plate;

[0056] 20 - second capacitor; 21 - first active layer; 22 - second active layer;

[0057] 23 - third active layer; 24 - fourth active layer; 25 - fifth active layer;

[0058] 26 - sixth active layer; 27 - seventh active layer; 28 - active connection strip;

[0059] 30 - third capacitor; 31 - first gate electrode; 32 - second gate electrode;

[0060] 33 - third gate electrode; 34 - fourth gate electrode; 37 - seventh gate electrode;

[0061] 38 - plate connection strip; 41 - first light-emitting signal line; 42 - second light-emitting signal line;

[0062] 51 - first connection electrode; 52 - second connection electrode; 53 - third connection electrode;

[0063] 54 - fourth connection electrode; 55 - fifth connection electrode; 56 - sixth connection electrode;

[0064] 61 - first scan signal line; 62 - second scan signal line; 63 - third scan signal line;

[0065] 64 - fourth scan signal line; 65 - first power supply connection line; 66 - second power supply connection line;

[0066] 71 - first initial signal line; 72 - second initial signal line; 73 - first initial connection line;

[0067] 74 - second initial connection line; 81 - first power supply line; 82 - second power supply line;

[0068] 83 - data signal line; 84 - anode connection electrode; 91 - first insulating layer;

[0069] 92 - second insulating layer; 93 - third insulating layer; 94 - fourth insulating layer;

[0070] 101 - substrate; 102 - driving structure layer; 103 - light emitting structure layer;

[0071] 104 - encapsulation structure layer. DETAILED DESCRIPTION

[0072] In order to make the objects, technical solutions and advantages of the present disclosure clearer, below the embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the embodiments can be implemented in a variety of different forms. One of ordinary skill in the art can easily understand that the means and content can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the content described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other as long as there is no conflict.

[0073] The scale of the drawings in the present disclosure can be used as a reference in the actual process, but is not limited thereto. For example, the width-length ratio of the channel, the thickness and interval of each film layer, and the width and interval of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the number shown in the drawings. The drawings described in the present disclosure are only schematic diagrams, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0074] The ordinal numbers "first", "second", "third" and the like in the present specification are set in order to avoid confusion of the components, and are not intended to be limiting in terms of numbers.

[0075] In this specification, terms of "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicating the positional or directional relationship of components are used to describe the positional relationship of components with reference to the drawings for the convenience of explanation and simplification of the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be construed as limiting on the present disclosure. The positional relationship of components is appropriately changed according to the direction in which each component is described. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0076] In this specification, unless explicitly defined and limited otherwise, the terms "mount", "connected", "connected" should be broadly understood. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate, or communication between two elements. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0077] In this specification, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region through which current mainly flows.

[0078] In this specification, the first electrode can be a drain electrode, and the second electrode can be a source electrode, or the first electrode can be a source electrode, and the second electrode can be a drain electrode. In the case of using a transistor with opposite polarity or in the case of changing the direction of current in the circuit during operation, the functions of "source electrode" and "drain electrode" are sometimes exchanged with each other. Therefore, in this specification, "source electrode" and "drain electrode" can be exchanged with each other, and "source terminal" and "drain terminal" can be exchanged with each other.

[0079] In this specification, "electrically connected" includes the case where components are connected together through an element having some electrical action. The element having some electrical action is not particularly limited as long as it can transmit and receive an electrical signal between the components to be connected. Examples of the element having some electrical action include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0080] In this specification, "parallel" means a state where the angle formed by two straight lines is -10° or more and 10° or less, and thus, an angle of -5° or more and 5° or less is also included. In addition, "perpendicular" means a state where the angle formed by two straight lines is 80° or more and 100° or less, and thus, an angle of 85° or more and 95° or less is also included.

[0081] In this specification, "film" and "layer" can be interchanged with each other. For example, "conductive layer" can be sometimes interchanged with "conductive film". Similarly, "insulating film" can be sometimes interchanged with "insulating layer".

[0082] In this specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, and the like are not strictly so, and can be an approximate triangle, an approximate rectangle, an approximate trapezoid, an approximate pentagon, or an approximate hexagon, and can include some small deformation due to a tolerance, can include a rounded corner, a rounded side, and deformation, and the like. In this disclosure, "about" means not strictly limited to a boundary, and allows a value within a range of a process and a measurement error.

[0083] FIG. 1 is a structural schematic diagram of a display device. As shown in FIG. 1, the display device can include a timing controller, a data driver, a scan driver, a light emitting driver, and a pixel array, the timing controller is connected with the data driver, the scan driver, and the light emitting driver respectively, the data driver is connected with a plurality of data signal lines (D1 to Dn) respectively, the scan driver is connected with a plurality of scan signal lines (S1 to Sm) respectively, and the light emitting driver is connected with a plurality of first light emitting signal lines (E1 to Eo) respectively. The pixel array can include a plurality of sub-pixels Pxij, i and j can be natural numbers, at least one sub-pixel Pxij can include a circuit unit and a light emitting unit, the circuit unit can include at least a pixel driving circuit, the pixel driving circuit is connected with the scan signal line, the first light emitting signal line, and the data signal line respectively, and the light emitting unit can include a light emitting device connected with the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller can provide a gray value and a control signal suitable for the specification of the data driver to the data driver, can provide a clock signal, a scan start signal, and the like suitable for the specification of the scan driver to the scan driver, and can provide a clock signal, an emission stop signal, and the like suitable for the specification of the light emitting driver to the light emitting driver. The data driver can generate data voltages to be provided to the data signal lines D1, D2, D3, …, and Dn by using the gray value and the control signal received from the timing controller. For example, the data driver can sample the gray value by using the clock signal, and apply data voltages corresponding to the gray value to the data signal lines D1 to Dn in units of a pixel row. n can be a natural number. The scan driver can generate scan signals to be provided to the scan signal lines S1, S2, S3, …, and Sm by receiving the clock signal, the scan start signal, and the like from the timing controller. For example, the scan driver can sequentially provide the scan signal having an on-level pulse to the scan signal lines S1 to Sm. For example, the scan driver can be configured in the form of a shift register, and can generate the scan signal in a manner that sequentially transfers the scan start signal provided in the form of an on-level pulse to a next stage circuit under the control of the clock signal. m can be a natural number. The light emitting driver can generate emission signals to be provided to the first light emitting signal lines E1, E2, E3, …, and Eo by receiving the clock signal, the emission stop signal, and the like from the timing controller. For example, the light emitting driver can sequentially provide the emission signal having an off-level pulse to the first light emitting signal lines E1 to Eo. For example, the light emitting driver can be configured in the form of a shift register, and can generate the emission signal in a manner that sequentially transfers the emission stop signal provided in the form of an off-level pulse to a next stage circuit under the control of the clock signal. o can be a natural number. In an exemplary embodiment, the pixel array can be disposed on a display substrate.

[0084] FIG. 2 is a schematic diagram of a planar structure of a display substrate. As shown in FIG. 2, the display substrate can include a plurality of pixel units P arranged in a matrix manner, and at least one pixel unit P can include a first sub-pixel P1, a second sub-pixel P2 and a third sub-pixel P3. Each sub-pixel can include a circuit unit and a light-emitting unit, and the circuit unit can include at least a pixel driving circuit. The pixel driving circuit is connected with a scan signal line, a light-emitting signal line and a data signal line respectively, and is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit can include a light-emitting device connected with the pixel driving circuit of the sub-pixel where the light-emitting device is located, and the light-emitting device is configured to emit light with a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel where the light-emitting device is located.

[0085] In an example embodiment, the first sub-pixel P1 can be a red sub-pixel (R) emitting red light, the second sub-pixel P2 can be a green sub-pixel (G) emitting green light, and the third sub-pixel P3 can be a blue sub-pixel (B) emitting blue light. In an example embodiment, the shape of the sub-pixel can be rectangular, diamond, pentagonal or hexagonal, and the three sub-pixels can be arranged in a horizontal parallel, vertical parallel or triangular manner.

[0086] In other example embodiments, the pixel unit can include four sub-pixels, and the four sub-pixels can be arranged in a horizontal parallel, vertical parallel or square manner, which is not limited in the present disclosure.

[0087] FIG. 3 is a schematic diagram of a cross-sectional structure of a display substrate, illustrating the structure of three sub-pixels in the display substrate. As shown in FIG. 3, in a plane perpendicular to the display substrate, the display area can include a driving structure layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on a side of the driving structure layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display area can include other film layers, such as a touch structure layer, which is not limited in the present disclosure.

[0088] In the example embodiment, the substrate 101 can be a flexible substrate or a rigid substrate. The driving structure layer 102 can include a plurality of circuit units, each of which can include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 can include a plurality of light-emitting units, each of which can include a light-emitting device, which can include at least an anode, an organic light-emitting layer, and a cathode, the anode being connected to the pixel driving circuit, the organic light-emitting layer being connected to the anode, and the cathode being connected to the organic light-emitting layer, the organic light-emitting layer emitting light of a corresponding color under the driving of the anode and the cathode. The encapsulation structure layer 104 can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together, the first encapsulation layer and the third encapsulation layer can be made of inorganic material, and the second encapsulation layer can be made of organic material, the second encapsulation layer being arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can prevent external water vapor from entering the light-emitting structure layer 103.

[0089] The example embodiment of the present disclosure provides a display substrate. In the example embodiment, the display substrate can include a plurality of circuit units, at least one of which includes a pixel driving circuit, the pixel driving circuit including at least a first capacitor, a second capacitor, a third capacitor, a first connection electrode having a first node potential, a second connection electrode having a second node potential, and a third connection electrode having a third node potential, the first end of the second capacitor and the first end of the third capacitor being connected to the first connection electrode, the second end of the first capacitor and the second end of the second capacitor being connected to the second connection electrode, the first end of the first capacitor and the second end of the third capacitor being connected to the third connection electrode, the first capacitor, the second capacitor, and the third capacitor each including at least two capacitor plates stacked together; in a direction perpendicular to the display substrate, the display substrate includes at least a first conductive layer arranged on a substrate, a second conductive layer arranged on a side of the first conductive layer away from the substrate, and a semiconductor layer arranged on a side of the second conductive layer away from the substrate; in at least one of the circuit units, one of the capacitor plates of the third capacitor is arranged in the semiconductor layer.

[0090] In the example embodiment, the display substrate further includes a third conductive layer arranged on a side of the semiconductor layer away from the substrate, and a fourth conductive layer arranged on a side of the third conductive layer away from the substrate, the other capacitor plate of the third capacitor is arranged in at least one of the conductive layers and shares one of the capacitor plates in the first capacitor or one of the capacitor plates in the second capacitor.

[0091] In an exemplary embodiment, the first capacitor at least includes a first plate as a second end of the first capacitor and a second plate as a first end of the first capacitor, the second capacitor at least includes a third plate as a second end of the second capacitor and a fourth plate as a first end of the second capacitor, the first plate and the third plate are disposed in the first conductive layer, the second plate and the fourth plate are disposed in the second conductive layer, a normal projection of the second plate on the substrate at least partially overlaps a normal projection of the first plate on the substrate, a normal projection of the fourth plate on the substrate at least partially overlaps a normal projection of the third plate on the substrate; the first plate is connected with the third plate, the third plate is connected with the second connection electrode, the second plate is connected with the third connection electrode, and the fourth plate is connected with the first connection electrode.

[0092] In an exemplary embodiment, the third capacitor includes the fourth plate as a first end of the third capacitor and a fifth plate as a second end of the third capacitor; the fifth plate is disposed in the semiconductor layer, a normal projection of the fifth plate on the substrate at least partially overlaps a normal projection of the fourth plate on the substrate, and the fifth plate is connected with the third connection electrode.

[0093] In an exemplary embodiment, the third capacitor includes a first sub-capacitor and a second sub-capacitor in a parallel structure, the first sub-capacitor includes the fourth plate as a first end of the first sub-capacitor and a fifth plate as a second end of the first sub-capacitor, and the second sub-capacitor includes a sixth plate as a first end of the second sub-capacitor and the fifth plate as a second end of the second sub-capacitor; the fifth plate is disposed in the semiconductor layer, a normal projection of the fifth plate on the substrate at least partially overlaps a normal projection of the fourth plate on the substrate, and the fifth plate is connected with the third connection electrode; the sixth plate is disposed in the third conductive layer, a normal projection of the sixth plate on the substrate at least partially overlaps a normal projection of the fifth plate on the substrate, and the sixth plate is connected with the fourth plate through a plate connection strip and a sixth connection electrode.

[0094] The display substrate of the present embodiment is illustrated below by some examples.

[0095] The display substrate provided by the exemplary embodiments of the present disclosure can include at least a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate in a direction perpendicular to the display substrate. In a plane parallel to the display substrate, the driving structure layer can include a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, the circuit units can include at least a pixel driving circuit, and the light-emitting structure layer can include a plurality of light-emitting units, the light-emitting units can include at least a light-emitting device, at least one pixel driving circuit is connected with at least one light-emitting unit, and the pixel driving circuit is configured to provide a driving signal to the connected light-emitting device to drive the corresponding light-emitting device to emit light.

[0096] In the exemplary embodiments, the circuit unit refers to an area divided according to the pixel driving circuit, and the light-emitting unit refers to an area divided according to the light-emitting device. In the exemplary embodiments, the position of the light-emitting unit orthogonally projected on the substrate can correspond to the position of the circuit unit orthogonally projected on the substrate, or the position of the light-emitting unit orthogonally projected on the substrate can not correspond to the position of the circuit unit orthogonally projected on the substrate.

[0097] FIG. 4 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure. As shown in FIG. 4, the pixel driving circuit according to the exemplary embodiment of the present disclosure adopts a 7T3C structure, each pixel driving circuit can include 7 transistors (a first transistor T1 to a seventh transistor T7) and 3 capacitors (a first capacitor C1, a second capacitor C2 and a third capacitor C3), and the pixel driving circuit is connected with 10 signal lines (a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a fourth scan signal line S4, a first light-emitting signal line EM1, a second light-emitting signal line EM2, a first initial signal line INIT1, a second initial signal line INIT2, a data signal line DATA and a first power supply line VDD).

[0098] In an example embodiment, the pixel driving circuit can include a first node N1, a second node N2, a third node N3, a fourth node N4, and a fifth node N5. The first node N1 is connected to the second electrode of the first transistor T1, the gate electrode of the third transistor T3, the second electrode of the fourth transistor T4, the first end of the second capacitor C2, and the first end of the third capacitor C3, respectively. The second node N2 is connected to the second electrode of the second transistor T2, the second end of the first capacitor C1, and the second end of the second capacitor C2, respectively. The third node N3 is connected to the second electrode of the third transistor T3, the first electrode of the sixth transistor T6, the first end of the first capacitor C1, and the second end of the third capacitor C3, respectively. The fourth node N4 is connected to the first electrode of the third transistor T3 and the second electrode of the fifth transistor T5, respectively. The fifth node N5 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, respectively.

[0099] In an example embodiment, the first transistor T1 can be referred to as a first reset transistor. The gate electrode of the first transistor T1 is connected to the first scan signal line S1. The first electrode of the first transistor T1 is connected to the first initial signal line INIT1. The second electrode of the first transistor T1 is connected to the first node N1.

[0100] In an example embodiment, the second transistor T2 can be referred to as a second reset transistor. The gate electrode of the second transistor T2 is connected to the second scan signal line S2. The first electrode of the second transistor T2 is connected to the first initial signal line INIT1. The second electrode of the second transistor T2 is connected to the second node N2.

[0101] In an example embodiment, the third transistor T3 can be referred to as a driving transistor. The gate electrode of the third transistor T3 is connected to the first node N1. The first electrode of the third transistor T3 is connected to the fourth node N4. The second electrode of the third transistor T3 is connected to the third node N3.

[0102] In an example embodiment, the fourth transistor T4 can be referred to as a data write transistor. The gate electrode of the fourth transistor T4 is connected to the fourth scan signal line S4. The first electrode of the fourth transistor T4 is connected to the data signal line DATA. The second electrode of the fourth transistor T4 is connected to the first node N1.

[0103] In an example embodiment, the fifth transistor T5 can be referred to as a first light emitting control transistor. The gate electrode of the fifth transistor T5 is connected to the first light emitting signal line EM1. The first electrode of the fifth transistor T5 is connected to the first power supply line VDD. The second electrode of the fifth transistor T5 is connected to the fourth node N4.

[0104] In an exemplary embodiment, the sixth transistor T6 can be referred to as a second light-emitting control transistor, the gate electrode of the sixth transistor T6 is connected with the second light-emitting signal line EM2, the first electrode of the sixth transistor T6 is connected with the third node N3, and the second electrode of the sixth transistor T6 is connected with the fifth node N5.

[0105] In an exemplary embodiment, the seventh transistor T7 can be referred to as a third reset transistor, the gate electrode of the seventh transistor T7 is connected with the third scan signal line S3, the first electrode of the seventh transistor T7 is connected with the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected with the fifth node N5.

[0106] In an exemplary embodiment, the first end of the first capacitor C1 is connected with the third node N3, and the second end of the first capacitor C1 is connected with the second node N2. The first end of the second capacitor C2 is connected with the first node N1, and the second end of the second capacitor C2 is connected with the second node N2. The first end of the third capacitor C3 is connected with the first node N1, and the second end of the third capacitor C3 is connected with the third node N3.

[0107] In an exemplary embodiment, the first electrode of the light-emitting device EL is connected with the fifth node N5, and the second electrode of the light-emitting device EL is connected with the second power supply line VSS. The light-emitting device EL can be an OLED including a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked, or can be a QLED including a first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode) stacked.

[0108] In an exemplary embodiment, the seven transistors of the pixel driving circuit can be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product.

[0109] In an exemplary embodiment, the seven transistors of the pixel driving circuit can all be oxide transistors. The active layer of the oxide transistor can be an oxide semiconductor (Oxide). The oxide transistor has the advantages of high electron mobility, low operating voltage, low leakage characteristics, etc. Using the display substrate provided with the oxide transistor can realize low-frequency driving, can reduce power consumption, and can improve display quality.

[0110] In an example embodiment, the first power supply line VDD can be configured to provide a constant first voltage signal to the pixel driving circuit, the second power supply line VSS can be configured to provide a constant second voltage signal to the light emitting device, and the voltage of the first voltage signal is greater than the voltage of the second voltage signal, i.e., the first voltage signal is a high-level signal and the second voltage signal is a low-level signal. The first initial signal line INIT1 and the second initial signal line INIT2 can be configured to provide a constant signal to the pixel driving circuit, which is not limited in the present disclosure.

[0111] FIG. 5 is a driving timing diagram of the pixel driving circuit shown in FIG. 4. As shown in FIG. 5, the working process of the pixel driving circuit can include:

[0112] The first stage A1 is called a reset stage. The signals of the first scan signal line S1, the second scan signal line S2, the third scan signal line S3 and the second emission signal line EM2 are high-level signals, and the signals of the fourth scan signal line S4 and the first emission signal line EM1 are low-level signals, so that the first transistor T1, the second transistor T2, the sixth transistor T6 and the seventh transistor T7 are turned on, and the other switch transistors are turned off.

[0113] The conduction of the first transistor T1 and the second transistor T2 enables the first initial signal provided by the first initial signal line INIT1 to be provided to the first node N1 and the second node N2, so that the first node N1 and the second node N2 are initialized, and the potentials of the first node N1 and the second node N2 are Vinit1. The conduction of the sixth transistor T6 and the seventh transistor T7 enables the second initial signal provided by the second initial signal line INIT2 to be provided to the third node N3 and the fifth node N5, so that the third node N3 and the fifth node N5 are initialized, and the potentials of the third node N3 and the fifth node N5 are Vinit2. At the same time, the third transistor T3 is turned on by the voltage difference (Vinit1-Vinit2) between the first node N1 and the third node N3, so that the third node N3 and the fourth node N4 are connected, and the fourth node N4 is initialized, and the potential of the fourth node N4 is Vinit2.

[0114] In an example embodiment, Vinit1 is the voltage of the first initial signal, and Vinit2 is the voltage of the second initial signal. For example, Vinit1 can be 1.5V to 3.5V, and Vinit2 can be 0.5V to 2.5V. For another example, Vinit1 can be about 2.5V or so, and Vinit2 can be about 1.5V or so.

[0115] In the example embodiment, the reset of the first node N1, the second node N2, the third node N3 and the fifth node N5 can be performed in stages. For example, at the first time, the first scan signal line S1 changes from a low level signal to a high level signal, the first transistor T1 is turned on, and the first node N1 is reset. At the second time, the third scan signal line S3 changes from a low level signal to a high level signal, the seventh transistor T7 is turned on, and the fifth node N5 is reset. At the third time, the second scan signal line S2 changes from a low level signal to a high level signal, the second transistor T2 is turned on, and the second node N2 is reset. At the fourth time, the second emission signal line EM2 changes from a low level signal to a high level signal, the sixth transistor T6 is turned on, and the third node N3 is reset.

[0116] The second stage A2 is called a compensation stage. The signals of the first scan signal line S1, the second scan signal line S2 and the first emission signal line EM1 are high level signals, and the signals of the third scan signal line S3, the fourth scan signal line S4 and the second emission signal line EM2 are low level signals, so that the first transistor T1, the second transistor T2 and the fifth transistor T5 are turned on, and the other switch transistors are turned off.

[0117] The turning on of the first transistor T1 and the second transistor T2 makes the potentials of the first node N1 and the second node N2 continue to be Vinit1, and the turning on of the fifth transistor T5 makes the first power signal output by the first power supply line VDD be written to the fourth node N4 through the turned-on fifth transistor T5. Since the third transistor T3 is turned on, the potential of the third node N3 gradually increases to Vinit1-Vth, where Vth is the threshold voltage of the third transistor T3. At this time, since the potential of the second node N2 is Vinit1, the potential stored by the first capacitor C1 is the threshold voltage Vth, that is, the threshold voltage Vth of the third transistor T3 is written to the first capacitor C1.

[0118] The third stage A3 is called a data writing stage. The signals of the first scan signal line S1 and the second scan signal line S2 change from high level signals to low level signals after a period of time, the signal of the fourth scan signal line S4 is a high level signal for a short time, and the signals of the third scan signal line S3, the first emission signal line EM1 and the second emission signal line EM2 are low level signals, so that the first transistor T1, the second transistor T2 and the fourth transistor T4 are turned on and then turned off.

[0119] At the first time, the first scan signal line S1 changes from a high level signal to a low level signal, the first transistor T1 is turned off, and the potential of the first node N1 is slightly fluctuated, but the potentials of the second node N2 and the third node N3 are less disturbed.

[0120] At the second moment, the signal of the fourth scan signal line S4 changes from a low level signal to a high level signal, the fourth transistor T4 is turned on, the data signal output by the data signal line DATA is written into the first node N1, that is, stored in the second capacitor C2, the potential of the first node N1 becomes Vd, and Vd is the voltage of the data signal output by the data signal line DATA. When the data signal is written into the first node N1, the second node N2 is stabilized at the Vinit1 potential because the second transistor T2 is turned on, so that the potential of the third node N3 is Vinit1-Vth. In addition, because the third transistor T3 between the first node N1 and the third node N3 is disconnected, the writing of the data signal into the first node N1 does not disturb the potential of the third node N3.

[0121] At the third moment, the second scan signal line S2 changes from a high level signal to a low level signal, the second transistor T2 is disconnected, and because the data writing has been completed at this time, the potential of the first node N1 does not change.

[0122] The fourth stage A4 is called the light emitting stage. The signals of the first emitting signal line EM1 and the second emitting signal line EM2 are high level signals, the signals of the first scan signal line S1, the second scan signal line S2, the third scan signal line S3 and the fourth scan signal line S4 are low level signals, and the fifth transistor T5 and the sixth transistor T6 are turned on.

[0123] At the first moment, the second emitting signal line EM2 changes from a low level signal to a high level signal, the sixth transistor T6 is turned on, the potential of the third node N3 is written into the fifth node N5, and the fifth node N5 is pre-charged in advance. At the second moment, the first emitting signal line EM1 changes from a low level signal to a high level signal, the fifth transistor T5 is turned on, and the first power supply signal output by the first power supply line VDD provides a driving voltage to the first electrode of the light emitting element EL through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, so as to drive the light emitting element EL to emit light.

[0124] The output current I of the third transistor T3 OLED satisfies the following formula: I OLED =1 / 2*K1*[Vd-[Vinit1-Vth]-Vth] 2 =1 / 2*K2*(Vd-Vinit1) 2 .

[0125] wherein K1 is a constant related to process and design.

[0126] According to the formula of the output current of the third transistor T3, it can be seen that the output current of the pixel driving circuit is irrelevant to the threshold voltage Vth of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the output current, and the control of the output current can be realized by controlling the voltage Vd of the data signal, so as to control the brightness of the light emitting device EL.

[0127] FIG. 6 is a structural schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure, which illustrates the structure of three circuit units. FIG. 7 is a schematic diagram of a capacitor structure according to an exemplary embodiment of the present disclosure, and FIG. 8 is a sectional view along A-A in FIG. 6. As shown in FIG. 6, FIG. 7 and FIG. 8, in a plane parallel to the display substrate, the display substrate can include a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit can include a pixel driving circuit, and a first light emitting signal line 41, a second light emitting signal line 42, a first scan signal line 61, a second scan signal line 62, a third scan signal line 63, a fourth scan signal line 64, a first initial signal line 71, a second initial signal line 72, a first power supply line (not shown) and a data signal line (not shown) connected to the pixel driving circuit. At least one pixel driving circuit can include at least a first capacitor 10, a second capacitor 20, a third capacitor 30, a first connection electrode 51 having a first node potential, a second connection electrode 52 having a second node potential, a third connection electrode 53 having a third node potential, a first transistor T1 as a first reset transistor, a second transistor T2 as a second reset transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first light emitting control transistor, a sixth transistor T6 as a second light emitting control transistor, and a seventh transistor T7 as a third reset transistor.

[0128] In the exemplary implementation, the first light emitting signal line 41 and the second light emitting signal line 42 are configured to provide a first light emitting control signal and a second light emitting control signal to the pixel driving circuit, respectively, the first scan signal line 61 to the fourth scan signal line 64 are configured to provide a first scan signal to a fourth scan signal to the pixel driving circuit, respectively, the first initial signal line 71 and the second initial signal line 72 are configured to provide a first initial signal and a second initial signal to the pixel driving circuit, respectively, the first power supply line is configured to provide a first power supply signal to the pixel driving circuit, and the data signal line is configured to provide a data signal to the pixel driving circuit.

[0129] In the exemplary embodiment, the first to seventh transistors T1 to T7 can be oxide transistors. The first capacitor 10 can include at least the first plate 11 as a second terminal of the first capacitor and the second plate 12 as a first terminal of the first capacitor, the second capacitor 20 can include at least the third plate 13 as a second terminal of the second capacitor and the fourth plate 14 as a first terminal of the second capacitor, and the third capacitor 30 can include at least the fourth plate 14 as a first terminal of the third capacitor and the fifth plate 15 as a second terminal of the third capacitor.

[0130] In the exemplary embodiment, the gate electrode of the first transistor T1 is connected to the first scan signal line 61, the first electrode of the first transistor T1 is connected to the first initial signal line 71, the second electrode of the first transistor T1 and the second electrode of the fourth transistor T4 are connected to each other and connected to the gate electrode of the third transistor T3 through the first connection electrode 51, and the gate electrode of the third transistor T3 is connected to the fourth plate 14 through the plate-level connection bar 38 and the sixth connection electrode. The gate electrode of the second transistor T2 is connected to the second scan signal line 62, the first electrode of the second transistor T2 is connected to the first initial signal line 71, and the second electrode of the second transistor T2 is connected to the first plate 11 and the third plate 13 through the second connection electrode 52, respectively. The first electrode of the third transistor T3 and the second electrode of the fifth transistor T5 are connected to each other, the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6 are connected to each other and connected to the second plate 12 through the third connection electrode 53. The gate electrode of the fourth transistor T4 is connected to the fourth scan signal line 64, and the first electrode of the fourth transistor T4 is connected to the data signal line. The gate electrode of the fifth transistor T5 is connected to the first emission signal line 41, and the first electrode of the fifth transistor T5 is connected to the first power supply line. The gate electrode of the sixth transistor T6 is connected to the second emission signal line 42, and the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 are connected to each other. The gate electrode of the seventh transistor T7 is connected to the third scan signal line 63, and the first electrode of the seventh transistor T7 is connected to the second initial signal line 72.

[0131] In the exemplary embodiment, the first scan signal line 61, the second scan signal line 62, the third scan signal line 63, the fourth scan signal line 64, the first emission signal line 41, the second emission signal line 42, the first initial signal line 71, and the second initial signal line 72 can have a shape of a straight line or a broken line in which a main body portion extends in the first direction X, and the first power supply line and the data signal line can have a shape of a straight line or a broken line in which a main body portion extends in the second direction Y.

[0132] In the present disclosure, A extending along the direction of B means that A can include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a bar-shaped body, the main part extends along the direction of B, and the length of the main part extending along the direction of B is greater than the length of the secondary part extending along other directions. In the following description, "A extending along the direction of B" means "the main part of A extending along the direction of B".

[0133] In the example embodiment, in the direction perpendicular to the display substrate, the display substrate can at least include a first conductive layer (a first gate metal layer) disposed on the base 101, a first insulating layer 91 disposed on the side of the first conductive layer away from the base 101, a second conductive layer (a second gate metal layer) disposed on the side of the first insulating layer 91 away from the base 101, a second insulating layer 92 disposed on the side of the second conductive layer away from the base 101, a semiconductor layer disposed on the side of the second insulating layer 92 away from the base 101, a third insulating layer 93 disposed on the side of the semiconductor layer away from the base 101, a third conductive layer (a third gate metal layer) disposed on the side of the third insulating layer 93 away from the base 101, a fourth insulating layer 94 disposed on the side of the third conductive layer away from the base 101, and a fourth conductive layer (a first source-drain metal layer) disposed on the side of the fourth insulating layer 94 away from the base 101.

[0134] In the example embodiment, the first plate 11 and the third plate 13 can be disposed in the first conductive layer, the first plate 11 and the third plate 13 can be an integrated structure connected to each other, and the first plate 11 and the third plate 13 of the integrated structure are connected to the first end of the second connecting electrode 52, and the second end of the second connecting electrode 52 is connected to the second electrode of the second transistor T2, that is, the first plate 11 and the third plate 13 can be connected to the second electrode of the second transistor T2 through the second connecting electrode 52. The first plate 11 can serve as the second end of the first capacitor 10, the third plate 13 can serve as the second end of the second capacitor 20, and the first plate 11 and the third plate 13 have a second node potential, which refers to the potential of the second node N2 in the pixel driving circuit.

[0135] In the example embodiment, the second plate 12 can be disposed in the second conductive layer, the second plate 12 is connected to the second end of the third connecting electrode 53, and the first end of the third connecting electrode 53 is connected to the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6, that is, the second plate 12 can be connected to the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6 through the third connecting electrode 53. The second plate 12 can serve as the first end of the first capacitor 10 and has a third node potential, which refers to the potential of the second node N3 in the pixel driving circuit.

[0136] In an exemplary embodiment, the second plate 12 has a first node potential, and the first plate 11 has a second node potential. The first plate 11 and the second plate 12 form a first capacitor C1 of the pixel driving circuit.

[0137] In an exemplary embodiment, the fourth plate 14 can be disposed in the second conductive layer. The fourth plate 14 can be connected to the second electrode of the first transistor T1 and the second electrode of the fourth transistor T4 through the sixth connection electrode 56, the plate connection strip 38, the third gate electrode 33, and the first connection electrode 51. The fourth plate 14 can serve as a first terminal of the second capacitor 20, and has a first node potential, which refers to the potential of the first node N1 in the pixel driving circuit.

[0138] In an exemplary embodiment, the first end of the first connection electrode 51 is connected to the second electrode of the first transistor T1 and the second electrode of the fourth transistor T4, and the second end of the first connection electrode 51 is connected to the third gate electrode 33 (the gate electrode of the third transistor T3). The third gate electrode 33 is connected to the fourth plate 14 through the plate connection strip 38 and the sixth connection electrode 56.

[0139] In an exemplary embodiment, the first end of the sixth connection electrode 56 is connected to the fourth plate 14, and the second end of the sixth connection electrode 56 is connected to the plate connection strip 38. The plate connection strip 38 is connected to the third gate electrode 33.

[0140] In an exemplary embodiment, in at least one circuit unit, the third gate electrode 33 and the plate connection strip 38 can be disposed in the third conductive layer and form an integrated structure.

[0141] In an exemplary embodiment, the fourth plate 14 has a first node potential, and the third plate 13 has a second node potential. The third plate 13 and the fourth plate 14 form a second capacitor C2 of the pixel driving circuit.

[0142] In an exemplary embodiment, the fifth plate 15 can be disposed in the semiconductor layer, and the fifth plate 15 can be connected to the second plate 12 through the third connection electrode 53. The fourth plate 14 can serve as a first terminal of the third capacitor 30 and has a first node potential. The fifth plate 15 can serve as a second terminal of the third capacitor 30 and has a third node potential. The fourth plate 14 serves as one capacitor plate of the second capacitor C2 and one capacitor plate of the third capacitor C3, i.e., the second capacitor C2 and the third capacitor C3 share the same capacitor plate.

[0143] In an exemplary embodiment, the first end of the third connection electrode 53 is connected with the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6, the second end of the third connection electrode 53 is connected with the second plate 12, the fifth plate 15 is connected with the first electrode of the sixth transistor T6, thus realizing the connection between the fifth plate 15 and the second plate 12, and the second plate 12 and the fifth plate 15 have the same third node potential.

[0144] In an exemplary embodiment, the sixth transistor T6 can at least include a sixth active layer, and the fifth plate 15 and the sixth active layer can be an integrated structure connected with each other.

[0145] In an exemplary embodiment, the orthogonal projection of the fifth plate 15 on the substrate at least partially overlaps with the orthogonal projection of the fourth plate 14 on the substrate, and the fourth plate 14 having the first node potential and the fifth plate 15 having the third node potential form a third capacitor C3 of the pixel driving circuit.

[0146] In an exemplary embodiment, the pixel driving circuits in part of the adjacent unit columns can be mirror-symmetrical relative to a column center line, and the column center line can be a fold line located between the adjacent unit columns and extending along the second direction Y. For example, the pixel driving circuits in the Nth unit column and the (N+1)th unit column can be mirror-symmetrical relative to the column center line. For another example, the pixel driving circuits in the (N+1)th unit column and the (N+2)th unit column can be mirror-symmetrical relative to the column center line.

[0147] In an exemplary embodiment, the pixel driving circuits in part of the adjacent unit columns can be substantially the same. For example, the pixel driving circuits in the Nth unit column and the (N+2)th unit column can be substantially the same.

[0148] In an exemplary embodiment, in at least one unit row, the active layers of the fifth transistors T5 of part of the two adjacent circuit units can be an integrated structure connected with each other, and the two circuit units can share the same first electrode of the fifth transistor T5.

[0149] In an exemplary embodiment, in at least one unit row, the active layers of the seventh transistors T7 of part of the two adjacent circuit units can be an integrated structure connected with each other, and the two circuit units can share the same first electrode of the seventh transistor T7.

[0150] In an exemplary embodiment, in at least one unit row, the gate electrodes of the first transistors T1 of part of the two adjacent circuit units can be an integrated structure connected with each other.

[0151] In an exemplary embodiment, in at least one unit row, the gate electrodes of the second transistors T2 of part of the two adjacent circuit units can be an integrated structure connected with each other.

[0152] In an exemplary embodiment, in at least one unit row, the gate electrodes of the fourth transistors T4 of two circuit units adjacent to each other can be integrated into one structure.

[0153] In an exemplary embodiment, the first light-emitting signal line 41 and the second light-emitting signal line 42 can be disposed in the third conductive layer, and the first scan signal line 61, the second scan signal line 62, the third scan signal line 63, and the fourth scan signal line 64 can be disposed in the fourth conductive layer.

[0154] In an exemplary embodiment, the display substrate can further include a fifth insulating layer disposed on the fourth conductive layer away from the base 101, a first planar layer disposed on the fifth insulating layer away from the base 101, and a fifth conductive layer (second source-drain metal layer) disposed on the first planar layer away from the base 101. The fifth conductive layer can include at least a first power supply line, a second power supply line, and a data signal line.

[0155] In an exemplary embodiment, the fourth conductive layer can further include a first power supply connection line 65 extending along the first direction X and connected to the first power supply line, and the first power supply connection line 65 and the first power supply line form a mesh communication structure for transmitting a first power supply signal on the display substrate.

[0156] In an exemplary embodiment, the fourth conductive layer can further include a second power supply connection line 66 extending along the first direction X and connected to the second power supply line, and the second power supply connection line 66 and the second power supply line form a mesh communication structure for transmitting a second power supply signal on the display substrate.

[0157] In an exemplary embodiment, the fifth conductive layer can further include a first initial connection line extending along the second direction Y and connected to the first initial signal line 71, and the first initial signal line 71 and the first initial connection line form a mesh communication structure for transmitting a first initial signal on the display substrate.

[0158] In an exemplary embodiment, the fifth conductive layer can further include a second initial connection line extending along the second direction Y and connected to the second initial signal line 72, and the second initial signal line 72 and the second initial connection line form a mesh communication structure for transmitting a second initial signal on the display substrate.

[0159] The preparation process of the substrate is exemplarily illustrated below by the present exemplary embodiment. The "patterning process" in the present disclosure includes deposition of a film layer, coating photoresist on the film layer, mask exposure, development, etching, stripping of photoresist, etc. for metal materials, inorganic materials or transparent conductive materials, and includes coating of organic materials, mask exposure and development, etc. for organic materials. The deposition can use any one or more of sputtering, evaporation, chemical vapor deposition, the coating can use any one or more of spraying, spin coating and inkjet printing, and the etching can use any one or more of dry etching and wet etching, which are not limited by the present disclosure. The "thin film" refers to a thin film of a certain material on a substrate made by deposition, coating or other processes. If the "thin film" does not need a patterning process during the entire production process, the "thin film" can also be referred to as a "layer". If the "thin film" needs a patterning process during the entire production process, it is referred to as a "thin film" before the patterning process and as a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed at the same time by the same patterning process. The "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps the boundary of the orthographic projection of B.

[0160] In the exemplary embodiments, taking three circuit units of one unit row and three unit columns (the Nth unit column, the N+1th unit column and the N+2th unit column) as an example, the preparation process of the substrate can include the following operations.

[0161] (11) Forming a first conductive layer pattern. In the exemplary embodiments, forming the first conductive layer pattern can include: depositing a first conductive thin film on the substrate, patterning the first conductive thin film by a patterning process, and forming a first conductive layer pattern on the substrate, as shown in FIG. 9. In the exemplary embodiments, the first conductive layer can be referred to as a first gate metal (GATE1) layer.

[0162] In the exemplary embodiments, the first conductive layer pattern of each circuit unit in the display substrate can at least include the first plate 11 of the first capacitor and the third plate 13 of the second capacitor.

[0163] In the exemplary embodiments, the shape of the first plate 11 of the first capacitor can be rectangular, and the first plate 11 is configured as one capacitor plate (the second end of the first capacitor C1) of the first capacitor.

[0164] In an example embodiment, the third plate 13 of the second capacitor can be rectangular in shape, and the third plate 13 is configured as one of the capacitor plates of the second capacitor (the second end of the second capacitor C2).

[0165] In an example embodiment, the third plate 13 can be disposed on one side of the first plate 11 in the second direction Y and connected to the first plate 11, i.e., the second end of the first capacitor C1 and the second end of the second capacitor C2 are connected to each other.

[0166] In an example embodiment, the first plate 11 and the third plate 13 can be an integrated structure connected to each other in at least one of the circuit units.

[0167] In an example embodiment, the first conductive layers in some adjacent unit columns can be mirror-symmetrical with respect to the column center line. For example, the first conductive layers in the Nth unit column and the (N+1)th unit column can be mirror-symmetrical with respect to the column center line. For another example, the first conductive layers in the (N+1)th unit column and the (N+2)th unit column can be mirror-symmetrical with respect to the column center line.

[0168] In an example embodiment, the first conductive layers in some adjacent unit columns can be substantially the same. For example, the first conductive layers in the Nth unit column and the (N+2)th unit column can be substantially the same.

[0169] (12) Forming a second conductive layer pattern. In an example embodiment, forming the second conductive layer pattern can include: sequentially depositing a first insulating thin film and a second conductive thin film on the substrate on which the aforementioned pattern is formed, patterning the second conductive thin film by a patterning process, forming a first insulating layer covering the first conductive layer pattern, and a second conductive layer pattern disposed on the first insulating layer, as shown in FIGS. 10A and 10B, FIG. 10B is a plan view of the second conductive layer in FIG. 10A. In an example embodiment, the second conductive layer can be referred to as a second gate metal (GATE2) layer.

[0170] In an example embodiment, the second conductive layer pattern of each circuit unit in the display substrate at least includes: a second plate 12 of the first capacitor and a fourth plate 14 of the second capacitor.

[0171] In an example embodiment, the second plate 12 of the first capacitor can be rectangular in shape, and the orthographic projection of the second plate 12 on the substrate at least partially overlaps the orthographic projection of the first plate 11 on the substrate, the second plate 12 is configured as the other capacitor plate of the first capacitor (the first end of the first capacitor C1), and the first plate 11 and the second plate 12 constitute the first capacitor C1 of the pixel driving circuit.

[0172] In an example embodiment, the orthographic projection of the second plate 12 on the substrate can be located within the orthographic projection of the first plate 11 on the substrate.

[0173] In an example embodiment, the fourth plate 14 of the second capacitor can be rectangular in shape, can be disposed on one side of the second plate 12 in the second direction Y, the orthographic projection of the fourth plate 14 on the substrate at least partially overlaps with the orthographic projection of the third plate 13 on the substrate, the fourth plate 14 is configured as another capacitor plate of the second capacitor (the first end of the second capacitor C2), and the third plate 13 and the fourth plate 14 constitute the second capacitor C2 of the pixel driving circuit.

[0174] In an example embodiment, the orthographic projection of the third plate 13 on the substrate can be located within the orthographic projection of the fourth plate 14 on the substrate.

[0175] In an example embodiment, the fourth plate 14 is also configured as a lower plate of the third capacitor (the first end of the third capacitor C3), and the fourth plate 14 and the fifth plate formed subsequently constitute the third capacitor C3 of the pixel driving circuit.

[0176] In an example embodiment, the corner (upper left corner) of the fourth plate 14 away from the second plate 12 can be provided with a recess, and the recess is configured to accommodate the seventeenth via hole formed subsequently.

[0177] In an example embodiment, the ratio of the area of the orthographic projection of the second plate 12 on the first plate 11 to the area of the orthographic projection of the fourth plate 14 on the third plate 13 can be about 0.95 to 1.05, i.e. the ratio of the capacitance value of the first capacitor to the capacitance value of the second capacitor can be about 0.95 to 1.05.

[0178] In an example embodiment, the area of the orthographic projection of the second plate 12 on the substrate and the area of the orthographic projection of the fourth plate 14 on the substrate can be substantially equal, i.e. the capacitance value of the first capacitor and the capacitance value of the second capacitor can be substantially equal. By setting the capacitance values of the first capacitor and the second capacitor to be substantially equal, the present disclosure is advantageous for stabilizing the voltage of the source node (third node N3) of the driving transistor in the compensation stage, for stabilizing the voltage of the gate node (first node N1) of the driving transistor in the data writing stage, for facilitating the voltage coupling jump (the coupling path is the third node N3 coupling the second node N2, and the second node N2 coupling the first node N1) of the source node to the gate node in the light emitting stage, and for stabilizing the voltage of each node.

[0179] By designing the two capacitor plates of the first capacitor and the two capacitor plates of the second capacitor to be rectangular in shape, the present disclosure can be advantageous for the stability of the process manufacturing and for approaching the theoretical capacitance value of the design.

[0180] In an example embodiment, the second conductive layers in the partially adjacent cell columns can be mirror symmetrical with respect to the column center line. For example, the second conductive layers in the Nth cell column and the N+1th cell column can be mirror symmetrical with respect to the column center line. For another example, the second conductive layers in the N+1th cell column and the N+2th cell column can be mirror symmetrical with respect to the column center line.

[0181] In an example embodiment, the second conductive layers in the partially adjacent cell columns can be substantially the same. For example, the second conductive layers in the Nth cell column and the N+2th cell column can be substantially the same.

[0182] (13) Forming a semiconductor layer pattern. In an example embodiment, forming a semiconductor layer pattern can include: on a substrate on which the aforementioned pattern is formed, sequentially depositing a second insulating thin film and a semiconductor thin film, patterning the semiconductor thin film by a patterning process, forming a second insulating layer covering the second conductive layer, and a semiconductor layer pattern disposed on the second insulating layer, as shown in FIGS. 11A and 11B, FIG. 11B being a plan view of the semiconductor layer in FIG. 11A.

[0183] In an example embodiment, the semiconductor layer pattern of each circuit unit in the display substrate can include a first active layer 21 of the first transistor T1 to a seventh active layer 27 of the seventh transistor T7, and the first active layer 21, the second active layer 22, and the fourth active layer 24 can be an integral structure connected to each other, and the third active layer 23, the fifth active layer 25, the sixth active layer 26, and the seventh active layer 27 can be an integral structure connected to each other.

[0184] In an example embodiment, in the first direction X, the first active layer 21, the second active layer 22, and the fourth active layer 24 can be located on the same side of the third active layer 23 in the first direction X. In the second direction Y, the first active layer 21, the second active layer 22, the sixth active layer 26, and the seventh active layer 27 can be located on one side of the third active layer 23 in the second direction Y, and the fifth active layer 25 can be located on the opposite side of the third active layer 23 in the second direction Y.

[0185] In an example embodiment, the second active layer 22 can be located on one side of the first active layer 21 in the second direction Y, and the fourth active layer 24 can be located on the opposite side of the first active layer 21 in the second direction Y, i.e., the second active layer 22 and the fourth active layer 24 can be located on both sides of the first active layer 21 in the second direction Y, respectively.

[0186] In an example embodiment, the sixth active layer 26 can be located on one side of the third active layer 23 in the second direction Y, the seventh active layer 27 can be located on one side of the sixth active layer 26 in the second direction Y, and the fifth active layer 25 can be located on the opposite side of the third active layer 23 in the second direction Y.

[0187] In the example embodiment, the first to fourth active layers 21 to 24 and the sixth active layer 26 can have a strip shape extending along the second direction Y, and the fifth active layer 25 and the seventh active layer 27 can have an "L" shape.

[0188] In the example embodiment, the active layer of each transistor can include a first region, a second region, and a channel region between the first region and the second region. In the example embodiment, the first region 21-1 of the first active layer and the first region 22-1 of the second active layer can be connected to each other, and the first region 21-1 of the first active layer can serve as the first region 22-1 of the second active layer. The second region 21-2 of the first active layer and the second region 24-2 of the fourth active layer can be connected to each other, and the second region 21-2 of the first active layer can serve as the second region 24-2 of the fourth active layer. The first region 23-1 of the third active layer and the second region 25-2 of the fifth active layer can be connected to each other, and the first region 23-1 of the third active layer can serve as the second region 25-2 of the fifth active layer. The second region 23-2 of the third active layer and the first region 26-1 of the sixth active layer can be connected to each other, and the second region 23-2 of the third active layer can serve as the first region 26-1 of the sixth active layer. The second region 26-2 of the sixth active layer and the second region 27-2 of the seventh active layer can be connected to each other, and the second region 26-2 of the sixth active layer can serve as the second region 27-2 of the seventh active layer. The second region 22-2 of the second active layer, the first region 24-1 of the fourth active layer, the first region 25-1 of the fifth active layer, and the first region 27-1 of the seventh active layer can be separately provided,

[0189] In the example embodiment, in at least one unit row, the first regions 25-1 of the fifth active layers in some adjacent circuit units can be connected to each other, the fifth active layers 25 of the two circuit units can be an integrated structure connected to each other, and the two circuit units can share the same first region 25-1 of the fifth active layer. For example, the fifth active layer 25 in the Nth unit column and the fifth active layer 25 in the N+1th unit column can be an integrated structure connected to each other. By providing that some adjacent circuit units share the first electrode of the fifth transistor T5, the present disclosure can effectively reduce the lateral wiring space, reduce the number of vias, reduce the occupied area of the pixel driving circuit, and facilitate the realization of high resolution.

[0190] In the example embodiment, in at least one unit row, the first regions 27-1 of the seventh active layers in some adjacent circuit units can be connected to each other, the seventh active layers 27 in two circuit units can be an integrated structure connected to each other, and the two circuit units can share the same first region 27-1 of the seventh active layer. For example, the seventh active layer 27 in the N+1 unit column and the seventh active layer 27 in the N+2 unit column can be an integrated structure connected to each other. By arranging the first poles of the seventh transistors T7 to be shared by some adjacent circuit units, the present disclosure can effectively reduce the lateral wiring space, reduce the number of vias, reduce the area occupied by the pixel driving circuit, and facilitate the realization of high resolution.

[0191] In the example embodiment, the first region 21-1 of the first active layer can be used as the first pole of the first transistor T1, the second region 21-2 of the first active layer can be used as the second pole of the first transistor T1, the first region 22-1 of the second active layer can be used as the first pole of the second transistor T2, the second region 22-2 of the second active layer can be used as the second pole of the second transistor T2, the first region 23-1 of the third active layer can be used as the first pole of the third transistor T3, the second region 23-2 of the third active layer can be used as the second pole of the third transistor T3, the first region 24-1 of the fourth active layer can be used as the first pole of the fourth transistor T4, the second region 24-2 of the fourth active layer can be used as the second pole of the fourth transistor T4, the first region 25-1 of the fifth active layer can be used as the first pole of the fifth transistor T5, the second region 25-2 of the fifth active layer can be used as the second pole of the fifth transistor T5, the first region 26-1 of the sixth active layer can be used as the first pole of the sixth transistor T6, the second region 26-2 of the sixth active layer can be used as the second pole of the sixth transistor T6, the first region 27-1 of the seventh active layer can be used as the first pole of the seventh transistor T7, and the second region 27-2 of the seventh active layer can be used as the second pole of the seventh transistor T7.

[0192] In the example embodiment, the semiconductor layer pattern of each circuit unit in the display substrate can further include a fifth plate 15. The fifth plate 15 can have a rectangular shape, the orthographic projection of the fifth plate 15 on the base at least partially overlaps the orthographic projection of the fourth plate 14 on the base, and the fifth plate 15 is configured as one of the capacitor poles of the third capacitor (the second end of the third capacitor C3). The fourth plate 14 and the fifth plate 15 constitute the third capacitor.

[0193] In the example embodiment, the fifth plate 15 can be arranged on one side of the first direction X of the sixth active layer 26 or on the side opposite to the first direction X, and connected to the first region 26-1 of the sixth active layer (also the second region 23-2 of the third active layer).

[0194] In the example embodiment, the third active layer 23, the fifth active layer 25, the sixth active layer 26, the seventh active layer 27, and the fifth plate 15 in the at least one circuit unit can be an integrated structure connected to each other.

[0195] In the example embodiment, the semiconductor layer pattern can further include an active connection strip 28. The active connection strip 28 can have a strip shape extending along the first direction X, can be arranged between part of the adjacent circuit units, a first end of the active connection strip 28 is connected to the first region 21-1 of the first active layer and the first region 22-1 of the second active layer in one circuit unit, a second end of the active connection strip 28 is connected to the first region 21-1 of the first active layer and the first region 22-1 of the second active layer in another circuit unit, and the active connection strip 28 is configured to simultaneously serve as the first region 21-1 of the first active layer and the first region 22-1 of the second active layer shared by the two circuit units.

[0196] In the example embodiment, in part of the adjacent unit columns, the active connection strip 28 and the first active layer 21 and the second active layer 22 in the two circuit units can be an integrated structure connected to each other. For example, the active connection strip 28 can be arranged between the N+1th unit column and the N+2th unit column, the first active layer 21 and the second active layer 22 in the N+1th unit column, the first active layer 21 and the second active layer 22 in the N+2th unit column, and the active connection strip 28 arranged between the N+1th unit column and the N+2th unit column can be an integrated structure connected to each other. The present disclosure can effectively reduce the wiring space, reduce the number of vias, reduce the occupied area of the pixel driving circuit, and facilitate the realization of high resolution by arranging part of the adjacent circuit units to share the first electrode of the first transistor T1 and the first electrode of the second transistor T2.

[0197] In the example embodiment, the orthographic projection of the third active layer 23 on the substrate at least partially overlaps the orthographic projection of the second plate 12 on the substrate, and the second plate 12 can also serve as the bottom gate electrode of the third transistor T3.

[0198] In the example embodiment, the semiconductor layers in part of the adjacent unit columns can be mirror symmetrical with respect to the column center line. For example, the semiconductor layers in the Nth unit column and the N+1th unit column can be mirror symmetrical with respect to the column center line. For another example, the semiconductor layers in the N+1th unit column and the N+2th unit column can be mirror symmetrical with respect to the column center line.

[0199] In the example embodiment, the semiconductor layers in part of the adjacent unit columns can be substantially the same. For example, the semiconductor layers in the Nth unit column and the N+2th unit column can be substantially the same.

[0200] In an example embodiment, the semiconductor layer can employ an oxide, i.e., the first transistor T1 to the seventh transistor T7 are oxide transistors, which have advantages of high electron mobility, low operating voltage, low leakage characteristics, etc. In an example embodiment, the oxide can be any one or more of indium gallium zinc oxide (InGaZnO), indium gallium zinc nitride oxide (InGaZnON), zinc oxide (ZnO), zinc nitride oxide (ZnON), zinc tin oxide (ZnSnO), cadmium tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), strontium copper oxide (SrCuO), lanthanum copper oxide sulfur oxide (LaCuOS), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium gallium aluminum nitride (InGaAlN). In some possible implementations, the semiconductor thin film can employ indium gallium zinc oxide (IGZO), which has a higher electron mobility than amorphous silicon.

[0201] (14) Forming a third conductive layer pattern. In an example embodiment, forming the third conductive layer pattern can include: on the substrate on which the aforementioned patterns are formed, sequentially depositing a third insulating thin film and a third conductive thin film, patterning the third conductive thin film by a patterning process, forming a third insulating layer covering the semiconductor layer pattern, and a third conductive layer pattern disposed on the third insulating layer, as shown in FIGS. 12A and 12B, which is a schematic view of the third conductive layer in FIG. 12A. In an example embodiment, the third conductive layer can be referred to as a third gate metal (GATE3) layer.

[0202] In an example embodiment, the third conductive layer pattern of each circuit unit in the display substrate at least includes: a first gate electrode 31, a second gate electrode 32, a third gate electrode 33, a fourth gate electrode 34, a seventh gate electrode 37, a plate connecting strip 38, a first light-emitting signal line 41, and a second light-emitting signal line 42.

[0203] In an example embodiment, the first gate electrode 31 can have a block shape (e.g., a rectangular shape), and a normal projection of the first gate electrode 31 on the substrate at least partially overlaps a normal projection of the first active layer on the substrate, and the first gate electrode 31 can serve as a gate electrode of the first transistor T1.

[0204] In an exemplary embodiment, in at least one unit row, the first gate electrodes 31 in some adjacent circuit units can be connected to each other, and the first gate electrodes 31 in two circuit units can be an integrated structure connected to each other. For example, the first gate electrode 31 in the N+1th unit column and the first gate electrode 31 in the N+2th unit column can be an integrated structure connected to each other. The present disclosure can effectively reduce the wiring space, reduce the number of vias, reduce the occupied area of the pixel driving circuit, and facilitate the realization of high resolution by setting the first gate electrodes 31 in some adjacent circuit units as an integrated structure connected to each other.

[0205] In an exemplary embodiment, the second gate electrode 32 can be in a block shape (such as a rectangular shape), and can be arranged on one side of the first gate electrode 31 in the second direction Y. The orthographic projection of the second gate electrode 32 on the substrate at least partially overlaps the orthographic projection of the second active layer on the substrate, and the second gate electrode 32 can serve as the gate electrode of the second transistor T2.

[0206] In an exemplary embodiment, in at least one unit row, the second gate electrodes 32 in some adjacent circuit units can be connected to each other, and the second gate electrodes 32 in two circuit units can be an integrated structure connected to each other. For example, the second gate electrode 32 in the N+1th unit column and the second gate electrode 32 in the N+2th unit column can be an integrated structure connected to each other. The present disclosure can effectively reduce the wiring space, reduce the number of vias, reduce the occupied area of the pixel driving circuit, and facilitate the realization of high resolution by setting the second gate electrodes 32 in some adjacent circuit units as an integrated structure connected to each other.

[0207] In an exemplary embodiment, the third gate electrode 33 can be in a block shape (such as a rectangular shape), and the orthographic projection of the third gate electrode 33 on the substrate at least partially overlaps the orthographic projection of the third active layer on the substrate. The third gate electrode 33 can serve as the top gate electrode of the third transistor T3.

[0208] In an exemplary embodiment, the fourth gate electrode 34 can be in a block shape (such as a rectangular shape), and can be arranged on one side of the first gate electrode 31 in the opposite direction of the second direction Y. The orthographic projection of the fourth gate electrode 34 on the substrate at least partially overlaps the orthographic projection of the fourth active layer on the substrate, and the fourth gate electrode 34 can serve as the gate electrode of the fourth transistor T4.

[0209] In the example embodiment, the fourth gate electrodes 34 in the at least one unit row of the partially adjacent circuit units can be connected to each other, and the fourth gate electrodes 34 of the two circuit units can be an integrated structure connected to each other. For example, the fourth gate electrode 34 in the N+1th unit column and the fourth gate electrode 34 in the N+2th unit column can be an integrated structure connected to each other. The present disclosure can effectively reduce the wiring space, reduce the number of vias, and reduce the area occupied by the pixel driving circuit by setting the fourth gate electrodes 34 in the partially adjacent circuit units as an integrated structure connected to each other, which is conducive to achieving high resolution.

[0210] In the example embodiment, the seventh gate electrode 37 can be in the shape of a block (such as a rectangle), and can be arranged on one side of the second gate electrode 32 in the second direction Y. The orthogonal projection of the seventh gate electrode 37 on the substrate at least partially overlaps the orthogonal projection of the seventh active layer on the substrate, and the seventh gate electrode 37 can serve as the gate electrode of the seventh transistor T7.

[0211] In the example embodiment, the first light-emitting signal line 41 can be in the shape of a straight line or a polyline extending along the first direction X, and can be arranged between the second gate electrode 32 and the seventh gate electrode 37. The orthogonal projection of the first light-emitting signal line 41 on the substrate at least partially overlaps the orthogonal projection of the fifth active layer 25 on the substrate, and the overlapping region can serve as the gate electrode of the fifth transistor T5, thereby achieving that the first light-emitting signal line 41 can control the on or off of the fifth transistor T5.

[0212] In the example embodiment, the first light-emitting signal line 41 can be in a variable-width structure, and the width can be in the second direction Y. The first light-emitting signal line 41 can include a first region overlapping the fifth active layer 25 and a second region not overlapping the fifth active layer 25, and the width of the first region can be greater than the width of the second region.

[0213] In the example embodiment, the second light-emitting signal line 42 can be in the shape of a straight line or a polyline extending along the first direction X, and can be arranged on the side of the fourth gate electrode 34 away from the first gate electrode 31. The orthogonal projection of the second light-emitting signal line 42 on the substrate at least partially overlaps the orthogonal projection of the sixth active layer 26 on the substrate, and the overlapping region can serve as the gate electrode of the sixth transistor T6, thereby achieving that the second light-emitting signal line 42 can control the on or off of the sixth transistor T6.

[0214] In the example embodiment, the second light-emitting signal line 42 can be in a variable-width structure, and the width can be in the second direction Y. The second light-emitting signal line 42 can include a first region overlapping the sixth active layer 26 and a second region not overlapping the sixth active layer 26, and the width of the first region can be greater than the width of the second region.

[0215] In an example embodiment, the shape of the plate connecting strip 38 can be a strip shape extending along the second direction Y, the plate connecting strip 38 can be disposed at one side of the third gate electrode 33 in the second direction Y, the first end of the plate connecting strip 38 is connected with the third gate electrode 33, the second end of the plate connecting strip 38 extends away from the third gate electrode 33, and the orthographic projection of the second end of the plate connecting strip 38 on the substrate at least partially overlaps with the orthographic projection of the fourth plate 14 on the substrate.

[0216] In an example embodiment, in at least one circuit unit, the third gate electrode 33 and the plate connecting strip 38 can be an integrated structure connected with each other.

[0217] In an example embodiment, the third conductive layer in part of the adjacent unit columns can be mirror-symmetrical relative to the column center line. For example, the third conductive layer in the Nth unit column and the N+1th unit column can be mirror-symmetrical relative to the column center line. For another example, the third conductive layer in the N+1th unit column and the N+2th unit column can be mirror-symmetrical relative to the column center line.

[0218] In an example embodiment, the third conductive layer in part of the adjacent unit columns can be substantially the same. For example, the third conductive layer in the Nth unit column and the N+2th unit column can be substantially the same.

[0219] (15) Forming a fourth insulating layer pattern. In an example embodiment, forming the fourth insulating layer pattern can include: on the substrate on which the aforementioned patterns are formed, depositing a fourth insulating thin film, patterning the fourth insulating thin film by using a patterning process, and forming a fourth insulating layer covering the third conductive layer, the fourth insulating layer being provided with a plurality of vias, as shown in FIG. 13.

[0220] In an example embodiment, the plurality of vias in each circuit unit of the display substrate at least includes: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, and a seventeenth via V17.

[0221] In an example embodiment, in the circuit unit of the Nth unit column, the orthographic projection of the first via V1 on the substrate is located within the range of the orthographic projection of the first region of the first active layer (also the first region of the second active layer) on the substrate, the third insulating layer and the fourth insulating layer within the first via V1 are etched away, exposing the surface of the first region of the first active layer (also the first region of the second active layer), and the first via V1 is configured to enable the first initial signal line formed subsequently to pass through the via and be connected with the first region of the first active layer (also the first region of the second active layer).

[0222] In the circuit units of the N+1th unit column and the N+2th unit column, in the exemplary embodiments, the first via V1 is located within the range of the orthogonal projection of the active connection strip 28 on the substrate, the third insulating layer and the fourth insulating layer in the first via V1 are etched away to expose the surface of the active connection strip 28, and the first via V1 is configured to enable the first initial signal line formed subsequently to connect with the active connection strip 28 through the via. Since the active connection strip 28 simultaneously serves as the first region of the first active layer and the first region of the second active layer shared by two circuit units, the two circuit units share the first via V1, and three circuit units are provided with only two first vias V1, thereby effectively reducing the number of vias, reducing the area occupied by the pixel driving circuit, and facilitating the realization of high resolution.

[0223] In the exemplary embodiments, the second via V2 is located within the range of the orthogonal projection of the second region of the first active layer (also the second region of the fourth active layer) on the substrate, the third insulating layer and the fourth insulating layer in the second via V2 are etched away to expose the surface of the second region of the first active layer (also the second region of the fourth active layer), and the second via V2 is configured to enable the first connection electrode formed subsequently to connect with the second region of the first active layer (also the second region of the fourth active layer) through the via.

[0224] In the exemplary embodiments, the third via V3 is located within the range of the orthogonal projection of the second region of the second active layer on the substrate, the third insulating layer and the fourth insulating layer in the third via V3 are etched away to expose the surface of the second region of the second active layer, and the third via V3 is configured to enable the second connection electrode formed subsequently to connect with the second region of the second active layer through the via.

[0225] In the exemplary embodiments, the fourth via V4 is located within the range of the orthogonal projection of the first region of the fourth active layer on the substrate, the third insulating layer and the fourth insulating layer in the fourth via V4 are etched away to expose the surface of the first region of the fourth active layer, and the fourth via V4 is configured to enable the fourth connection electrode formed subsequently to connect with the first region of the fourth active layer through the via.

[0226] In the exemplary embodiments, the fifth via V5 is located within the range of the orthogonal projection of the second region of the third active layer (also the first region of the sixth active layer) on the substrate, the third insulating layer and the fourth insulating layer in the fifth via V5 are etched away to expose the surface of the second region of the third active layer (also the first region of the sixth active layer), and the fifth via V5 is configured to enable the third connection electrode formed subsequently to connect with the second region of the third active layer (also the first region of the sixth active layer) through the via.

[0227] In the example embodiment, the orthogonal projection of the sixth via V6 on the substrate is located within the orthogonal projection of the first region of the fifth active layer on the substrate, the third insulating layer and the fourth insulating layer within the sixth via V6 are etched away to expose the surface of the first region of the fifth active layer, and the sixth via V6 is configured to enable a power connection line formed subsequently to connect with the first region of the fifth active layer through the via. Since two adjacent circuit units partially share the same first region of the fifth active layer, the two adjacent circuit units partially can share the sixth via V6, and the three circuit units are provided with only two sixth vias V6, which effectively reduces the number of vias, reduces the area occupied by the pixel driving circuit, and is conducive to achieving high resolution.

[0228] In the example embodiment, the orthogonal projection of the seventh via V7 on the substrate is located within the orthogonal projection of the second region of the sixth active layer (also the second region of the seventh active layer) on the substrate, the third insulating layer and the fourth insulating layer within the seventh via V7 are etched away to expose the surface of the second region of the sixth active layer (also the second region of the seventh active layer), and the seventh via V7 is configured to enable a fifth connection electrode formed subsequently to connect with the second region of the sixth active layer (also the second region of the seventh active layer) through the via.

[0229] In the example embodiment, the orthogonal projection of the eighth via V8 on the substrate is located within the orthogonal projection of the first region of the seventh active layer on the substrate, the third insulating layer and the fourth insulating layer within the eighth via V8 are etched away to expose the surface of the first region of the seventh active layer, and the eighth via V8 is configured to enable a second initial signal line formed subsequently to connect with the first region of the seventh active layer through the via. Since two adjacent circuit units partially share the same first region of the seventh active layer, the two adjacent circuit units partially can share the eighth via V8, and the three circuit units are provided with only two eighth vias V8, which effectively reduces the number of vias, reduces the area occupied by the pixel driving circuit, and is conducive to achieving high resolution.

[0230] In the example embodiment, the orthogonal projection of the ninth via V9 on the substrate is located within the orthogonal projection of the second plate 12 on the substrate, the second insulating layer, the third insulating layer, and the fourth insulating layer within the ninth via V9 are etched away to expose the surface of the second plate 12, and the ninth via V9 is configured to enable a third connection electrode formed subsequently to connect with the second plate 12 through the via.

[0231] In the example embodiment, the normal projection of the tenth via V10 on the substrate is within the range of the normal projection of the fourth plate 14 on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the tenth via V10 are etched away to expose the surface of the fourth plate 14, and the tenth via V10 is configured to connect the sixth connection electrode formed subsequently therethrough with the fourth plate 14.

[0232] In the example embodiment, the normal projection of the eleventh via V11 on the substrate is within the range of the normal projection of the first gate electrode 31 on the substrate, the fourth insulating layer in the eleventh via V11 is etched away to expose the surface of the first gate electrode 31, and the eleventh via V11 is configured to connect the first scan signal line formed subsequently therethrough. Since the first gate electrodes 31 in the two adjacent circuit units are integrally connected with each other, the two adjacent circuit units can share the eleventh via V11, and the three circuit units are provided with only two eleventh vias V11, which effectively reduces the number of vias, reduces the area occupied by the pixel driving circuit, and is conducive to achieving high resolution.

[0233] In the example embodiment, the normal projection of the twelfth via V12 on the substrate is within the range of the normal projection of the second gate electrode 32 on the substrate, the fourth insulating layer in the twelfth via V12 is etched away to expose the surface of the second gate electrode 32, and the twelfth via V12 is configured to connect the second scan signal line formed subsequently therethrough with the second gate electrode 32. Since the second gate electrodes 32 in the two adjacent circuit units are integrally connected with each other, the two adjacent circuit units can share the twelfth via V12, and the three circuit units are provided with only two twelfth vias V12, which effectively reduces the number of vias, reduces the area occupied by the pixel driving circuit, and is conducive to achieving high resolution.

[0234] In the example embodiment, the normal projection of the thirteenth via V13 on the substrate is within the range of the normal projection of the third gate electrode 33 on the substrate, the fourth insulating layer in the thirteenth via V13 is etched away to expose the surface of the third gate electrode 33, and the thirteenth via V13 is configured to connect the first connection electrode formed subsequently therethrough with the third gate electrode 33.

[0235] In the example embodiment, the fourth gate electrode 34 is formed on the substrate 10. The fourth gate electrode 34 is configured to be connected to the fourth scan signal line. In the example embodiment, the fourth gate electrode 34 is formed by depositing a fourth conductive thin film on the substrate 10, and patterning the fourth conductive thin film by using a patterning process. In the example embodiment, the fourth gate electrode 34 can be referred to as a first gate electrode.

[0236] In the example embodiment, the fourth gate electrode 34 is formed on the substrate 10. The fourth gate electrode 34 is configured to be connected to the fourth scan signal line. In the example embodiment, the fourth gate electrode 34 is formed by depositing a fourth conductive thin film on the substrate 10, and patterning the fourth conductive thin film by using a patterning process. In the example embodiment, the fourth gate electrode 34 can be referred to as a first gate electrode.

[0237] In the example embodiment, the fourth gate electrode 34 is formed on the substrate 10. The fourth gate electrode 34 is configured to be connected to the fourth scan signal line. In the example embodiment, the fourth gate electrode 34 is formed by depositing a fourth conductive thin film on the substrate 10, and patterning the fourth conductive thin film by using a patterning process. In the example embodiment, the fourth gate electrode 34 can be referred to as a first gate electrode.

[0238] In the example embodiment, the fourth gate electrode 34 is formed on the substrate 10. The fourth gate electrode 34 is configured to be connected to the fourth scan signal line. In the example embodiment, the fourth gate electrode 34 is formed by depositing a fourth conductive thin film on the substrate 10, and patterning the fourth conductive thin film by using a patterning process. In the example embodiment, the fourth gate electrode 34 can be referred to as a first gate electrode.

[0239] (16) Forming a fourth conductive layer pattern. In the example embodiment, forming the fourth conductive layer can include: depositing a fourth conductive thin film on the substrate on which the aforementioned patterns are formed, and patterning the fourth conductive thin film by using a patterning process, to form the fourth conductive layer disposed on the fourth insulating layer. In the example embodiment, the fourth conductive layer can be referred to as a first source-drain metal (SD1) layer.

[0240] In the exemplary embodiment, the fourth conductive layer of each circuit unit in the display substrate at least includes: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, a first scan signal line 61, a second scan signal line 62, a third scan signal line 63, a fourth scan signal line 64, a first power connection line 65, a second power connection line 66, a first initial signal line 71, and a second initial signal line 72.

[0241] In the exemplary embodiment, the first connection electrode 51 can be in the shape of a strip extending along the first direction X, a first end of the first connection electrode 51 is connected to the second region of the first active layer (also the second region of the fourth active layer) through the second via V2, and a second end of the first connection electrode 51 is connected to the third gate electrode 33 through the thirteenth via V13. Since the third gate electrode 33 is connected to the fourth plate 14 through the plate connection strip 38 and the sixth connection electrode 56, the first connection electrode 51 realizes the connection between the second electrode of the first transistor T1, the gate electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the first end (the fourth plate 14) of the second capacitor C2, forms the first node N1 of the pixel driving circuit, that is, the first connection electrode 51, the third gate electrode 33, the plate connection strip 38, the sixth connection electrode 56, and the fourth plate 14 have the first node potential. In the exemplary embodiment, the first connection electrode 51 can serve as the first node electrode of the present disclosure.

[0242] In the exemplary embodiment, the second connection electrode 52 can be in the shape of a strip extending along the first direction X, a first end of the second connection electrode 52 is connected to the second region of the second active layer through the third via V3, and a second end of the second connection electrode 52 is connected to the third plate 13 through the seventeenth via V17. Since the first plate 11 and the third plate 13 are an integrated structure connected to each other, the second connection electrode 52 realizes the connection between the second electrode of the second transistor T2, the second end (the first plate 11) of the first capacitor C1, and the second end (the third plate 13) of the second capacitor C2, forms the second node N2 of the pixel driving circuit, that is, the second connection electrode 52, the first plate 11, and the third plate 13 have the second node potential. In the exemplary embodiment, the second connection electrode 52 can serve as the second node electrode of the present disclosure.

[0243] In the example embodiment, the third connection electrode 53 can have a strip shape extending along the first direction X, a first end of the third connection electrode 53 is connected to the first region of the second region of the third active layer (also the first region of the sixth active layer) through the fifth via V5, and a second end of the third connection electrode 53 is connected to the second plate 12 through the ninth via V9, thereby realizing the interconnection between the second electrode of the third transistor T3, the first electrode of the sixth transistor T6, and the first end (the second plate 12) of the first capacitor C1, forming the third node N3 of the pixel driving circuit, that is, the second plate 12 and the third connection electrode 53 have the third node potential. In the example embodiment, the third connection electrode 53 can serve as the third node electrode of the present disclosure.

[0244] In the example embodiment, since the fifth plate 15 is connected to the first region of the sixth active layer (also the second region of the third active layer), and the first region of the sixth active layer (also the second region of the third active layer) is connected to the second plate 12 through the third connection electrode 53, the second plate 12 and the fifth plate 15 have the same third node potential.

[0245] In the example embodiment, since the first plate 11 has the second node potential and the second plate 12 has the third node potential, the first plate 11 having the second node potential and the second plate 12 having the third node potential form the first capacitor C1 of the pixel driving circuit.

[0246] In the example embodiment, since the third plate 13 has the second node potential and the fourth plate 14 has the first node potential, the third plate 13 having the second node potential and the fourth plate 14 having the first node potential form the second capacitor C2 of the pixel driving circuit.

[0247] In the example embodiment, since the fourth plate has the first node potential and the fifth plate 15 has the third node potential, the fourth plate 14 having the first node potential and the fifth plate 15 having the third node potential can form the third capacitor C3 of the pixel driving circuit.

[0248] In the example embodiment, since the second plate 12 also serves as the bottom gate electrode of the third transistor T3, the bottom gate electrode of the third transistor T3 has the third node potential of the pixel driving circuit.

[0249] In the example embodiment, the fourth connection electrode 54 can have a block shape (such as a rectangular shape), the fourth connection electrode 54 is connected to the first region of the fourth active layer through the fourth via V4, and the fourth connection electrode 54 is configured to be connected to the subsequently formed data signal line.

[0250] In the example embodiment, the fifth connection electrode 55 can be in a block shape (e.g., a rectangular shape), the fifth connection electrode 55 is connected with the second region of the sixth active layer (also the second region of the seventh active layer) through the seventh via V7, and the fifth connection electrode 55 is configured to be connected with the anode connection electrode formed subsequently.

[0251] In the example embodiment, the sixth connection electrode 56 can be in a strip shape extending along the first direction X, the first end of the sixth connection electrode 56 is connected with the fourth plate 14 through the tenth via V10, and the second end of the sixth connection electrode 56 is connected with the plate connection strip 38 through the fifteenth via V15. Since the plate connection strip 38 is connected with the third gate electrode 33, the third gate electrode 33 is connected with the second region of the first active layer (also the second region of the fourth active layer) through the first connection electrode 51, the first connection electrode 51, the third gate electrode 33, the plate connection strip 38, the sixth connection electrode 56, and the fourth plate 14 have the first node potential.

[0252] In the example embodiment, the first scan signal line 61 can be in a straight line shape or a broken line shape extending along the first direction X and can be arranged continuously in one unit row. The orthographic projection of the first scan signal line 61 on the substrate at least partially overlaps the orthographic projection of the first gate electrode 31 on the substrate, the first scan signal line 61 is connected with the first gate electrode 31 in each circuit unit through the eleventh via V11, thus realizing the connection of the first scan signal line 61 with the gate electrode of the first transistor T1 in each circuit unit, and the first scan signal line 61 can control the turn-on or turn-off of the first transistor T1.

[0253] In the example embodiment, in at least one circuit unit, the orthographic projection of the first scan signal line 61 on the substrate at least partially overlaps the orthographic projection of the plate connection strip 38 on the substrate.

[0254] In the example embodiment, in at least one circuit unit, the orthographic projection of the first scan signal line 61 on the substrate does not overlap the orthographic projection of the first connection electrode 51 on the substrate, and / or the orthographic projection of the first scan signal line 61 on the substrate does not overlap the orthographic projection of the third gate electrode 33 on the substrate, and / or the orthographic projection of the first scan signal line 61 on the substrate does not overlap the orthographic projection of the sixth connection electrode 56 on the substrate, and / or the orthographic projection of the first scan signal line 61 on the substrate does not overlap the orthographic projection of the fourth plate 14 on the substrate. Since the first connection electrode 51, the third gate electrode 33, the sixth connection electrode 56, and the fourth plate 14 all have the first node potential, the overlap capacitance between the first node N1 and the first scan signal line 61 can be effectively reduced by the position arrangement of the first scan signal line 61, and thus the parasitic capacitance of the first node N1 is reduced.

[0255] In the example embodiment, in at least one circuit unit, the orthogonal projection of the first scan signal line 61 on the substrate does not overlap with the orthogonal projection of the second connection electrode 52 on the substrate. Since the second connection electrode 52 has the second node potential, the overlapping capacitance between the second node N2 and the first scan signal line 61 can be effectively reduced by the position setting of the first scan signal line 61, and the parasitic capacitance of the second node N2 is reduced.

[0256] In the example embodiment, in at least one circuit unit, the orthogonal projection of the first scan signal line 61 on the substrate does not overlap with the orthogonal projection of the third connection electrode 53 on the substrate.

[0257] In the example embodiment, the second scan signal line 62 can be linear or zigzag in shape and can be continuously arranged in one unit row. The second scan signal line 62 can be provided with a scan connection strip 62-1 in the shape of a strip extending along the second direction Y. The orthogonal projection of the scan connection strip 62-1 on the substrate at least partially overlaps with the orthogonal projection of the second gate electrode 32 on the substrate. The first end of the scan connection strip 62-1 is connected to the second scan signal line 62, and the second end of the scan connection strip 62-1 extends toward the direction close to the first scan signal line 61 and is connected to the second gate electrode 32 through the twelfth via V12. Thus, the second scan signal line 62 is connected to the gate electrode of the second transistor T2 in each circuit unit, and the second scan signal line 62 can control the conduction or disconnection of the second transistor T2.

[0258] In the example embodiment, in at least one circuit unit, the second scan signal line 62 and the scan connection strip 62-1 can be an integrated structure connected to each other.

[0259] In the exemplary embodiments, in at least one circuit unit, the orthogonal projection of the second scan signal line 62 on the substrate does not overlap with the orthogonal projection of the first connection electrode 51 on the substrate, and / or, the orthogonal projection of the second scan signal line 62 on the substrate does not overlap with the orthogonal projection of the third gate electrode 33 on the substrate, and / or, the orthogonal projection of the second scan signal line 62 on the substrate does not overlap with the orthogonal projection of the plate connection strip 38 on the substrate, and / or, the orthogonal projection of the second scan signal line 62 on the substrate does not overlap with the orthogonal projection of the sixth connection electrode 56 on the substrate, and / or, the orthogonal projection of the second scan signal line 62 on the substrate does not overlap with the orthogonal projection of the fourth plate 14 on the substrate. Since the first connection electrode 51, the third gate electrode 33, the plate connection strip 38, the sixth connection electrode 56 and the fourth plate 14 have the first node potential, the overlapping capacitance between the first node N1 and the second scan signal line 62 can be effectively reduced by the position setting of the second scan signal line 62, and the parasitic capacitance of the first node N1 is further reduced.

[0260] In the exemplary embodiments, in at least one circuit unit, the orthogonal projection of the second scan signal line 62 on the substrate does not overlap with the orthogonal projection of the second connection electrode 52 on the substrate, and / or, the orthogonal projection of the second scan signal line 62 on the substrate does not overlap with the orthogonal projection of the first plate 11 on the substrate, and / or, the orthogonal projection of the second scan signal line 62 on the substrate does not overlap with the orthogonal projection of the third plate 13 on the substrate. Since the second connection electrode 52, the first plate 11 and the third plate 13 have the second node potential, the overlapping capacitance between the second node N2 and the second scan signal line 62 can be effectively reduced by the position setting of the second scan signal line 62, and the parasitic capacitance of the second node N2 is further reduced.

[0261] In the exemplary embodiments, in at least one circuit unit, the orthogonal projection of the second scan signal line 62 on the substrate does not overlap with the orthogonal projection of the third connection electrode 53 on the substrate.

[0262] In the exemplary embodiments, the shape of the third scan signal line 63 can be a straight line or a broken line extending along the first direction X, and the third scan signal line 63 can be continuously arranged in one unit row. The orthogonal projection of the third scan signal line 63 on the substrate at least partially overlaps with the orthogonal projection of the seventh gate electrode 37 on the substrate, and the third scan signal line 63 is connected with the seventh gate electrode 37 in each circuit unit through the sixteenth via V16, so that the connection between the third scan signal line 63 and the gate electrode of the seventh transistor T7 in each circuit unit is realized, and the third scan signal line 63 can control the turn-on or turn-off of the seventh transistor T7.

[0263] In the at least one circuit unit, a projection of the third scan signal line 63 on the substrate does not overlap with a projection of the first connection electrode 51 on the substrate, and / or a projection of the third scan signal line 63 on the substrate does not overlap with a projection of the third gate electrode 33 on the substrate, and / or a projection of the third scan signal line 63 on the substrate does not overlap with a projection of the plate connection strip 38 on the substrate, and / or a projection of the third scan signal line 63 on the substrate does not overlap with a projection of the sixth connection electrode 56 on the substrate, and / or a projection of the third scan signal line 63 on the substrate does not overlap with a projection of the fourth plate 14 on the substrate. Since the first connection electrode 51, the third gate electrode 33, the plate connection strip 38, the sixth connection electrode 56 and the fourth plate 14 have the first node potential, the overlapping capacitance between the first node N1 and the third scan signal line 63 can be effectively reduced by the position setting of the third scan signal line 63, and the parasitic capacitance of the first node N1 is further reduced.

[0264] In the at least one circuit unit, a projection of the third scan signal line 63 on the substrate does not overlap with a projection of the second connection electrode 52 on the substrate, and / or a projection of the third scan signal line 63 on the substrate does not overlap with a projection of the first plate 11 on the substrate, and / or a projection of the third scan signal line 63 on the substrate does not overlap with a projection of the third plate 13 on the substrate. Since the second connection electrode 52, the first plate 11 and the third plate 13 have the second node potential, the overlapping capacitance between the second node N2 and the third scan signal line 63 can be effectively reduced by the position setting of the third scan signal line 63, and the parasitic capacitance of the second node N2 is further reduced.

[0265] In the at least one circuit unit, a projection of the third scan signal line 63 on the substrate does not overlap with a projection of the third connection electrode 53 on the substrate.

[0266] In the at least one circuit unit, a projection of the third scan signal line 63 on the substrate does not overlap with a projection of the third connection electrode 53 on the substrate.

[0267] In the at least one circuit unit, a projection of the fourth scan signal line 64 on the substrate does not overlap with a projection of the first connection electrode 51 on the substrate, and / or a projection of the fourth scan signal line 64 on the substrate does not overlap with a projection of the third gate electrode 33 on the substrate, and / or a projection of the fourth scan signal line 64 on the substrate does not overlap with a projection of the plate connecting strip 38 on the substrate, and / or a projection of the fourth scan signal line 64 on the substrate does not overlap with a projection of the sixth connection electrode 56 on the substrate, and / or a projection of the fourth scan signal line 64 on the substrate does not overlap with a projection of the fourth plate 14 on the substrate. Since the first connection electrode 51, the third gate electrode 33, the plate connecting strip 38, the sixth connection electrode 56 and the fourth plate 14 all have the first node potential, the overlap capacitance between the first node N1 and the fourth scan signal line 64 can be effectively reduced by the position setting of the first scan signal line 61, and the parasitic capacitance of the first node N1 is further reduced.

[0268] In the at least one circuit unit, a projection of the fourth scan signal line 64 on the substrate does not overlap with a projection of the second connection electrode 52 on the substrate. Since the second connection electrode 52 has the second node potential, the overlap capacitance between the second node N2 and the third scan signal line 63 can be effectively reduced by the position setting of the fourth scan signal line 64, and the parasitic capacitance of the second node N2 is further reduced.

[0269] In the at least one circuit unit, a projection of the fourth scan signal line 64 on the substrate at least partially overlaps with a projection of the first plate 11 and the second plate 12 on the substrate, and the second plate 12 is arranged between the first plate 11 and the fourth scan signal line 64. In this way, the second plate 12 can effectively shield the overlap capacitance between the fourth scan signal line 64 and the second node N2, and further reduce the parasitic capacitance of the second node N2.

[0270] In the at least one circuit unit, a projection of the fourth scan signal line 64 on the substrate does not overlap with a projection of the third connection electrode 53 on the substrate.

[0271] In the at least one circuit unit, a projection of the fourth scan signal line 64 on the substrate does not overlap with a projection of the third connection electrode 53 on the substrate.

[0272] In the example embodiment, the first power connection line 65 can be in the shape of a straight line or a broken line extending along the first direction X, and can be arranged continuously in one unit row. The first power connection line 65 is connected to the first region of the fifth active layer in each circuit unit through the sixth via hole V6. The first power connection line 65 is configured to be connected to the first power line formed subsequently, so that the first power line can write the first power signal to the first electrode of the fifth transistor T5 in each circuit unit.

[0273] In the example embodiment, the first power connection line 65 can be provided with a first power connection block 65-1. The first power connection block 65-1 can be in the shape of a block (e.g., a rectangle), and can be arranged on the side of the first power connection line 65 close to the fourth scan signal line 64 and connected to the first power connection line 65. The first power connection block 65-1 is configured to be connected to the first power line formed subsequently.

[0274] In the example embodiment, the first power connection line 65 and the first power connection block 65-1 in at least one circuit unit can be an integrated structure connected to each other.

[0275] In the example embodiment, the first power connection block 65-1 can be arranged in the circuit units in the (N+1)th unit column and the (N+2)th unit column, respectively.

[0276] In the example embodiment, in at least one circuit unit, the orthographic projection of the first power connection line 65 on the substrate does not overlap with the orthographic projection of the first connection electrode 51 on the substrate, and / or the orthographic projection of the first power connection line 65 on the substrate does not overlap with the orthographic projection of the third gate electrode 33 on the substrate, and / or the orthographic projection of the first power connection line 65 on the substrate does not overlap with the orthographic projection of the plate connection strip 38 on the substrate, and / or the orthographic projection of the first power connection line 65 on the substrate does not overlap with the orthographic projection of the sixth connection electrode 56 on the substrate, and / or the orthographic projection of the first power connection line 65 on the substrate does not overlap with the orthographic projection of the fourth plate 14 on the substrate. Since the first connection electrode 51, the third gate electrode 33, the plate connection strip 38, the sixth connection electrode 56, and the fourth plate 14 have the first node potential, the overlap capacitance between the first node N1 and the first power connection line 65 can be effectively reduced by the position arrangement of the first power connection line 65, and the parasitic capacitance of the first node N1 can be reduced.

[0277] In the exemplary embodiments, in at least one circuit unit, the first power connection line 65 has no overlap with the second connection electrode 52 in the orthogonal projection on the substrate, and / or the first power connection line 65 has no overlap with the first plate 11 in the orthogonal projection on the substrate, and / or the first power connection line 65 has no overlap with the third plate 13 in the orthogonal projection on the substrate. Since the second connection electrode 52, the first plate 11 and the third plate 13 have the second node potential, the overlap capacitance between the second node N2 and the first power connection line 65 can be effectively reduced by the position setting of the first power connection line 65, and the parasitic capacitance of the second node N2 is further reduced.

[0278] In the exemplary embodiments, in at least one circuit unit, the first power connection line 65 has no overlap with the third connection electrode 53 in the orthogonal projection on the substrate.

[0279] In the exemplary embodiments, the second power connection line 66 can be linear or zigzag in shape and extend along the first direction X, and can be continuously arranged in one unit row. The second power connection line 66 can be provided with a second power connection block 66-1. The second power connection block 66-1 can be in the shape of a block (e.g., a rectangle) and can be arranged on the side of the second power connection line 66 close to the first power connection line 65 and connected to the second power connection line 66. The second power connection block 66-1 is configured to be connected to the second power line formed subsequently.

[0280] In the exemplary embodiments, in at least one circuit unit, the second power connection line 66 and the second power connection block 66-1 can be an integrated structure connected to each other.

[0281] In the exemplary embodiments, the second power connection block 66-1 can be arranged between the Nth unit column and the N+1th unit column.

[0282] In the exemplary embodiments, in at least one circuit unit, the orthogonal projection of the second power connection line 66 on the substrate does not overlap with the orthogonal projection of the first connection electrode 51 on the substrate, and / or the orthogonal projection of the second power connection line 66 on the substrate does not overlap with the orthogonal projection of the third gate electrode 33 on the substrate, and / or the orthogonal projection of the second power connection line 66 on the substrate does not overlap with the orthogonal projection of the plate connection strip 38 on the substrate, and / or the orthogonal projection of the second power connection line 66 on the substrate does not overlap with the orthogonal projection of the sixth connection electrode 56 on the substrate, and / or the orthogonal projection of the second power connection line 66 on the substrate does not overlap with the orthogonal projection of the fourth plate 14 on the substrate. Since the first connection electrode 51, the third gate electrode 33, the plate connection strip 38, the sixth connection electrode 56 and the fourth plate 14 have the first node potential, the overlap capacitance between the first node N1 and the second power connection line 66 can be effectively reduced by the position setting of the second power connection line 66, and the parasitic capacitance of the first node N1 is further reduced.

[0283] In the exemplary embodiments, in at least one circuit unit, the orthogonal projection of the second power connection line 66 on the substrate does not overlap with the orthogonal projection of the second connection electrode 52 on the substrate. Since the second connection electrode 52 has the second node potential, the overlap capacitance between the second node N2 and the second power connection line 66 can be effectively reduced by the position setting of the second power connection line 66, and the parasitic capacitance of the second node N2 is further reduced.

[0284] In the exemplary embodiments, in at least one circuit unit, the orthogonal projection of the second power connection line 66 on the substrate does not overlap with the orthogonal projection of the third connection electrode 53 on the substrate.

[0285] In the exemplary embodiments, the shape of the first initial signal line 71 can be a straight line or a broken line extending along the first direction X, and can be continuously arranged in one unit row. In the circuit unit of the Nth unit column, the first initial signal line 71 is connected to the first region of the first active layer (also the first region of the second active layer) through the first via V1. In the circuit units of the N+1th unit column and the N+2th unit column, the first initial signal line 71 is connected to the active connection strip 28 through the first via V1. The first initial signal line 71 realizes writing the first initial signal to the first electrode of the first transistor T1 and the first electrode of the second transistor T2 in each circuit unit at the same time.

[0286] In the exemplary embodiment, the first initial signal line 71 can be provided with a first initial connection block 71-1. The first initial connection block 71-1 can be in a block shape (e.g., a rectangular shape), can be provided on a side of the first initial signal line 71 close to the second scan signal line 62, and can be connected to the second scan signal line 62. The first initial connection block 71-1 is configured to be connected to a first initial connection line to be formed later.

[0287] In the exemplary embodiment, the first initial signal line 71 and the first initial connection block 71-1 can be an integrated structure connected to each other in at least one circuit unit.

[0288] In the exemplary embodiment, the first initial connection block 71-1 can be provided in the circuit unit of the Nth unit column.

[0289] In the exemplary embodiment, the first initial signal line 71 can not overlap with the first connection electrode 51, and / or can not overlap with the third gate electrode 33, and / or can not overlap with the plate connection strip 38, and / or can not overlap with the sixth connection electrode 56 in the projection of the first initial signal line 71 on the substrate in at least one circuit unit. Since the first connection electrode 51, the third gate electrode 33, the plate connection strip 38, and the sixth connection electrode 56 all have the first node potential, the parasitic capacitance of the first node N1 can be effectively reduced by the position of the first initial signal line 71.

[0290] In the exemplary embodiment, the first initial signal line 71 can at least partially overlap with the fourth plate 14 and the fifth plate 15 in the projection of the first initial signal line 71 on the substrate in at least one circuit unit. The fifth plate 15 is provided between the fourth plate 14 and the first initial signal line 71 in a direction perpendicular to the substrate. In this way, the fifth plate 15 can effectively shield the overlap capacitance between the first initial signal line 71 and the first node N1, further reducing the parasitic capacitance of the first node N1.

[0291] In the exemplary embodiment, the first initial signal line 71 can not overlap with the second connection electrode 52 and the first plate 11 in the projection of the first initial signal line 71 on the substrate in at least one circuit unit. Since the second connection electrode 52 and the first plate 11 have the second node potential, the parasitic capacitance of the second node N2 can be effectively reduced by the position of the second scan signal line 62, further reducing the parasitic capacitance of the second node N2.

[0292] In the example embodiment, in at least one circuit unit, the orthogonal projection of the first initial signal line 71 on the substrate at least partially overlaps the orthogonal projection of the third plate 13, the fourth plate 14 and the fifth plate 15 on the substrate, and the fourth plate 14 and the fifth plate 15 are arranged between the third plate 13 and the first initial signal line 71 in the direction perpendicular to the substrate. In this way, the fourth plate 14 and the fifth plate 15 can effectively shield the overlapping capacitance between the first initial signal line 71 and the second node N2, further reducing the parasitic capacitance of the second node N2.

[0293] In the example embodiment, in at least one circuit unit, the orthogonal projection of the first initial signal line 71 on the substrate does not overlap the orthogonal projection of the third connection electrode 53 on the substrate.

[0294] In the example embodiment, the second initial signal line 72 can be in the shape of a straight line or a broken line extending along the first direction X, and can be arranged continuously in one unit row. The second initial signal line 72 is connected to the first region of the seventh active layer in each circuit unit through the eighth via V8, so that the second initial signal line 72 can write the second initial signal to the first electrode of the seventh transistor T7 in each circuit unit.

[0295] In the example embodiment, the second initial signal line 72 can be provided with a second initial connection block 72-1. The second initial connection block 72-1 can be in the shape of a block (such as a rectangle), and can be arranged on the side of the second initial signal line 72 close to the second scan signal line 62 and connected to the second initial signal line 72. The second initial connection block 72-1 is configured to be connected to the second initial connection line formed subsequently.

[0296] In the example embodiment, in at least one circuit unit, the second initial signal line 72 and the second initial connection block 72-1 can be an integrated structure connected to each other.

[0297] In the example embodiment, the second initial connection block 72-1 can be arranged in the circuit unit of the (N+2)th unit column.

[0298] In the at least one circuit unit, a projection of the second initial signal line 72 on the substrate does not overlap with a projection of the first connection electrode 51 on the substrate, and / or a projection of the second initial signal line 72 on the substrate does not overlap with a projection of the third gate electrode 33 on the substrate, and / or a projection of the second initial signal line 72 on the substrate does not overlap with a projection of the plate connection strip 38 on the substrate, and / or a projection of the second initial signal line 72 on the substrate does not overlap with a projection of the sixth connection electrode 56 on the substrate, and / or a projection of the second initial signal line 72 on the substrate does not overlap with a projection of the fourth plate 14 on the substrate. Since the first connection electrode 51, the third gate electrode 33, the plate connection strip 38, the sixth connection electrode 56 and the fourth plate 14 all have the first node potential, the overlap capacitance between the first node N1 and the second initial signal line 72 can be effectively reduced by the position setting of the second initial signal line 72, and thus the parasitic capacitance of the first node N1 is reduced.

[0299] In the at least one circuit unit, a projection of the second initial signal line 72 on the substrate does not overlap with a projection of the second connection electrode 52 on the substrate, and / or a projection of the second initial signal line 72 on the substrate does not overlap with a projection of the first plate 11 on the substrate, and / or a projection of the second initial signal line 72 on the substrate does not overlap with a projection of the third plate 13 on the substrate. Since the second connection electrode 52, the first plate 11 and the third plate 13 have the second node potential, the overlap capacitance between the second node N2 and the second initial signal line 72 can be effectively reduced by the position setting of the second initial signal line 72, and thus the parasitic capacitance of the second node N2 is reduced.

[0300] In the at least one circuit unit, a projection of the second initial signal line 72 on the substrate does not overlap with a projection of the third connection electrode 53 on the substrate.

[0301] In the at least one circuit unit, a projection of the second initial signal line 72 on the substrate does not overlap with a projection of the third connection electrode 53 on the substrate.

[0302] In the example embodiment, the fourth scan signal line 64 can be located on the side of the third gate electrode 33 in the opposite direction of the second direction Y, the second power supply connection line 66 can be located on the side of the fourth scan signal line 64 away from the third gate electrode 33, and the first power supply connection line 65 can be located on the side of the second power supply connection line 66 away from the third gate electrode 33. The first scan signal line 61 can be located on the side of the third gate electrode 33 in the second direction Y, the first initial signal line 71 can be located on the side of the first scan signal line 61 away from the third gate electrode 33, the second scan signal line 62 can be located on the side of the first initial signal line 71 away from the third gate electrode 33, the second initial signal line 72 can be located on the side of the second scan signal line 62 away from the third gate electrode 33, and the third scan signal line 63 can be located on the side of the second initial signal line 72 away from the third gate electrode 33.

[0303] In the example embodiment, the orthographic projection of the first power supply connection line 65 on the substrate at least partially overlaps the orthographic projection of the first light-emitting signal line 41 on the substrate. The first power supply connection line 65 having a constant potential can effectively shield the first light-emitting signal transmitted by the first light-emitting signal line 41 from affecting the pixel driving circuit, thereby improving the working stability of the pixel driving circuit.

[0304] In the example embodiment, the fourth conductive layers in some adjacent unit columns can be mirror-symmetrical relative to the column center line. For example, the fourth conductive layers in the Nth unit column and the N+1th unit column can be mirror-symmetrical relative to the column center line. For another example, the fourth conductive layers in the N+1th unit column and the N+2th unit column can be mirror-symmetrical relative to the column center line.

[0305] In the example embodiment, the fourth conductive layers in some adjacent unit columns can be substantially the same. For example, the fourth conductive layers in the Nth unit column and the N+2th unit column can be substantially the same.

[0306] In some possible embodiments, the distance between the fourth plate 14 and the fifth plate 15 can be reduced by reducing the thickness of the fourth insulating layer to effectively improve the capacitance value of the third capacitor C3, without affecting the process stability, which is not limited in the present disclosure.

[0307] (17) Forming a fifth insulating layer and a first planar layer pattern. In the example embodiment, forming the fifth insulating layer and the first planar layer pattern can include: on the substrate on which the aforementioned patterns are formed, first depositing a fifth insulating thin film, then coating a first planar thin film, and patterning the fifth insulating thin film and the first planar thin film by using a patterning process to form a fifth insulating layer covering the fourth conductive layer pattern and a first planar layer disposed on the fifth insulating layer, and the fifth insulating layer and the first planar layer are provided with a plurality of vias, as shown in FIG. 15.

[0308] In an exemplary embodiment, the plurality of via holes in each circuit unit in the display substrate at least includes: a twenty-first via hole V21 and a twenty-second via hole V22.

[0309] In an exemplary embodiment, a projection of the twenty-first via hole V21 on the substrate is within a projection of the fourth connection electrode 54 on the substrate, the fifth insulating layer and the first planar layer in the twenty-first via hole V21 are removed to expose a surface of the fourth connection electrode 54, and the twenty-first via hole V21 is configured to allow a data signal line formed subsequently to connect to the fourth connection electrode 54 through the via hole.

[0310] In an exemplary embodiment, a projection of the twenty-second via hole V22 on the substrate is within a projection of the fifth connection electrode 55 on the substrate, the fifth insulating layer and the first planar layer in the twenty-second via hole V22 are removed to expose a surface of the fifth connection electrode 55, and the twenty-second via hole V22 is configured to allow an anode connection electrode formed subsequently to connect to the fifth connection electrode 55 through the via hole.

[0311] In an exemplary embodiment, the at least one circuit unit can further include a twenty-third via hole V23. A projection of the twenty-third via hole V23 on the substrate is within a projection of the first power connection block 65-1 on the substrate, the fifth insulating layer and the first planar layer in the twenty-third via hole V23 are removed to expose a surface of the first power connection block 65-1, and the twenty-third via hole V23 is configured to allow a first power line formed subsequently to connect to the first power connection block 65-1 through the via hole.

[0312] In an exemplary embodiment, the twenty-third via hole V23 can be respectively arranged in the circuit units in the (N+1)th unit column and the (N+2)th unit column.

[0313] In an exemplary embodiment, the at least one circuit unit can further include a twenty-fourth via hole V24. A projection of the twenty-fourth via hole V24 on the substrate is within a projection of the second power connection block 66-1 on the substrate, the fifth insulating layer and the first planar layer in the twenty-fourth via hole V24 are removed to expose a surface of the second power connection block 66-1, and the twenty-fourth via hole V24 is configured to allow a second power line formed subsequently to connect to the second power connection block 66-1 through the via hole.

[0314] In an exemplary embodiment, the twenty-fourth via hole V24 can be arranged between the Nth unit column and the (N+1)th unit column.

[0315] In an exemplary embodiment, the at least one circuit unit can further include a twenty-fifth via V25. A projection of the twenty-fifth via V25 on the substrate is within a projection of the first initial connection block 71-1 on the substrate, a fifth insulating layer and the first planar layer within the twenty-fifth via V25 are removed to expose a surface of the first initial connection block 71-1, and the twenty-fifth via V25 is configured to enable a subsequently formed first initial connection line to connect to the first initial connection block 71-1 through the via.

[0316] In an exemplary embodiment, the twenty-fifth via V25 can be disposed in a circuit unit of the Nth unit column.

[0317] In an exemplary embodiment, the at least one circuit unit can further include a twenty-sixth via V26. A projection of the twenty-sixth via V26 on the substrate is within a projection of the second initial connection block 72-1 on the substrate, a fifth insulating layer and the first planar layer within the twenty-sixth via V26 are removed to expose a surface of the second initial connection block 72-1, and the twenty-sixth via V26 is configured to enable a subsequently formed second initial connection line to connect to the second initial connection block 72-1 through the via.

[0318] In an exemplary embodiment, the twenty-sixth via V26 can be disposed in a circuit unit of the N+2th unit column.

[0319] (18) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer can include: on the substrate on which the aforementioned pattern is formed, depositing a fifth conductive thin film, and patterning the fifth conductive thin film using a patterning process to form a fifth conductive layer disposed on the first planar layer, as shown in FIGS. 16A and 16B, FIG. 16B being a plan view of the fifth conductive layer in FIG. 16A. In an exemplary embodiment, the fifth conductive layer can be referred to as a second source-drain metal (SD2) layer.

[0320] In an exemplary embodiment, the fifth conductive layer of each circuit unit at least includes: a data signal line 83 and an anode connection electrode 84.

[0321] In an exemplary embodiment, the data signal line 83 can have a shape of a straight line or a broken line with a main body portion extending along the second direction Y, and the data signal line 83 is connected to the fourth connection electrode 54 through the twenty-first via V21. Since the fourth connection electrode 54 is connected to the first region of the fourth active layer through the via, it is achieved that the data signal line 83 can write a data signal to the first electrode of the fourth transistor T4.

[0322] In the exemplary embodiments, the data signal line 83 in the Nth unit column and the data signal line 83 in the N+lth unit column can be mirror symmetrical relative to the column center line, the data signal line 83 in the N+lth unit column and the data signal line 83 in the N+2th unit column can be mirror symmetrical relative to the column center line, and the data signal line 83 in the Nth unit column and the data signal line 83 in the N+2th unit column can be substantially the same.

[0323] In the exemplary embodiments, in at least one circuit unit, the orthogonal projection of the data signal line 83 on the substrate does not overlap with the orthogonal projection of the first connection electrode 51 on the substrate, and / or the orthogonal projection of the data signal line 83 on the substrate does not overlap with the orthogonal projection of the third gate electrode 33 on the substrate, and / or the orthogonal projection of the data signal line 83 on the substrate does not overlap with the orthogonal projection of the plate connecting strip 38 on the substrate, and / or the orthogonal projection of the data signal line 83 on the substrate does not overlap with the orthogonal projection of the sixth connection electrode 56 on the substrate, and / or the orthogonal projection of the data signal line 83 on the substrate does not overlap with the orthogonal projection of the fourth plate 14 on the substrate. Since the first connection electrode 51, the third gate electrode 33, the plate connecting strip 38, the sixth connection electrode 56 and the fourth plate 14 have the first node potential, the overlapping capacitance between the first node N1 and the data signal line 83 can be effectively reduced by the position setting of the data signal line 83, and the parasitic capacitance of the first node N1 is further reduced.

[0324] In the exemplary embodiments, in at least one circuit unit, the orthogonal projection of the data signal line 83 on the substrate does not overlap with the orthogonal projection of the second connection electrode 52 on the substrate, and / or the orthogonal projection of the data signal line 83 on the substrate does not overlap with the orthogonal projection of the first plate 11 on the substrate, and / or the orthogonal projection of the data signal line 83 on the substrate does not overlap with the orthogonal projection of the third plate 13 on the substrate. Since the second connection electrode 52, the first plate 11 and the third plate 13 have the second node potential, the overlapping capacitance between the second node N2 and the data signal line 83 can be effectively reduced by the position setting of the data signal line 83, and the parasitic capacitance of the second node N2 is further reduced.

[0325] In the exemplary embodiments, in at least one circuit unit, the orthogonal projection of the data signal line 83 on the substrate does not overlap with the orthogonal projection of the third connection electrode 53 on the substrate.

[0326] In the exemplary embodiments, the data signal line 83 does not overlap with the plurality of connection electrodes, which can also avoid the influence of data voltage jump on the driving transistor and maximize the reduction of crosstalk influence.

[0327] In the example embodiment, the anode connecting electrode 84 can have a strip shape extending along the second direction Y, the anode connecting electrode 84 is connected with the fifth connecting electrode 55 through the twenty-second via V22, and the anode connecting electrode 84 is configured to be connected with the anode to be formed subsequently. Since the fifth connecting electrode 55 is connected with the second region of the sixth active layer (also the second region of the seventh active layer) through the via, the pixel driving circuit can output a driving current to the light emitting device.

[0328] In the example embodiment, the fifth conductive layer of the at least one circuit unit can further include a first power supply line 81. The first power supply line 81 can have a straight line shape or a broken line shape with a main body portion extending along the second direction Y, and the first power supply line 81 is connected with the first power supply connecting block 65-1 through the twenty-third via V23. Since the first power supply connecting block 65-1 is connected with the first power supply connecting line 65, the first power supply connecting line 65 having a main body portion extending along the first direction X and the first power supply line 81 having a main body portion extending along the second direction Y are connected with each other, and the first power supply connecting line 65 and the first power supply line 81 form a meshed communication structure for transmitting the first power supply signal on the display substrate, which can effectively reduce the resistance of the first power supply line, reduce the voltage drop of the first power supply signal, effectively improve the uniformity of the first power supply signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0329] In the example embodiment, the first power supply line 81 can be arranged in the circuit units of the (N+1)th unit column and the (N+2)th unit column respectively, and the first power supply line 81 in the (N+1)th unit column and the first power supply line 81 in the (N+2)th unit column can be mirror symmetrical relative to the column center line.

[0330] In the example embodiment, in the at least one circuit unit, the orthographic projection of the first power supply line 81 on the substrate does not overlap with the orthographic projection of the third gate electrode 33 on the substrate, and / or the orthographic projection of the first power supply line 81 on the substrate does not overlap with the orthographic projection of the plate connecting strip 38 on the substrate, and / or the orthographic projection of the first power supply line 81 on the substrate does not overlap with the orthographic projection of the sixth connecting electrode 56 on the substrate, and / or the orthographic projection of the first power supply line 81 on the substrate does not overlap with the orthographic projection of the fourth plate 14 on the substrate. Since the third gate electrode 33, the plate connecting strip 38, the sixth connecting electrode 56 and the fourth plate 14 have the first node potential, the position of the first power supply line 81 and the broken line shape of the first power supply line 81 can effectively reduce the overlapping capacitance between the first node N1 and the first power supply line 81, and further reduce the parasitic capacitance of the first node N1.

[0331] In the example embodiment, in at least one circuit unit, the first power line 81 has no intersection with the orthogonal projection of the first plate 11 on the substrate, and / or the first power line 81 has no intersection with the orthogonal projection of the third plate 13 on the substrate. Since the first plate 11 and the third plate 13 have the second node potential, the position setting and the zigzag setting of the first power line 81 can effectively reduce the overlapping capacitance between the second node N2 and the first power line 81, and further reduce the parasitic capacitance of the second node N2.

[0332] In the example embodiment, in at least one circuit unit, the first power line 81 has no intersection with the orthogonal projection of the third connection electrode 53 on the substrate.

[0333] In the example embodiment, the fifth conductive layer of the at least one circuit unit can further include a second power line 82. The second power line 82 can have a shape of a straight line or a zigzag line with a main body portion extending along the second direction Y, and the second power line 82 is connected to the second power connection block 66-1 through the twenty-fourth via hole V24. Since the second power connection block 66-1 is connected to the second power connection line 66, the mutual connection between the second power connection line 66 extending along the first direction X and the second power line 82 extending along the second direction Y is achieved, and the second power connection line 66 and the second power line 82 form a meshed communication structure for transmitting the second power signal on the display substrate, which can effectively reduce the resistance of the second power line, reduce the voltage drop of the second power signal, effectively improve the uniformity of the second power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance. In addition, by arranging the second power line in the display area, the second power line is arranged in the SIP (SIP) structure, which can greatly reduce the width of the frame power lead, greatly reduce the left and right frame widths, improve the screen-to-body ratio, and be conducive to realizing the full-screen display.

[0334] In the example embodiment, the second power line 82 can be arranged in the circuit unit of the Nth unit column and the N+1th unit column, respectively. The second power line 82 in the Nth unit column and the second power line 82 in the N+1th unit column can be mirror-symmetrical relative to the column center line, and the second power lines 82 in the two unit columns can be an integrated structure connected to each other.

[0335] In the example embodiment, the second power line 82 can have a variable width structure, and the width of the second power line is the size of the first direction X.

[0336] In the exemplary embodiments, in at least one of the circuit units, the orthogonal projection of the second power line 82 on the substrate does not overlap with the orthogonal projection of the first connection electrode 51 on the substrate, and / or the orthogonal projection of the second power line 82 on the substrate does not overlap with the orthogonal projection of the third gate electrode 33 on the substrate, and / or the orthogonal projection of the second power line 82 on the substrate does not overlap with the orthogonal projection of the plate connection strip 38 on the substrate, and / or the orthogonal projection of the second power line 82 on the substrate does not overlap with the orthogonal projection of the sixth connection electrode 56 on the substrate. Since the first connection electrode 51, the third gate electrode 33, the plate connection strip 38 and the sixth connection electrode 56 all have the first node potential, the overlap capacitance between the first node N1 and the second power line 82 can be effectively reduced by changing the width of the second power line, thereby reducing the parasitic capacitance of the first node N1.

[0337] In the exemplary embodiments, in at least one of the circuit units, the orthogonal projection of the second power line 82 on the substrate at least partially overlaps with the orthogonal projection of the fourth plate 14 and the fifth plate 15 on the substrate, and the fifth plate 15 is arranged between the fourth plate 14 and the second power line 82 in the direction perpendicular to the substrate. In this way, the fifth plate 15 can effectively shield the overlap capacitance between the second power line 82 and the first node N1, further reducing the parasitic capacitance of the first node N1.

[0338] In the exemplary embodiments, in at least one of the circuit units, the orthogonal projection of the second power line 82 on the substrate does not overlap with the orthogonal projection of the second connection electrode 52 on the substrate. Since the second connection electrode 52 has the second node potential, the overlap capacitance between the second node N2 and the second power line 82 can be effectively reduced by changing the width of the second power line, thereby reducing the parasitic capacitance of the second node N2.

[0339] In some possible embodiments, the anode formed subsequently can shield the third transistor T3, i.e., the orthogonal projection of the anode on the substrate at least partially overlaps with the orthogonal projection of the third gate electrode on the substrate, which is not limited in the present disclosure.

[0340] In the example embodiment, the fifth conductive layer of the at least one circuit unit can further include a first initial connection line 73. The first initial connection line 73 can have a shape of a straight line or a broken line with a main body extending along the second direction Y, and the first initial connection line 73 can be connected to the first initial connection block 71-1 through a twenty-fifth via hole V25. Since the first initial connection block 71-1 is connected to the first initial signal line 71, the first initial signal line 71 with the main body extending along the first direction X and the first initial connection line 73 with the main body extending along the second direction Y are connected to each other, and the first initial signal line 71 and the first initial connection line 73 form a meshed and connected structure for transmitting the first initial signal on the display substrate, which can effectively reduce the resistance of the first initial connection line, reduce the voltage drop of the first initial signal, effectively improve the uniformity of the first initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0341] In the example embodiment, the first initial connection line 73 can be arranged in the circuit unit of the Nth unit column.

[0342] In the example embodiment, in the at least one circuit unit, the orthographic projection of the first initial connection line 73 on the substrate does not overlap the orthographic projection of the third gate electrode 33 on the substrate, and / or the orthographic projection of the first initial connection line 73 on the substrate does not overlap the orthographic projection of the plate connection strip 38 on the substrate, and / or the orthographic projection of the first initial connection line 73 on the substrate does not overlap the orthographic projection of the sixth connection electrode 56 on the substrate, and / or the orthographic projection of the first initial connection line 73 on the substrate does not overlap the orthographic projection of the fourth plate 14 on the substrate. Since the third gate electrode 33, the plate connection strip 38, the sixth connection electrode 56, and the fourth plate 14 have the first node potential, the position arrangement and the broken line arrangement of the first initial connection line 73 can effectively reduce the overlapping capacitance between the first node N1 and the first initial connection line 73, and further reduce the parasitic capacitance of the first node N1.

[0343] In the example embodiment, in the at least one circuit unit, the orthographic projection of the first initial connection line 73 on the substrate does not overlap the orthographic projection of the first plate 11 on the substrate, and / or the orthographic projection of the first initial connection line 73 on the substrate does not overlap the orthographic projection of the third plate 13 on the substrate. Since the first plate 11 and the third plate 13 have the second node potential, the position arrangement and the broken line arrangement of the first initial connection line 73 can effectively reduce the overlapping capacitance between the second node N2 and the first initial connection line 73, and further reduce the parasitic capacitance of the second node N2.

[0344] In the example embodiment, in the at least one circuit unit, the first initial connection line 73 has no intersection with the orthogonal projection of the third connection electrode 53 on the substrate.

[0345] In the example embodiment, the fifth conductive layer of the at least one circuit unit can further include a second initial connection line 74. The second initial connection line 74 can have a shape of a straight line or a broken line with a main body extending along the second direction Y, and the second initial connection line 74 is connected to the second initial connection block 72-1 through a twenty-sixth via V26. Since the second initial connection block 72-1 is connected to the second initial signal line 72, the second initial signal line 72 with the main body extending along the first direction X and the second initial connection line 74 with the main body extending along the second direction Y are connected to each other, and the second initial signal line 72 and the second initial connection line 74 form a meshed and connected structure for transmitting the second initial signal on the display substrate, which can effectively reduce the resistance of the second initial connection line, reduce the voltage drop of the second initial signal, effectively improve the uniformity of the second initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0346] In the example embodiment, the second initial connection line 74 can be arranged in the circuit unit of the (N+2)th unit column, and the position and shape of the second initial connection line 74 in the (N+2)th unit column can be substantially the same as the position and shape of the second power line 82 in the Nth unit column.

[0347] In the example embodiment, in the at least one circuit unit, the second initial connection line 74 has no intersection with the orthogonal projection of the first connection electrode 51 on the substrate, and / or the second initial connection line 74 has no intersection with the orthogonal projection of the third gate electrode 33 on the substrate, and / or the second initial connection line 74 has no intersection with the orthogonal projection of the plate connection strip 38 on the substrate, and / or the second initial connection line 74 has no intersection with the orthogonal projection of the sixth connection electrode 56 on the substrate. Since the first connection electrode 51, the third gate electrode 33, the plate connection strip 38, and the sixth connection electrode 56 all have the first node potential, the overlapping capacitance between the first node N1 and the second initial connection line 74 can be effectively reduced by changing the width of the second power line, and the parasitic capacitance of the first node N1 can be reduced.

[0348] In the example embodiment, in the at least one circuit unit, the orthogonal projection of the second initial connection line 74 on the substrate at least partially overlaps the orthogonal projection of the fourth plate 14 and the fifth plate 15 on the substrate, and the fifth plate 15 is arranged between the fourth plate 14 and the second initial connection line 74 in the direction perpendicular to the substrate. In this way, the fifth plate 15 can effectively shield the overlapping capacitance between the second initial connection line 74 and the first node N1, further reducing the parasitic capacitance of the first node N1.

[0349] In the example embodiment, in the at least one circuit unit, the orthogonal projection of the second initial connection line 74 on the substrate does not overlap the orthogonal projection of the second connection electrode 52 on the substrate. Since the second connection electrode 52 has the second node potential, the overlapping capacitance between the second node N2 and the second initial connection line 74 can be effectively reduced by changing the width of the second power line, thereby reducing the parasitic capacitance of the second node N2.

[0350] In the example embodiment, the average width of the second power line 82 can be greater than the average width of the first power line 81, and the width can be the size of the first direction X. The present disclosure effectively reduces the resistance of the second power line 82 by arranging the second power line 82 with a wider wiring, not only reduces the voltage drop of the second power signal transmission, but also effectively improves the uniformity of the second power signal in the display substrate, effectively improves the display uniformity, and improves the display quality and display quality.

[0351] In the example embodiment, the average width of the first initial connection line 73 can be substantially the same as the average width of the first power line 81, and the average width of the second initial connection line 74 can be substantially the same as the average width of the second power line 82.

[0352] FIG. 17 is a schematic diagram of a mesh communication structure according to an example embodiment of the present disclosure. As shown in FIG. 17, the first power connection line 65, the second power connection line 66, the first initial signal line 71, and the second initial signal line 72 can have a shape of a straight line or a broken line with a main part extending along the first direction X, and can be arranged in the fourth conductive layer. The first initial connection line 73, the second initial connection line 74, the first power line 81, and the second power line 82 can have a shape of a straight line or a broken line with a main part extending along the second direction Y, and can be arranged in the fifth conductive layer.

[0353] In the example embodiment, the first power connection line 65 can be arranged in each unit row, the first power line 81 can be arranged in part of the unit columns (such as the N+1 unit column and the N+2 unit column), and the first power line 81 is connected to the first power connection line 65 through a via. The first power connection line 65 and the first power line 81 form a mesh communication structure for transmitting the first power signal on the display substrate.

[0354] In the example embodiment, the second power connection lines 66 can be arranged in each unit row, the second power lines 82 can be arranged in part of the unit columns (such as the Nth unit column and the N+1th unit column), and the second power lines 82 are connected with the second power connection lines 66 through the vias. The second power connection lines 66 and the second power lines 82 form a meshed communication structure for transmitting the second power signal on the display substrate.

[0355] In the example embodiment, the first initial signal lines 71 can be arranged in each unit row, the first initial connection lines 73 can be arranged in part of the unit columns (such as the Nth unit column), and the first initial connection lines 73 are connected with the first initial signal lines 71 through the vias. The first initial signal lines 71 and the first initial connection lines 73 form a meshed communication structure for transmitting the first initial signal on the display substrate.

[0356] In the example embodiment, the second initial signal lines 72 can be arranged in each unit row, the second initial connection lines 74 can be arranged in part of the unit columns (such as the N+2th unit column), and the second initial connection lines 74 are connected with the second initial signal lines 72 through the vias. The second initial signal lines 72 and the second initial connection lines 74 form a meshed communication structure for transmitting the second initial signal on the display substrate.

[0357] The subsequent preparation process can include forming a second planar layer, the second planar layer is provided with an anode via, the anode via exposes a surface of the anode connection electrode 84, and the anode via is configured to enable the subsequent formation of the anode to be connected with the anode connection electrode through the via.

[0358] So far, the driving structure layer of the present embodiment is prepared on the substrate. In the plane parallel to the display substrate, the driving structure layer can include a plurality of circuit units, each of which can include a pixel driving circuit, and a first scan signal line, a second scan signal line, a third scan signal line, a fourth scan signal line, a first light-emitting signal line, a second light-emitting signal line, a first initial signal line, a second initial signal line, a first power line, and a data signal line connected with the pixel driving circuit.

[0359] In the plane perpendicular to the display substrate, the driving structure layer can include, in sequence on the base, a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, a semiconductor layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fourth conductive layer, a fifth insulating layer, a first planar layer, a fifth conductive layer, and a second planar layer. The first conductive layer can include at least a first plate of a first capacitor and a third plate of a second capacitor, the second conductive layer can include at least a second plate of the first capacitor and a fourth plate of the second capacitor, the semiconductor layer can include at least a fifth plate, an active layer of a first transistor T1 to a seventh transistor T7, the third conductive layer can include at least a first light-emitting signal line, a second light-emitting signal line, and a gate electrode of a plurality of transistors, the fourth conductive layer can include at least a first scan signal line, a second scan signal line, a third scan signal line, a fourth scan signal line, a first power connection line, a second power connection line, a first initial signal line, and a second initial signal line, and the fifth conductive layer can include at least a first power line, a second power line, a data signal line, a first initial connection line, and a second initial connection line.

[0360] In an example embodiment, the base can be a flexible base, or can be a rigid base. The rigid base can include, but is not limited to, one or more of glass, quartz, and the flexible base can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an example embodiment, the flexible base can include, in sequence on a glass carrier plate, a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the like, and the materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), and the like, for improving the water and oxygen resistance of the base. The first and second inorganic material layers are also referred to as barrier layers, and the material of the semiconductor layer can be amorphous silicon (a-si).

[0361] In the exemplary embodiments, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer, multiple layers or a composite layer. The first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer can be a metal material such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) or molybdenum (Mo), or can be an alloy material composed of metals such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single layer structure or a multiple layer composite structure such as Ti / Al / Ti. The first planar layer and the second planar layer can be an organic material such as resin or polyimide.

[0362] In the exemplary embodiments, after the preparation of the driving structure layer is completed, the light emitting structure layer can be prepared on the driving structure layer, and the packaging structure layer can be prepared on the light emitting structure layer, which will not be described herein.

[0363] With the development of display technology, consumers have increasingly high requirements for the display effect and display quality of display products. In a display substrate using oxide transistors, the off-state current of the oxide transistor is low, and the leakage phenomenon is not easy to occur, the performance in the low frequency field is good, the process is relatively simple, and the cost is low, so it has attracted widespread attention. In a display substrate using all oxide transistors, there are problems such as display watermark (Mura) caused by thermal instability. Research has found that the temperature characteristics of the oxide driving transistor and the temperature characteristics of the light emitting device are the main causes of the display watermark and other problems. On the one hand, since the source electrode of the oxide driving transistor is at the third node N3, the threshold voltage is compensated at the third node N3 in the compensation stage, as the display time is prolonged, the temperature of the display substrate gradually increases, as the temperature increases, the threshold voltage of the driving transistor is negatively biased, the on current (Ion) increases, and after the threshold voltage compensation, there is a phenomenon of current increase caused by the increase of the on current, and the light emitting brightness increases. On the other hand, as the temperature gradually increases, the voltage of the light emitting device decreases, causing the third node N3 to jump, and the first node N1 is coupled to jump, but the potential change amount AV N3 of the third node N3 is greater than the potential change amount AV N1， of the first node N1, which causes the gate-source voltage Vgs (= V N1 -V N3 ) of the third transistor T3 (driving transistor) to increase, the output current of the pixel driving circuit to increase, and the light emitting brightness to increase. Since different positions on the display substrate have different temperatures, the brightness of different positions increases differently, the brightness of the display substrate is uneven, and display watermark appears.

[0364] This exemplary embodiment provides a display substrate that, by optimizing the structure of the pixel driving circuit and setting a third capacitor between the first node N1 and the third node N3, can effectively avoid displaying watermarks. Studies have shown that after setting the third capacitor, ΔV N1 / △V N3 Inversely proportional to the capacitance of the third capacitor, when the potential of the third node N3 changes, it can be transmitted to the first node N1 through the third capacitor, so that the potential of the first node N1 can change by the same amount, i.e., ΔV. N1 / △V N3 It is basically close to 1, which can effectively reduce the increase of the gate-source voltage Vgs of the third transistor T3, effectively reduce the change of the output current of the pixel driving circuit, effectively reduce the change of the light emission brightness, and effectively avoid displaying watermarks.

[0365] This disclosure provides a more compact arrangement of the pixel driving circuit while meeting design requirements. This effectively improves the layout space utilization, results in a more reasonable structural arrangement, and simplifies the signal line connection structure without complex overlap. This can effectively improve product yield and reduce production costs. By setting a first electrode plate and a third electrode plate in a first conductive layer, a second electrode plate and a fourth electrode plate in a second conductive layer, and a fifth electrode plate in a semiconductor layer, the first and second electrode plates form a first capacitor, the third and fourth electrode plates form a second capacitor, and the fourth and fifth electrode plates form a third capacitor.

[0366] This disclosure improves the uniformity and symmetry of the pixel driving circuit by setting a mirrored arrangement of the pixel driving circuits in some adjacent unit columns. This not only enables the design of uniform process and coupling capacitors, but also enables the design of uniform current distribution, effectively improving display stability and uniformity, and effectively enhancing display effect and display quality.

[0367] This disclosure sets the fifth and seventh active layers of some adjacent cell columns into an interconnected integrated structure, and the first, second, and fourth gate electrodes of some adjacent cell columns into an interconnected integrated structure. On the one hand, this can effectively reduce the lateral wiring space, reduce the number of vias, and reduce the area occupied by the pixel driving circuit, which is conducive to achieving high resolution. On the other hand, it can effectively increase the size of the capacitor plate and effectively increase the capacitance value of the capacitor, thereby maximizing the stability of the pixel driving circuit.

[0368] This embodiment of the present disclosure provides a first power connection line and a first power line, which form a mesh-like interconnected structure on the display substrate to transmit the first power signal. This not only effectively reduces the resistance of the first power line and the voltage drop of the first power signal, but also effectively improves the uniformity of the first power signal in the display substrate, thereby improving display uniformity and display quality.

[0369] The second power supply connection line and the second power supply line form a meshed communication structure for transmitting the second power supply signal on the display substrate, which can effectively reduce the resistance of the second power supply line, reduce the voltage drop of the second power supply signal, effectively improve the uniformity of the second power supply signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display effect.

[0370] The second power supply line is arranged in the display area, and the second power supply line is arranged in a panel (VSS in Panel, SIP for short) structure, which can greatly reduce the width of the frame power supply lead, greatly reduce the left and right frame widths, improve the screen-to-body ratio, and be conducive to realizing a full-screen display.

[0371] The first initial connection line and the second initial connection line form a meshed communication structure for transmitting the first initial signal and the second initial signal on the display substrate, which can effectively reduce the resistance of the initial signal line, reduce the voltage drop of the initial signal, effectively improve the uniformity of the initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display effect.

[0372] The data signal line and the plurality of connection electrodes are arranged without overlapping each other, which can avoid signal crosstalk caused by data voltage jump of the data signal line, avoid the influence of data voltage jump on the transistor, improve the working stability of the pixel driving circuit, and improve the display effect.

[0373] The plurality of scanning signal lines are arranged in the first source-drain metal layer, which can effectively reduce the resistance of the scanning signal line, reduce the voltage drop of the scanning signal, improve the compensation speed, and improve the display quality.

[0374] The preparation process of the display substrate can be well compatible with the existing preparation process, and the process is simple to implement, high in production efficiency, low in production cost, and high in yield.

[0375] FIG. 18 is a structural schematic diagram of another display substrate according to an example embodiment of the present disclosure, which illustrates the structure of three circuit units. FIG. 19 is a schematic diagram of another capacitor structure according to an example embodiment of the present disclosure, and FIG. 20 is a sectional view in the direction of B-B in FIG. 18. As shown in FIGS. 18, 19 and 20, in the example embodiment, the structure of the display substrate of the present embodiment is basically the same as that of the foregoing embodiments, except that the third capacitor 30 of the present embodiment can include at least a fourth plate 14 and a sixth plate 16 as a first end, and a fifth plate 15 as a second end.

[0376] In an exemplary embodiment, the third capacitor 30 can comprise at least a first sub-capacitor and a second sub-capacitor. The first sub-capacitor can comprise the fourth plate 14 as a first terminal of the first sub-capacitor and the fifth plate 15 as a second terminal of the first sub-capacitor, and the second sub-capacitor can comprise the sixth plate as a first terminal of the second sub-capacitor and the fifth plate 15 as a second terminal of the second sub-capacitor, the first sub-capacitor and the second sub-capacitor sharing the fifth plate 15.

[0377] In an exemplary embodiment, the fifth plate 15 can be disposed in the semiconductor layer, the fifth plate 15 can be connected with the second plate 12 through the third connecting electrode 53, the fifth plate 15 can serve as a second terminal of the third capacitor 30 and has a third node potential. The fourth plate 14 can serve as a first terminal of the third capacitor 30 and has a first node potential. The fourth plate 14 serves as a capacitor plate of the second capacitor C2 on one hand and serves as a capacitor plate of the third capacitor C3 on the other hand, i.e. the second capacitor C2 and the third capacitor C3 share the same capacitor plate.

[0378] In an exemplary embodiment, the fifth plate 15 has an orthographic projection on the substrate which at least partially overlaps with an orthographic projection of the fourth plate 14 on the substrate, the fourth plate 14 having the first node potential and the fifth plate 15 having the third node potential form a first sub-capacitor of the third capacitor C3.

[0379] In an exemplary embodiment, the sixth plate 16 can be disposed in the third conductive layer, the sixth plate 16 can be connected with the fourth plate 14 through the plate connecting strip 38 and the sixth connecting electrode 56, thus the fourth plate 14 and the sixth plate 16 have the same first node potential.

[0380] In an exemplary embodiment, a first end of the sixth connecting electrode 56 is connected with the fourth plate 14, a second end of the sixth connecting electrode 56 is connected with the plate connecting strip 38, a first end of the plate connecting strip 38 is connected with the third gate electrode 33, and a second end of the plate connecting strip 38 is connected with the sixth plate 16.

[0381] In an exemplary embodiment, in at least one circuit unit, the sixth plate 16, the third gate electrode 33 and the plate connecting strip 38 can be an integrated structure connected with each other.

[0382] In an exemplary embodiment, the sixth plate 16 has an orthographic projection on the substrate which at least partially overlaps with an orthographic projection of the fifth plate 15 on the substrate, the sixth plate 16 having the first node potential and the fifth plate 15 having the third node potential form a second sub-capacitor of the third capacitor C3.

[0383] In an exemplary embodiment, the first sub-capacitor and the second sub-capacitor of the parallel structure form the third capacitor C3 of the pixel driving circuit.

[0384] In an example embodiment, the orthographic projection of the sixth plate 16 on the substrate can be located within the orthographic projection of the fifth plate 15 on the substrate.

[0385] In an example embodiment, the preparation process of the substrate can include the following operations.

[0386] (21) The first conductive layer, the second conductive layer and the semiconductor layer pattern are sequentially formed. In an example embodiment, the process of forming the first conductive layer, the second conductive layer and the semiconductor layer pattern and the structure of the formed first conductive layer, the second conductive layer and the semiconductor layer are substantially the same as the foregoing embodiments, which will not be repeated here.

[0387] (24) The third conductive layer pattern is formed. In an example embodiment, the process of forming the third conductive layer pattern and the structure of the formed third conductive layer are substantially the same as the foregoing embodiments, except that the third conductive layer can further include the sixth plate 16, as shown in FIGS. 21A and 21B, which is a schematic view of the third conductive layer in FIG. 21A.

[0388] In an example embodiment, the shape of the sixth plate 16 can be rectangular, the orthographic projection of the sixth plate 16 on the substrate at least partially overlaps the orthographic projection of the fifth plate 15 on the substrate, and the sixth plate 16 is configured as another capacitor plate of the third capacitor.

[0389] In an example embodiment, the sixth plate 16 can be disposed on one side of the plate connecting strip 38 in the second direction Y and connected with the plate connecting strip 38, i.e., the first end of the plate connecting strip 38 is connected with the third gate electrode 33, and the second end of the plate connecting strip 38 is connected with the sixth plate 16.

[0390] In an example embodiment, in at least one circuit unit, the sixth plate 16, the third gate electrode 33 and the plate connecting strip 38 can be an integrated structure connected with each other.

[0391] In an example embodiment, the orthographic projection of the sixth plate 16 on the substrate can be located within the orthographic projection of the fifth plate 15 on the substrate, so that the semiconductor layer between the third gate electrode 33 and the second light emitting signal line 42 retains a current channel.

[0392] In an example embodiment, taking the circuit unit in the N+2th unit column as an example, a current channel can be formed between the edge of the sixth plate 16 on the first direction X side and the edge of the fifth plate 15 on the first direction X side.

[0393] (25) to (28) form a fourth insulating layer, a fourth conductive layer, a fifth insulating layer, a first planar layer, and a fifth conductive layer pattern in sequence, and the forming process and the structure of the fourth insulating layer, the fourth conductive layer, the fifth insulating layer, the first planar layer, and the fifth conductive layer formed are substantially the same as those of the foregoing embodiments, as shown in FIG. 18.

[0394] In the exemplary embodiment, the first plate 11 having the second node potential and the second plate 12 having the third node potential form a first capacitor C1 of the pixel driving circuit, the third plate 13 having the second node potential and the fourth plate 14 having the first node potential form a second capacitor C2 of the pixel driving circuit, and the structure of the first capacitor C1 and the second capacitor C2 is substantially the same as that of the foregoing embodiments.

[0395] In the exemplary embodiment, since the sixth plate 16 is connected to the fourth plate 14 through the plate connection strip 38 and the sixth connection electrode 56, the fourth plate 14 and the sixth plate 16 have the same first node potential. In this way, the fifth plate 15 having the third node potential and the fourth plate 14 having the first node potential can form a first sub-capacitor, the fifth plate 15 having the third node potential and the sixth plate 16 having the first node potential can form a second sub-capacitor, and the first sub-capacitor and the second sub-capacitor in parallel form a third capacitor C3 of the pixel driving circuit.

[0396] The display substrate provided by the embodiment not only has the technical effects of the foregoing embodiments, but also maximizes the capacitance value of the third capacitor by arranging the first plate and the third plate in the first conductive layer, the second plate and the fourth plate in the second conductive layer, the fifth plate in the semiconductor layer, and the sixth plate in the third conductive layer, forming the first plate and the second plate into a first capacitor, the third plate and the fourth plate into a second capacitor, the fourth plate and the fifth plate into a first sub-capacitor of a third capacitor, the fifth plate and the sixth plate into a second sub-capacitor of the third capacitor, and the first sub-capacitor and the second sub-capacitor in a parallel structure into the third capacitor, maximizes the change of the output current of the pixel driving circuit, maximizes the change of the luminance of light emission, and maximizes the avoidance of display watermarking.

[0397] FIG. 22 is a schematic view of another capacitor structure of an exemplary embodiment of the present disclosure. As shown in FIG. 22, the display substrate of the embodiment can at least include a first conductive layer, a second conductive layer, a semiconductor layer, and a third conductive layer arranged in sequence on a substrate 101, can at least include a second plate 12 in the first conductive layer, can at least include a seventh plate 17 in the second conductive layer, can at least include a fifth plate 15 in the semiconductor layer, and can at least include a fourth plate 14 in the third conductive layer.

[0398] In the example embodiment, the seventh plate 17 can serve as the second terminal of the first capacitor and as the second terminal of the second capacitor, i.e. the first capacitor and the second capacitor share the same seventh plate 17, and the seventh plate 17 has the second node potential.

[0399] In the example embodiment, the second plate 12 can serve as the first terminal of the first capacitor and has the third node potential. The seventh plate 17 has a projection on the substrate that at least partially overlaps with a projection of the second plate 12 on the substrate, and the seventh plate 17 having the second node potential and the second plate 12 having the third node potential form the first capacitor C1 of the pixel driving circuit.

[0400] In the example embodiment, the fourth plate 14 can serve as the first terminal of the second capacitor and has the first node potential. The fourth plate 14 has a projection on the substrate that at least partially overlaps with a projection of the seventh plate 17 on the substrate, and the seventh plate 17 having the second node potential and the fourth plate 14 having the first node potential form the second capacitor C2 of the pixel driving circuit.

[0401] In the example embodiment, the fifth plate 15 can serve as the second terminal of the third capacitor and has the third node potential. The fifth plate 15 has a projection on the substrate that at least partially overlaps with a projection of the fourth plate 14 on the substrate, and the fourth plate 14 having the first node potential and the fifth plate 15 having the third node potential form the third capacitor C3 of the pixel driving circuit.

[0402] In the example embodiment, the fourth plate 14 serves as one capacitor plate (first terminal) of the second capacitor C2 and as one capacitor plate (first terminal) of the third capacitor C3, i.e. the second capacitor C2 and the third capacitor C3 share the same capacitor plate.

[0403] In some possible embodiments, the second plate 12 can serve as the first terminal of the second capacitor and has the first node potential, and the second plate 12 and the seventh plate 17 form the second capacitor C2 of the pixel driving circuit. The fourth plate 14 can serve as the first terminal of the first capacitor and has the third node potential, and the fourth plate 14 and the seventh plate 17 form the first capacitor C1 of the pixel driving circuit. The fifth plate 15 can serve as the first terminal of the third capacitor and has the first node potential, and the fifth plate 15 and the fourth plate 14 form the third capacitor C3 of the pixel driving circuit.

[0404] FIG. 23 is a schematic diagram of yet another capacitor structure according to an example embodiment of the present disclosure. As shown in FIG. 23, the main structure of the first capacitor, the second capacitor and the third capacitor in the present embodiment is basically the same as that in the embodiment shown in FIG. 22, except that the third capacitor can include a third sub-capacitor and a fourth sub-capacitor.

[0405] In the example embodiment, the fourth plate 14 can serve as a first terminal of a third sub-capacitor and have a first node potential, and the fifth plate 15 can serve as a second terminal of the third sub-capacitor and have a third node potential. The fourth plate 14 can serve as a first terminal of a fourth sub-capacitor and have the first node potential, and the second plate 12 can serve as a second terminal of the fourth sub-capacitor and have the third node potential. The fifth plate 15 has a projection on the substrate that at least partially overlaps with a projection of the fourth plate 14 on the substrate, and the fourth plate 14 having the first node potential and the fifth plate 15 having the third node potential form the third sub-capacitor. The second plate 12 has a projection on the substrate that at least partially overlaps with a projection of the fourth plate 14 on the substrate, and the fourth plate 14 having the first node potential and the second plate 12 having the third node potential form the fourth sub-capacitor. In this way, the third sub-capacitor and the fourth sub-capacitor in parallel form the third capacitor C3 of the pixel driving circuit.

[0406] In the example embodiment, the fourth sub-capacitor can be formed by extending the second plate 12 in the first conductive layer and the fourth plate 14 in the third conductive layer, and the present disclosure is not limited in this regard.

[0407] In some possible embodiments, the second plate 12 can serve as a first terminal of a second capacitor and have a first node potential, and the second plate 12 and the seventh plate 17 form the second capacitor C2 of the pixel driving circuit. The fourth plate 14 can serve as a first terminal of a first capacitor and have a third node potential, and the fourth plate 14 and the seventh plate 17 form the first capacitor C1 of the pixel driving circuit. The fifth plate 15 can serve as a first terminal of a third capacitor, the second plate 12 can serve as another first terminal of the third capacitor, and both have the first node potential, and the fourth plate 14 can serve as a second terminal of the third capacitor. The fifth plate 15 and the fourth plate 14 form a third sub-capacitor, the second plate 12 and the fourth plate 14 form a fourth sub-capacitor, and the third sub-capacitor and the fourth sub-capacitor in parallel form the third capacitor C3 of the pixel driving circuit. In this way, the fourth plate 14 serves as a capacitor plate of both the first capacitor C1 and the third capacitor C3, i.e., the first capacitor C1 and the third capacitor C3 share the same capacitor plate.

[0408] In other possible embodiments, the fifth plate 15 can have a third node potential, the fifth plate 15 and the second plate 12 form a third sub-capacitor, the second plate 12 and the fourth plate 14 form a fourth sub-capacitor, and the third sub-capacitor and the fourth sub-capacitor in parallel form the third capacitor C3 of the pixel driving circuit.

[0409] FIG. 24 is a schematic view of another capacitive structure according to an exemplary embodiment of the present disclosure. As shown in FIG. 24, the display substrate according to the present embodiment can include, in sequence on the substrate 101, a first conductive layer, a second conductive layer, a semiconductor layer, a third conductive layer, and a fourth conductive layer. The first conductive layer can include at least the second plate 12, the second conductive layer can include at least the seventh plate 17, the semiconductor layer can include at least the fifth plate 15, the third conductive layer can include at least the fourth plate 14, and the fourth conductive layer can include at least the eighth plate 18. The eighth plate 18 is connected to the seventh plate 17 through a via.

[0410] In the exemplary implementation, the seventh plate 17 can serve as the second end of the first capacitor and the second end of the second capacitor, i.e., the first capacitor and the second capacitor share the same seventh plate 17, and the seventh plate 17 has the second node potential. Since the eighth plate 18 is connected to the seventh plate 17, the eighth plate 18 has the second node potential.

[0411] In the exemplary implementation, the second plate 12 can serve as the first end of the first capacitor and has the third node potential. The seventh plate 17 has the second node potential, and the seventh plate 17 and the second plate 12 form the first capacitor C1 of the pixel driving circuit.

[0412] In the exemplary implementation, the second capacitor C2 can include a fifth sub-capacitor and a sixth sub-capacitor. The fifth sub-capacitor can include the fourth plate 14 as the first end of the fifth sub-capacitor and the seventh plate 17 as the second end of the fifth sub-capacitor. The fourth plate 14 has the first node potential, and the seventh plate 17 has the second node potential. The sixth sub-capacitor can include the fourth plate 14 as the first end of the sixth sub-capacitor and the eighth plate 18 as the second end of the sixth sub-capacitor. The fourth plate 14 has the first node potential, and the eighth plate 18 has the second node potential. In this way, the fifth sub-capacitor and the sixth sub-capacitor in parallel form the second capacitor C2 of the pixel driving circuit.

[0413] In the exemplary implementation, the fifth plate 15 can serve as the second end of the third capacitor and has the third node potential. The fifth plate 15 has the third node potential, and the fourth plate 14 has the first node potential. The fifth plate 15 and the fourth plate 14 form the third capacitor C3 of the pixel driving circuit.

[0414] In the exemplary embodiment, the fourth plate 14 serves as one of the capacitor plates of the second capacitor C2 on the one hand, and as one of the capacitor plates of the third capacitor C3 on the other hand, i.e. the second capacitor C2 and the third capacitor C3 share the same capacitor plate.

[0415] In some possible embodiments, the second plate 12 can have the first node potential, the second plate 12 and the seventh plate 17 form the second capacitor C2 of the pixel driving circuit. The fourth plate 14 can have the third node potential, the fourth plate 14 and the seventh plate 17 form the fifth sub-capacitor, the fourth plate 14 and the eighth plate 18 form the sixth sub-capacitor, and the fifth sub-capacitor and the sixth sub-capacitor in parallel structure constitute the first capacitor C1 of the pixel driving circuit. The fifth plate 15 can have the first node potential, the fifth plate 15 and the fourth plate 14 form the third capacitor C3 of the pixel driving circuit.

[0416] FIG. 25 is a schematic view of another capacitor structure of the exemplary embodiments of the present disclosure. As shown in FIG. 25, the main structure of the first capacitor, the second capacitor and the third capacitor of the present embodiment is basically the same as that of the embodiment shown in FIG. 24, except that the third capacitor can include a third sub-capacitor and a fourth sub-capacitor.

[0417] In the exemplary embodiment, the fifth plate 15 has at least partial overlap with the fourth plate 14 in the orthographic projection on the substrate, and the fourth plate 14 having the first node potential and the fifth plate 15 having the third node potential form the third sub-capacitor. The second plate 12 has at least partial overlap with the fourth plate 14 in the orthographic projection on the substrate, and the fourth plate 14 having the first node potential and the second plate 12 having the third node potential form the fourth sub-capacitor. In this way, the third sub-capacitor and the fourth sub-capacitor in parallel structure constitute the third capacitor C3 of the pixel driving circuit.

[0418] In some possible embodiments, the second plate 12 and the fifth plate 15 can be provided with the first node potential, and the fourth plate 14 can be provided with the third node potential, or the second plate 12 can be provided with the first node potential, and the fourth plate 14 and the fifth plate 15 can be provided with the third node potential, so as to realize that the first capacitor C1 and the third capacitor C3 share the same capacitor plate, which is not limited in the present disclosure.

[0419] The embodiments shown in FIGS. 22-25 not only have the technical effects of the foregoing embodiments, but also can further increase the capacitance of the first capacitor, the second capacitor and the third capacitor, so as to make the arrangement of the pixel driving circuit more compact and help to improve the resolution of the display device under the premise of meeting the design requirements.

[0420] The foregoing structure and preparation process of the present disclosure are merely exemplary, and in the exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or reduced according to actual needs, which are not limited herein.

[0421] In the exemplary embodiments, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as an OLED, a quantum dot display (QLED), a light-emitting diode display (Micro LED or Mini LED), or a quantum dot light-emitting diode display (QDLED), which are not limited herein.

[0422] The present disclosure also provides another display substrate. In the exemplary embodiments, the display substrate includes a plurality of circuit units, at least one of which includes a pixel driving circuit, the pixel driving circuit including at least a first capacitor, a second capacitor, a third capacitor, a first transistor as a first reset transistor, a second transistor as a second reset transistor, and a third transistor as a driving transistor, a first end of the second capacitor and a first end of the third capacitor being connected to a second electrode of the first transistor and a gate electrode of the third transistor, a second end of the first capacitor and a second end of the second capacitor being connected to a second electrode of the second transistor, a first end of the first capacitor and a second end of the third capacitor being connected to a second electrode of the third transistor, and a first electrode of the first transistor and a first electrode of the second transistor being connected to a first initial signal line.

[0423] The present disclosure also provides a display device including the foregoing display substrate. The display device can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like, which are not limited herein.

[0424] Although the embodiments of the present disclosure are disclosed as above, it should be noted that the above embodiments are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, and omissions can be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

1. A display substrate comprising a plurality of circuit units, at least one of the circuit units comprising a pixel driving circuit, the pixel driving circuit comprising at least a first capacitor, a second capacitor, a third capacitor, a first connection electrode having a first node potential, a second connection electrode having a second node potential, and a third connection electrode having a third node potential, a first terminal of the second capacitor and a first terminal of the third capacitor each being connected to the first connection electrode, a second terminal of the first capacitor and a second terminal of the second capacitor each being connected to the second connection electrode, a first terminal of the first capacitor and a second terminal of the third capacitor each being connected to the third connection electrode, the first capacitor, the second capacitor, and the third capacitor each comprising at least two capacitor plates stacked together; in a direction perpendicular to the display substrate, the display substrate comprising at least a first conductive layer disposed on a base, a second conductive layer disposed on a side of the first conductive layer distal to the base, and a semiconductor layer disposed on a side of the second conductive layer distal to the base; in at least one of the circuit units, one of the capacitor plates of the third capacitor is disposed in the semiconductor layer. 2.The display substrate of claim 1, wherein, The display substrate further comprises a third conductive layer disposed on a side of the semiconductor layer distal to the base, and a fourth conductive layer disposed on a side of the third conductive layer distal to the base, another of the capacitor plates of the third capacitor is disposed in at least one of the conductive layers and is shared with one of the capacitor plates in the first capacitor, or is shared with one of the capacitor plates in the second capacitor. 3.The display substrate of claim 1, wherein, The first capacitor comprises at least a first plate as a second terminal of the first capacitor and a second plate as a first terminal of the first capacitor, the second capacitor comprises at least a third plate as a second terminal of the second capacitor and a fourth plate as a first terminal of the second capacitor, the first plate and the third plate are disposed in the first conductive layer, the second plate and the fourth plate are disposed in the second conductive layer, a projection of the second plate on the base at least partially overlaps a projection of the first plate on the base, a projection of the fourth plate on the base at least partially overlaps a projection of the third plate on the base. In at least one of the circuit units, the first plate is connected to the third plate, the third plate is connected to the second connection electrode, the second plate is connected to the third connection electrode, and the fourth plate is connected to the first connection electrode. 4.The display substrate of claim 3, wherein, The pixel driving circuit further comprises a first transistor as a first reset transistor, a second transistor as a second reset transistor, and a third transistor as a driving transistor, a first electrode of the first transistor and a first electrode of the second transistor each being connected to a first initial signal line; in at least one of the circuit units, a first terminal of the first connection electrode is connected to a second electrode of the first transistor, a second terminal of the first connection electrode is connected to a gate electrode of the third transistor, and the gate electrode of the third transistor is connected to the fourth plate through a plate connection strip and a sixth connection electrode. 5.The display substrate of claim 4, wherein, In at least one circuit unit, a first end of the sixth connection electrode is connected to the fourth plate, and a second end of the sixth connection electrode is connected to the plate connection strip, and the plate connection strip is connected to the gate electrode of the third transistor. 6.The display substrate of claim 5, wherein, The display substrate further comprises a third conductive layer disposed on a side of the semiconductor layer away from the base; in at least one circuit unit, the gate electrode of the third transistor and the plate connection strip are disposed in the third conductive layer and are an integrated structure connected to each other. 7.The display substrate of claim 6, wherein, In at least one circuit unit, a first end of the second connection electrode is connected to the second electrode of the second transistor, and a second end of the second connection electrode is connected to the third plate, and the first plate and the third plate are an integrated structure connected to each other. 8.The display substrate of claim 4, wherein, In at least one circuit unit, a first end of the third connection electrode is connected to the second electrode of the third transistor, and a second end of the third connection electrode is connected to the second plate. 9.The display substrate of claim 4, wherein, The third capacitor comprises the fourth plate as a first end of the third capacitor and a fifth plate as a second end of the third capacitor; In at least one circuit unit, the fifth plate is disposed in the semiconductor layer, and a projection of the fifth plate on the base at least partially overlaps a projection of the fourth plate on the base, and the fifth plate is connected to the third connection electrode. 10.The display substrate of claim 9, wherein, The pixel driving circuit further comprises a fifth transistor as a first light-emitting control transistor and a sixth transistor as a second light-emitting control transistor, a first electrode of the third transistor is connected to a second electrode of the fifth transistor, and a second electrode of the third transistor is connected to a first electrode of the sixth transistor; in at least one circuit unit, a first end of the third connection electrode is connected to the second electrode of the third transistor and the first electrode of the sixth transistor, a second end of the third connection electrode is connected to the second plate, and the fifth plate is connected to the first electrode of the sixth transistor. 11.The display substrate of claim 10, wherein, The sixth transistor at least comprises a sixth active layer, and the fifth plate and the sixth active layer are an integrated structure connected to each other. 12.The display substrate of claim 4, wherein, The display substrate further comprises a third conductive layer disposed on a side of the semiconductor layer away from the base; the third capacitor comprises a first sub-capacitor and a second sub-capacitor in a parallel structure, the first sub-capacitor comprises the fourth plate as a first end of the first sub-capacitor and a fifth plate as a second end of the first sub-capacitor, and the second sub-capacitor comprises a sixth plate as a first end of the second sub-capacitor and the fifth plate as a second end of the second sub-capacitor; the fifth plate is disposed in the semiconductor layer, and a projection of the fifth plate on the base at least partially overlaps a projection of the fourth plate on the base, and the fifth plate is connected to the third connection electrode; in at least one circuit unit, the sixth plate is disposed in the third conductive layer, a projection of the sixth plate on the base at least partially overlaps a projection of the fifth plate on the base, and the sixth plate is connected to the fourth plate through a plate connection strip and a sixth connection electrode. 13.The display substrate of claim 12, wherein, In at least one circuit unit, a first end of the sixth connection electrode is connected to the fourth plate, and a second end of the sixth connection electrode is connected to the plate connecting strip, and the sixth plate and the plate connecting strip are an integrated structure connected to each other. 14.The display substrate of claim 12, wherein, In at least one circuit unit, the orthogonal projection of the sixth plate on the substrate is located within the range of the orthogonal projection of the fifth plate on the substrate. 15.The display substrate of claim 1, wherein, The display substrate further comprises a third conductive layer arranged on the side of the semiconductor layer away from the substrate; the first capacitor at least comprises a second plate as a first end of the first capacitor and a seventh plate as a second end of the first capacitor, the second capacitor at least comprises a fourth plate as a first end of the second capacitor and the seventh plate as a second end of the second capacitor, and the third capacitor at least comprises the fourth plate as a first end of the third capacitor and a fifth plate as a second end of the third capacitor; the second plate is arranged in the first conductive layer, the seventh plate is arranged in the second conductive layer, the fifth plate is arranged in the semiconductor layer, and the fourth plate is arranged in the third conductive layer. The seventh plate having the second node potential and the second plate having the third node potential form the first capacitor, the seventh plate having the second node potential and the fourth plate having the first node potential form the second capacitor, and the fourth plate having the first node potential and the fifth plate having the third node potential form the third capacitor. 16.The display substrate of claim 1, wherein, The display substrate further comprises a third conductive layer arranged on the side of the semiconductor layer away from the substrate; the first capacitor at least comprises a second plate as a first end of the first capacitor and a seventh plate as a second end of the first capacitor, the second capacitor at least comprises a fourth plate as a first end of the second capacitor and the seventh plate as a second end of the second capacitor, and the third capacitor comprises a third sub-capacitor and a fourth sub-capacitor, the third sub-capacitor at least comprises the fourth plate as a first end of the third sub-capacitor and a fifth plate as a second end of the third sub-capacitor, and the fourth sub-capacitor at least comprises the fourth plate as a first end of the fourth sub-capacitor and the second plate as a second end of the third sub-capacitor; the second plate is arranged in the first conductive layer, the seventh plate is arranged in the second conductive layer, the fifth plate is arranged in the semiconductor layer, and the fourth plate is arranged in the third conductive layer; The seventh plate with the second node potential and the second plate with the third node potential form the first capacitor, the seventh plate with the second node potential and the fourth plate with the first node potential form the second capacitor, the fourth plate with the first node potential and the fifth plate with the third node potential form the third sub-capacitor, the fourth plate with the first node potential and the second plate with the third node potential form the fourth sub-capacitor, and the third sub-capacitor and the fourth sub-capacitor in parallel structure constitute the third capacitor. 17.The display substrate of claim 1, wherein, The display substrate further comprises a third conductive layer disposed on the side of the semiconductor layer away from the base and a fourth conductive layer disposed on the side of the third conductive layer away from the base; the first capacitor comprises at least a second plate as a first end of the first capacitor and a seventh plate as a second end of the first capacitor, the second capacitor comprises at least a fifth sub-capacitor and a sixth sub-capacitor, the fifth sub-capacitor comprises a fourth plate as a first end of the fifth sub-capacitor and a seventh plate as a second end of the fifth sub-capacitor, the sixth sub-capacitor comprises a fourth plate as a first end of the sixth sub-capacitor and an eighth plate as a second end of the sixth sub-capacitor, and the third capacitor comprises at least a fourth plate as a first end of the third capacitor and a fifth plate as a second end of the third capacitor; the second plate is disposed in the first conductive layer, the seventh plate is disposed in the second conductive layer, the fifth plate is disposed in the semiconductor layer, the fourth plate is disposed in the third conductive layer, the eighth plate is disposed in the fourth conductive layer, and the eighth plate is connected to the seventh plate; The seventh plate with the second node potential and the second plate with the third node potential form the first capacitor, the seventh plate with the second node potential and the fourth plate with the first node potential form the fifth sub-capacitor, the eighth plate with the second node potential and the fourth plate with the first node potential form the sixth sub-capacitor, the fifth sub-capacitor and the sixth sub-capacitor in parallel structure constitute the second capacitor, and the fourth plate with the first node potential and the fifth plate with the third node potential form the third capacitor. 18.The display substrate of claim 1, wherein, The display substrate further comprises a third conductive layer arranged on a side of the semiconductor layer away from the substrate, and a fourth conductive layer arranged on a side of the third conductive layer away from the substrate; the first capacitor at least comprises a second plate as a first end of the first capacitor and a seventh plate as a second end of the first capacitor, the second capacitor at least comprises a fifth sub-capacitor and a sixth sub-capacitor, the fifth sub-capacitor comprises a fourth plate as a first end of the fifth sub-capacitor and the seventh plate as a second end of the fifth sub-capacitor, the sixth sub-capacitor comprises the fourth plate as a first end of the sixth sub-capacitor and an eighth plate as a second end of the sixth sub-capacitor, the third capacitor comprises a third sub-capacitor and a fourth sub-capacitor, the third sub-capacitor at least comprises the fourth plate as a first end of the third sub-capacitor and a fifth plate as a second end of the third sub-capacitor, and the fourth sub-capacitor at least comprises the fourth plate as a first end of the fourth sub-capacitor and the second plate as a second end of the third sub-capacitor; the second plate is arranged in the first conductive layer, the seventh plate is arranged in the second conductive layer, the fifth plate is arranged in the semiconductor layer, the fourth plate is arranged in the third conductive layer, the eighth plate is arranged in the fourth conductive layer, and is connected with the seventh plate; The seventh plate with the second node potential and the second plate with the third node potential form the first capacitor, the seventh plate with the second node potential and the fourth plate with the first node potential form the fifth sub-capacitor, the eighth plate with the second node potential and the fourth plate with the first node potential form the sixth sub-capacitor, the fifth sub-capacitor and the sixth sub-capacitor in parallel structure constitute the second capacitor, the fourth plate with the first node potential and the fifth plate with the third node potential form the third sub-capacitor, and the fourth plate with the first node potential and the second plate with the third node potential form the fourth sub-capacitor, and the third sub-capacitor and the fourth sub-capacitor in parallel structure constitute the third capacitor.

19. A display substrate comprising a plurality of circuit units, at least one of which comprises a pixel driving circuit, the pixel driving circuit comprising at least a first capacitor, a second capacitor, a third capacitor, a first transistor as a first reset transistor, a second transistor as a second reset transistor, and a third transistor as a driving transistor, a first end of the second capacitor and a first end of the third capacitor are connected to a second electrode of the first transistor and a gate electrode of the third transistor, a second end of the first capacitor and a second end of the second capacitor are connected to a second electrode of the second transistor, a first end of the first capacitor and a second end of the third capacitor are connected to a second electrode of the third transistor, and a first electrode of the first transistor and a first electrode of the second transistor are connected to a first initial signal line.

20. A display device comprising the display substrate according to any one of claims 1 to 18.

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