Display substrate, preparation method thereof and display device

Abstract

A display substrate, a manufacturing method thereof, and a display device. The display substrate includes a plurality of circuit units, at least one of which includes a pixel driving circuit. The pixel driving circuit includes at least a first capacitor (10), a second capacitor (20), a third capacitor (30), a first connection electrode (51), a second connection electrode (52), and a third connection electrode (53). The first capacitor (10) includes a first plate (11) and a second plate (12). The second capacitor (20) includes a third plate (13) and a fourth plate (14). The third capacitor (30) includes the fourth plate (14) and a fifth plate (15). The first plate (11) and the third plate (13) are connected to the second connection electrode (52). The second plate (12) and the fifth plate (15) are connected to the third connection electrode (53). The fourth plate (14) is connected to the first connection electrode (51).

Description

Display substrate, preparation method thereof and display device TECHNICAL FIELD

[0001] The present document relates to, but is not limited to, the technical field of display, in particular to a display substrate, a preparation method thereof and a display device. BACKGROUND

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, lightness, flexibility, low cost, etc. With the continuous development of display technology, flexible display devices with OLED or QLED as light-emitting devices and controlled by Thin Film Transistor (TFT) have become the mainstream products in the current display field.

[0003] SUMMARY

[0004] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0005] In one aspect, the present disclosure provides a display substrate, comprising a plurality of circuit units, at least one circuit unit comprising a pixel driving circuit, the pixel driving circuit comprising at least a first capacitor, a second capacitor, a third capacitor, a first connection electrode having a first node potential, a second connection electrode having a second node potential, and a third connection electrode having a third node potential; the first capacitor comprising at least a first plate and a second plate, a normal projection of the second plate on a display substrate plane at least partially overlaps a normal projection of the first plate on the display substrate plane, the second capacitor comprising at least a third plate and a fourth plate, a normal projection of the fourth plate on the display substrate plane at least partially overlaps a normal projection of the third plate on the display substrate plane, the third capacitor comprising a fourth plate and a fifth plate, a normal projection of the fifth plate on the display substrate plane at least partially overlaps a normal projection of the fourth plate on the display substrate plane; in at least one circuit unit, the first plate and the third plate are connected to the second connection electrode, the second plate and the fifth plate are connected to the third connection electrode, and the fourth plate is connected to the first connection electrode.

[0006] In an exemplary embodiment, the pixel driving circuit further comprises a first transistor as a first reset transistor, a third transistor as a driving transistor, and a fourth transistor as a data writing transistor, a first electrode of the first transistor is connected with a first initial signal line, and a first electrode of the fourth transistor is connected with a data signal line; in at least one circuit unit, a first end of the first connecting electrode is connected with a second electrode of the first transistor and a second electrode of the fourth transistor, and a second end of the first connecting electrode is connected with a gate electrode of the third transistor, and the gate electrode of the third transistor is connected with the fourth electrode plate through an electrode plate connecting strip.

[0007] In an exemplary embodiment, in at least one circuit unit, the gate electrode of the third transistor is connected with the fourth electrode plate through an electrode plate connecting strip and a sixth connecting electrode.

[0008] In an exemplary embodiment, the first transistor comprises at least a first active layer, the fourth transistor comprises at least a fourth active layer, the first active layer and the fourth active layer are an integrated structure connected with each other, a first end of the first connecting electrode is connected with a second region of the first active layer and a second region of the fourth active layer through a via, and the data signal line is arranged on a side of the first connecting electrode away from the gate electrode of the third transistor; in at least one circuit unit, a first distance is provided between the first connecting electrode and the data signal line, a second distance is provided between the first active layer or the fourth active layer and the data signal line, the first distance is greater than the second distance, the first distance is a minimum distance between an edge of the first connecting electrode close to the data signal line and an edge of the data signal line close to the first connecting electrode, and the second distance is a minimum distance between an edge of the first active layer or the fourth active layer close to the data signal line and an edge of the data signal line close to the first active layer or the fourth active layer.

[0009] In an exemplary embodiment, in at least one circuit unit, a projection of the first initial signal line on a display substrate plane does not overlap with a projection of the first connecting electrode on the display substrate plane, and / or a projection of the first initial signal line on the display substrate plane does not overlap with a projection of the gate electrode of the third transistor on the display substrate plane, and / or a projection of the first initial signal line on the display substrate plane does not overlap with a projection of the electrode plate connecting strip on the display substrate plane.

[0010] In an exemplary embodiment, in at least one circuit unit, a projection of the first initial signal line on a display substrate plane at least partially overlaps with a projection of the fourth plate and the fifth plate on the display substrate plane; in a direction perpendicular to the display substrate, the fifth plate is arranged between the fourth plate and the first initial signal line.

[0011] In an exemplary embodiment, the first transistor at least includes a first gate electrode connected with a first scan signal line; in at least one circuit unit, a projection of the first scan signal line on a display substrate plane does not overlap with a projection of the first connecting electrode on the display substrate plane, and / or a projection of the first scan signal line on the display substrate plane does not overlap with a projection of a gate electrode of the third transistor on the display substrate plane, and / or a projection of the first scan signal line on the display substrate plane does not overlap with a projection of the fourth plate on the display substrate plane.

[0012] In an exemplary embodiment, the fourth transistor at least includes a fourth gate electrode connected with a fourth scan signal line; in at least one circuit unit, a projection of the fourth scan signal line on a display substrate plane does not overlap with a projection of the first connecting electrode on the display substrate plane, and / or a projection of the fourth scan signal line on the display substrate plane does not overlap with a projection of a gate electrode of the third transistor on the display substrate plane, and / or a projection of the fourth scan signal line on the display substrate plane does not overlap with a projection of the plate connecting strip on the display substrate plane, and / or a projection of the fourth scan signal line on the display substrate plane does not overlap with a projection of the fourth plate on the display substrate plane.

[0013] In an exemplary embodiment, the pixel driving circuit further includes a second transistor as a second reset transistor, a first electrode of the second transistor being connected with the reset signal line; in at least one circuit unit, a first end of the second connecting electrode is connected with a second electrode of the second transistor, and a second end of the second connecting electrode is connected with the third plate, the first plate and the third plate being an integrated structure connected with each other.

[0014] In an exemplary embodiment, the second transistor comprises at least a second gate electrode connected with a second scan signal line; in at least one circuit unit, a projection of the second scan signal line on a display substrate plane does not overlap with a projection of the second connection electrode on the display substrate plane, and / or a projection of the second scan signal line on the display substrate plane does not overlap with a projection of the first plate on the display substrate plane, and / or a projection of the second scan signal line on the display substrate plane does not overlap with a projection of the third plate on the display substrate plane.

[0015] In an exemplary embodiment, the second transistor comprises at least a second gate electrode connected with a second scan signal line; in at least one circuit unit, a projection of the second scan signal line on a display substrate plane does not overlap with a projection of the first connection electrode on the display substrate plane, and / or a projection of the second scan signal line on the display substrate plane does not overlap with a projection of a gate electrode of the third transistor on the display substrate plane, and / or a projection of the second scan signal line on the display substrate plane does not overlap with a projection of the plate connection strip on the display substrate plane, and / or a projection of the second scan signal line on the display substrate plane does not overlap with a projection of the fourth plate on the display substrate plane.

[0016] In an exemplary embodiment, in at least one circuit unit, a projection of the reset signal line on a display substrate plane does not overlap with a projection of the second connection electrode on the display substrate plane.

[0017] In an exemplary embodiment, the pixel driving circuit further comprises a fifth transistor as a first light-emitting control transistor and a sixth transistor as a second light-emitting control transistor, a first electrode of the fifth transistor is connected with a first power supply line, a second electrode of the fifth transistor is connected with a first electrode of the third transistor, a second electrode of the third transistor is connected with a first electrode of the sixth transistor; in at least one circuit unit, a first end of the third connection electrode is connected with the second electrode of the third transistor and the first electrode of the sixth transistor, a second end of the third connection electrode is connected with the second plate, and the fifth plate is connected with the first electrode of the sixth transistor.

[0018] In an exemplary embodiment, the sixth transistor comprises at least a sixth active layer, and in at least one circuit unit, the fifth plate and the sixth active layer are an integrated structure connected with each other.

[0019] In an exemplary embodiment, the at least one circuit unit further comprises a second power supply line, a projection of the second power supply line on a display substrate plane does not overlap with a projection of the first connection electrode on the display substrate plane, and / or a projection of the second power supply line on the display substrate plane does not overlap with a projection of the second connection electrode on the display substrate plane.

[0020] In an exemplary embodiment, the pixel driving circuit further comprises a first transistor as a first reset transistor, a third transistor as a driving transistor, and a fourth transistor as a data writing transistor, a first electrode of the first transistor is connected with a first initial signal line, and a first electrode of the fourth transistor is connected with a data signal line; a first end of the first connection electrode is connected with a second electrode of the first transistor and a second electrode of the fourth transistor, a second end of the first connection electrode is connected with a gate electrode of the third transistor, and the gate electrode of the third transistor is connected with the fourth plate connection through a plate connection strip; in the at least one circuit unit, a projection of the second power supply line on a display substrate plane does not overlap with a projection of the gate electrode of the third transistor on the display substrate plane, and / or a projection of the second power supply line on the display substrate plane does not overlap with a projection of the plate connection strip on the display substrate plane.

[0021] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate comprises at least a first conductive layer disposed on a base, a second conductive layer disposed on a side of the first conductive layer away from the base, a semiconductor layer disposed on a side of the second conductive layer away from the base, and a third conductive layer disposed on a side of the semiconductor layer away from the base, the first plate and the third plate are disposed in the first conductive layer, the second plate and the fourth plate are disposed in the second conductive layer, and the fifth plate is disposed in the semiconductor layer.

[0022] In an exemplary embodiment, in the at least one circuit unit, a ratio of an area of a projection of the second plate on the first plate to an area of a projection of the fourth plate on the third plate is 0.95 to 1.05.

[0023] In another aspect, the present disclosure further provides a display device comprising the aforementioned display substrate.

[0024] In yet another aspect, the present disclosure further provides a preparation method of a display substrate comprising a plurality of circuit units, the preparation method comprising:

[0025] The pixel driving circuit is formed in at least one circuit unit, and the pixel driving circuit at least includes a first capacitor, a second capacitor, a third capacitor, a first connection electrode with a first node potential, a second connection electrode with a second node potential, and a third connection electrode with a third node potential; the first capacitor at least includes a first plate and a second plate, a normal projection of the second plate on a display substrate plane at least partially overlaps a normal projection of the first plate on the display substrate plane, the second capacitor at least includes a third plate and a fourth plate, a normal projection of the fourth plate on the display substrate plane at least partially overlaps a normal projection of the third plate on the display substrate plane, and the third capacitor includes a fourth plate and a fifth plate, a normal projection of the fifth plate on the display substrate plane at least partially overlaps a normal projection of the fourth plate on the display substrate plane; the first plate and the third plate are connected with the second connection electrode, the second plate and the fifth plate are connected with the third connection electrode, and the fourth plate is connected with the first connection electrode.

[0026] Other aspects can become apparent after reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0027] The accompanying drawings are included to provide a further understanding of the present disclosure and constitute a part of the specification, which together with the detailed description, serve to explain the technical solutions of the present disclosure, but do not constitute a limitation on the technical solutions of the present disclosure.

[0028] FIG. 1 is a structural schematic diagram of a display device;

[0029] FIG. 2 is a plan structural schematic diagram of a display substrate;

[0030] FIG. 3 is a cross-sectional structural schematic diagram of a display substrate;

[0031] FIG. 4 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0032] FIG. 5 is a driving timing diagram of the pixel driving circuit shown in FIG. 4;

[0033] FIG. 6 is a structural schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0034] FIG. 7 is a schematic diagram of a capacitor structure according to an exemplary embodiment of the present disclosure;

[0035] FIG. 8 is a cross-sectional view along A-A direction in FIG. 6;

[0036] FIG. 9 is a schematic diagram of a display substrate after forming a first conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0037] FIGS. 10A and 10B are schematic diagrams of a display substrate after forming a second conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0038] FIGS. 11A and 11B are schematic diagrams of a display substrate after forming a semiconductor layer pattern according to the present disclosure;

[0039] FIGS. 12A and 12B are schematic diagrams of a display substrate after forming a third conductive layer pattern according to the present disclosure;

[0040] FIG. 13 is a schematic diagram of a display substrate after forming a fourth insulating layer pattern according to the present disclosure;

[0041] FIGS. 14A and 14B are schematic diagrams of a display substrate after forming a fourth conductive layer pattern according to the present disclosure;

[0042] FIG. 15 is a schematic diagram of a display substrate after forming a fifth insulating layer and a first planarization layer pattern according to the present disclosure;

[0043] FIGS. 16A and 16B are schematic diagrams of a display substrate after forming a fifth conductive layer pattern according to the present disclosure;

[0044] FIG. 16C is a schematic diagram of the positional relationship between the first connection electrode and the data signal line in FIG. 16A;

[0045] FIG. 17 is a schematic diagram of a meshed connection structure according to an exemplary embodiment of the present disclosure;

[0046] FIG. 18 is a schematic diagram of another display substrate structure according to an exemplary embodiment of the present disclosure;

[0047] FIG. 19 is a schematic diagram of still another display substrate structure according to an exemplary embodiment of the present disclosure;

[0048] FIG. 20 is a schematic diagram of still another display substrate structure according to an exemplary embodiment of the present disclosure.

[0049] Explanation of Reference Numerals:

[0050] 10 - first capacitor; 11 - first plate; 12 - second plate;

[0051] 13 - third plate; 14 - fourth plate; 15 - fifth plate;

[0052] 20 - second capacitor; 21 - first active layer; 22 - second active layer;

[0053] 23 - third active layer; 24 - fourth active layer; 25 - fifth active layer;

[0054] 26 - sixth active layer; 27 - seventh active layer; 28 - active connection strip;

[0055] 29 - arc portion; 30 - third capacitor; 31 - first gate electrode;

[0056] 32 - second gate electrode; 33 - third gate electrode; 34 - fourth gate electrode;

[0057] 37 - seventh gate electrode; 38 - plate connection strip; 41 - first light emitting signal line;

[0058] 42 - second light emitting signal line; 51 - first connection electrode; 52 - second connection electrode;

[0059] 53 - third connection electrode; 54 - fourth connection electrode; 55 - fifth connection electrode;

[0060] 56 - sixth connection electrode; 61 - first scan signal line; 62 - second scan signal line;

[0061] 63 - third scan signal line; 64 - fourth scan signal line; 65 - first power supply connection line;

[0062] 66 - second power supply connection line; 71 - first initial signal line; 72 - second initial signal line;

[0063] 73 - first initial connection line; 74 - second initial connection line; 81 - first power supply line;

[0064] 82 - second power supply line; 83 - data signal line; 84 - anode connection electrode;

[0065] 91 - first insulating layer; 92 - second insulating layer; 93 - third insulating layer;

[0066] 94 - fourth insulating layer; 101 - substrate; 102 - driving structure layer;

[0067] 103 - light emitting structure layer; 104 - encapsulation structure layer. DETAILED DESCRIPTION

[0068] For the purpose of making the objects, technical solutions and advantages of the present disclosure clearer, below, the embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the embodiments can be implemented in multiple different forms. It can be easily understood by those skilled in the art that the means and content can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the content described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other as long as there is no conflict.

[0069] The scale of the drawings in the present disclosure can be used as a reference in the actual process, but is not limited thereto. For example, the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in the present disclosure are only schematic structural diagrams, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0070] In the present specification, ordinal numbers such as "first", "second", "third", and the like are provided in order to avoid confusion of components, and are not intended to be limited in terms of quantity.

[0071] In the present specification, for the purpose of convenience, words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the components with reference to the drawings, and are only for the purpose of facilitating the description of the present specification and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction of describing each component. Therefore, it is not limited to the words described in the specification, and can be appropriately replaced according to the situation.

[0072] In the present specification, unless explicitly specified and limited, the terms "mount", "connected", "connected" should be understood broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate piece, or the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0073] In this specification, a transistor means an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and the source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that, in this specification, the channel region means a region where current flows mainly.

[0074] In this specification, the first terminal can be a drain electrode and the second terminal can be a source electrode, or the first terminal can be a source electrode and the second terminal can be a drain electrode. The functions of the "source electrode" and the "drain electrode" are sometimes interchanged with each other in the case of using a transistor whose polarity is reversed or in the case where the direction of current flowing in a circuit is changed, and the like. Therefore, in this specification, the "source electrode" and the "drain electrode" can be interchanged with each other, and the "source terminal" and the "drain terminal" can be interchanged with each other.

[0075] In this specification, "electrically connected" includes the case where components are connected through an element having some function of electricity. The element having some function of electricity is not particularly limited as long as electric signals can be transmitted and received between components to be connected. Examples of the element having some function of electricity include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, and another element having some function.

[0076] In this specification, "parallel" means a state where the angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus includes a state where the angle is greater than or equal to -5° and less than or equal to 5°. In addition, "perpendicular" means a state where the angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus includes a state where the angle is greater than or equal to 85° and less than or equal to 95°.

[0077] In this specification, a "film" and a "layer" can be interchanged with each other. For example, a "conductive layer" can be replaced with a "conductive film". Similarly, an "insulating film" can be replaced with an "insulating layer".

[0078] In this specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not necessarily a strict one, and can be an approximate triangle, rectangle, trapezoid, pentagon, or hexagon. There can be some small deformation due to a tolerance, a rounded corner, a rounded side, or the like. In this specification, "about" means that a value includes a range of error due to a process and measurement.

[0079] FIG. 1 is a structural schematic diagram of a display device. As shown in FIG. 1, the display device can include a timing controller, a data driver, a scan driver, a light emitting driver, and a pixel array, the timing controller is connected with the data driver, the scan driver, and the light emitting driver respectively, the data driver is connected with a plurality of data signal lines (D1 to Dn) respectively, the scan driver is connected with a plurality of scan signal lines (S1 to Sm) respectively, and the light emitting driver is connected with a plurality of first light emitting signal lines (E1 to Eo) respectively. The pixel array can include a plurality of sub-pixels Pxij, i and j can be natural numbers, at least one sub-pixel Pxij can include a circuit unit and a light emitting unit, the circuit unit can include at least a pixel driving circuit, the pixel driving circuit is connected with the scan signal line, the first light emitting signal line, and the data signal line respectively, and the light emitting unit can include a light emitting device connected with the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller can provide a gray value and a control signal suitable for the specification of the data driver to the data driver, can provide a clock signal, a scan start signal, and the like suitable for the specification of the scan driver to the scan driver, and can provide a clock signal, an emission stop signal, and the like suitable for the specification of the light emitting driver to the light emitting driver. The data driver can generate data voltages to be provided to the data signal lines D1, D2, D3, …, and Dn by using the gray value and the control signal received from the timing controller. For example, the data driver can sample the gray value by using the clock signal, and apply data voltages corresponding to the gray value to the data signal lines D1 to Dn in units of a pixel row. n can be a natural number. The scan driver can generate scan signals to be provided to the scan signal lines S1, S2, S3, …, and Sm by receiving the clock signal, the scan start signal, and the like from the timing controller. For example, the scan driver can sequentially provide the scan signal having an on-level pulse to the scan signal lines S1 to Sm. For example, the scan driver can be configured in the form of a shift register, and can generate the scan signal in a manner that sequentially transfers the scan start signal provided in the form of an on-level pulse to a next stage circuit under the control of the clock signal. m can be a natural number. The light emitting driver can generate emission signals to be provided to the first light emitting signal lines E1, E2, E3, …, and Eo by receiving the clock signal, the emission stop signal, and the like from the timing controller. For example, the light emitting driver can sequentially provide the emission signal having an off-level pulse to the first light emitting signal lines E1 to Eo. For example, the light emitting driver can be configured in the form of a shift register, and can generate the emission signal in a manner that sequentially transfers the emission stop signal provided in the form of an off-level pulse to a next stage circuit under the control of the clock signal. o can be a natural number. In an exemplary embodiment, the pixel array can be disposed on a display substrate.

[0080] FIG. 2 is a schematic diagram of a planar structure of a display substrate. As shown in FIG. 2, the display substrate can include a plurality of pixel units P arranged in a matrix manner, and at least one pixel unit P can include a first sub-pixel P1, a second sub-pixel P2 and a third sub-pixel P3. Each sub-pixel can include a circuit unit and a light-emitting unit, and the circuit unit can include at least a pixel driving circuit. The pixel driving circuit is connected with a scan signal line, a light-emitting signal line and a data signal line respectively, and is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit can include a light-emitting device connected with the pixel driving circuit of the sub-pixel where the light-emitting device is located, and the light-emitting device is configured to emit light with a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel where the light-emitting device is located.

[0081] In an example embodiment, the first sub-pixel P1 can be a red sub-pixel (R) emitting red light, the second sub-pixel P2 can be a green sub-pixel (G) emitting green light, and the third sub-pixel P3 can be a blue sub-pixel (B) emitting blue light. In an example embodiment, the shape of the sub-pixel can be rectangular, diamond, pentagonal or hexagonal, and the three sub-pixels can be arranged in a horizontal parallel, vertical parallel or triangular manner.

[0082] In other example embodiments, the pixel unit can include four sub-pixels, and the four sub-pixels can be arranged in a horizontal parallel, vertical parallel or square manner, which is not limited in the present disclosure.

[0083] FIG. 3 is a schematic diagram of a cross-sectional structure of a display substrate, illustrating the structure of three sub-pixels in the display substrate. As shown in FIG. 3, in a plane perpendicular to the display substrate, the display area can include a driving structure layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on a side of the driving structure layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementation manners, the display area can include other film layers, such as a touch structure layer, which is not limited in the present disclosure.

[0084] In the example embodiment, the substrate 101 can be a flexible substrate or can be a rigid substrate. The driving structure layer 102 can include a plurality of circuit units, each of which can include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 can include a plurality of light-emitting units, each of which can include a light-emitting device, which can include at least an anode, an organic light-emitting layer, and a cathode, the anode being connected to the pixel driving circuit, the organic light-emitting layer being connected to the anode, and the cathode being connected to the organic light-emitting layer, the organic light-emitting layer emitting light of a corresponding color under the driving of the anode and the cathode. The encapsulating structure layer 104 can include a first encapsulating layer, a second encapsulating layer, and a third encapsulating layer stacked together, the first encapsulating layer and the third encapsulating layer can be made of inorganic material, and the second encapsulating layer can be made of organic material, the second encapsulating layer being arranged between the first encapsulating layer and the third encapsulating layer to form an inorganic material / organic material / inorganic material stacked structure, which can prevent external water vapor from entering the light-emitting structure layer 103.

[0085] An example embodiment of the present disclosure provides a display substrate. In the example embodiment, the display substrate can include a plurality of circuit units, at least one of which includes a pixel driving circuit, the pixel driving circuit including at least a first capacitor, a second capacitor, a third capacitor, a first connection electrode having a first node potential, a second connection electrode having a second node potential, and a third connection electrode having a third node potential; the first capacitor including at least a first plate and a second plate, a projection of the second plate on a display substrate plane at least partially overlapping a projection of the first plate on the display substrate plane, the second capacitor including at least a third plate and a fourth plate, a projection of the fourth plate on the display substrate plane at least partially overlapping a projection of the third plate on the display substrate plane, the third capacitor including the fourth plate and a fifth plate, a projection of the fifth plate on the display substrate plane at least partially overlapping a projection of the fourth plate on the display substrate plane; the first plate and the third plate being connected to the second connection electrode, the second plate and the fifth plate being connected to the third connection electrode, and the fourth plate being connected to the first connection electrode.

[0086] In an exemplary embodiment, the first transistor comprises at least a first active layer, the fourth transistor comprises at least a fourth active layer, the first active layer and the fourth active layer are an integrated structure connected to each other, and a first end of the first connecting electrode is connected to a second region of the first active layer and a second region of the fourth active layer through a via hole; the data signal line is arranged on a side of the first connecting electrode away from the gate electrode of the third transistor, the first connecting electrode and the data signal line have a first distance therebetween, the first active layer or the fourth active layer and the data signal line have a second distance therebetween, the first distance is greater than the second distance, the first distance is a minimum distance between an edge of the side of the first connecting electrode close to the data signal line and an edge of the side of the data signal line close to the first connecting electrode, and the second distance is a minimum distance between an edge of the side of the first active layer or the fourth active layer close to the data signal line and an edge of the side of the data signal line close to the first active layer or the fourth active layer.

[0087] In an exemplary embodiment, a projection of the first initial signal line on a display substrate plane does not overlap with a projection of the first connecting electrode on the display substrate plane, and / or a projection of the first initial signal line on the display substrate plane does not overlap with a projection of the gate electrode of the third transistor on the display substrate plane, and / or a projection of the first initial signal line on the display substrate plane does not overlap with a projection of the plate connecting strip on the display substrate plane, and / or a projection of the first initial signal line on the display substrate plane does not overlap with a projection of the sixth connecting electrode on the display substrate plane.

[0088] In an exemplary embodiment, a projection of the first initial signal line on a display substrate plane at least partially overlaps with projections of the fourth plate and the fifth plate on the display substrate plane; in a direction perpendicular to the display substrate, the fifth plate is arranged between the fourth plate and the first initial signal line.

[0089] In an exemplary embodiment, a projection of the first initial signal line on a display substrate plane does not overlap with a projection of the second connecting electrode on the display substrate plane.

[0090] In an exemplary embodiment, the at least one circuit unit further comprises a second power supply line, a projection of the second power supply line on a display substrate plane does not overlap with a projection of the first connecting electrode on the display substrate plane, and / or a projection of the second power supply line on the display substrate plane does not overlap with a projection of the second connecting electrode on the display substrate plane.

[0091] In an exemplary embodiment, in the at least one circuit unit, a ratio of an area of a second electrode plate orthogonally projected on the first electrode plate to an area of a fourth electrode plate orthogonally projected on the third electrode plate is 0.95 to 1.05.

[0092] The display substrate of the present embodiment is illustrated below by some examples.

[0093] An exemplary embodiment of the present disclosure provides a display substrate. In a direction perpendicular to the display substrate, the display substrate can at least include a driving structure layer disposed on a base and a light-emitting structure layer disposed on a side of the driving structure layer away from the base. In a plane parallel to the display substrate, the driving structure layer can include a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, the circuit units can at least include a pixel driving circuit, and the light-emitting structure layer can include a plurality of light-emitting units, the light-emitting units can at least include a light-emitting device, at least one pixel driving circuit is connected with at least one light-emitting unit, and the pixel driving circuit is configured to provide a driving signal to the connected light-emitting device to drive the corresponding light-emitting device to emit light.

[0094] In an exemplary embodiment, the circuit unit referred to in the present disclosure refers to an area divided according to the pixel driving circuit, and the light-emitting unit referred to in the present disclosure refers to an area divided according to the light-emitting device. In an exemplary embodiment, a position orthogonally projected on the base of the light-emitting unit can correspond to a position orthogonally projected on the base of the circuit unit, or the position orthogonally projected on the base of the light-emitting unit can not correspond to the position orthogonally projected on the base of the circuit unit.

[0095] FIG. 4 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure. As shown in FIG. 4, the pixel driving circuit according to an exemplary embodiment of the present disclosure adopts a 7T3C structure, each pixel driving circuit can include 7 transistors (a first transistor T1 to a seventh transistor T7) and 3 capacitors (a first capacitor C1, a second capacitor C2, and a third capacitor C3), and the pixel driving circuit is connected with 11 signal lines (a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a fourth scan signal line S4, a first emission signal line EM1, a second emission signal line EM2, a first initial signal line INIT1, a reset signal line RESET, a second initial signal line INIT2, a data signal line DATA, and a first power supply line VDD).

[0096] In the example embodiment, the pixel driving circuit can include a first node N1, a second node N2, a third node N3, a fourth node N4, and a fifth node N5. The first node N1 is connected with the second electrode of the first transistor T1, the gate electrode of the third transistor T3, the second electrode of the fourth transistor T4, the first end of the second capacitor C2, and the first end of the third capacitor C3 respectively, the second node N2 is connected with the second electrode of the second transistor T2, the second end of the first capacitor C1, and the second end of the second capacitor C2 respectively, the third node N3 is connected with the second electrode of the third transistor T3, the first electrode of the sixth transistor T6, the first end of the first capacitor C1, and the second end of the third capacitor C3 respectively, the fourth node N4 is connected with the first electrode of the third transistor T3 and the second electrode of the fifth transistor T5 respectively, and the fifth node N5 is connected with the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 respectively.

[0097] In the example embodiment, the first transistor T1 can be referred to as a first reset transistor, the gate electrode of the first transistor T1 is connected with the first scan signal line S1, the first electrode of the first transistor T1 is connected with the first initial signal line INIT1, and the second electrode of the first transistor T1 is connected with the first node N1.

[0098] In the example embodiment, the second transistor T2 can be referred to as a second reset transistor, the gate electrode of the second transistor T2 is connected with the second scan signal line S2, the first electrode of the second transistor T2 is connected with the reset signal line RESET, and the second electrode of the second transistor T2 is connected with the second node N2.

[0099] In the example embodiment, the third transistor T3 can be referred to as a driving transistor, the gate electrode of the third transistor T3 is connected with the first node N1, the first electrode of the third transistor T3 is connected with the fourth node N4, and the second electrode of the third transistor T3 is connected with the third node N3.

[0100] In the example embodiment, the fourth transistor T4 can be referred to as a data writing transistor, the gate electrode of the fourth transistor T4 is connected with the fourth scan signal line S4, the first electrode of the fourth transistor T4 is connected with the data signal line DATA, and the second electrode of the fourth transistor T4 is connected with the first node N1.

[0101] In the example embodiment, the fifth transistor T5 can be referred to as a first light emitting control transistor, the gate electrode of the fifth transistor T5 is connected with the first light emitting signal line EM1, the first electrode of the fifth transistor T5 is connected with the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected with the fourth node N4.

[0102] In an exemplary embodiment, the sixth transistor T6 can be referred to as a second light-emitting control transistor, the gate electrode of the sixth transistor T6 is connected with the second light-emitting signal line EM2, the first electrode of the sixth transistor T6 is connected with the third node N3, and the second electrode of the sixth transistor T6 is connected with the fifth node N5.

[0103] In an exemplary embodiment, the seventh transistor T7 can be referred to as a third reset transistor, the gate electrode of the seventh transistor T7 is connected with the third scan signal line S3, the first electrode of the seventh transistor T7 is connected with the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected with the fifth node N5.

[0104] In an exemplary embodiment, the first end of the first capacitor C1 is connected with the third node N3, and the second end of the first capacitor C1 is connected with the second node N2. The first end of the second capacitor C2 is connected with the first node N1, and the second end of the second capacitor C2 is connected with the second node N2. The first end of the third capacitor C3 is connected with the first node N1, and the second end of the third capacitor C3 is connected with the third node N3.

[0105] In an exemplary embodiment, the first electrode of the light-emitting device EL is connected with the fifth node N5, and the second electrode of the light-emitting device EL is connected with the second power supply line VSS. The light-emitting device EL can be an OLED including a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked, or can be a QLED including a first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode) stacked.

[0106] In an exemplary embodiment, the seven transistors of the pixel driving circuit can be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product.

[0107] In an exemplary embodiment, the seven transistors of the pixel driving circuit can all be oxide transistors. The active layer of the oxide transistor can be an oxide semiconductor (Oxide). The oxide transistor has advantages such as high electron mobility, low operating voltage, and low leakage characteristics. Using the display substrate provided with the oxide transistor can realize low-frequency driving, reduce power consumption, and improve display quality.

[0108] In an example embodiment, the first power line VDD can be configured to provide a constant first voltage signal to the pixel driving circuit, the second power line VSS can be configured to provide a constant second voltage signal to the light emitting device, and the voltage of the first voltage signal is greater than the voltage of the second voltage signal, i.e., the first voltage signal is a high-level signal and the second voltage signal is a low-level signal. The first initial signal line INIT1, the reset signal line RESET, and the second initial signal line INIT2 can be configured to provide a constant signal to the pixel driving circuit, which is not limited in the present disclosure.

[0109] In an example embodiment, the first initial signal line INIT1 and the reset signal line RESET can be the same signal line, and the pixel driving circuit is connected with 10 signal lines respectively.

[0110] FIG. 5 is a driving timing diagram of the pixel driving circuit shown in FIG. 4. As shown in FIG. 5, in an example embodiment, taking the reset signal line RESET as the first initial signal line INIT1 as an example, the working process of the pixel driving circuit can include:

[0111] The first stage A1 is called the reset stage. The signals of the first scan signal line S1, the second scan signal line S2, the third scan signal line S3, and the second emission signal line EM2 are high-level signals, and the signals of the fourth scan signal line S4 and the first emission signal line EM1 are low-level signals, so that the first transistor T1, the second transistor T2, the sixth transistor T6, and the seventh transistor T7 are turned on, and other switch transistors are turned off.

[0112] The conduction of the first transistor T1 and the second transistor T2 enables the first initial signal provided by the first initial signal line INIT1 to be provided to the first node N1 and the second node N2, so as to initialize the first node N1 and the second node N2, and the potentials of the first node N1 and the second node N2 are Vinit1. The conduction of the sixth transistor T6 and the seventh transistor T7 enables the second initial signal provided by the second initial signal line INIT2 to be provided to the third node N3 and the fifth node N5, so as to initialize the third node N3 and the fifth node N5, and the potentials of the third node N3 and the fifth node N5 are Vinit2. At the same time, the third transistor T3 can be turned on by the voltage difference (Vinit1-Vinit2) between the first node N1 and the third node N3, so that the third node N3 and the fourth node N4 are connected, and the fourth node N4 is initialized, and the potential of the fourth node N4 is Vinit2.

[0113] In exemplary embodiments, Vinit1 is the voltage of the first initial signal, and Vinit2 is the voltage of the second initial signal. For example, Vinit1 can be 1.5V to 3.5V, and Vinit2 can be 0.5V to 2.5V. For another example, Vinit1 can be about 2.5V, and Vinit2 can be about 1.5V.

[0114] In exemplary embodiments, the reset of the first node N1, the second node N2, the third node N3 and the fifth node N5 can be performed in stages. For example, at a first time, the first scan signal line S1 changes from a low level signal to a high level signal, the first transistor T1 is turned on, and the first node N1 is reset. At a second time, the third scan signal line S3 changes from a low level signal to a high level signal, the seventh transistor T7 is turned on, and the fifth node N5 is reset. At a third time, the second scan signal line S2 changes from a low level signal to a high level signal, the second transistor T2 is turned on, and the second node N2 is reset. At a fourth time, the second emission signal line EM2 changes from a low level signal to a high level signal, the sixth transistor T6 is turned on, and the third node N3 is reset.

[0115] The second stage A2 is called a compensation stage. The signals of the first scan signal line S1, the second scan signal line S2 and the first emission signal line EM1 are high level signals, and the signals of the third scan signal line S3, the fourth scan signal line S4 and the second emission signal line EM2 are low level signals, so that the first transistor T1, the second transistor T2 and the fifth transistor T5 are turned on, and other switch transistors are turned off.

[0116] The turn-on of the first transistor T1 and the second transistor T2 makes the potentials of the first node N1 and the second node N2 continue to be Vinit1, and the turn-on of the fifth transistor T5 makes the first power signal output by the first power supply line VDD be written to the fourth node N4 through the turned-on fifth transistor T5. Since the third transistor T3 is turned on, the potential of the third node N3 gradually increases to Vinit1-Vth, where Vth is the threshold voltage of the third transistor T3. At this time, since the potential of the second node N2 is Vinit1, the potential stored by the first capacitor C1 is the threshold voltage Vth, that is, the threshold voltage Vth of the third transistor T3 is written to the first capacitor C1.

[0117] The third stage A3 is called a data writing stage. The signals of the first scan signal line S1 and the second scan signal line S2 change from high level signals to low level signals after a period of time, the signal of the fourth scan signal line S4 is a high level signal for a short time, and the signals of the third scan signal line S3, the first emission signal line EM1 and the second emission signal line EM2 are low level signals. The first transistor T1, the second transistor T2 and the fourth transistor T4 are turned on and then turned off.

[0118] At the first time, the first scan signal line S1 changes from high level signal to low level signal, the first transistor T1 is turned off, the potential of the first node N1 is slightly fluctuated, but the potential of the second node N2 and the third node N3 is less disturbed.

[0119] At the second time, the signal of the fourth scan signal line S4 changes from low level signal to high level signal, the fourth transistor T4 is turned on, the data signal outputted by the data signal line DATA is written into the first node N1, i.e. stored in the second capacitor C2, the potential of the first node N1 becomes Vd, Vd is the voltage of the data signal outputted by the data signal line DATA. When the data signal is written into the first node N1, the second node N2 is stabilized at the potential of Vinit1 because the second transistor T2 is turned on, so the potential of the third node N3 is Vinit1-Vth. In addition, because the third transistor T3 between the first node N1 and the third node N3 is turned off, the potential of the third node N3 is not disturbed when the data signal is written into the first node N1.

[0120] At the third time, the second scan signal line S2 changes from high level signal to low level signal, the second transistor T2 is turned off, because the data writing has been completed at this time, the potential of the first node N1 will not change.

[0121] The fourth stage A4 is called light emitting stage. The signals of the first light emitting signal line EM1 and the second light emitting signal line EM2 are high level signals, the signals of the first scan signal line S1, the second scan signal line S2, the third scan signal line S3 and the fourth scan signal line S4 are low level signals, the fifth transistor T5 and the sixth transistor T6 are turned on.

[0122] At the first time, the second light emitting signal line EM2 changes from low level signal to high level signal, the sixth transistor T6 is turned on, the potential of the third node N3 is written into the fifth node N5, the fifth node N5 is pre-charged in advance. At the second time, the first light emitting signal line EM1 changes from low level signal to high level signal, the fifth transistor T5 is turned on, the first power signal outputted by the first power supply line VDD provides driving voltage to the first electrode of the light emitting element EL through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, and drives the light emitting element EL to emit light.

[0123] The output current I of the third transistor T3 OLED The following formula is satisfied:

[0124] I OLED =1 / 2*K1*[Vd-[Vinit1-Vth]-Vth] 2 =1 / 2*K2*(Vd-Vinit1) 2 .

[0125] wherein K1 is a constant related to process and design.

[0126] As can be seen from the formula of the output current of the third transistor T3, the output current of the pixel driving circuit is irrelevant to the threshold voltage Vth of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the output current, and the control of the output current can be realized by controlling the voltage Vd of the data signal, so as to control the brightness of the light emitting device EL.

[0127] FIG. 6 is a structural schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure, which illustrates the structure of three circuit units. FIG. 7 is a schematic diagram of a capacitor structure according to an exemplary embodiment of the present disclosure, and FIG. 8 is a sectional view along A-A direction in FIG. 6. As shown in FIG. 6, FIG. 7 and FIG. 8, in a plane parallel to the display substrate, the display substrate can include a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, and at least one circuit unit can include a pixel driving circuit, and a first light emitting signal line 41, a second light emitting signal line 42, a first scan signal line 61, a second scan signal line 62, a third scan signal line 63, a fourth scan signal line 64, a first initial signal line 71, a second initial signal line 72, a first power supply line (not shown) and a data signal line (not shown) connected to the pixel driving circuit. The at least one pixel driving circuit can include at least a first capacitor 10, a second capacitor 20, a third capacitor 30, a first connection electrode 51 having a first node potential, a second connection electrode 52 having a second node potential, a third connection electrode 53 having a third node potential, a first transistor T1 as a first reset transistor, a second transistor T2 as a second reset transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first light emitting control transistor, a sixth transistor T6 as a second light emitting control transistor, and a seventh transistor T7 as a third reset transistor.

[0128] In the exemplary embodiment, the first light emitting signal line 41 and the second light emitting signal line 42 are configured to provide a first light emitting control signal and a second light emitting control signal to the pixel driving circuit respectively, the first scan signal line 61 to the fourth scan signal line 64 are configured to provide a first scan signal to a fourth scan signal to the pixel driving circuit respectively, the first initial signal line 71 and the second initial signal line 72 are configured to provide a first initial signal and a second initial signal to the pixel driving circuit respectively, the first power supply line is configured to provide a first power supply signal to the pixel driving circuit, and the data signal line is configured to provide a data signal to the pixel driving circuit.

[0129] In the example embodiment, the first to seventh transistors T1 to T7 can be oxide transistors. The first capacitor 10 can include at least a first plate 11 and a second plate 12, the second capacitor 20 can include at least a third plate 13 and a fourth plate 14, and the third capacitor 30 can include at least the fourth plate 14 and a fifth plate 15.

[0130] In the example embodiment, the gate electrode of the first transistor T1 is connected to the first scan signal line 61, the first electrode of the first transistor T1 is connected to the first initial signal line 71, the second electrode of the first transistor T1 and the second electrode of the fourth transistor T4 are connected to each other, and the second electrode of the fourth transistor T4 is connected to the gate electrode of the third transistor T3 through the first connection electrode 51, the gate electrode of the third transistor T3 is connected to the fourth plate 14 through the plate-level connection bar 38 and the sixth connection electrode. The gate electrode of the second transistor T2 is connected to the second scan signal line 62, the first electrode of the second transistor T2 is connected to the first initial signal line 71, and the second electrode of the second transistor T2 is connected to the first plate 11 and the third plate 13 through the second connection electrode 52, respectively. The first electrode of the third transistor T3 and the second electrode of the fifth transistor T5 are connected to each other, the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6 are connected to each other, and the second electrode of the third transistor T3 is connected to the second plate 12 through the third connection electrode 53. The gate electrode of the fourth transistor T4 is connected to the fourth scan signal line 64, and the first electrode of the fourth transistor T4 is connected to the data signal line. The gate electrode of the fifth transistor T5 is connected to the first emission signal line 41, and the first electrode of the fifth transistor T5 is connected to the first power supply line. The gate electrode of the sixth transistor T6 is connected to the second emission signal line 42, and the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 are connected to each other. The gate electrode of the seventh transistor T7 is connected to the third scan signal line 63, and the first electrode of the seventh transistor T7 is connected to the second initial signal line 72.

[0131] In the example embodiment, the first scan signal line 61, the second scan signal line 62, the third scan signal line 63, the fourth scan signal line 64, the first emission signal line 41, the second emission signal line 42, the first initial signal line 71, and the second initial signal line 72 can have a shape of a straight line or a broken line in which a main portion extends along the first direction X. The first power supply line and the data signal line can have a shape of a straight line or a broken line in which a main portion extends along the second direction Y.

[0132] In the present disclosure, A extending along a direction B means that A can include a main portion and a sub-portion connected to the main portion, the main portion is a line, a line segment, or a bar-shaped body, the main portion extends along the direction B, and the length of the main portion extending along the direction B is greater than the length of the sub-portion extending along other directions. In the following description, A extending along the direction B always means that the main portion of A extends along the direction B.

[0133] In the example embodiment, in a direction perpendicular to the display substrate, the display substrate can at least include a first conductive layer (a first gate metal layer) disposed on the base 101, a first insulating layer 91 disposed on a side of the first conductive layer away from the base 101, a second conductive layer (a second gate metal layer) disposed on a side of the first insulating layer 91 away from the base 101, a second insulating layer 92 disposed on a side of the second conductive layer away from the base 101, a semiconductor layer disposed on a side of the second insulating layer 92 away from the base 101, a third insulating layer 93 disposed on a side of the semiconductor layer away from the base 101, a third conductive layer (a third gate metal layer) disposed on a side of the third insulating layer 93 away from the base 101, a fourth insulating layer 94 disposed on a side of the third conductive layer away from the base 101, and a fourth conductive layer (a first source-drain metal layer) disposed on a side of the fourth insulating layer 94 away from the base 101.

[0134] In the example embodiment, the first plate 11 and the third plate 13 can be disposed in the first conductive layer, the first plate 11 and the third plate 13 can be an integral structure connected to each other, and the first plate 11 and the third plate 13 of the integral structure are connected to the first end of the second connecting electrode 52, and the second end of the second connecting electrode 52 is connected to the second electrode of the second transistor T2, that is, the first plate 11 and the third plate 13 can be connected to the second electrode of the second transistor T2 through the second connecting electrode 52. The first plate 11 can serve as the second end of the first capacitor 10, the third plate 13 can serve as the second end of the second capacitor 20, and the first plate 11 and the third plate 13 have a second node potential, which refers to the potential of the second node N2 in the pixel driving circuit.

[0135] In the example embodiment, the second plate 12 can be disposed in the second conductive layer, the second plate 12 is connected to the second end of the third connecting electrode 53, and the first end of the third connecting electrode 53 is connected to the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6, that is, the second plate 12 can be connected to the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6 through the third connecting electrode 53. The second plate 12 can serve as the first end of the first capacitor 10 and has a third node potential, which refers to the potential of the second node N3 in the pixel driving circuit.

[0136] In the example embodiment, the orthographic projection of the second plate 12 on the base at least partially overlaps the orthographic projection of the first plate 11 on the base, and the first plate 11 having the second node potential and the second plate 12 having the third node potential form the first capacitor C1 of the pixel driving circuit.

[0137] In the example embodiment, the fourth plate 14 can be disposed in the second conductive layer, and the fourth plate 14 can be connected to the second electrode of the first transistor T1 and the second electrode of the fourth transistor T4 through the sixth connection electrode 56, the plate connection strip 38, the third gate electrode 33, and the first connection electrode 51. The fourth plate 14 can serve as a first terminal of the second capacitor 20, and has a first node potential, which refers to the potential of the first node N1 in the pixel driving circuit.

[0138] In the example embodiment, the first end of the first connection electrode 51 is connected to the second electrode of the first transistor T1 and the second electrode of the fourth transistor T4, and the second end of the first connection electrode 51 is connected to the third gate electrode 33 (the gate electrode of the third transistor T3), and the third gate electrode 33 is connected to the fourth plate 14 through the plate connection strip 38 and the sixth connection electrode 56.

[0139] In the example embodiment, the first end of the sixth connection electrode 56 is connected to the fourth plate 14, and the second end of the sixth connection electrode 56 is connected to the plate connection strip 38, and the plate connection strip 38 is connected to the third gate electrode 33.

[0140] In the example embodiment, in at least one circuit unit, the third gate electrode 33 and the plate connection strip 38 can be disposed in the third conductive layer and form an integrated structure.

[0141] In the example embodiment, the orthographic projection of the fourth plate 14 on the substrate at least partially overlaps the orthographic projection of the third plate 13 on the substrate, and the third plate 13 having the second node potential and the fourth plate 14 having the first node potential form the second capacitor C2 of the pixel driving circuit.

[0142] In the example embodiment, the fifth plate 15 can be disposed in the semiconductor layer, and the fifth plate 15 can be connected to the second plate 12 through the third connection electrode 53. The fourth plate 14 can serve as a first terminal of the third capacitor 30 and has the first node potential, and the fifth plate 15 can serve as a second terminal of the third capacitor 30 and has a third node potential. The fourth plate 14 serves as one capacitor plate of the second capacitor C2 and one capacitor plate of the third capacitor C3, that is, the second capacitor C2 and the third capacitor C3 share the same capacitor plate.

[0143] In the example embodiment, the first end of the third connection electrode 53 is connected to the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6, the second end of the third connection electrode 53 is connected to the second plate 12, the fifth plate 15 is connected to the first electrode of the sixth transistor T6, and thus the connection between the fifth plate 15 and the second plate 12 is realized, and the second plate 12 and the fifth plate 15 have the same third node potential.

[0144] In the example embodiment, the sixth transistor T6 can at least include a sixth active layer, and the fifth plate 15 and the sixth active layer can be an integrated structure connected to each other.

[0145] In the example embodiment, a normal projection of the fifth plate 15 on the substrate at least partially overlaps a normal projection of the fourth plate 14 on the substrate, and the fourth plate 14 having the first node potential and the fifth plate 15 having the third node potential form a third capacitor C3 of the pixel driving circuit.

[0146] In the example embodiment, the fourth conductive layer can further include a first power connection line 65 extending along the first direction X and connected to the first power line, and the first power connection line 65 and the first power line form a mesh communication structure for transmitting the first power signal on the display substrate.

[0147] In the example embodiment, the fourth conductive layer can further include a second power connection line 66 extending along the first direction X and connected to the second power line, and the second power connection line 66 and the second power line form a mesh communication structure for transmitting the second power signal on the display substrate.

[0148] In the example embodiment, the fourth scan signal line 64 can be located on a side of the third gate electrode 33 in the second direction Y opposite to the first direction X, the second power connection line 66 can be located on a side of the fourth scan signal line 64 away from the third gate electrode 33, and the first power connection line 65 can be located on a side of the second power connection line 66 away from the third gate electrode 33. The first scan signal line 61 can be located on a side of the third gate electrode 33 in the second direction Y, the first initial signal line 71 can be located on a side of the first scan signal line 61 away from the third gate electrode 33, the second scan signal line 62 can be located on a side of the first initial signal line 71 away from the third gate electrode 33, the second initial signal line 72 can be located on a side of the second scan signal line 62 away from the third gate electrode 33, and the third scan signal line 63 can be located on a side of the second initial signal line 72 away from the third gate electrode 33.

[0149] In the example embodiment, a normal projection of the first scan signal line 61 on the substrate does not overlap a normal projection of the first connection electrode 51 on the substrate, and / or a normal projection of the first scan signal line 61 on the substrate does not overlap a normal projection of the third gate electrode 33 on the substrate, and / or a normal projection of the first scan signal line 61 on the substrate does not overlap a normal projection of the sixth connection electrode 56 on the substrate, and / or a normal projection of the first scan signal line 61 on the substrate does not overlap a normal projection of the fourth plate 14 on the substrate.

[0150] In the example embodiment, a normal projection of the first scan signal line 61 on the substrate does not overlap a normal projection of the second connection electrode 52 on the substrate.

[0151] In an example embodiment, the orthogonal projection of the second scan signal line 62 onto the substrate does not overlap with the orthogonal projection of the first connection electrode 51 onto the substrate, and / or the orthogonal projection of the second scan signal line 62 onto the substrate does not overlap with the orthogonal projection of the third gate electrode 33 onto the substrate, and / or the orthogonal projection of the second scan signal line 62 onto the substrate does not overlap with the orthogonal projection of the plate connection strip 38 onto the substrate, and / or the orthogonal projection of the second scan signal line 62 onto the substrate does not overlap with the orthogonal projection of the sixth connection electrode 56 onto the substrate, and / or the orthogonal projection of the second scan signal line 62 onto the substrate does not overlap with the orthogonal projection of the fourth plate 14 onto the substrate.

[0152] In an example embodiment, the orthogonal projection of the second scan signal line 62 onto the substrate does not overlap with the orthogonal projection of the second connection electrode 52 onto the substrate, and / or the orthogonal projection of the second scan signal line 62 onto the substrate does not overlap with the orthogonal projection of the first plate 11 onto the substrate, and / or the orthogonal projection of the second scan signal line 62 onto the substrate does not overlap with the orthogonal projection of the third plate 13 onto the substrate.

[0153] In an example embodiment, the orthogonal projection of the third scan signal line 63 onto the substrate does not overlap with the orthogonal projection of the first connection electrode 51 onto the substrate, and / or the orthogonal projection of the third scan signal line 63 onto the substrate does not overlap with the orthogonal projection of the third gate electrode 33 onto the substrate, and / or the orthogonal projection of the third scan signal line 63 onto the substrate does not overlap with the orthogonal projection of the plate connection strip 38 onto the substrate, and / or the orthogonal projection of the third scan signal line 63 onto the substrate does not overlap with the orthogonal projection of the sixth connection electrode 56 onto the substrate, and / or the orthogonal projection of the third scan signal line 63 onto the substrate does not overlap with the orthogonal projection of the fourth plate 14 onto the substrate.

[0154] In an example embodiment, the orthogonal projection of the third scan signal line 63 onto the substrate does not overlap with the orthogonal projection of the second connection electrode 52 onto the substrate, and / or the orthogonal projection of the third scan signal line 63 onto the substrate does not overlap with the orthogonal projection of the first plate 11 onto the substrate, and / or the orthogonal projection of the third scan signal line 63 onto the substrate does not overlap with the orthogonal projection of the third plate 13 onto the substrate.

[0155] In an example embodiment, the orthogonal projection of the fourth scan signal line 64 onto the substrate does not overlap with the orthogonal projection of the first connection electrode 51 onto the substrate, and / or, the orthogonal projection of the fourth scan signal line 64 onto the substrate does not overlap with the orthogonal projection of the third gate electrode 33 onto the substrate, and / or, the orthogonal projection of the fourth scan signal line 64 onto the substrate does not overlap with the orthogonal projection of the plate connection strip 38 onto the substrate, and / or, the orthogonal projection of the fourth scan signal line 64 onto the substrate does not overlap with the orthogonal projection of the sixth connection electrode 56 onto the substrate, and / or, the orthogonal projection of the fourth scan signal line 64 onto the substrate does not overlap with the orthogonal projection of the fourth plate 14 onto the substrate.

[0156] In an example embodiment, the orthogonal projection of the fourth scan signal line 64 onto the substrate does not overlap with the orthogonal projection of the second connection electrode 52 onto the substrate.

[0157] In an example embodiment, the orthogonal projection of the first initial signal line 71 onto the substrate does not overlap with the orthogonal projection of the first connection electrode 51 onto the substrate, and / or, the orthogonal projection of the first initial signal line 71 onto the substrate does not overlap with the orthogonal projection of the third gate electrode 33 onto the substrate, and / or, the orthogonal projection of the first initial signal line 71 onto the substrate does not overlap with the orthogonal projection of the plate connection strip 38 onto the substrate, and / or, the orthogonal projection of the first initial signal line 71 onto the substrate does not overlap with the orthogonal projection of the sixth connection electrode 56 onto the substrate.

[0158] In an example embodiment, the orthogonal projection of the first initial signal line 71 onto the substrate at least partially overlaps with the orthogonal projection of the fourth plate 14 onto the substrate, and the orthogonal projection of the first initial signal line 71 onto the substrate at least partially overlaps with the orthogonal projection of the fifth plate 15 onto the substrate, the fifth plate 15 being disposed between the fourth plate 14 and the first initial signal line 71 in a direction perpendicular to the substrate.

[0159] In an example embodiment, the orthogonal projection of the first initial signal line 71 onto the substrate does not overlap with the orthogonal projection of the second connection electrode 52 onto the substrate.

[0160] In an example embodiment, the orthogonal projection of the second initial signal line 72 onto the substrate does not overlap with the orthogonal projection of the first connection electrode 51 onto the substrate, and / or, the orthogonal projection of the second initial signal line 72 onto the substrate does not overlap with the orthogonal projection of the third gate electrode 33 onto the substrate, and / or, the orthogonal projection of the second initial signal line 72 onto the substrate does not overlap with the orthogonal projection of the plate connection strip 38 onto the substrate, and / or, the orthogonal projection of the second initial signal line 72 onto the substrate does not overlap with the orthogonal projection of the sixth connection electrode 56 onto the substrate, and / or, the orthogonal projection of the second initial signal line 72 onto the substrate does not overlap with the orthogonal projection of the fourth plate 14 onto the substrate.

[0161] In an example embodiment, the second initial signal line 72 has no overlap with the second connection electrode 52 on the substrate, and / or the second initial signal line 72 has no overlap with the first plate 11 on the substrate, and / or the second initial signal line 72 has no overlap with the third plate 13 on the substrate.

[0162] In an example embodiment, the pixel driving circuits in part of the adjacent unit columns can be mirror symmetrical with respect to a column center line, which can be a fold line located between the adjacent unit columns and extending along the second direction Y. For example, the pixel driving circuits in the Nth unit column and the (N+1)th unit column can be mirror symmetrical with respect to the column center line. For another example, the pixel driving circuits in the (N+1)th unit column and the (N+2)th unit column can be mirror symmetrical with respect to the column center line.

[0163] In an example embodiment, the pixel driving circuits in part of the adjacent unit columns can be substantially the same. For example, the pixel driving circuits in the Nth unit column and the (N+2)th unit column can be substantially the same.

[0164] In an example embodiment, in at least one unit row, the active layers of the fifth transistors T5 of part of the two adjacent circuit units can be a connected integral structure, and the two circuit units can share the first electrode of the same fifth transistor T5.

[0165] In an example embodiment, in at least one unit row, the active layers of the seventh transistors T7 of part of the two adjacent circuit units can be a connected integral structure, and the two circuit units can share the first electrode of the same seventh transistor T7.

[0166] In an example embodiment, in at least one unit row, the gate electrodes of the first transistors T1 of part of the two adjacent circuit units can be a connected integral structure.

[0167] In an example embodiment, in at least one unit row, the gate electrodes of the second transistors T2 of part of the two adjacent circuit units can be a connected integral structure.

[0168] In an example embodiment, in at least one unit row, the gate electrodes of the fourth transistors T4 of part of the two adjacent circuit units can be a connected integral structure.

[0169] In an example embodiment, the first light emitting signal line 41 and the second light emitting signal line 42 can be provided in the third conductive layer, and the first scan signal line 61, the second scan signal line 62, the third scan signal line 63, and the fourth scan signal line 64 can be provided in the fourth conductive layer.

[0170] In the exemplary embodiment, the display substrate can further include a fifth insulating layer disposed on the fourth conductive layer away from the base 101, a first planar layer disposed on the fifth insulating layer away from the base 101, and a fifth conductive layer (second source-drain metal layer) disposed on the first planar layer away from the base 101. The fifth conductive layer can include at least a first power line, a second power line, and a data signal line.

[0171] In the exemplary embodiment, the fifth conductive layer can further include a first initial connection line extending along the second direction Y and connected to the first initial signal line 71, and the first initial signal line 71 and the first initial connection line form a meshed communication structure on the display substrate for transmitting the first initial signal.

[0172] In the exemplary embodiment, the fifth conductive layer can further include a second initial connection line extending along the second direction Y and connected to the second initial signal line 72, and the second initial signal line 72 and the second initial connection line form a meshed communication structure on the display substrate for transmitting the second initial signal.

[0173] The preparation process of the display substrate according to the exemplary embodiment will be described below. The "patterning process" in the present disclosure refers to the process of depositing a film layer, coating photoresist on the film layer, mask exposure, development, etching, stripping photoresist, etc. for metal materials, inorganic materials or transparent conductive materials, and refers to the process of coating organic materials, mask exposure and development, etc. for organic materials. The deposition can use any one or more of sputtering, evaporation, chemical vapor deposition, the coating can use any one or more of spraying, spin coating and inkjet printing, and the etching can use any one or more of dry etching and wet etching, which are not limited in the present disclosure. The "thin film" refers to a thin film of a certain material on a substrate made by deposition, coating or other processes. If the "thin film" does not need to be patterned during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" needs to be patterned during the entire manufacturing process, it is referred to as a "thin film" before the patterning process and as a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are disposed in the same layer" in the present disclosure means that A and B are formed at the same time by the same patterning process. The "thickness" of the film layer refers to the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiment of the present disclosure, "the orthographic projection of B is within the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0174] In an example embodiment, taking three circuit units of one unit row and three unit columns (Nth unit column, N+1th unit column, N+2th unit column) as an example, the embodiment shows that the preparation process of the substrate can include the following operations.

[0175] (11) Forming a first conductive layer pattern. In an example embodiment, forming the first conductive layer pattern can include: depositing a first conductive film on the substrate, patterning the first conductive film by a patterning process, and forming the first conductive layer pattern on the substrate, as shown in FIG. 9. In an example embodiment, the first conductive layer can be referred to as a first gate metal (GATE1) layer.

[0176] In an example embodiment, the first conductive layer pattern of each circuit unit in the display substrate can include at least a first plate 11 of a first capacitor and a third plate 13 of a second capacitor.

[0177] In an example embodiment, the first plate 11 of the first capacitor can be rectangular in shape, and the first plate 11 is configured as one capacitor plate (second end of the first capacitor C1) of the first capacitor.

[0178] In an example embodiment, the third plate 13 of the second capacitor can be rectangular in shape, and the third plate 13 is configured as one capacitor plate (second end of the second capacitor C2) of the second capacitor.

[0179] In an example embodiment, the third plate 13 can be disposed on one side of the first plate 11 in the second direction Y and connected to the first plate 11, i.e., the second end of the first capacitor C1 and the second end of the second capacitor C2 are connected to each other.

[0180] In an example embodiment, in at least one circuit unit, the first plate 11 and the third plate 13 can be an integrated structure connected to each other.

[0181] In an example embodiment, the first conductive layer in part of the adjacent unit columns can be mirror-symmetrical with respect to the column center line. For example, the first conductive layer in the Nth unit column and the N+1th unit column can be mirror-symmetrical with respect to the column center line. For another example, the first conductive layer in the N+1th unit column and the N+2th unit column can be mirror-symmetrical with respect to the column center line.

[0182] In an example embodiment, the first conductive layer in part of the adjacent unit columns can be substantially the same. For example, the first conductive layer in the Nth unit column and the N+2th unit column can be substantially the same.

[0183] (12) forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern can include: sequentially depositing a first insulating thin film and a second conductive thin film on the substrate on which the aforementioned pattern is formed, patterning the second conductive thin film by a patterning process, forming a first insulating layer covering the first conductive layer pattern, and forming the second conductive layer pattern on the first insulating layer, as shown in FIG. 10A and FIG. 10B, which is a plan view of the second conductive layer in FIG. 10A. In an exemplary embodiment, the second conductive layer can be referred to as a second gate metal (GATE2) layer.

[0184] In an exemplary embodiment, the second conductive layer pattern of each circuit unit in the display substrate at least includes: a second plate 12 of a first capacitor and a fourth plate 14 of a second capacitor.

[0185] In an exemplary embodiment, the second plate 12 of the first capacitor can be rectangular in shape, the orthographic projection of the second plate 12 on the substrate at least partially overlaps the orthographic projection of the first plate 11 on the substrate, the second plate 12 is configured as another capacitor plate of the first capacitor (the first terminal of the first capacitor C1), and the first plate 11 and the second plate 12 constitute the first capacitor C1 of the pixel driving circuit.

[0186] In an exemplary embodiment, the orthographic projection of the second plate 12 on the substrate can be located within the range of the orthographic projection of the first plate 11 on the substrate.

[0187] In an exemplary embodiment, the fourth plate 14 of the second capacitor can be rectangular in shape, can be disposed on one side of the second plate 12 in the second direction Y, the orthographic projection of the fourth plate 14 on the substrate at least partially overlaps the orthographic projection of the third plate 13 on the substrate, the fourth plate 14 is configured as another capacitor plate of the second capacitor (the first terminal of the second capacitor C2), and the third plate 13 and the fourth plate 14 constitute the second capacitor C2 of the pixel driving circuit.

[0188] In an exemplary embodiment, the orthographic projection of the third plate 13 on the substrate can be located within the range of the orthographic projection of the fourth plate 14 on the substrate.

[0189] In an exemplary embodiment, the fourth plate 14 is also configured as a lower plate of a third capacitor (the first terminal of the third capacitor C3), and the fourth plate 14 and a fifth plate formed subsequently constitute the third capacitor C3 of the pixel driving circuit.

[0190] In an exemplary embodiment, the corner (top left corner) of the fourth plate 14 away from the second plate 12 can be provided with a recess, and the recess is configured to accommodate a seventeenth via hole formed subsequently.

[0191] In an exemplary embodiment, the ratio of the area of the orthographic projection of the second plate 12 on the first plate 11 to the area of the orthographic projection of the fourth plate 14 on the third plate 13 can be about 0.95 to 1.05, i.e., the ratio of the capacitance value of the first capacitor to the capacitance value of the second capacitor can be about 0.95 to 1.05.

[0192] In an exemplary embodiment, the area of the orthographic projection of the second plate 12 on the substrate and the area of the orthographic projection of the fourth plate 14 on the substrate can be substantially equal, i.e., the capacitance value of the first capacitor and the capacitance value of the second capacitor can be substantially equal. The present disclosure is advantageous for stabilizing the voltage of the source node (third node N3) of the driving transistor in the compensation stage, for stabilizing the voltage of the gate node (first node N1) of the driving transistor in the data writing stage, for facilitating the voltage coupling jump of the source node to the gate node (the coupling path is the third node N3 coupling the second node N2, and the second node N2 coupling the first node N1) in the light emitting stage, and for stabilizing the voltage of each node by setting the capacitance values of the first capacitor and the second capacitor to be substantially equal.

[0193] The present disclosure can be advantageous for the stability of the process and for approaching the designed theoretical capacitance value by designing the two capacitor plates of the first capacitor and the two capacitor plates of the second capacitor to be rectangular.

[0194] In an exemplary embodiment, the second conductive layers in some adjacent unit columns can be mirror symmetrical with respect to the column center line. For example, the second conductive layers in the Nth unit column and the N+1th unit column can be mirror symmetrical with respect to the column center line. For another example, the second conductive layers in the N+1th unit column and the N+2th unit column can be mirror symmetrical with respect to the column center line.

[0195] In an exemplary embodiment, the second conductive layers in some adjacent unit columns can be substantially the same. For example, the second conductive layers in the Nth unit column and the N+2th unit column can be substantially the same.

[0196] (13) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern can include: sequentially depositing a second insulating thin film and a semiconductor thin film on the substrate on which the aforementioned pattern is formed, patterning the semiconductor thin film by a patterning process, forming a second insulating layer covering the second conductive layer, and a semiconductor layer pattern disposed on the second insulating layer, as shown in FIGS. 11A and 11B, FIG. 11B being a plan view of the semiconductor layer in FIG. 11A.

[0197] In the exemplary embodiment, the semiconductor layer pattern of each circuit unit in the display substrate can include the fifth plate 15, the first active layer 21 of the first transistor T1 to the seventh active layer 27 of the seventh transistor T7, and the first active layer 21, the second active layer 22, and the fourth active layer 24 can be an integrated structure connected to each other, and the third active layer 23, the fifth active layer 25, the sixth active layer 26, and the seventh active layer 27 can be an integrated structure connected to each other.

[0198] In the exemplary embodiment, in the first direction X, the first active layer 21, the second active layer 22, and the fourth active layer 24 can be located on the same side of the third active layer 23 in the first direction X. In the second direction Y, the first active layer 21, the second active layer 22, the sixth active layer 26, and the seventh active layer 27 can be located on one side of the third active layer 23 in the second direction Y, and the fifth active layer 25 can be located on the opposite side of the third active layer 23 in the second direction Y.

[0199] In the exemplary embodiment, the second active layer 22 can be located on one side of the first active layer 21 in the second direction Y, and the fourth active layer 24 can be located on the opposite side of the first active layer 21 in the second direction Y, that is, the second active layer 22 and the fourth active layer 24 can be located on both sides of the first active layer 21 in the second direction Y, respectively.

[0200] In the exemplary embodiment, the sixth active layer 26 can be located on one side of the third active layer 23 in the second direction Y, the seventh active layer 27 can be located on one side of the sixth active layer 26 in the second direction Y, and the fifth active layer 25 can be located on the opposite side of the third active layer 23 in the second direction Y.

[0201] In the exemplary embodiment, the first active layer 21 to the fourth active layer 24, and the sixth active layer 26 can have a strip shape extending along the second direction Y, and the fifth active layer 25 and the seventh active layer 27 can have an "L" shape.

[0202] In the example embodiment, the active layer of each transistor can include a first region, a second region, and a channel region between the first region and the second region. In the example embodiment, the first region 21-1 of the first active layer and the first region 22-1 of the second active layer can be connected to each other, and the first region 21-1 of the first active layer can serve as the first region 22-1 of the second active layer. The second region 21-2 of the first active layer and the second region 24-2 of the fourth active layer can be connected to each other, and the second region 21-2 of the first active layer can serve as the second region 24-2 of the fourth active layer. The first region 23-1 of the third active layer and the second region 25-2 of the fifth active layer can be connected to each other, and the first region 23-1 of the third active layer can serve as the second region 25-2 of the fifth active layer. The second region 23-2 of the third active layer and the first region 26-1 of the sixth active layer can be connected to each other, and the second region 23-2 of the third active layer can serve as the first region 26-1 of the sixth active layer. The second region 26-2 of the sixth active layer and the second region 27-2 of the seventh active layer can be connected to each other, and the second region 26-2 of the sixth active layer can serve as the second region 27-2 of the seventh active layer. The second region 22-2 of the second active layer, the first region 24-1 of the fourth active layer, the first region 25-1 of the fifth active layer, and the first region 27-1 of the seventh active layer can be separately provided.

[0203] In some possible embodiments, the first region 21-1 of the first active layer and the first region 22-1 of the second active layer can be separately provided, i.e., the first region 21-1 of the first active layer and the first region 22-1 of the second active layer are not connected, so as to realize that the first region of the first active layer and the first region of the second active layer are connected to different signal lines, which is not limited in the disclosure.

[0204] In the example embodiment, in at least one unit row, the first region 25-1 of the fifth active layer in part of the adjacent circuit units can be connected to each other, and the fifth active layers 25 of the two circuit units can be an integrated structure connected to each other, and the two circuit units can share the same first region 25-1 of the fifth active layer. For example, the fifth active layer 25 in the Nth unit column and the fifth active layer 25 in the N+1th unit column can be an integrated structure connected to each other. By providing that part of the adjacent circuit units share the first electrode of the fifth transistor T5, the disclosure can effectively reduce the lateral wiring space, reduce the number of vias, reduce the occupied area of the pixel driving circuit, and be conducive to realizing high resolution.

[0205] In the example embodiment, in at least one unit row, the first regions 27-1 of the seventh active layers in the partially adjacent circuit units can be connected to each other, the seventh active layers 27 in the two circuit units can be an integrated structure connected to each other, and the two circuit units can share the same first region 27-1 of the seventh active layer. For example, the seventh active layer 27 in the N+1th unit column and the seventh active layer 27 in the N+2th unit column can be an integrated structure connected to each other. By arranging the first poles of the seventh transistors T7 to be shared by the partially adjacent circuit units, the present disclosure can effectively reduce the lateral wiring space, reduce the number of vias, reduce the area occupied by the pixel driving circuit, and facilitate the realization of high resolution.

[0206] In the example embodiment, the first active layer 21 and the fourth active layer 24 of the integrated structure can have a strip shape with a main body extending along the second direction Y, and at least one arc-shaped portion 29, and the arc-shaped portion 29 protrudes towards the third active layer 23.

[0207] In the example embodiment, the second region 21-2 of the first active layer (also the second region 24-2 of the fourth active layer) can be arranged in the arc-shaped portion 29. Since the second region 21-2 of the first active layer and the second region 24-2 of the fourth active layer are configured to be connected to the first connection electrode formed later, the design of the arc-shaped portion 29 can increase the distance between the first connection electrode and the data signal line formed later, i.e., the first node N1 is as far away from the data signal line as possible, thereby reducing the capacitance between the first node N1 and the data signal line, and further reducing the parasitic capacitance of the first node N1.

[0208] In the example embodiment, the first region 21-1 of the first active layer can be used as the first pole of the first transistor T1, the second region 21-2 of the first active layer can be used as the second pole of the first transistor T1, the first region 22-1 of the second active layer can be used as the first pole of the second transistor T2, the second region 22-2 of the second active layer can be used as the second pole of the second transistor T2, the first region 23-1 of the third active layer can be used as the first pole of the third transistor T3, the second region 23-2 of the third active layer can be used as the second pole of the third transistor T3, the first region 24-1 of the fourth active layer can be used as the first pole of the fourth transistor T4, the second region 24-2 of the fourth active layer can be used as the second pole of the fourth transistor T4, the first region 25-1 of the fifth active layer can be used as the first pole of the fifth transistor T5, the second region 25-2 of the fifth active layer can be used as the second pole of the fifth transistor T5, the first region 26-1 of the sixth active layer can be used as the first pole of the sixth transistor T6, the second region 26-2 of the sixth active layer can be used as the second pole of the sixth transistor T6, the first region 27-1 of the seventh active layer can be used as the first pole of the seventh transistor T7, and the second region 27-2 of the seventh active layer can be used as the second pole of the seventh transistor T7.

[0209] In an example embodiment, the fifth electrode plate 15 can be rectangular in shape, the corners of the rectangular shape can be provided with chamfers or grooves, the fifth electrode plate 15 is configured as one of the capacitor plates of the third capacitor (the second end of the third capacitor C3), and the fourth electrode plate 14 and the fifth electrode plate 15 constitute the third capacitor.

[0210] In an example embodiment, the ratio of the area of the fifth electrode plate 15 orthogonally projected on the fourth electrode plate 14 to the area of the fourth electrode plate 14 orthogonally projected on the substrate can be greater than 0.5, so as to increase the capacitance value of the third capacitor.

[0211] In an example embodiment, the fifth electrode plate 15 can be arranged on one side of the first direction X of the sixth active layer 26 or on the opposite side of the first direction X and connected to the first area 26-1 of the sixth active layer (also the second area 23-2 of the third active layer).

[0212] In an example embodiment, in at least one circuit unit, the third active layer 23, the fifth active layer 25, the sixth active layer 26, the seventh active layer 27, and the fifth electrode plate 15 can be an integrated structure connected to each other.

[0213] In an example embodiment, the semiconductor layer pattern can further include an active connection strip 28. The active connection strip 28 can be strip-shaped extending along the first direction X, and can be arranged between part of adjacent circuit units. The first end of the active connection strip 28 is connected to the first area 21-1 of the first active layer and the first area 22-1 of the second active layer in one circuit unit, the second end of the active connection strip 28 is connected to the first area 21-1 of the first active layer and the first area 22-1 of the second active layer in another circuit unit, and the active connection strip 28 is configured to simultaneously serve as the first area 21-1 of the first active layer and the first area 22-1 of the second active layer shared by the two circuit units.

[0214] In the example embodiment, the first active layer 21 and the second active layer 22 in the two circuit units and the active connection strip 28 in the partially adjacent unit columns can be an integrated structure connected to each other. For example, the active connection strip 28 can be arranged between the N+1th unit column and the N+2th unit column, the first active layer 21 and the second active layer 22 in the N+1th unit column, the first active layer 21 and the second active layer 22 in the N+2th unit column, and the active connection strip 28 arranged between the N+1th unit column and the N+2th unit column are an integrated structure connected to each other. The present disclosure can effectively reduce the wiring space, reduce the number of vias, reduce the occupied area of the pixel driving circuit, and facilitate the realization of high resolution by arranging the first electrode of the first transistor T1 and the first electrode of the second transistor T2 to be shared by the partially adjacent circuit units.

[0215] In the example embodiment, the third active layer 23 has a projection on the substrate that at least partially overlaps with a projection of the second electrode plate 12 on the substrate, and the second electrode plate 12 can also serve as the bottom gate electrode of the third transistor T3.

[0216] In the example embodiment, the semiconductor layers in the partially adjacent unit columns can be mirror symmetrical with respect to the column center line. For example, the semiconductor layers in the Nth unit column and the N+1th unit column can be mirror symmetrical with respect to the column center line. For another example, the semiconductor layers in the N+1th unit column and the N+2th unit column can be mirror symmetrical with respect to the column center line.

[0217] In the example embodiment, the semiconductor layers in the partially adjacent unit columns can be substantially the same. For example, the semiconductor layers in the Nth unit column and the N+2th unit column can be substantially the same.

[0218] In the example embodiment, the semiconductor layer can be an oxide, i.e., the first transistor T1 to the seventh transistor T7 are oxide transistors. Oxide transistors have the advantages of high electron mobility, low operating voltage, low leakage characteristics, etc. In the example embodiment, the oxide can be any one or more of the following: indium gallium zinc oxide (InGaZnO), indium gallium zinc nitrogen oxide (InGaZnON), zinc oxide (ZnO), zinc nitrogen oxide (ZnON), zinc tin oxide (ZnSnO), cadmium tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), strontium copper oxide (SrCuO), lanthanum copper oxide sulfur oxide (LaCuOS), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium gallium aluminum nitride (InGaAlN). In some possible implementations, the semiconductor thin film can use indium gallium zinc oxide (IGZO), and the electron mobility of indium gallium zinc oxide (IGZO) is higher than that of amorphous silicon.

[0219] (14) forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern can include: sequentially depositing a third insulating thin film and a third conductive thin film on the substrate on which the aforementioned patterns are formed, patterning the third conductive thin film by a patterning process, forming a third insulating layer covering the semiconductor layer pattern, and a third conductive layer pattern disposed on the third insulating layer, as shown in FIGS. 12A and 12B, which is a schematic view of the third conductive layer in FIG. 12A. In an exemplary embodiment, the third conductive layer can be referred to as a third gate metal (GATE3) layer.

[0220] In an exemplary embodiment, the third conductive layer pattern of each circuit unit in the display substrate at least includes: a first gate electrode 31, a second gate electrode 32, a third gate electrode 33, a fourth gate electrode 34, a seventh gate electrode 37, a plate connecting strip 38, a first light-emitting signal line 41, and a second light-emitting signal line 42.

[0221] In an exemplary embodiment, the shape of the first gate electrode 31 can be block-shaped (such as rectangular), and the orthographic projection of the first gate electrode 31 on the substrate at least partially overlaps the orthographic projection of the first active layer on the substrate, and the first gate electrode 31 can serve as the gate electrode of the first transistor T1.

[0222] In an exemplary embodiment, in at least one unit row, the first gate electrodes 31 in some adjacent circuit units can be connected to each other, and the first gate electrodes 31 of two circuit units can be an integrated structure connected to each other. For example, the first gate electrode 31 in the N+1th unit column and the first gate electrode 31 in the N+2th unit column can be an integrated structure connected to each other. By setting the first gate electrodes 31 in some adjacent circuit units to be an integrated structure connected to each other, the present disclosure can effectively reduce the wiring space, reduce the number of vias, reduce the occupied area of the pixel driving circuit, and be conducive to achieving high resolution.

[0223] In an exemplary embodiment, the shape of the second gate electrode 32 can be block-shaped (such as rectangular), and the second gate electrode 32 can be disposed on one side of the first gate electrode 31 in the second direction Y, and the orthographic projection of the second gate electrode 32 on the substrate at least partially overlaps the orthographic projection of the second active layer on the substrate, and the second gate electrode 32 can serve as the gate electrode of the second transistor T2.

[0224] In the example embodiment, in at least one unit row, the second gate electrodes 32 in some adjacent circuit units can be connected to each other, and the second gate electrodes 32 of two circuit units can be an integrated structure connected to each other. For example, the second gate electrode 32 in the N+1th unit column and the second gate electrode 32 in the N+2th unit column can be an integrated structure connected to each other. The disclosure can effectively reduce the wiring space, reduce the number of vias, and reduce the occupied area of the pixel driving circuit by setting the second gate electrodes 32 in some adjacent circuit units as an integrated structure connected to each other, which is conducive to achieving high resolution.

[0225] In the example embodiment, the third gate electrode 33 can be in a block shape (such as a rectangular shape), and a normal projection of the third gate electrode 33 on the substrate at least partially overlaps a normal projection of the third active layer on the substrate, and the third gate electrode 33 can serve as a top gate electrode of the third transistor T3.

[0226] In the example embodiment, the fourth gate electrode 34 can be in a block shape (such as a rectangular shape), and can be arranged on a side opposite to the second direction Y of the first gate electrode 31, and a normal projection of the fourth gate electrode 34 on the substrate at least partially overlaps a normal projection of the fourth active layer on the substrate, and the fourth gate electrode 34 can serve as a gate electrode of the fourth transistor T4.

[0227] In the example embodiment, in at least one unit row, the fourth gate electrodes 34 in some adjacent circuit units can be connected to each other, and the fourth gate electrodes 34 of two circuit units can be an integrated structure connected to each other. For example, the fourth gate electrode 34 in the N+1th unit column and the fourth gate electrode 34 in the N+2th unit column can be an integrated structure connected to each other. The disclosure can effectively reduce the wiring space, reduce the number of vias, and reduce the occupied area of the pixel driving circuit by setting the fourth gate electrodes 34 in some adjacent circuit units as an integrated structure connected to each other, which is conducive to achieving high resolution.

[0228] In the example embodiment, the seventh gate electrode 37 can be in a block shape (such as a rectangular shape), and can be arranged on a side of the second gate electrode 32 in the second direction Y, and a normal projection of the seventh gate electrode 37 on the substrate at least partially overlaps a normal projection of the seventh active layer on the substrate, and the seventh gate electrode 37 can serve as a gate electrode of the seventh transistor T7.

[0229] In the example embodiment, the first light-emitting signal line 41 can be in a straight line shape or a polyline shape extending along the first direction X, and can be arranged between the second gate electrode 32 and the seventh gate electrode 37, and a normal projection of the first light-emitting signal line 41 on the substrate at least partially overlaps a normal projection of the fifth active layer 25 on the substrate, and the overlapping area can serve as a gate electrode of the fifth transistor T5, so that the first light-emitting signal line 41 can control the conduction or disconnection of the fifth transistor T5.

[0230] In an exemplary embodiment, the first light-emitting signal line 41 can be of a variable width structure, the width of the first light-emitting signal line being the dimension of the second direction Y. The first light-emitting signal line 41 can include a first region overlapping the fifth active layer 25 and a second region not overlapping the fifth active layer 25, the width of the first region being greater than the width of the second region.

[0231] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the first light-emitting signal line 41 on the substrate does not overlap the orthographic projection of the first, second, third, fourth and fifth plates 11, 12, 13, 14 and 15 on the substrate.

[0232] In an exemplary embodiment, the second light-emitting signal line 42 can be of a straight line shape or a broken line shape extending along the first direction X, and can be disposed on the side of the fourth gate electrode 34 away from the first gate electrode 31. The orthographic projection of the second light-emitting signal line 42 on the substrate at least partially overlaps the orthographic projection of the sixth active layer 26 on the substrate, and the overlapping region can serve as the gate electrode of the sixth transistor T6, so that the second light-emitting signal line 42 can control the on or off of the sixth transistor T6.

[0233] In an exemplary embodiment, the second light-emitting signal line 42 can be of a variable width structure, the width of the second light-emitting signal line being the dimension of the second direction Y. The second light-emitting signal line 42 can include a first region overlapping the sixth active layer 26 and a second region not overlapping the sixth active layer 26, the width of the first region being greater than the width of the second region.

[0234] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the second light-emitting signal line 42 on the substrate does not overlap the orthographic projection of the first, second, third, fourth and fifth plates 11, 12, 13, 14 and 15 on the substrate.

[0235] In an exemplary embodiment, the plate connection strip 38 can be of a strip shape extending along the second direction Y, and can be disposed on the side of the third gate electrode 33 in the second direction Y. The first end of the plate connection strip 38 is connected to the third gate electrode 33, the second end of the plate connection strip 38 extends away from the third gate electrode 33, and the orthographic projection of the second end of the plate connection strip 38 on the substrate at least partially overlaps the orthographic projection of the fourth plate 14 on the substrate.

[0236] In an exemplary embodiment, in at least one circuit unit, the third gate electrode 33 and the plate connection strip 38 can be of an integrated structure connected to each other.

[0237] In an example embodiment, the third conductive layers in some adjacent cell columns can be mirror symmetrical with respect to the column center line. For example, the third conductive layers in the Nth cell column and the N+1th cell column can be mirror symmetrical with respect to the column center line. For another example, the third conductive layers in the N+1th cell column and the N+2th cell column can be mirror symmetrical with respect to the column center line.

[0238] In an example embodiment, the third conductive layers in some adjacent cell columns can be substantially the same. For example, the third conductive layers in the Nth cell column and the N+2th cell column can be substantially the same.

[0239] (15) Forming a fourth insulating layer pattern. In an example embodiment, forming the fourth insulating layer pattern can include: on the substrate on which the aforementioned patterns are formed, depositing a fourth insulating thin film, patterning the fourth insulating thin film by using a patterning process, forming a fourth insulating layer covering the third conductive layer, and the fourth insulating layer being provided with a plurality of vias, as shown in FIG. 13.

[0240] In an example embodiment, the plurality of vias in each circuit unit of the display substrate at least include: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, and a seventeenth via V17.

[0241] In an example embodiment, in the circuit unit of the Nth cell column, the orthographic projection of the first via V1 on the substrate is within the range of the orthographic projection of the first region of the first active layer (also the first region of the second active layer) on the substrate, the third insulating layer and the fourth insulating layer within the first via V1 are etched away, exposing the surface of the first region of the first active layer (also the first region of the second active layer), and the first via V1 is configured to allow the first initial signal line formed subsequently to pass through the via and connect with the first region of the first active layer (also the first region of the second active layer).

[0242] In the exemplary embodiments, in the circuit units of the N+1th unit column and the N+2th unit column, the first via V1 has a projection on the substrate within the projection on the substrate of the active connection strip 28, the third insulating layer and the fourth insulating layer in the first via V1 are etched away to expose the surface of the active connection strip 28, and the first via V1 is configured to connect the subsequently formed first initial signal line with the active connection strip 28 through the via. Since the active connection strip 28 simultaneously serves as the first region of the first active layer and the first region of the second active layer shared by two circuit units, the two circuit units share the first via V1, and three circuit units are provided with only two first vias V1, thereby effectively reducing the number of vias, reducing the area occupied by the pixel driving circuit, and facilitating the realization of high resolution.

[0243] In the exemplary embodiments, the second via V2 has a projection on the substrate within the projection on the substrate of the second region of the first active layer (also the second region of the fourth active layer), the third insulating layer and the fourth insulating layer in the second via V2 are etched away to expose the surface of the second region of the first active layer (also the second region of the fourth active layer), and the second via V2 is configured to connect the subsequently formed first connection electrode with the second region of the first active layer (also the second region of the fourth active layer) through the via.

[0244] In the exemplary embodiments, the first active layer and the fourth active layer of the integral structure include at least one arc-shaped portion, and the second via V2 can be arranged in the region of the arc-shaped portion.

[0245] In the exemplary embodiments, the third via V3 has a projection on the substrate within the projection on the substrate of the second region of the second active layer, the third insulating layer and the fourth insulating layer in the third via V3 are etched away to expose the surface of the second region of the second active layer, and the third via V3 is configured to connect the subsequently formed second connection electrode with the second region of the second active layer through the via.

[0246] In the exemplary embodiments, the fourth via V4 has a projection on the substrate within the projection on the substrate of the first region of the fourth active layer, the third insulating layer and the fourth insulating layer in the fourth via V4 are etched away to expose the surface of the first region of the fourth active layer, and the fourth via V4 is configured to connect the subsequently formed fourth connection electrode with the first region of the fourth active layer through the via.

[0247] In the example embodiment, the normal projection of the fifth via V5 on the substrate is located within the normal projection of the second region of the third active layer (also the first region of the sixth active layer) on the substrate, the third insulating layer and the fourth insulating layer in the fifth via V5 are etched away to expose the surface of the second region of the third active layer (also the first region of the sixth active layer), and the fifth via V5 is configured to enable a third connection electrode formed subsequently to connect with the second region of the third active layer (also the first region of the sixth active layer) through the via.

[0248] In the example embodiment, the normal projection of the sixth via V6 on the substrate is located within the normal projection of the first region of the fifth active layer on the substrate, the third insulating layer and the fourth insulating layer in the sixth via V6 are etched away to expose the surface of the first region of the fifth active layer, and the sixth via V6 is configured to enable a power connection line formed subsequently to connect with the first region of the fifth active layer through the via. Since two adjacent circuit units partially share the same first region of the fifth active layer, the two adjacent circuit units partially can share the sixth via V6, and three circuit units are provided with only two sixth vias V6, which effectively reduces the number of vias, reduces the area occupied by the pixel driving circuit, and is conducive to achieving high resolution.

[0249] In the example embodiment, the normal projection of the seventh via V7 on the substrate is located within the normal projection of the second region of the sixth active layer (also the second region of the seventh active layer) on the substrate, the third insulating layer and the fourth insulating layer in the seventh via V7 are etched away to expose the surface of the second region of the sixth active layer (also the second region of the seventh active layer), and the seventh via V7 is configured to enable a fifth connection electrode formed subsequently to connect with the second region of the sixth active layer (also the second region of the seventh active layer) through the via.

[0250] In the example embodiment, the normal projection of the eighth via V8 on the substrate is located within the normal projection of the first region of the seventh active layer on the substrate, the third insulating layer and the fourth insulating layer in the eighth via V8 are etched away to expose the surface of the first region of the seventh active layer, and the eighth via V8 is configured to enable a second initial signal line formed subsequently to connect with the first region of the seventh active layer through the via. Since two adjacent circuit units partially share the same first region of the seventh active layer, the two adjacent circuit units partially can share the eighth via V8, and three circuit units are provided with only two eighth vias V8, which effectively reduces the number of vias, reduces the area occupied by the pixel driving circuit, and is conducive to achieving high resolution.

[0251] In the example embodiment, the normal projection of the ninth via V9 on the substrate is within the range of the normal projection of the second plate 12 on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the ninth via V9 are etched away to expose the surface of the second plate 12, and the ninth via V9 is configured to connect the third connecting electrode formed subsequently therewith the second plate 12 through the via.

[0252] In the example embodiment, the normal projection of the tenth via V10 on the substrate is within the range of the normal projection of the fourth plate 14 on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the tenth via V10 are etched away to expose the surface of the fourth plate 14, and the tenth via V10 is configured to connect the sixth connecting electrode formed subsequently therewith the fourth plate 14 through the via.

[0253] In the example embodiment, the normal projection of the eleventh via V11 on the substrate is within the range of the normal projection of the first gate electrode 31 on the substrate, the fourth insulating layer in the eleventh via V11 is etched away to expose the surface of the first gate electrode 31, and the eleventh via V11 is configured to connect the first scanning signal line formed subsequently therewith the first gate electrode 31 through the via. Since the first gate electrodes 31 in the two adjacent circuit units are integrally connected with each other, the two adjacent circuit units can share the eleventh via V11, and the three circuit units are provided with only two eleventh vias V11, which effectively reduces the number of vias and reduces the area occupied by the pixel driving circuit, and is conducive to achieving high resolution.

[0254] In the example embodiment, the normal projection of the twelfth via V12 on the substrate is within the range of the normal projection of the second gate electrode 32 on the substrate, the fourth insulating layer in the twelfth via V12 is etched away to expose the surface of the second gate electrode 32, and the twelfth via V12 is configured to connect the second scanning signal line formed subsequently therewith the second gate electrode 32 through the via. Since the second gate electrodes 32 in the two adjacent circuit units are integrally connected with each other, the two adjacent circuit units can share the twelfth via V12, and the three circuit units are provided with only two twelfth vias V12, which effectively reduces the number of vias and reduces the area occupied by the pixel driving circuit, and is conducive to achieving high resolution.

[0255] In the example embodiment, the normal projection of the thirteenth via V13 on the substrate is within the range of the normal projection of the third gate electrode 33 on the substrate, the fourth insulating layer in the thirteenth via V13 is etched away to expose the surface of the third gate electrode 33, and the thirteenth via V13 is configured to connect the first connecting electrode formed subsequently therewith the third gate electrode 33 through the via.

[0256] In the example embodiment, the fourth gate electrode 34 is formed on the substrate 10. The fourth gate electrode 34 is configured to be connected to the fourth scan signal line. In the example embodiment, the fourth gate electrode 34 is formed by depositing a fourth conductive thin film on the substrate 10, and patterning the fourth conductive thin film by using a patterning process. In the example embodiment, the fourth gate electrode 34 can be referred to as a first gate electrode.

[0257] In the example embodiment, the fifteenth via V15 is formed on the substrate 10. The fourth insulating layer in the fifteenth via V15 is etched away, exposing the surface of the plate connecting strip 38. The fifteenth via V15 is configured to enable the sixth connecting electrode formed subsequently to be connected to the plate connecting strip 38 through the via.

[0258] In the example embodiment, the sixteenth via V16 is formed on the substrate 10. The fourth insulating layer in the sixteenth via V16 is etched away, exposing the surface of the seventh gate electrode 37. The sixteenth via V16 is configured to enable the third scan signal line formed subsequently to be connected to the seventh gate electrode 37 through the via.

[0259] In the example embodiment, the seventeenth via V17 is formed on the substrate 10. The first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer in the seventeenth via V17 are etched away, exposing the surface of the third plate 13. The seventeenth via V17 is configured to enable the second connecting electrode formed subsequently to be connected to the third plate 13 through the via.

[0260] (16) Forming a fourth conductive layer pattern. In the example embodiment, forming the fourth conductive layer can include: on the substrate on which the aforementioned pattern is formed, depositing a fourth conductive thin film, and patterning the fourth conductive thin film by using a patterning process, to form a fourth conductive layer disposed on the fourth insulating layer. In the example embodiment, the fourth conductive layer can be referred to as a first source-drain metal (SD1) layer.

[0261] In the exemplary embodiment, the fourth conductive layer of each circuit unit in the display substrate at least includes: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, a first scan signal line 61, a second scan signal line 62, a third scan signal line 63, a fourth scan signal line 64, a first power connection line 65, a second power connection line 66, a first initial signal line 71, and a second initial signal line 72.

[0262] In the exemplary embodiment, the first connection electrode 51 can be in the shape of a strip extending along the first direction X, a first end of the first connection electrode 51 is connected to the second region of the first active layer (also the second region of the fourth active layer) through the second via V2, and a second end of the first connection electrode 51 is connected to the third gate electrode 33 through the thirteenth via V13. Since the third gate electrode 33 is connected to the fourth plate 14 through the plate connection strip 38 and the sixth connection electrode 56, the first connection electrode 51 realizes the connection between the second electrode of the first transistor T1, the gate electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the first end (the fourth plate 14) of the second capacitor C2, forms the first node N1 of the pixel driving circuit, that is, the first connection electrode 51, the third gate electrode 33, the plate connection strip 38, the sixth connection electrode 56, and the fourth plate 14 have the first node potential. In the exemplary embodiment, the first connection electrode 51 can serve as the first node electrode of the present disclosure.

[0263] In the exemplary embodiment, the second connection electrode 52 can be in the shape of a strip extending along the first direction X, a first end of the second connection electrode 52 is connected to the second region of the second active layer through the third via V3, and a second end of the second connection electrode 52 is connected to the third plate 13 through the seventeenth via V17. Since the first plate 11 and the third plate 13 are an integrated structure connected to each other, the second connection electrode 52 realizes the connection between the second electrode of the second transistor T2, the second end (the first plate 11) of the first capacitor C1, and the second end (the third plate 13) of the second capacitor C2, forms the second node N2 of the pixel driving circuit, that is, the second connection electrode 52, the first plate 11, and the third plate 13 have the second node potential. In the exemplary embodiment, the second connection electrode 52 can serve as the second node electrode of the present disclosure.

[0264] In the example embodiment, the third connection electrode 53 can have a strip shape extending along the first direction X, a first end of the third connection electrode 53 is connected to the first region of the second region of the third active layer (also the first region of the sixth active layer) through the fifth via V5, and a second end of the third connection electrode 53 is connected to the second plate 12 through the ninth via V9, thereby realizing the interconnection between the second electrode of the third transistor T3, the first electrode of the sixth transistor T6, and the first end (the second plate 12) of the first capacitor C1, forming the third node N3 of the pixel driving circuit, that is, the second plate 12 and the third connection electrode 53 have the third node potential. In the example embodiment, the third connection electrode 53 can serve as the third node electrode of the present disclosure.

[0265] In the example embodiment, since the fifth plate 15 is connected to the first region of the sixth active layer (also the second region of the third active layer), and the first region of the sixth active layer (also the second region of the third active layer) is connected to the second plate 12 through the third connection electrode 53, the second plate 12 and the fifth plate 15 have the same third node potential.

[0266] In the example embodiment, since the first plate 11 has the second node potential and the second plate 12 has the third node potential, the first plate 11 having the second node potential and the second plate 12 having the third node potential form the first capacitor C1 of the pixel driving circuit.

[0267] In the example embodiment, since the third plate 13 has the second node potential and the fourth plate 14 has the first node potential, the third plate 13 having the second node potential and the fourth plate 14 having the first node potential form the second capacitor C2 of the pixel driving circuit.

[0268] In the example embodiment, since the fourth plate has the first node potential and the fifth plate 15 has the third node potential, the fourth plate 14 having the first node potential and the fifth plate 15 having the third node potential can form the third capacitor C3 of the pixel driving circuit.

[0269] In the example embodiment, since the second plate 12 also serves as the bottom gate electrode of the third transistor T3, the bottom gate electrode of the third transistor T3 has the third node potential of the pixel driving circuit.

[0270] In the example embodiment, the fourth connection electrode 54 can have a block shape (such as a rectangular shape), the fourth connection electrode 54 is connected to the first region of the fourth active layer through the fourth via V4, and the fourth connection electrode 54 is configured to be connected to the subsequently formed data signal line.

[0271] In the example embodiment, the fifth connection electrode 55 can be in a block shape (e.g., a rectangular shape), the fifth connection electrode 55 is connected with the second region of the sixth active layer (also the second region of the seventh active layer) through the seventh via V7, and the fifth connection electrode 55 is configured to be connected with the anode connection electrode formed subsequently.

[0272] In the example embodiment, the sixth connection electrode 56 can be in a strip shape extending along the first direction X, the first end of the sixth connection electrode 56 is connected with the fourth plate 14 through the tenth via V10, and the second end of the sixth connection electrode 56 is connected with the plate connection strip 38 through the fifteenth via V15. Since the plate connection strip 38 is connected with the third gate electrode 33, the third gate electrode 33 is connected with the second region of the first active layer (also the second region of the fourth active layer) through the first connection electrode 51, the first connection electrode 51, the third gate electrode 33, the plate connection strip 38, the sixth connection electrode 56, and the fourth plate 14 have the first node potential.

[0273] In the example embodiment, the first scan signal line 61 can be in a straight line shape or a broken line shape extending along the first direction X and can be arranged continuously in one unit row. The orthographic projection of the first scan signal line 61 on the substrate at least partially overlaps the orthographic projection of the first gate electrode 31 on the substrate, the first scan signal line 61 is connected with the first gate electrode 31 in each circuit unit through the eleventh via V11, thus realizing the connection of the first scan signal line 61 with the gate electrode of the first transistor T1 in each circuit unit, and the first scan signal line 61 can control the turn-on or turn-off of the first transistor T1.

[0274] In the example embodiment, in at least one circuit unit, the orthographic projection of the first scan signal line 61 on the substrate at least partially overlaps the orthographic projection of the plate connection strip 38 on the substrate.

[0275] In the example embodiment, in at least one circuit unit, the orthographic projection of the first scan signal line 61 on the substrate does not overlap the orthographic projection of the first connection electrode 51 on the substrate, and / or the orthographic projection of the first scan signal line 61 on the substrate does not overlap the orthographic projection of the third gate electrode 33 on the substrate, and / or the orthographic projection of the first scan signal line 61 on the substrate does not overlap the orthographic projection of the sixth connection electrode 56 on the substrate, and / or the orthographic projection of the first scan signal line 61 on the substrate does not overlap the orthographic projection of the fourth plate 14 on the substrate. Since the first connection electrode 51, the third gate electrode 33, the sixth connection electrode 56, and the fourth plate 14 all have the first node potential, the overlap capacitance between the first node N1 and the first scan signal line 61 can be effectively reduced by the position arrangement of the first scan signal line 61, and thus the parasitic capacitance of the first node N1 is reduced.

[0276] In the example embodiment, in at least one circuit unit, the orthogonal projection of the first scan signal line 61 on the substrate does not overlap with the orthogonal projection of the second connection electrode 52 on the substrate. Since the second connection electrode 52 has the second node potential, the overlap capacitance between the second node N2 and the first scan signal line 61 can be effectively reduced by the position setting of the first scan signal line 61, and the parasitic capacitance of the second node N2 is further reduced.

[0277] In the example embodiment, in at least one circuit unit, the orthogonal projection of the first scan signal line 61 on the substrate does not overlap with the orthogonal projection of the third connection electrode 53 on the substrate.

[0278] In the example embodiment, the second scan signal line 62 can be in a straight line or a broken line shape extending along the first direction X and can be continuously arranged in one unit row. The second scan signal line 62 can be provided with a scan connection strip 62-1, which can be in a strip shape extending along the second direction Y. The orthogonal projection of the scan connection strip 62-1 on the substrate at least partially overlaps with the orthogonal projection of the second gate electrode 32 on the substrate. The first end of the scan connection strip 62-1 is connected to the second scan signal line 62, and the second end of the scan connection strip 62-1 extends towards the first scan signal line 61 and is connected to the second gate electrode 32 through the twelfth via V12, so that the second scan signal line 62 is connected to the gate electrode of the second transistor T2 in each circuit unit, and the second scan signal line 62 can control the conduction or disconnection of the second transistor T2.

[0279] In the example embodiment, in at least one circuit unit, the second scan signal line 62 and the scan connection strip 62-1 can be an integrated structure connected to each other.

[0280] In the example embodiment, in at least one circuit unit, the orthogonal projection of the second scan signal line 62 on the substrate does not overlap with the orthogonal projection of the first connection electrode 51 on the substrate, and / or the orthogonal projection of the second scan signal line 62 on the substrate does not overlap with the orthogonal projection of the third gate electrode 33 on the substrate, and / or the orthogonal projection of the second scan signal line 62 on the substrate does not overlap with the orthogonal projection of the plate connection strip 38 on the substrate, and / or the orthogonal projection of the second scan signal line 62 on the substrate does not overlap with the orthogonal projection of the sixth connection electrode 56 on the substrate, and / or the orthogonal projection of the second scan signal line 62 on the substrate does not overlap with the orthogonal projection of the fourth plate 14 on the substrate. Since the first connection electrode 51, the third gate electrode 33, the plate connection strip 38, the sixth connection electrode 56 and the fourth plate 14 have the first node potential, the overlap capacitance between the first node N1 and the second scan signal line 62 can be effectively reduced by the position setting of the second scan signal line 62, and the parasitic capacitance of the first node N1 is further reduced.

[0281] In the example embodiment, in at least one circuit unit, the orthogonal projection of the second scan signal line 62 on the substrate does not overlap with the orthogonal projection of the second connection electrode 52 on the substrate, and / or the orthogonal projection of the second scan signal line 62 on the substrate does not overlap with the orthogonal projection of the first plate 11 on the substrate, and / or the orthogonal projection of the second scan signal line 62 on the substrate does not overlap with the orthogonal projection of the third plate 13 on the substrate. Since the second connection electrode 52, the first plate 11 and the third plate 13 have the second node potential, the overlapping capacitance between the second node N2 and the second scan signal line 62 can be effectively reduced by the position setting of the second scan signal line 62, and the parasitic capacitance of the second node N2 is further reduced.

[0282] In the example embodiment, in at least one circuit unit, the orthogonal projection of the second scan signal line 62 on the substrate does not overlap with the orthogonal projection of the third connection electrode 53 on the substrate.

[0283] In the example embodiment, the third scan signal line 63 can be in a straight line or a broken line shape extending along the first direction X, and can be continuously arranged in one unit row. The orthogonal projection of the third scan signal line 63 on the substrate at least partially overlaps with the orthogonal projection of the seventh gate electrode 37 on the substrate, and the third scan signal line 63 is connected to the seventh gate electrode 37 in each circuit unit through the sixteenth via V16, so that the connection between the third scan signal line 63 and the gate electrode of the seventh transistor T7 in each circuit unit is realized, and the third scan signal line 63 can control the conduction or disconnection of the seventh transistor T7.

[0284] In the example embodiment, in at least one circuit unit, the orthogonal projection of the third scan signal line 63 on the substrate does not overlap with the orthogonal projection of the first connection electrode 51 on the substrate, and / or the orthogonal projection of the third scan signal line 63 on the substrate does not overlap with the orthogonal projection of the third gate electrode 33 on the substrate, and / or the orthogonal projection of the third scan signal line 63 on the substrate does not overlap with the orthogonal projection of the plate connection strip 38 on the substrate, and / or the orthogonal projection of the third scan signal line 63 on the substrate does not overlap with the orthogonal projection of the sixth connection electrode 56 on the substrate, and / or the orthogonal projection of the third scan signal line 63 on the substrate does not overlap with the orthogonal projection of the fourth plate 14 on the substrate. Since the first connection electrode 51, the third gate electrode 33, the plate connection strip 38, the sixth connection electrode 56 and the fourth plate 14 have the first node potential, the overlapping capacitance between the first node N1 and the third scan signal line 63 can be effectively reduced by the position setting of the third scan signal line 63, and the parasitic capacitance of the first node N1 is further reduced.

[0285] In the exemplary embodiments, in at least one circuit unit, the orthogonal projection of the third scan signal line 63 on the substrate does not overlap with the orthogonal projection of the second connection electrode 52 on the substrate, and / or the orthogonal projection of the third scan signal line 63 on the substrate does not overlap with the orthogonal projection of the first plate 11 on the substrate, and / or the orthogonal projection of the third scan signal line 63 on the substrate does not overlap with the orthogonal projection of the third plate 13 on the substrate. Since the second connection electrode 52, the first plate 11 and the third plate 13 have the second node potential, the overlapping capacitance between the second node N2 and the third scan signal line 63 can be effectively reduced by the position setting of the third scan signal line 63, and the parasitic capacitance of the second node N2 is further reduced.

[0286] In the exemplary embodiments, in at least one circuit unit, the orthogonal projection of the third scan signal line 63 on the substrate does not overlap with the orthogonal projection of the third connection electrode 53 on the substrate.

[0287] In the exemplary embodiments, the fourth scan signal line 64 can be in a linear or zigzag shape extending along the first direction X, and can be continuously arranged in one unit row. The orthogonal projection of the fourth scan signal line 64 on the substrate at least partially overlaps with the orthogonal projection of the fourth gate electrode 34 on the substrate, and the fourth scan signal line 64 is connected to the fourth gate electrode 34 in each circuit unit through the fourteenth via V14, so that the connection of the fourth scan signal line 64 and the gate electrode of the fourth transistor T4 in each circuit unit is realized, and the fourth scan signal line 64 can control the turn-on or turn-off of the fourth transistor T4.

[0288] In the exemplary embodiments, in at least one circuit unit, the orthogonal projection of the fourth scan signal line 64 on the substrate does not overlap with the orthogonal projection of the first connection electrode 51 on the substrate, and / or the orthogonal projection of the fourth scan signal line 64 on the substrate does not overlap with the orthogonal projection of the third gate electrode 33 on the substrate, and / or the orthogonal projection of the fourth scan signal line 64 on the substrate does not overlap with the orthogonal projection of the plate connection strip 38 on the substrate, and / or the orthogonal projection of the fourth scan signal line 64 on the substrate does not overlap with the orthogonal projection of the sixth connection electrode 56 on the substrate, and / or the orthogonal projection of the fourth scan signal line 64 on the substrate does not overlap with the orthogonal projection of the fourth plate 14 on the substrate. Since the first connection electrode 51, the third gate electrode 33, the plate connection strip 38, the sixth connection electrode 56 and the fourth plate 14 all have the first node potential, the overlapping capacitance between the first node N1 and the fourth scan signal line 64 can be effectively reduced by the position setting of the first scan signal line 61, and the parasitic capacitance of the first node N1 is further reduced.

[0289] In the example embodiment, in at least one circuit unit, the fourth scan signal line 64 has no overlap with the second connection electrode 52 on the substrate.

[0290] In the example embodiment, in at least one circuit unit, the fourth scan signal line 64 at least partially overlaps with the first plate 11 and the second plate 12 on the substrate, and the second plate 12 is arranged between the first plate 11 and the fourth scan signal line 64. In this way, the second plate 12 can effectively shield the overlap capacitance between the fourth scan signal line 64 and the second node N2, further reducing the parasitic capacitance of the second node N2.

[0291] In the example embodiment, the fourth scan signal line 64 has no overlap with the third connection electrode 53 on the substrate.

[0292] The present disclosure effectively reduces the resistance of the scan signal line by arranging the first scan signal line 61, the second scan signal line 62, the third scan signal line 63, and the fourth scan signal line 64 in the first source-drain metal (SD1) layer, reduces the voltage drop of the scan signal, improves the compensation speed, and improves the display quality.

[0293] In the example embodiment, the first power connection line 65 can be in the shape of a straight line or a broken line extending along the first direction X, and can be continuously arranged in one unit row. The first power connection line 65 is connected to the first area of the fifth active layer in each circuit unit through the sixth via hole V6. The first power connection line 65 is configured to be connected to the first power line formed subsequently, so that the first power line can write the first power signal to the first electrode of the fifth transistor T5 in each circuit unit.

[0294] In the example embodiment, the first power connection line 65 can be provided with a first power connection block 65-1. The first power connection block 65-1 can be in the shape of a block (such as a rectangle), and can be arranged on the side of the first power connection line 65 close to the fourth scan signal line 64, and connected to the first power connection line 65. The first power connection block 65-1 is configured to be connected to the first power line formed subsequently.

[0295] In the example embodiment, in at least one circuit unit, the first power connection line 65 and the first power connection block 65-1 can be an integrated structure connected to each other.

[0296] In the example embodiment, the first power supply connection block 65-1 can be arranged in the circuit units of the (N+1)th unit column and the (N+2)th unit column, respectively.

[0297] In the example embodiment, in at least one of the circuit units, the first power supply connection line 65 has no overlap with the first connection electrode 51 in the orthographic projection of the substrate, and / or the first power supply connection line 65 has no overlap with the third gate electrode 33 in the orthographic projection of the substrate, and / or the first power supply connection line 65 has no overlap with the plate connection strip 38 in the orthographic projection of the substrate, and / or the first power supply connection line 65 has no overlap with the sixth connection electrode 56 in the orthographic projection of the substrate, and / or the first power supply connection line 65 has no overlap with the fourth plate 14 in the orthographic projection of the substrate. Since the first connection electrode 51, the third gate electrode 33, the plate connection strip 38, the sixth connection electrode 56 and the fourth plate 14 have the first node potential, the overlap capacitance between the first node N1 and the first power supply connection line 65 can be effectively reduced by the position arrangement of the first power supply connection line 65, and the parasitic capacitance of the first node N1 is reduced.

[0298] In the example embodiment, in at least one of the circuit units, the first power supply connection line 65 has no overlap with the second connection electrode 52 in the orthographic projection of the substrate, and / or the first power supply connection line 65 has no overlap with the first plate 11 in the orthographic projection of the substrate, and / or the first power supply connection line 65 has no overlap with the third plate 13 in the orthographic projection of the substrate. Since the second connection electrode 52, the first plate 11 and the third plate 13 have the second node potential, the overlap capacitance between the second node N2 and the first power supply connection line 65 can be effectively reduced by the position arrangement of the first power supply connection line 65, and the parasitic capacitance of the second node N2 is reduced.

[0299] In the example embodiment, in at least one of the circuit units, the first power supply connection line 65 has no overlap with the third connection electrode 53 in the orthographic projection of the substrate.

[0300] In the example embodiment, the second power supply connection line 66 can be in the shape of a straight line or a broken line extending along the first direction X, and can be arranged continuously in one unit row. The second power supply connection line 66 can be provided with a second power supply connection block 66-1. The second power supply connection block 66-1 can be in the shape of a block (such as a rectangle), and can be arranged on the side of the second power supply connection line 66 close to the first power supply connection line 65, and connected with the second power supply connection line 66. The second power supply connection block 66-1 is configured to be connected with the second power supply line formed subsequently.

[0301] In the at least one circuit unit, the second power supply connection line 66 and the second power supply connection block 66-1 can be an integrated structure connected to each other.

[0302] In the at least one circuit unit, the second power supply connection block 66-1 can be arranged between the Nth unit column and the N+1th unit column.

[0303] In the at least one circuit unit, a projection of the second power supply connection line 66 on the substrate does not overlap with a projection of the first connection electrode 51 on the substrate, and / or a projection of the second power supply connection line 66 on the substrate does not overlap with a projection of the third gate electrode 33 on the substrate, and / or a projection of the second power supply connection line 66 on the substrate does not overlap with a projection of the plate connection strip 38 on the substrate, and / or a projection of the second power supply connection line 66 on the substrate does not overlap with a projection of the sixth connection electrode 56 on the substrate, and / or a projection of the second power supply connection line 66 on the substrate does not overlap with a projection of the fourth plate 14 on the substrate. Since the first connection electrode 51, the third gate electrode 33, the plate connection strip 38, the sixth connection electrode 56 and the fourth plate 14 have the first node potential, the overlap capacitance between the first node N1 and the second power supply connection line 66 can be effectively reduced by the position arrangement of the second power supply connection line 66, and the parasitic capacitance of the first node N1 is reduced.

[0304] In the at least one circuit unit, a projection of the second power supply connection line 66 on the substrate does not overlap with a projection of the second connection electrode 52 on the substrate. Since the second connection electrode 52 has the second node potential, the overlap capacitance between the second node N2 and the second power supply connection line 66 can be effectively reduced by the position arrangement of the second power supply connection line 66, and the parasitic capacitance of the second node N2 is reduced.

[0305] In the at least one circuit unit, a projection of the second power supply connection line 66 on the substrate does not overlap with a projection of the third connection electrode 53 on the substrate.

[0306] In the at least one circuit unit, the first initial signal line 71 can be a straight line or a broken line extending along the first direction X, and can be arranged continuously in one unit row. In the circuit unit of the Nth unit column, the first initial signal line 71 is connected to the first area of the first active layer (also the first area of the second active layer) through the first via V1. In the circuit units of the N+1th unit column and the N+2th unit column, the first initial signal line 71 is connected to the active connection strip 28 through the first via V1. The first initial signal line 71 realizes writing the first initial signal to the first electrode of the first transistor T1 and the first electrode of the second transistor T2 in each circuit unit at the same time.

[0307] In an example embodiment, the first initial signal line 71 can be provided with a first initial connection block 71-1. The first initial connection block 71-1 can be in a block shape (e.g., a rectangular shape), can be provided on a side of the first initial signal line 71 close to the second scan signal line 62, and can be connected to the second scan signal line 62. The first initial connection block 71-1 is configured to be connected to a first initial connection line to be formed later.

[0308] In an example embodiment, in at least one circuit unit, the first initial signal line 71 and the first initial connection block 71-1 can be an integrated structure connected to each other.

[0309] In an example embodiment, the first initial connection block 71-1 can be provided in the circuit unit of the Nth unit column.

[0310] In an example embodiment, in at least one circuit unit, a projection of the first initial signal line 71 on the substrate does not overlap a projection of the first connection electrode 51 on the substrate, and / or a projection of the first initial signal line 71 on the substrate does not overlap a projection of the third gate electrode 33 on the substrate, and / or a projection of the first initial signal line 71 on the substrate does not overlap a projection of the plate connection strip 38 on the substrate, and / or a projection of the first initial signal line 71 on the substrate does not overlap a projection of the sixth connection electrode 56 on the substrate. Since the first connection electrode 51, the third gate electrode 33, the plate connection strip 38, and the sixth connection electrode 56 all have a first node potential, by the position of the first initial signal line 71, the overlapping capacitance between the first node N1 and the first initial signal line 71 can be effectively reduced, and thus the parasitic capacitance of the first node N1 can be reduced.

[0311] In an example embodiment, in at least one circuit unit, a projection of the first initial signal line 71 on the substrate at least partially overlaps a projection of the fourth plate 14 and the fifth plate 15 on the substrate, and in a direction perpendicular to the substrate, the fifth plate 15 is provided between the fourth plate 14 and the first initial signal line 71. In this way, the fifth plate 15 can effectively shield the overlapping capacitance between the first initial signal line 71 and the first node N1, and further reduce the parasitic capacitance of the first node N1.

[0312] In an example embodiment, in at least one circuit unit, a projection of the first initial signal line 71 on the substrate does not overlap a projection of the second connection electrode 52 and the first plate 11 on the substrate. Since the second connection electrode 52 and the first plate 11 have a second node potential, by the position of the second scan signal line 62, the overlapping capacitance between the second node N2 and the second scan signal line 62 can be effectively reduced, and thus the parasitic capacitance of the second node N2 can be reduced.

[0313] In the example embodiment, in at least one circuit unit, the orthogonal projection of the first initial signal line 71 on the substrate at least partially overlaps the orthogonal projection of the third plate 13, the fourth plate 14 and the fifth plate 15 on the substrate, and the fourth plate 14 and the fifth plate 15 are arranged between the third plate 13 and the first initial signal line 71 in the direction perpendicular to the substrate. In this way, the fourth plate 14 and the fifth plate 15 can effectively shield the overlapping capacitance between the first initial signal line 71 and the second node N2, further reducing the parasitic capacitance of the second node N2.

[0314] In the example embodiment, in at least one circuit unit, the orthogonal projection of the first initial signal line 71 on the substrate does not overlap the orthogonal projection of the third connection electrode 53 on the substrate.

[0315] In some possible embodiments, the first region of the first active layer and the first region of the second active layer can be arranged separately, and the fourth conductive layer can further include a reset signal line, the first initial signal line is connected to the first region of the first active layer through a via, and the reset signal line is connected to the first region of the second active layer through a via, which is not limited in the present disclosure.

[0316] In the example embodiment, the second initial signal line 72 can be in the shape of a straight line or a broken line extending along the first direction X, and can be arranged continuously in one unit row. The second initial signal line 72 is connected to the first region of the seventh active layer in each circuit unit through the eighth via V8, so that the second initial signal line 72 can write the second initial signal to the first electrode of the seventh transistor T7 in each circuit unit.

[0317] In the example embodiment, the second initial signal line 72 can be provided with a second initial connection block 72-1. The second initial connection block 72-1 can be in the shape of a block (such as a rectangle), and can be arranged on the side of the second initial signal line 72 close to the second scan signal line 62 and connected to the second initial signal line 72. The second initial connection block 72-1 is configured to be connected to the second initial connection line formed subsequently.

[0318] In the example embodiment, in at least one circuit unit, the second initial signal line 72 and the second initial connection block 72-1 can be an integrated structure connected to each other.

[0319] In the example embodiment, the second initial connection block 72-1 can be arranged in the circuit unit of the (N+2)th unit column.

[0320] In the exemplary embodiments, in at least one circuit unit, the orthogonal projection of the second initial signal line 72 on the substrate does not overlap with the orthogonal projection of the first connection electrode 51 on the substrate, and / or the orthogonal projection of the second initial signal line 72 on the substrate does not overlap with the orthogonal projection of the third gate electrode 33 on the substrate, and / or the orthogonal projection of the second initial signal line 72 on the substrate does not overlap with the orthogonal projection of the plate connecting strip 38 on the substrate, and / or the orthogonal projection of the second initial signal line 72 on the substrate does not overlap with the orthogonal projection of the sixth connection electrode 56 on the substrate, and / or the orthogonal projection of the second initial signal line 72 on the substrate does not overlap with the orthogonal projection of the fourth plate 14 on the substrate. Since the first connection electrode 51, the third gate electrode 33, the plate connecting strip 38, the sixth connection electrode 56 and the fourth plate 14 all have the first node potential, the overlap capacitance between the first node N1 and the second initial signal line 72 can be effectively reduced by the position setting of the second initial signal line 72, and thus the parasitic capacitance of the first node N1 is reduced.

[0321] In the exemplary embodiments, in at least one circuit unit, the orthogonal projection of the second initial signal line 72 on the substrate does not overlap with the orthogonal projection of the second connection electrode 52 on the substrate, and / or the orthogonal projection of the second initial signal line 72 on the substrate does not overlap with the orthogonal projection of the first plate 11 on the substrate, and / or the orthogonal projection of the second initial signal line 72 on the substrate does not overlap with the orthogonal projection of the third plate 13 on the substrate. Since the second connection electrode 52, the first plate 11 and the third plate 13 have the second node potential, the overlap capacitance between the second node N2 and the second initial signal line 72 can be effectively reduced by the position setting of the second initial signal line 72, and thus the parasitic capacitance of the second node N2 is reduced.

[0322] In the exemplary embodiments, in at least one circuit unit, the orthogonal projection of the second initial signal line 72 on the substrate does not overlap with the orthogonal projection of the third connection electrode 53 on the substrate.

[0323] In the exemplary embodiments, in at least one circuit unit, the fourth scan signal line 64, the first power supply connection line 65 and the second power supply connection line 66 can be located on the side opposite to the second direction Y of the third gate electrode 33, and the first scan signal line 61, the second scan signal line 62, the third scan signal line 63, the first initial signal line 71 and the second initial signal line 72 can be located on the side of the second direction Y of the third gate electrode 33.

[0324] In the exemplary embodiments, in at least one circuit unit, the fourth scan signal line 64 can be located on the side of the third gate electrode 33 in the opposite direction of the second direction Y, the second power supply connection line 66 can be located on the side of the fourth scan signal line 64 away from the third gate electrode 33, and the first power supply connection line 65 can be located on the side of the second power supply connection line 66 away from the third gate electrode 33. The first scan signal line 61 can be located on the side of the third gate electrode 33 in the second direction Y, the first initial signal line 71 can be located on the side of the first scan signal line 61 away from the third gate electrode 33, the second scan signal line 62 can be located on the side of the first initial signal line 71 away from the third gate electrode 33, the second initial signal line 72 can be located on the side of the second scan signal line 62 away from the third gate electrode 33, and the third scan signal line 63 can be located on the side of the second initial signal line 72 away from the third gate electrode 33.

[0325] In the exemplary embodiments, in at least one circuit unit, the orthographic projection of the first power supply connection line 65 on the substrate at least partially overlaps the orthographic projection of the first light-emitting signal line 41 on the substrate. The first power supply connection line 65 with a constant potential can effectively shield the first light-emitting signal transmitted by the first light-emitting signal line 41 from affecting the pixel driving circuit, thereby improving the working stability of the pixel driving circuit.

[0326] In the exemplary embodiments, the fourth conductive layers in some adjacent unit columns can be mirror-symmetrical with respect to the column center line. For example, the fourth conductive layers in the Nth unit column and the N+1th unit column can be mirror-symmetrical with respect to the column center line. For another example, the fourth conductive layers in the N+1th unit column and the N+2th unit column can be mirror-symmetrical with respect to the column center line.

[0327] In the exemplary embodiments, the fourth conductive layers in some adjacent unit columns can be substantially the same. For example, the fourth conductive layers in the Nth unit column and the N+2th unit column can be substantially the same.

[0328] In some possible embodiments, the distance between the fourth plate 14 and the fifth plate 15 can be reduced by reducing the thickness of the fourth insulating layer to effectively increase the capacitance value of the third capacitor C3, without affecting the process stability, which is not limited in the present disclosure.

[0329] (17) Forming a fifth insulating layer and a first planar layer pattern. In the exemplary embodiments, forming the fifth insulating layer and the first planar layer pattern can include: on the substrate on which the aforementioned patterns are formed, first depositing a fifth insulating thin film, then coating a first planar thin film, and patterning the fifth insulating thin film and the first planar thin film by using a patterning process to form a fifth insulating layer covering the fourth conductive layer pattern and a first planar layer disposed on the fifth insulating layer, and the fifth insulating layer and the first planar layer are provided with a plurality of vias, as shown in FIG. 15.

[0330] In an example embodiment, the plurality of vias in each circuit unit in the display substrate at least includes: a twenty-first via V21 and a twenty-second via V22.

[0331] In an example embodiment, a projection of the twenty-first via V21 on the substrate is within a projection of the fourth connection electrode 54 on the substrate, the fifth insulating layer and the first planar layer in the twenty-first via V21 are removed to expose a surface of the fourth connection electrode 54, and the twenty-first via V21 is configured to allow a data signal line formed subsequently to connect to the fourth connection electrode 54 through the via.

[0332] In an example embodiment, a projection of the twenty-second via V22 on the substrate is within a projection of the fifth connection electrode 55 on the substrate, the fifth insulating layer and the first planar layer in the twenty-second via V22 are removed to expose a surface of the fifth connection electrode 55, and the twenty-second via V22 is configured to allow an anode connection electrode formed subsequently to connect to the fifth connection electrode 55 through the via.

[0333] In an example embodiment, the at least one circuit unit can further include a twenty-third via V23. A projection of the twenty-third via V23 on the substrate is within a projection of the first power connection block 65-1 on the substrate, the fifth insulating layer and the first planar layer in the twenty-third via V23 are removed to expose a surface of the first power connection block 65-1, and the twenty-third via V23 is configured to allow a first power line formed subsequently to connect to the first power connection block 65-1 through the via.

[0334] In an example embodiment, the twenty-third via V23 can be respectively arranged in the circuit units in the (N+1)th unit column and the (N+2)th unit column.

[0335] In an example embodiment, the at least one circuit unit can further include a twenty-fourth via V24. A projection of the twenty-fourth via V24 on the substrate is within a projection of the second power connection block 66-1 on the substrate, the fifth insulating layer and the first planar layer in the twenty-fourth via V24 are removed to expose a surface of the second power connection block 66-1, and the twenty-fourth via V24 is configured to allow a second power line formed subsequently to connect to the second power connection block 66-1 through the via.

[0336] In an example embodiment, the twenty-fourth via V24 can be arranged between the Nth unit column and the (N+1)th unit column.

[0337] In the example embodiment, the at least one circuit unit can further include a twenty-fifth via V25. A projection of the twenty-fifth via V25 on the substrate is within a projection of the first initial connection block 71-1 on the substrate, a fifth insulating layer and the first planar layer within the twenty-fifth via V25 are removed to expose a surface of the first initial connection block 71-1, and the twenty-fifth via V25 is configured to enable a subsequently formed first initial connection line to connect to the first initial connection block 71-1 through the via.

[0338] In the example embodiment, the twenty-fifth via V25 can be disposed in a circuit unit of the Nth unit column.

[0339] In the example embodiment, the at least one circuit unit can further include a twenty-sixth via V26. A projection of the twenty-sixth via V26 on the substrate is within a projection of the second initial connection block 72-1 on the substrate, a fifth insulating layer and the first planar layer within the twenty-sixth via V26 are removed to expose a surface of the second initial connection block 72-1, and the twenty-sixth via V26 is configured to enable a subsequently formed second initial connection line to connect to the second initial connection block 72-1 through the via.

[0340] In the example embodiment, the twenty-sixth via V26 can be disposed in a circuit unit of the N+2th unit column.

[0341] (18) Forming a fifth conductive layer pattern. In the example embodiment, forming the fifth conductive layer can include: on the substrate on which the aforementioned pattern is formed, depositing a fifth conductive thin film, and patterning the fifth conductive thin film using a patterning process to form a fifth conductive layer disposed on the first planar layer, as shown in FIGS. 16A and 16B, where FIG. 16B is a plan view of the fifth conductive layer in FIG. 16A. In the example embodiment, the fifth conductive layer can be referred to as a second source-drain metal (SD2) layer.

[0342] In the example embodiment, the fifth conductive layer of each circuit unit at least includes: a data signal line 83 and an anode connection electrode 84.

[0343] In the example embodiment, the data signal line 83 can have a shape of a straight line or a broken line with a main body portion extending along the second direction Y, and the data signal line 83 is connected to the fourth connection electrode 54 through the twenty-first via V21. Since the fourth connection electrode 54 is connected to the first region of the fourth active layer through the via, the data signal line 83 can write a data signal to the first electrode of the fourth transistor T4.

[0344] In the example embodiment, the data signal line 83 in the Nth unit column and the data signal line 83 in the N+1th unit column can be mirror symmetrical relative to the column center line, the data signal line 83 in the N+1th unit column and the data signal line 83 in the N+2th unit column can be mirror symmetrical relative to the column center line, and the data signal line 83 in the Nth unit column and the data signal line 83 in the N+2th unit column can be substantially the same.

[0345] In the example embodiment, in at least one circuit unit, the orthogonal projection of the data signal line 83 on the substrate does not overlap the orthogonal projection of the first connection electrode 51 on the substrate, and / or the orthogonal projection of the data signal line 83 on the substrate does not overlap the orthogonal projection of the third gate electrode 33 on the substrate, and / or the orthogonal projection of the data signal line 83 on the substrate does not overlap the orthogonal projection of the plate connecting strip 38 on the substrate, and / or the orthogonal projection of the data signal line 83 on the substrate does not overlap the orthogonal projection of the sixth connection electrode 56 on the substrate, and / or the orthogonal projection of the data signal line 83 on the substrate does not overlap the orthogonal projection of the fourth plate 14 on the substrate. Since the first connection electrode 51, the third gate electrode 33, the plate connecting strip 38, the sixth connection electrode 56 and the fourth plate 14 have the first node potential, the overlap capacitance between the first node N1 and the data signal line 83 can be effectively reduced by the position setting of the data signal line 83, and the parasitic capacitance of the first node N1 is further reduced.

[0346] In the example embodiment, in at least one circuit unit, the orthogonal projection of the data signal line 83 on the substrate does not overlap the orthogonal projection of the second connection electrode 52 on the substrate, and / or the orthogonal projection of the data signal line 83 on the substrate does not overlap the orthogonal projection of the first plate 11 on the substrate, and / or the orthogonal projection of the data signal line 83 on the substrate does not overlap the orthogonal projection of the third plate 13 on the substrate. Since the second connection electrode 52, the first plate 11 and the third plate 13 have the second node potential, the overlap capacitance between the second node N2 and the data signal line 83 can be effectively reduced by the position setting of the data signal line 83, and the parasitic capacitance of the second node N2 is further reduced.

[0347] In the example embodiment, in at least one circuit unit, the orthogonal projection of the data signal line 83 on the substrate does not overlap the orthogonal projection of the third connection electrode 53 on the substrate.

[0348] In the example embodiment, the data signal line 83 does not overlap the plurality of connection electrodes, which can also avoid the influence of data voltage jump on the driving transistor and maximize the reduction of crosstalk influence.

[0349] FIG. 16C is a schematic view of the positional relationship between the first connection electrode and the data signal line in FIG. 16A. As shown in FIG. 16C, in at least one circuit unit, the first active layer 21 and the fourth active layer 24 of the integrated structure can have a shape of a strip extending along the second direction Y, and an arc-shaped portion 29 is arranged on the strip, the arc-shaped portion 29 protruding in a direction away from the data signal line 83, i.e., in a direction close to the third gate electrode 33. The second via hole can be arranged in the arc-shaped portion 29, the first end of the first connection electrode 51 is connected to the second region of the first active layer (also the second region of the fourth active layer) through the second via hole, the second end of the first connection electrode 51 is connected to the third gate electrode 33 through the thirteenth via hole, and the data signal line 83 can be arranged on the side of the first connection electrode 51 away from the third gate electrode 33.

[0350] In an example embodiment, the first distance L1 between the first end of the first connection electrode 51 and the data signal line 83 can be greater than the second distance L2 between the first active layer 21 or the fourth active layer 24 and the data signal line 83, and the first distance L1 and the second distance L2 are both dimensions of the first direction X. The first distance L1 can be the minimum distance between the edge of the side of the first connection electrode 51 close to the data signal line 83 and the edge of the side of the data signal line 83 close to the first connection electrode 51, and the second distance L2 can be the minimum distance between the edge of the side of the first active layer 21 or the fourth active layer 24 close to the data signal line 83 and the edge of the side of the data signal line 83 close to the first active layer 21 or the fourth active layer 24. By arranging the arc-shaped portion 29, the present disclosure can effectively increase the distance between the first connection electrode 51 and the data signal line 83, i.e., the first node N1 is as far away from the data signal line 83 as possible, reduce the parallel capacitance between the first node N1 and the data signal line 83, and further reduce the parasitic capacitance of the first node N1.

[0351] In an example embodiment, the anode connection electrode 84 can have a shape of a strip extending along the second direction Y, the anode connection electrode 84 is connected to the fifth connection electrode 55 through the twenty-second via hole V22, and the anode connection electrode 84 is configured to be connected to the anode to be formed subsequently. Since the fifth connection electrode 55 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the via hole, the pixel driving circuit can output a driving current to the light emitting device.

[0352] In the example embodiment, the fifth conductive layer of the at least one circuit unit can further include a first power supply line 81. The first power supply line 81 can have a shape of a broken line with a main body extending along the second direction Y, and the first power supply line 81 can be connected to the first power supply connection block 65-1 through the twenty-third via hole V23. The first power supply connection line 65 and the first power supply line 81 form a meshed communication structure for transmitting the first power supply signal on the display substrate, and can effectively reduce the resistance of the first power supply line, reduce the voltage drop of the first power supply signal, effectively improve the uniformity of the first power supply signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance, due to the mutual connection of the first power supply connection line 65 with the main body extending along the first direction X and the first power supply line 81 with the main body extending along the second direction Y, and due to the first power supply connection block 65-1.

[0353] In the example embodiment, the first power supply line 81 can be arranged in the circuit units of the (N+1)th unit column and the (N+2)th unit column respectively, and the first power supply line 81 in the (N+1)th unit column and the first power supply line 81 in the (N+2)th unit column can be mirror symmetrical with respect to the column center line.

[0354] In the example embodiment, in the at least one circuit unit, the orthogonal projection of the first power supply line 81 on the substrate does not overlap with the orthogonal projection of the third gate electrode 33 on the substrate, and / or the orthogonal projection of the first power supply line 81 on the substrate does not overlap with the orthogonal projection of the plate connection strip 38 on the substrate, and / or the orthogonal projection of the first power supply line 81 on the substrate does not overlap with the orthogonal projection of the sixth connection electrode 56 on the substrate, and / or the orthogonal projection of the first power supply line 81 on the substrate does not overlap with the orthogonal projection of the fourth plate 14 on the substrate. Since the third gate electrode 33, the plate connection strip 38, the sixth connection electrode 56 and the fourth plate 14 have the first node potential, the position and the broken line shape of the first power supply line 81 can effectively reduce the overlapping capacitance between the first node N1 and the first power supply line 81, and further reduce the parasitic capacitance of the first node N1.

[0355] In the example embodiment, in the at least one circuit unit, the orthogonal projection of the first power supply line 81 on the substrate does not overlap with the orthogonal projection of the first plate 11 on the substrate, and / or the orthogonal projection of the first power supply line 81 on the substrate does not overlap with the orthogonal projection of the third plate 13 on the substrate. Since the first plate 11 and the third plate 13 have the second node potential, the position and the broken line shape of the first power supply line 81 can effectively reduce the overlapping capacitance between the second node N2 and the first power supply line 81, and further reduce the parasitic capacitance of the second node N2.

[0356] In the example embodiment, in the at least one circuit unit, the orthographic projection of the first power supply line 81 on the substrate does not overlap the orthographic projection of the third connection electrode 53 on the substrate.

[0357] In the example embodiment, the fifth conductive layer of the at least one circuit unit can further include a second power supply line 82. The second power supply line 82 can have a shape of a straight line or a broken line with a main body portion extending along the second direction Y, and the second power supply line 82 is connected to the second power supply connection block 66-1 through the twenty-fourth via hole V24. Since the second power supply connection block 66-1 is connected to the second power supply connection line 66, the second power supply connection line 66 with the main body portion extending along the first direction X and the second power supply line 82 with the main body portion extending along the second direction Y are connected to each other, and the second power supply connection line 66 and the second power supply line 82 form a meshed communication structure for transmitting a second power supply signal on the display substrate. This not only effectively reduces the resistance of the second power supply line and the voltage drop of the second power supply signal, but also effectively improves the uniformity of the second power supply signal in the display substrate, effectively improves the display uniformity, and improves the display quality and display performance. In addition, by arranging the second power supply line in the display area, the second power supply line is arranged in a panel (VSS in Panel, SIP for short) structure, which can greatly reduce the width of the frame power supply lead, greatly reduce the left and right frame widths, improve the screen-to-body ratio, and be conducive to realizing a full-screen display.

[0358] In the example embodiment, the second power supply line 82 can be arranged in the circuit unit of the Nth unit column and the N+1th unit column, respectively. The second power supply line 82 in the Nth unit column and the second power supply line 82 in the N+1th unit column can be mirror-symmetrical relative to the column center line, and the second power supply lines 82 in the two unit columns can be an integrated structure connected to each other.

[0359] In the example embodiment, the second power supply line 82 can have a variable width structure, and the width of the second power supply line is the size of the first direction X.

[0360] In the exemplary embodiments, in at least one circuit unit, the orthogonal projection of the second power line 82 on the substrate does not overlap with the orthogonal projection of the first connection electrode 51 on the substrate, and / or the orthogonal projection of the second power line 82 on the substrate does not overlap with the orthogonal projection of the third gate electrode 33 on the substrate, and / or the orthogonal projection of the second power line 82 on the substrate does not overlap with the orthogonal projection of the plate connection strip 38 on the substrate, and / or the orthogonal projection of the second power line 82 on the substrate does not overlap with the orthogonal projection of the sixth connection electrode 56 on the substrate. Since the first connection electrode 51, the third gate electrode 33, the plate connection strip 38 and the sixth connection electrode 56 all have the first node potential, the overlap capacitance between the first node N1 and the second power line 82 can be effectively reduced by changing the width of the second power line, thereby reducing the parasitic capacitance of the first node N1.

[0361] In the exemplary embodiments, in at least one circuit unit, the orthogonal projection of the second power line 82 on the substrate at least partially overlaps with the orthogonal projection of the fourth plate 14 and the fifth plate 15 on the substrate, and the fifth plate 15 is arranged between the fourth plate 14 and the second power line 82 in the direction perpendicular to the substrate. In this way, the fifth plate 15 can effectively shield the overlap capacitance between the second power line 82 and the first node N1, further reducing the parasitic capacitance of the first node N1.

[0362] In the exemplary embodiments, in at least one circuit unit, the orthogonal projection of the second power line 82 on the substrate does not overlap with the orthogonal projection of the second connection electrode 52 on the substrate. Since the second connection electrode 52 has the second node potential, the overlap capacitance between the second node N2 and the second power line 82 can be effectively reduced by changing the width of the second power line, thereby reducing the parasitic capacitance of the second node N2.

[0363] In some possible embodiments, the anode formed later can shield the third transistor T3, i.e., the orthogonal projection of the anode on the substrate at least partially overlaps with the orthogonal projection of the third gate electrode on the substrate, which is not limited in the present disclosure.

[0364] In the example embodiment, the fifth conductive layer of the at least one circuit unit can further include a first initial connection line 73. The first initial connection line 73 can be in a shape of a broken line with a main body extending along the second direction Y, and the first initial connection line 73 can be connected to the first initial connection block 71-1 through a twenty-fifth via hole V25. Since the first initial connection block 71-1 is connected to the first initial signal line 71, the first initial signal line 71 with the main body extending along the first direction X and the first initial connection line 73 with the main body extending along the second direction Y are connected to each other, and the first initial signal line 71 and the first initial connection line 73 form a meshed and connected structure for transmitting the first initial signal on the display substrate, which can effectively reduce the resistance of the first initial connection line, reduce the voltage drop of the first initial signal, effectively improve the uniformity of the first initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0365] In the example embodiment, the first initial connection line 73 can be arranged in the circuit unit of the Nth unit column.

[0366] In the example embodiment, in the at least one circuit unit, the orthographic projection of the first initial connection line 73 on the substrate does not overlap with the orthographic projection of the third gate electrode 33 on the substrate, and / or the orthographic projection of the first initial connection line 73 on the substrate does not overlap with the orthographic projection of the plate connection strip 38 on the substrate, and / or the orthographic projection of the first initial connection line 73 on the substrate does not overlap with the orthographic projection of the sixth connection electrode 56 on the substrate, and / or the orthographic projection of the first initial connection line 73 on the substrate does not overlap with the orthographic projection of the fourth plate 14 on the substrate. Since the third gate electrode 33, the plate connection strip 38, the sixth connection electrode 56, and the fourth plate 14 have the first node potential, the position and the broken line shape of the first initial connection line 73 can effectively reduce the overlapping capacitance between the first node N1 and the first initial connection line 73, and further reduce the parasitic capacitance of the first node N1.

[0367] In the example embodiment, in the at least one circuit unit, the orthographic projection of the first initial connection line 73 on the substrate does not overlap with the orthographic projection of the first plate 11 on the substrate, and / or the orthographic projection of the first initial connection line 73 on the substrate does not overlap with the orthographic projection of the third plate 13 on the substrate. Since the first plate 11 and the third plate 13 have the second node potential, the position and the broken line shape of the first initial connection line 73 can effectively reduce the overlapping capacitance between the second node N2 and the first initial connection line 73, and further reduce the parasitic capacitance of the second node N2.

[0368] In the example embodiment, in the at least one circuit unit, the orthographic projection of the first initial connection line 73 on the substrate does not overlap with the orthographic projection of the third connection electrode 53 on the substrate.

[0369] In the example embodiment, the fifth conductive layer of the at least one circuit unit can further include a second initial connection line 74. The second initial connection line 74 can have a shape of a straight line or a broken line with a main body portion extending along the second direction Y, and the second initial connection line 74 is connected to the second initial connection block 72-1 through a twenty-sixth via hole V26. Since the second initial connection block 72-1 is connected to the second initial signal line 72, the second initial signal line 72 with the main body portion extending along the first direction X and the second initial connection line 74 with the main body portion extending along the second direction Y are connected to each other, and the second initial signal line 72 and the second initial connection line 74 form a meshed and connected structure for transmitting the second initial signal on the display substrate, which can effectively reduce the resistance of the second initial connection line, reduce the voltage drop of the second initial signal, effectively improve the uniformity of the second initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0370] In the example embodiment, the second initial connection line 74 can be arranged in the circuit unit of the (N+2)th unit column, and the position and shape of the second initial connection line 74 in the (N+2)th unit column can be substantially the same as the position and shape of the second power line 82 in the Nth unit column.

[0371] In the example embodiment, the second initial connection line 74 can have a variable width structure, and the width of the second initial connection line can be the size of the first direction X.

[0372] In the example embodiment, in the at least one circuit unit, the orthogonal projection of the second initial connection line 74 on the substrate does not overlap the orthogonal projection of the first connection electrode 51 on the substrate, and / or the orthogonal projection of the second initial connection line 74 on the substrate does not overlap the orthogonal projection of the third gate electrode 33 on the substrate, and / or the orthogonal projection of the second initial connection line 74 on the substrate does not overlap the orthogonal projection of the plate connection strip 38 on the substrate, and / or the orthogonal projection of the second initial connection line 74 on the substrate does not overlap the orthogonal projection of the sixth connection electrode 56 on the substrate. Since the first connection electrode 51, the third gate electrode 33, the plate connection strip 38, and the sixth connection electrode 56 all have the first node potential, the overlap capacitance between the first node N1 and the second initial connection line 74 can be effectively reduced by changing the width of the second power line, and the parasitic capacitance of the first node N1 can be reduced.

[0373] In the example embodiment, in at least one circuit unit, the orthogonal projection of the second initial connection line 74 on the substrate at least partially overlaps the orthogonal projection of the fourth plate 14 and the fifth plate 15 on the substrate, and the fifth plate 15 is arranged between the fourth plate 14 and the second initial connection line 74 in the direction perpendicular to the substrate. In this way, the fifth plate 15 can effectively shield the overlapping capacitance between the second initial connection line 74 and the first node N1, further reducing the parasitic capacitance of the first node N1.

[0374] In the example embodiment, in at least one circuit unit, the orthogonal projection of the second initial connection line 74 on the substrate does not overlap the orthogonal projection of the second connection electrode 52 on the substrate. Since the second connection electrode 52 has the second node potential, the overlapping capacitance between the second node N2 and the second initial connection line 74 can be effectively reduced by changing the width of the second power line, thereby reducing the parasitic capacitance of the second node N2.

[0375] In the example embodiment, the average width of the second power line 82 can be greater than the average width of the first power line 81, and the width can be the size of the first direction X. The present disclosure effectively reduces the resistance of the second power line 82 by arranging the second power line 82 with a wider wiring, not only reduces the voltage drop of the second power signal transmission, but also effectively improves the uniformity of the second power signal in the display substrate, effectively improves the display uniformity, and improves the display quality and display quality.

[0376] In the example embodiment, the average width of the first initial connection line 73 and the average width of the first power line 81 can be substantially the same, and the average width of the second initial connection line 74 and the average width of the second power line 82 can be substantially the same.

[0377] FIG. 17 is a schematic diagram of a mesh communication structure in an example embodiment of the present disclosure. As shown in FIG. 17, the shapes of the first power connection line 65, the second power connection line 66, the first initial signal line 71, and the second initial signal line 72 can be straight lines or broken lines with main parts extending along the first direction X, and can be arranged in the fourth conductive layer. The shapes of the first initial connection line 73, the second initial connection line 74, the first power line 81, and the second power line 82 can be straight lines or broken lines with main parts extending along the second direction Y, and can be arranged in the fifth conductive layer.

[0378] In the example embodiment, the first power connection line 65 can be arranged in each unit row, the first power line 81 can be arranged in part of the unit columns (such as the N+1 unit column and the N+2 unit column), and the first power line 81 is connected to the first power connection line 65 through a via. The first power connection line 65 and the first power line 81 form a mesh communication structure for transmitting the first power signal on the display substrate.

[0379] In the example embodiment, the second power connection lines 66 can be arranged in each unit row, the second power lines 82 can be arranged in part of the unit columns (such as the Nth unit column and the N+1th unit column), and the second power lines 82 are connected to the second power connection lines 66 through vias. The second power connection lines 66 and the second power lines 82 form a meshed communication structure for transmitting the second power signal on the display substrate.

[0380] In the example embodiment, the first initial signal lines 71 can be arranged in each unit row, the first initial connection lines 73 can be arranged in part of the unit columns (such as the Nth unit column), and the first initial connection lines 73 are connected to the first initial signal lines 71 through vias. The first initial signal lines 71 and the first initial connection lines 73 form a meshed communication structure for transmitting the first initial signal on the display substrate.

[0381] In the example embodiment, the second initial signal lines 72 can be arranged in each unit row, the second initial connection lines 74 can be arranged in part of the unit columns (such as the N+2th unit column), and the second initial connection lines 74 are connected to the second initial signal lines 72 through vias. The second initial signal lines 72 and the second initial connection lines 74 form a meshed communication structure for transmitting the second initial signal on the display substrate.

[0382] The subsequent preparation process can include forming a second planar layer, the second planar layer being provided with an anode via, the anode via exposing a surface of the anode connection electrode 84, and the anode via being configured to enable the subsequent formation of an anode to be connected to the anode connection electrode through the via.

[0383] So far, the driving structure layer of the present embodiment has been prepared on the substrate. In a plane parallel to the display substrate, the driving structure layer can include a plurality of circuit units, each of which can include a pixel driving circuit, and a first scan signal line, a second scan signal line, a third scan signal line, a fourth scan signal line, a first emission signal line, a second emission signal line, a first initial signal line, a second initial signal line, a first power line, and a data signal line connected to the pixel driving circuit.

[0384] In the plane perpendicular to the display substrate, the driving structure layer can include, sequentially arranged on the substrate, a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, a semiconductor layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fourth conductive layer, a fifth insulating layer, a first planar layer, a fifth conductive layer, and a second planar layer. The first conductive layer can include at least a first plate of a first capacitor and a third plate of a second capacitor, the second conductive layer can include at least a second plate of the first capacitor and a fourth plate of the second capacitor, the semiconductor layer can include at least a fifth plate, an active layer of a first transistor T1 to a seventh transistor T7, the third conductive layer can include at least a first light-emitting signal line, a second light-emitting signal line, and a gate electrode of a plurality of transistors, the fourth conductive layer can include at least a first scan signal line, a second scan signal line, a third scan signal line, a fourth scan signal line, a first power connection line, a second power connection line, a first initial signal line, and a second initial signal line, and the fifth conductive layer can include at least a first power line, a second power line, a data signal line, a first initial connection line, and a second initial connection line.

[0385] In an example embodiment, the substrate can be a flexible substrate, or can be a rigid substrate. The rigid substrate can include, but is not limited to, one or more of glass, quartz, and the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an example embodiment, the flexible substrate can include, stacked on a glass carrier plate, a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the like, and the materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), and the like, for improving the water and oxygen resistance of the substrate. The first and second inorganic material layers are also referred to as barrier layers, and the material of the semiconductor layer can be amorphous silicon (a-si).

[0386] In the exemplary embodiments, the first, second, third, fourth and fifth insulating layers can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer, multiple layers or a composite layer. The first, second, third, fourth and fifth conductive layers can be a metal material such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) or molybdenum (Mo), or an alloy material composed of metals such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single layer structure or a multiple layer composite structure such as Ti / Al / Ti. The first and second planar layers can be an organic material such as resin or polyimide.

[0387] In the exemplary embodiments, after the driving structure layer is prepared, a light emitting structure layer can be prepared on the driving structure layer, and an encapsulation structure layer can be prepared on the light emitting structure layer, which will not be described herein.

[0388] With the development of display technology, consumers have increasingly high requirements for the display effect and display quality of display products. In a display substrate using oxide transistors, the off-state current of the oxide transistor is low, and the leakage phenomenon is not easy to occur, the low-frequency field performs well, the process is relatively simple, and the cost is low, so it has attracted widespread attention. In a display substrate using all oxide transistors, there are problems such as display watermark (Mura) caused by thermal instability. Research has found that the temperature characteristics of the oxide driving transistor and the temperature characteristics of the light emitting device are the main causes of the display watermark and other problems. On the one hand, since the source electrode of the oxide driving transistor is at the third node N3, the threshold voltage is compensated at the third node N3 in the compensation stage, and as the display time increases, the temperature of the display substrate gradually increases, the threshold voltage of the driving transistor is negatively biased as the temperature increases, the on-current (Ion) increases, and after the threshold voltage compensation, there is an increase in current caused by the increase in on-current, and the light emitting brightness increases. On the other hand, as the temperature gradually increases, the voltage of the light emitting device decreases, causing the third node N3 to jump, and the first node N1 is coupled to jump, but the potential change amount AV N3 of the third node N3 is greater than the potential change amount AV N1 of the first node N1, causing the gate-source voltage Vgs (= V N1 -V N3 ) of the third transistor T3 (driving transistor) to increase, the output current of the pixel driving circuit to increase, and the light emitting brightness to increase. Since different positions on the display substrate have different temperatures, the brightness of different positions increases differently, the brightness of the display substrate is uneven, and display watermark appears.

[0389] This exemplary embodiment provides a display substrate that, by optimizing the structure of the pixel driving circuit and setting a third capacitor between the first node N1 and the third node N3, can effectively avoid displaying watermarks. Studies have shown that after setting the third capacitor, ΔV N1 / △V N3 Inversely proportional to the capacitance of the third capacitor, when the potential of the third node N3 changes, it can be transmitted to the first node N1 through the third capacitor, so that the potential of the first node N1 can change by the same amount, i.e., ΔV. N1 / △V N3 It is basically close to 1, which can effectively reduce the increase of the gate-source voltage Vgs of the third transistor T3, effectively reduce the change of the output current of the pixel driving circuit, effectively reduce the change of the light emission brightness, and effectively avoid displaying watermarks.

[0390] This disclosure effectively reduces the parasitic capacitance of the first node N1 and the second node N2 by setting multiple signal lines to avoid them as much as possible. This further reduces the increase in the gate-source voltage Vgs of the third transistor T3, further reduces the change in the output current of the pixel driving circuit, further reduces the change in the luminous brightness, and further avoids watermark display. Research shows that due to the voltage coupling jump during the light emission stage, the coupling path is that the third node N3 couples to the second node N2, and the second node N2 couples to the first node N1. Therefore, the first node N1, the second node N2, and the third node N3 have a significant impact on the gate-source voltage Vgs of the third transistor T3. Further research shows that reducing the parasitic capacitance of the first node N1 and the second node N2 can effectively reduce the increase in the gate-source voltage Vgs of the third transistor T3. Simulation experiments show that the parasitic capacitance of the first node N1 in the existing structure is 27.11f, while the parasitic capacitance of the first node N1 in this disclosure is 4.78f. Compared with the existing structure, the parasitic capacitance of the first node N1 in this disclosure can be reduced by about 80%. In the existing structure, the parasitic capacitance of the second node N2 is 16.5f, while the parasitic capacitance of the first node N1 in this disclosure is 9.12f. Compared with the existing structure, the parasitic capacitance of the second node N2 in this disclosure can be reduced by about 50%.

[0391] This disclosure provides a more compact arrangement of the pixel driving circuit while meeting design requirements. This effectively improves the layout space utilization, results in a more reasonable structural arrangement, and simplifies the signal line connection structure without complex overlap. This can effectively improve product yield and reduce production costs. By setting a first electrode plate and a third electrode plate in a first conductive layer, a second electrode plate and a fourth electrode plate in a second conductive layer, and a fifth electrode plate in a semiconductor layer, the first and second electrode plates form a first capacitor, the third and fourth electrode plates form a second capacitor, and the fourth and fifth electrode plates form a third capacitor.

[0392] The present disclosure improves the uniformity and symmetry of the pixel driving circuit by setting the pixel driving circuit mirror of part of the adjacent unit columns, which can not only realize the uniformity design of process and coupling capacitance, but also realize the uniformity design of current distribution, effectively improve the display stability and uniformity, and effectively improve the display effect and display quality.

[0393] The present disclosure sets the fifth active layer and the seventh active layer of part of the adjacent unit columns as an integrated structure connected to each other, and sets the first gate electrode, the second gate electrode and the fourth gate electrode of part of the adjacent unit columns as an integrated structure connected to each other, which can effectively reduce the horizontal wiring space, reduce the number of vias, reduce the occupied area of the pixel driving circuit, and is beneficial to realize high resolution, and can effectively increase the size of the capacitor plate and effectively increase the capacitance value of the capacitor, and maximize the stability of the pixel driving circuit.

[0394] The present disclosure sets the first power supply connection line and the first power supply line, and the first power supply connection line and the first power supply line form a mesh communication structure for transmitting the first power supply signal on the display substrate, which can not only effectively reduce the resistance of the first power supply line and reduce the voltage drop of the first power supply signal, but also effectively improve the uniformity of the first power supply signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0395] The present disclosure sets the second power supply connection line and the second power supply line, and the second power supply connection line and the second power supply line form a mesh communication structure for transmitting the second power supply signal on the display substrate, which can not only effectively reduce the resistance of the second power supply line and reduce the voltage drop of the second power supply signal, but also effectively improve the uniformity of the second power supply signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0396] The present disclosure sets the second power supply line in the display area to realize the second power supply line in the panel (VSS in Panel, SIP for short) structure, which can greatly reduce the width of the frame power supply lead, greatly reduce the left and right frame width, improve the screen ratio, and be beneficial to realize the full-screen display.

[0397] The present disclosure sets the first initial connection line and the second initial connection line, and the first initial signal line and the first initial connection line form a mesh communication structure for transmitting the first initial signal on the display substrate, and the second initial signal line and the second initial connection line form a mesh communication structure for transmitting the second initial signal on the display substrate, which can not only effectively reduce the resistance of the initial signal line and reduce the voltage drop of the initial signal, but also effectively improve the uniformity of the initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0398] The data signal line and the plurality of connection electrodes do not overlap, so that signal crosstalk caused by data voltage jump of the data signal line can be avoided, the influence of data voltage jump on the transistor can be avoided, the working stability of the pixel driving circuit is improved, and the display effect is improved.

[0399] The plurality of scanning signal lines are arranged in the first source-drain metal layer, so that the resistance of the scanning signal lines is effectively reduced, the voltage drop of the scanning signal is reduced, the compensation speed is improved, and the display quality is improved.

[0400] The preparation process of the display substrate is compatible with the existing preparation process, the process is simple to implement, the production efficiency is high, the production cost is low, and the yield is high.

[0401] FIG. 18 is a structural schematic diagram of another display substrate according to an example embodiment of the present disclosure. As shown in FIG. 18, the main structure of the display substrate according to the present embodiment can be basically the same as that of the display substrate according to the embodiment shown in FIG. 6, except that the third gate electrode 33 is connected to the fourth plate 14 through the plate connection strip 38.

[0402] In the example embodiment, the plate connection strip 38 can have a strip shape extending along the second direction Y, and can be arranged on one side of the third gate electrode 33 in the second direction Y. The first end of the plate connection strip 38 is connected to the third gate electrode 33, and the second end of the plate connection strip 38 extends away from the third gate electrode 33 and is connected to the fourth plate 14 through a via.

[0403] In the example embodiment, in at least one circuit unit, the third gate electrode 33 and the plate connection strip 38 can be arranged in the third conductive layer and form an integrated structure.

[0404] In the example embodiment, the fourth plate 14 can be connected to the second electrode of the first transistor T1 and the second electrode of the fourth transistor T4 through the plate connection strip 38, the third gate electrode 33 and the first connection electrode 51, i.e., the sixth connection electrode is not arranged in the present embodiment.

[0405] In the example embodiment, the preparation process of the display substrate according to the present embodiment can be basically the same as that of the display substrate according to the embodiment shown in FIG. 6, except that a via exposing the fourth plate is formed in the third insulating layer covering the semiconductor layer pattern through a patterning process, and the plate connection strip is connected to the fourth plate through the via in the formation of the third conductive layer pattern arranged on the third insulating layer.

[0406] FIG. 19 is a structural schematic diagram of another display substrate according to an example embodiment of the present disclosure. As shown in FIG. 19, the main structure of the display substrate of the present embodiment can be substantially the same as that of the present embodiment shown in FIG. 6, except that the third gate electrode 33 is connected to the fourth plate 14 through the plate connection strip 38, and the first scan signal line 61 is in the shape of a broken line.

[0407] In an example embodiment, the plate connection strip 38 can be in the shape of a strip extending along the second direction Y, and can be arranged on one side of the third gate electrode 33 in the second direction Y. The first end of the plate connection strip 38 is connected to the third gate electrode 33, and the second end of the plate connection strip 38 extends away from the third gate electrode 33 and is connected to the fourth plate 14 through a via hole.

[0408] In an example embodiment, the first scan signal line 61 can be in the shape of a broken line extending along the first direction X, and can be arranged continuously in one unit row. The orthographic projection of the first scan signal line 61 on the substrate at least partially overlaps the orthographic projection of the first gate electrode 31 on the substrate, and the first scan signal line 61 is connected to the first gate electrode in each circuit unit through a via hole.

[0409] In an example embodiment, in at least one circuit unit, the orthographic projection of the first scan signal line 61 on the substrate does not overlap the orthographic projection of the first connection electrode 51 on the substrate, and / or the orthographic projection of the first scan signal line 61 on the substrate does not overlap the orthographic projection of the third gate electrode 33 on the substrate, and / or the orthographic projection of the first scan signal line 61 on the substrate does not overlap the orthographic projection of the plate connection strip 38 on the substrate, which can reduce the overlap capacitance between the first node N1 and the first scan signal line 61, and further reduce the parasitic capacitance of the first node N1.

[0410] In an example embodiment, in at least one circuit unit, the orthographic projection of the first scan signal line 61 on the substrate does not overlap the orthographic projection of the second connection electrode 52 on the substrate, and the orthographic projection of the first scan signal line 61 on the substrate does not overlap the orthographic projection of the third connection electrode 53 on the substrate.

[0411] In the present embodiment, the first scan signal line 61 is arranged in the shape of a broken line, so that the fourth plate 14 is arranged between the first scan signal line 61 and the third plate 13. In this way, the fourth plate 14 can effectively shield the overlap capacitance between the first scan signal line 61 and the second node N2, and further reduce the parasitic capacitance of the second node N2.

[0412] FIG. 20 is a structural schematic diagram of another display substrate according to an example embodiment of the present disclosure. As shown in FIG. 20, the main structure of the display substrate of the present embodiment can be substantially the same as that of the present embodiment shown in FIG. 6, except that the plate connection strip 38 can be arranged in the fifth conductive layer (SD2).

[0413] In the example embodiment, the shape of the plate connecting strip 38 can be a "C" shape, the first end of the plate connecting strip 38 is connected with the first connecting electrode 51 through the via, and the second end of the plate connecting strip 38 is connected with the sixth connecting electrode 56 through the via. Since the first connecting electrode 51 is connected with the third gate electrode 33 and the second region of the first active layer (also the second region of the fourth active layer) respectively, and the sixth connecting electrode 56 is connected with the fourth plate 14, the first connecting electrode 51, the third gate electrode 33, the plate connecting strip 38, the sixth connecting electrode 56 and the fourth plate 14 have a first node potential.

[0414] In the example embodiment, the preparation process of the substrate of the present embodiment can be substantially the same as that shown in FIG. 6, except that: in the formed third conductive layer, no plate connecting strip is formed; in the formed fourth insulating layer, no fifteenth via is formed; in the formed fourth conductive layer, the sixth connecting electrode is only connected with the fourth plate through the via; in the formed fifth insulating layer and first planar layer, the twenty-seventh via and the twenty-eighth via are further included, the twenty-seventh via exposes the surface of the first connecting electrode, and the twenty-eighth via exposes the surface of the sixth connecting electrode; and in the formed fifth conductive layer, the plate connecting strip is further included, the first end of the plate connecting strip is connected with the first connecting electrode through the twenty-seventh via, and the second end of the plate connecting strip is connected with the sixth connecting electrode through the twenty-eighth via.

[0415] In the example embodiment, by arranging the plate connecting strip in the fifth conductive layer, and arranging a relatively thick first planar layer between the plate connecting strip and the first scan signal line, the plate connecting strip can be away from the first scan signal line, which can effectively reduce the overlapping capacitance between the first node N1 and the first scan signal line 61, and further reduce the parasitic capacitance of the first node N1.

[0416] The foregoing structures and preparation processes of the present disclosure are only exemplary descriptions, and in the example embodiment, the corresponding structures can be changed, and the patterning processes can be increased or reduced, which are not limited herein.

[0417] In the example embodiment, the display substrate of the present disclosure can be applied to a display device with a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED), or quantum dot light-emitting diode display (QDLED), etc., which are not limited herein.

[0418] The present disclosure further provides a preparation method of a display substrate to prepare the display substrate provided in the above embodiments. In the example embodiment, the display substrate includes a plurality of circuit units, and the preparation method includes:

[0419] The pixel driving circuit is formed in at least one circuit unit, and the pixel driving circuit at least includes a first capacitor, a second capacitor, a third capacitor, a first connection electrode with a first node potential, a second connection electrode with a second node potential, and a third connection electrode with a third node potential; the first capacitor at least includes a first plate and a second plate, a normal projection of the second plate on a display substrate plane at least partially overlaps a normal projection of the first plate on the display substrate plane, the second capacitor at least includes a third plate and a fourth plate, a normal projection of the fourth plate on the display substrate plane at least partially overlaps a normal projection of the third plate on the display substrate plane, and the third capacitor includes the fourth plate and a fifth plate, a normal projection of the fifth plate on the display substrate plane at least partially overlaps a normal projection of the fourth plate on the display substrate plane; the first plate and the third plate are connected with the second connection electrode, the second plate and the fifth plate are connected with the third connection electrode, and the fourth plate is connected with the first connection electrode.

[0420] The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like, and the embodiments of the present application are not limited thereto.

[0421] Although the embodiments disclosed in the present disclosure are as above, it should be noted that the above embodiments are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, and omissions can be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

1. A display substrate comprising a plurality of circuit units, at least one of the circuit units comprising a pixel driving circuit, the pixel driving circuit comprising at least a first capacitor, a second capacitor, a third capacitor, a first connection electrode having a first node potential, a second connection electrode having a second node potential, and a third connection electrode having a third node potential; the first capacitor comprising at least a first plate and a second plate, a projection of the second plate on a plane of the display substrate at least partially overlaps a projection of the first plate on the plane of the display substrate, the second capacitor comprising at least a third plate and a fourth plate, a projection of the fourth plate on the plane of the display substrate at least partially overlaps a projection of the third plate on the plane of the display substrate, the third capacitor comprising a fourth plate and a fifth plate, a projection of the fifth plate on the plane of the display substrate at least partially overlaps a projection of the fourth plate on the plane of the display substrate; in at least one of the circuit units, the first plate and the third plate are connected to the second connection electrode, the second plate and the fifth plate are connected to the third connection electrode, and the fourth plate is connected to the first connection electrode. 2.The display substrate of claim 1, wherein, The pixel driving circuit further comprises a first transistor as a first reset transistor, a third transistor as a driving transistor, and a fourth transistor as a data writing transistor, a first electrode of the first transistor is connected to a first initial signal line, and a first electrode of the fourth transistor is connected to a data signal line; in at least one of the circuit units, a first end of the first connection electrode is connected to a second electrode of the first transistor and a second electrode of the fourth transistor, a second end of the first connection electrode is connected to a gate electrode of the third transistor, and the gate electrode of the third transistor is connected to the fourth plate through a plate connection bar. 3.The display substrate of claim 2, wherein, In at least one of the circuit units, the gate electrode of the third transistor is connected to the fourth plate through a plate connection bar and a sixth connection electrode. 4.The display substrate of claim 2, wherein, The first transistor comprises at least a first active layer, the fourth transistor comprises at least a fourth active layer, the first active layer and the fourth active layer are an integrated structure connected to each other, the first end of the first connection electrode is connected to a second region of the first active layer and a second region of the fourth active layer through a via, and the data signal line is arranged on a side of the first connection electrode away from the gate electrode of the third transistor. In at least one of the circuit units, a first distance is provided between the first connection electrode and the data signal line, a second distance is provided between the first active layer or the fourth active layer and the data signal line, the first distance is greater than the second distance, the first distance is a minimum distance between an edge of the first connection electrode close to the data signal line and an edge of the data signal line close to the first connection electrode, and the second distance is a minimum distance between an edge of the first active layer or the fourth active layer close to the data signal line and an edge of the data signal line close to the first active layer or the fourth active layer. 5.The display substrate of claim 2, wherein, In at least one circuit unit, a projection of the first initial signal line on a display substrate plane does not overlap with a projection of the first connection electrode on the display substrate plane, and / or a projection of the first initial signal line on the display substrate plane does not overlap with a projection of the gate electrode of the third transistor on the display substrate plane, and / or a projection of the first initial signal line on the display substrate plane does not overlap with a projection of the plate connection strip on the display substrate plane. 6.The display substrate of claim 2, wherein, In at least one circuit unit, a projection of the first initial signal line on a display substrate plane at least partially overlaps with projections of the fourth plate and the fifth plate on the display substrate plane. In a direction perpendicular to the display substrate, the fifth plate is arranged between the fourth plate and the first initial signal line. 7.The display substrate of claim 2, wherein, The first transistor at least includes a first gate electrode connected with a first scan signal line; in at least one circuit unit, a projection of the first scan signal line on a display substrate plane does not overlap with a projection of the first connection electrode on the display substrate plane, and / or a projection of the first scan signal line on the display substrate plane does not overlap with a projection of the gate electrode of the third transistor on the display substrate plane, and / or a projection of the first scan signal line on the display substrate plane does not overlap with a projection of the fourth plate on the display substrate plane. 8.The display substrate of claim 2, wherein, The fourth transistor at least includes a fourth gate electrode connected with a fourth scan signal line; in at least one circuit unit, a projection of the fourth scan signal line on a display substrate plane does not overlap with a projection of the first connection electrode on the display substrate plane, and / or a projection of the fourth scan signal line on the display substrate plane does not overlap with a projection of the gate electrode of the third transistor on the display substrate plane, and / or a projection of the fourth scan signal line on the display substrate plane does not overlap with a projection of the plate connection strip on the display substrate plane, and / or a projection of the fourth scan signal line on the display substrate plane does not overlap with a projection of the fourth plate on the display substrate plane. 9.The display substrate of claim 2, wherein, The pixel driving circuit further includes a second transistor as a second reset transistor, a first electrode of the second transistor being connected with a reset signal line; in at least one circuit unit, a first end of the second connection electrode is connected with a second electrode of the second transistor, and a second end of the second connection electrode is connected with the third plate, the first plate and the third plate being an integrated structure connected with each other. 10.The display substrate of claim 9, wherein, The second transistor comprises at least a second gate electrode connected with a second scan signal line; in at least one circuit unit, a projection of the second scan signal line on a display substrate plane does not overlap with a projection of the second connection electrode on the display substrate plane, and / or a projection of the second scan signal line on the display substrate plane does not overlap with a projection of the first plate on the display substrate plane, and / or a projection of the second scan signal line on the display substrate plane does not overlap with a projection of the third plate on the display substrate plane. 11.The display substrate of claim 9, wherein, The second transistor comprises at least a second gate electrode connected with a second scan signal line; in at least one circuit unit, a projection of the second scan signal line on a display substrate plane does not overlap with a projection of the first connection electrode on the display substrate plane, and / or a projection of the second scan signal line on the display substrate plane does not overlap with a projection of a gate electrode of the third transistor on the display substrate plane, and / or a projection of the second scan signal line on the display substrate plane does not overlap with a projection of the plate connection strip on the display substrate plane, and / or a projection of the second scan signal line on the display substrate plane does not overlap with a projection of the fourth plate on the display substrate plane. 12.The display substrate of claim 9, wherein, In at least one circuit unit, a projection of the reset signal line on a display substrate plane does not overlap with a projection of the second connection electrode on the display substrate plane. 13.The display substrate of claim 2, wherein, The pixel driving circuit further comprises a fifth transistor as a first light-emitting control transistor and a sixth transistor as a second light-emitting control transistor, a first electrode of the fifth transistor is connected with a first power supply line, a second electrode of the fifth transistor is connected with a first electrode of the third transistor, a second electrode of the third transistor is connected with a first electrode of the sixth transistor; in at least one circuit unit, a first end of the third connection electrode is connected with the second electrode of the third transistor and the first electrode of the sixth transistor, a second end of the third connection electrode is connected with the second plate, and the fifth plate is connected with the first electrode of the sixth transistor. 14.The display substrate of claim 13, wherein, The sixth transistor comprises at least a sixth active layer; in at least one circuit unit, the fifth plate and the sixth active layer are an integrated structure connected with each other. 15.The display substrate according to any one of claims 1 to 14, wherein In at least one circuit unit, a projection of the second power supply line on a display substrate plane does not overlap with a projection of the first connection electrode on the display substrate plane, and / or a projection of the second power supply line on the display substrate plane does not overlap with a projection of the second connection electrode on the display substrate plane. 16.The display substrate of claim 15, wherein, The pixel driving circuit further comprises a first transistor as a first reset transistor, a third transistor as a driving transistor, and a fourth transistor as a data writing transistor, a first electrode of the first transistor is connected with a first initial signal line, a first electrode of the fourth transistor is connected with a data signal line; a first end of the first connecting electrode is connected with a second electrode of the first transistor and a second electrode of the fourth transistor, a second end of the first connecting electrode is connected with a gate electrode of the third transistor, the gate electrode of the third transistor is connected with the fourth plate through a plate connecting strip; in at least one circuit unit, a normal projection of the second power supply line on a display substrate plane does not overlap with a normal projection of the gate electrode of the third transistor on the display substrate plane, and / or a normal projection of the second power supply line on the display substrate plane does not overlap with a normal projection of the plate connecting strip on the display substrate plane.

17. The display substrate according to any one of claims 1 to 14, wherein, In a direction perpendicular to the display substrate, the display substrate comprises at least a first conductive layer arranged on a base, a second conductive layer arranged on a side of the first conductive layer away from the base, a semiconductor layer arranged on a side of the second conductive layer away from the base, and a third conductive layer arranged on a side of the semiconductor layer away from the base, the first plate and the third plate are arranged in the first conductive layer, the second plate and the fourth plate are arranged in the second conductive layer, and the fifth plate is arranged in the semiconductor layer.

18. The display substrate according to any one of claims 1 to 14, wherein, In at least one circuit unit, a ratio of an area of a normal projection of the second plate on the first plate to an area of a normal projection of the fourth plate on the third plate is 0.95 to 1.

05.

19. A display device comprising the display substrate according to any one of claims 1 to 18.

20. A manufacturing method of a display substrate, the display substrate comprising a plurality of circuit units, the manufacturing method comprising: forming a pixel driving circuit in at least one circuit unit, the pixel driving circuit comprising at least a first capacitor, a second capacitor, a third capacitor, a first connecting electrode having a first node potential, a second connecting electrode having a second node potential, and a third connecting electrode having a third node potential; the first capacitor comprising at least a first plate and a second plate, a normal projection of the second plate on a display substrate plane at least partially overlaps with a normal projection of the first plate on the display substrate plane, the second capacitor comprising at least a third plate and a fourth plate, a normal projection of the fourth plate on the display substrate plane at least partially overlaps with a normal projection of the third plate on the display substrate plane, and the third capacitor comprising a fourth plate and a fifth plate, a normal projection of the fifth plate on the display substrate plane at least partially overlaps with a normal projection of the fourth plate on the display substrate plane; in at least one circuit unit, the first plate and the third plate are connected with the second connecting electrode, the second plate and the fifth plate are connected with the third connecting electrode, and the fourth plate is connected with the first connecting electrode.

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