Integrated flash and complementary field effect transistor semiconductor processing

Abstract

The present disclosure relates generally to an integrated circuit (IC) including a flash bit structure. In an example, the IC includes a flash bit structure (112) and a transistor structure (114). The flash bit structure (112) is on a semiconductor substrate (102). The flash bit structure (112) includes a word line structure (184a) and a first oxide layer (130c) disposed between the semiconductor substrate (102) and the word line structure (184a). The first oxide layer (130c) is not subjected to a nitridation process. The transistor structure (114) is on the semiconductor substrate (102). The transistor structure (114) includes a gate structure (210a) and a gate oxide layer (202) including a nitridation process. The gate oxide layer (202) is over the semiconductor substrate (102). The gate structure (210a) is over the gate oxide layer (202).

Description

Background Technology

[0001] Non-volatile memory (NVM) bit cells are electronic components configured to store information. Threshold voltages can be used to distinguish the logic level of a bit cell, such as a logic low level ("0") or a logic high level ("1"). The stored value is sometimes referred to as information (or a bit), which can be read by a sense amplifier circuit system. While integrating NVM arrays with additional circuitry (e.g., logic circuitry) into the same integrated circuit (IC) is an ideal goal for the semiconductor manufacturing industry, it is not without its challenges. Summary of the Invention

[0002] This article describes an example of an integrated circuit (IC). An IC comprises a flash memory bit structure and a transistor structure. The flash memory bit structure is on a semiconductor substrate. The flash memory bit structure includes a word line structure and a first oxide layer disposed between the semiconductor substrate and the word line structure. The first oxide layer has not undergone nitriding. The transistor structure is on the semiconductor substrate. The transistor structure includes a gate structure and a gate oxide layer that has undergone nitriding. The gate oxide layer is above the semiconductor substrate. The gate structure is above the gate oxide layer.

[0003] Another example is a method. A flash memory bit structure is formed on a semiconductor substrate. Forming the flash memory bit structure includes forming a floating gate structure above the semiconductor substrate; forming a first oxide layer on a first side of the floating gate structure; and forming a word line structure on the first oxide layer. The first oxide layer is located between the word line structure and the semiconductor substrate. After forming the word line structure, a gate oxide layer of a transistor structure is formed on the semiconductor substrate.

[0004] Another example is a method. A floating gate structure is formed over a semiconductor substrate. An oxide-nitride-oxide stack is formed over the floating gate structure. A control gate structure is formed over the oxide-nitride-oxide stack. A word line oxide layer is laterally formed on a first side of the floating gate structure over the semiconductor substrate. A word line structure is formed over the word line oxide layer. After forming the word line structure, a gate oxide layer is formed. A gate electrode is formed over the gate oxide layer.

[0005] The foregoing summary provides a fairly broad overview of the various features of the examples disclosed herein in order to better understand the following detailed description. Additional features and advantages of such examples will be described below. The described examples can be readily used as a basis for modifying or designing other examples within the scope of the appended claims. Attached Figure Description

[0006] To understand the above features in detail, please refer to the following detailed description in conjunction with the accompanying drawings.

[0007] Figure 1 , 2Figures 3 and 4 are cross-sectional views of the corresponding semiconductor devices based on some examples.

[0008] Figure 4 , 5 Figures 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24A, 24B, 24C, and 25 are corresponding cross-sectional views of semiconductor devices at intermediate manufacturing stages according to some examples.

[0009] The drawings and accompanying detailed description are provided to help understand the features of various examples and do not limit the scope of the appended claims. Examples illustrated in the drawings and described in the accompanying detailed description can be readily used as a basis for modifying or designing other examples within the scope of the appended claims. Where possible, the same reference numerals may be used to refer to common elements in the drawings. The drawings are drawn to clearly illustrate the relevant elements or features, and are not necessarily drawn to scale. Detailed Implementation

[0010] Various features are described below with reference to the accompanying drawings. Other examples may include any arrangement of the included or excluded aspects or features described. The illustrated examples may not have all the aspects or advantages shown. The aspects or advantages described in connection with a particular example are not necessarily limited to the example described and may be practiced in any other example, even if not so stated or explicitly described. In addition, the methods described herein may be described with a specific order of operations, but may be implemented with various other orders of operations (e.g., different serial or parallel executions involving various operations) according to other examples.

[0011] This disclosure generally, but not exclusively, relates to an integrated circuit (IC) comprising a flash memory bit structure. In some instances, the IC comprises a flash memory bit structure and a transistor structure on a semiconductor substrate. The flash memory bit structure comprises a word line structure and a first dielectric (e.g., oxide) layer disposed between the semiconductor substrate and the word line structure. In some instances where the first dielectric layer is an oxide, the first dielectric layer may not be nitrided. The transistor structure comprises a gate structure and a gate dielectric (e.g., oxide) layer. The gate dielectric layer is above the semiconductor substrate, and the gate structure is above the gate oxide layer. In some instances, the gate dielectric layer may be an oxide containing nitridation. The various examples described herein allow independent control of the dielectric layer of the word line structure (e.g., word line gate), for example, allowing the thickness of the dielectric to be independent of other dielectric layers and allowing avoidance of nitriding of the dielectric layer. Additionally, some examples allow modular processing of the flash memory bit structure as well as other complementary processing (e.g., complementary metal-oxide-semiconductor (CMOS) processing). Such modular processing can allow for easy design of process flows, such as for inserting and / or removing processes for the flash memory structure. Other benefits and advantages can also be achieved.

[0012] Various examples are then described. While specific examples may illustrate aspects of the features generally described above, examples may be incorporated into any combination of features generally described above (which are described in more detail in the examples below).

[0013] Figure 1 , 2 Figures 100, 300, and 400 are cross-sectional views of corresponding semiconductor devices 100, 300, and 400 according to some examples. Each of the semiconductor devices 100, 300, and 400 may be an IC or may be contained in an IC, for example, on or within a semiconductor die or chip.

[0014] Each of semiconductor devices 100, 300, and 400 includes a semiconductor substrate 102 having a flash memory region 104, a transition region 106, a p-channel FET (pFET) region 108, and an n-channel FET (nFET) region 110. The pFET region 108 and the nFET region 110 may together form a complementary FET (CFET) region (e.g., a CMOS region). The structures in the transition region 106 of semiconductor devices 100, 300, and 400 differ. For simplicity, only components common to semiconductor devices 100, 300, and 400 will be described.

[0015] Flash-mirrored bit-pair cells 112 are located in flash memory region 104. Flash-mirrored bit-pair cells 112 contain two flash bit cells that are mirror images of each other. Although various instances are described in the context of flash-mirrored bit-pair cells 112, other instances may envision different numbers of flash bits in the cell, such as one or more flash bits in the cell.

[0016] The pFET region 108 includes a first pFET 114 and a second pFET 116, and the nFET region 110 includes a first nFET 118 and a second nFET 120. In the illustrated example, the operating voltage rating of the first pFET 114 is lower than that of the second pFET 116, and similarly, the operating voltage rating of the first nFET 118 is lower than that of the second nFET 120. Additionally, the operating voltage rating of the second pFET 116 is lower than that of the first nFET 118. The operating voltage ratings of pFETs 114, 116 and nFETs 118, 120 are merely examples illustrating how different operating voltage ratings can be implemented. Any pFET and / or nFET in the pFET region 108 and nFET region 110 can each have any operating voltage rating.

[0017] Semiconductor substrate 102 may be or comprise a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or any other suitable substrate. Semiconductor substrate 102 may also comprise a support (or processing) substrate and an epitaxial layer epitaxially grown on the support substrate. In some examples, semiconductor substrate 102 is or comprises a silicon substrate (which may be separated from a bulk silicon wafer at the end of semiconductor processing). In other examples, semiconductor substrate 102 comprises a silicon substrate on which an epitaxial silicon layer is grown. Semiconductor substrate 102 is or comprises a semiconductor material in which and / or on the semiconductor material are formed devices such as flash memory mirror-image bit pair cells 112, pFETs 114, 116, and nFETs 118, 120, etc. In some examples, the semiconductor material is or comprises silicon (Si), silicon germanium (SiGe), gallium arsenide (GaAs), gallium nitride (GaN), etc., or combinations thereof. Semiconductor substrate 102 has an upper surface 122 in which and / or on the upper surface are formed means (e.g., bit pair cells 112, pFETs 114, 116, and nFETs 118, 120 mirrored from flash memory). In the illustrated example, the semiconductor material of semiconductor substrate 102 is p-doped with a p-type dopant. In some examples, semiconductor substrate 102 is p-doped with a concentration of 1 × 10⁻⁶. 14 cm -3 Up to 1×10 15 cm -3p-type dopant (e.g., boron (B)) within the range can be p-doped. Another dopant type and / or other doping concentrations may be implemented.

[0018] Isolation structures 140, 142, 144, 146, and 148 are located in the semiconductor substrate 102. Additionally, regarding... Figure 1 The semiconductor device 100 has an isolation structure 150 within the semiconductor substrate 102. Regarding... Figure 2 The semiconductor device 300 has an isolation structure 350 within the semiconductor substrate 102. Regarding... Figure 3 The semiconductor device 400, and the isolation structures 450 and 452 are in the semiconductor substrate 102.

[0019] In the illustrated examples, isolation structures 140, 142, 144, 146, 148, 150, 350, 450, and 452 are typically shallow trench isolation structures (STIs) and / or trench oxides extending from the upper surface 122 of the semiconductor substrate 102 into the semiconductor substrate 102. Various isolation structures may also include a protrusion that laterally spans the entire or a portion of the upper surface of the semiconductor substrate above the upper surface 122. For example, as shown, isolation structures 142, 144, 146, 148, 150, 350, and 452 laterally protrude wholly or partially above the upper surface 122 of the semiconductor substrate 102. The isolation structures may have a corresponding upper surface coplanar with and / or below the upper surface 122 of the semiconductor substrate 102. The isolation structures 140, 142, 144, 146, 148, 150, 350, 450, and 452 may include a surface-conformable liner layer (e.g., silicon oxide or silicon nitride) along a corresponding trench in the semiconductor substrate 102, and a filling isolation material (e.g., silicon oxide) above and on the liner layer. Other isolation structures, such as localized oxidation of semiconductor (LOCOS) structures, may be implemented.

[0020] exist Figure 1 In the semiconductor device 100, isolation structures 140 and 150 laterally define the flash memory region 104 and the active region of the upper surface 122 of the semiconductor substrate 102, and bit pair cells 112 mirrored by the flash memory are formed on the active region. Figure 2 In the semiconductor device 300, isolation structures 140 and 350 laterally define the flash memory region 104 and the active region of the upper surface 122 of the semiconductor substrate 102, and bit pair cells 112 mirrored by the flash memory are formed on the active region. Figure 3 In the semiconductor device 400, isolation structures 140 and 450 laterally define the active region of the flash memory region 104 and the upper surface 122 of the semiconductor substrate 102, and the bit pair cells 112 mirrored by the flash memory are formed on the active region.

[0021] exist Figure 1 In the semiconductor device 100, the transition region 106 is defined by the lateral boundary of the isolation structure 150. In some instances, the isolation structure 150, and therefore the transition region 106, may laterally surround or enclose the flash memory region 104 (e.g., the active region of the semiconductor substrate 102, on which the bit pair cells 112 of the flash memory are formed). In this case, the isolation structure 140 may be part of the isolation structure 150.

[0022] exist Figure 2 In the semiconductor device 300, the transition region 106 is defined by the lateral boundary of the isolation structure 350. In some instances, the isolation structure 350, and therefore the transition region 106, may laterally surround or enclose the flash memory region 104 (e.g., the active region of the semiconductor substrate 102, on which the bit pair cells 112 of the flash memory are formed). In this case, the isolation structure 140 may be part of the isolation structure 350.

[0023] exist Figure 3 In the semiconductor device 400, a transition region 106 is defined by the lateral boundaries of isolation structures 450, 452, wherein a portion of the upper surface 122 of the semiconductor substrate 102 extends between the isolation structures 450, 452 in the transition region 106. In some instances, the isolation structure 450, and therefore the transition region 106, may laterally surround or enclose the flash memory region 104 (e.g., the active region of the semiconductor substrate 102, on which the bit pair cells 112 of the flash memory are formed). In this case, the isolation structure 140 may be a portion of the isolation structure 450. Additionally, the upper surface 122 of the semiconductor substrate 102 extending between the isolation structures 450, 452 may also laterally surround or enclose the flash memory region 104.

[0024] Isolation structure 144 and corresponding isolation structures 150, 350, and 452 laterally define pFET region 108. Isolation structures 142 and 144 laterally define active regions on the upper surface 122 of semiconductor substrate 102, on which a first pFET 114 is formed. Isolation structure 142 and corresponding isolation structures 150, 350, and 452 laterally define active regions on the upper surface 122 of semiconductor substrate 102, on which a second pFET 116 is formed. n-type doped wells 132a and 132b are formed in semiconductor substrate 102 within pFET region 108. n-type doped well 132a extends from the upper surface 122 of semiconductor substrate 102 to a certain depth within semiconductor substrate 102 and is laterally located between isolation structures 142 and 144. n-type doped well 132b extends from the upper surface 122 of the semiconductor substrate 102 to a certain depth into the semiconductor substrate 102, and is laterally located between the isolation structure 142 and the corresponding isolation structures 150, 350, and 452. The concentration of n-type dopant in the n-type doped wells 132a and 132b is greater than the concentration of p-type dopant in the p-type doped semiconductor substrate 102. In some examples, the n-type doped wells 132a and 132b use a concentration of 1 × 10⁻⁶. 15 cm -3 Up to 1×10 17 cm -3 Doping can be performed with n-type dopants within the range (e.g., phosphorus (P) or arsenic (As)). Another dopant type and / or other doping concentrations may be implemented.

[0025] Isolation structures 144 and 148 laterally define nFET region 110. Isolation structures 144 and 146 laterally define active regions on the upper surface 122 of semiconductor substrate 102, wherein a first nFET 118 is formed on said active region. Isolation structures 146 and 148 laterally define active regions on the upper surface 122 of semiconductor substrate 102, wherein a second nFET 120 is formed on said active region.

[0026] The flash memory mirror-image bit pair cell 112 includes a first flash memory bit structure and a second flash memory bit structure mirror-image of the first flash memory bit structure. The first flash memory bit structure includes a floating gate (FG) dielectric layer 130a above (e.g., on) the upper surface 122 of the semiconductor substrate 102. An FG electrode 134a is above the FG dielectric layer 130a. A control gate (CG) dielectric layer is above the FG electrode 134a. The CG dielectric layer includes a first dielectric layer 160a above the FG electrode 134a, a second dielectric layer 162a above the first dielectric layer 160a, and a third dielectric layer 164a above the second dielectric layer 162a. In other embodiments, the CG dielectric layer may be or include one or more dielectric layers. A CG electrode 166a is above the CG dielectric layer (e.g., above the third dielectric layer 164a). The first dielectric cap layer 168a is above the CG electrode 166a, and the second dielectric cap layer 170a is above the first dielectric cap layer 168a.

[0027] First CG dielectric spacers 172a and 172b are located on or along the opposite sidewalls of the CG electrode 166a and above the FG electrode 134a. The first CG dielectric spacers 172a and 172b are further located on or along the opposite corresponding sidewalls of the CG dielectric layers (e.g., dielectric layers 160a, 162a, 164a) and dielectric cap layers 168a and 170a. Second CG dielectric spacers 174a and 174b are located on or along the corresponding sidewalls of the respective first CG dielectric spacers 172a and 172b. A first CG dielectric spacer 172a is located between the second CG dielectric spacer 174a and the CG electrode 166a, and a first CG dielectric spacer 172b is located between the second CG dielectric spacer 174b and the CG electrode 166a.

[0028] A first word line gate (WLG) dielectric spacer 176a is on or along the respective sidewalls of CG dielectric spacers 172a, 174a and FG electrode 134a, and above FG dielectric layer 130a. A second WLG dielectric spacer 182a is on or along the sidewall of the first WLG dielectric spacer 176a, and above FG dielectric layer 130a. The first WLG dielectric spacer 176a is between (i) the second WLG dielectric spacer 182a and (ii) the CG dielectric spacers 172a, 174a and FG electrode 134a. WLG dielectric layer 130c extends laterally from FG dielectric layer 130a and is above the upper surface 122 of semiconductor substrate 102. WLG electrode 184a is above WLG dielectric layer 130c and is on or along the sidewall of the second WLG dielectric spacer 182a. The second WLG dielectric spacer 182a is located between the WLG electrode 184a and the first WLG dielectric spacer 176a. WLG dielectric spacers 176a, 182a and CG dielectric spacers 172a, 174a are located between the WLG electrode 184a and the CG electrode 166a. WLG dielectric spacers 176a, 182a are located between the WLG electrode 184a and the FG electrode 134a. The gate dielectric spacer 226e is located on or along the sidewall of the WLG electrode 184a opposite to the second WLG dielectric spacer 182a.

[0029] An n-type source / drain (NSD) region 228a extends from the upper surface 122 into the semiconductor substrate 102 at a certain depth. The NSD region 228a extends laterally from the WLG dielectric layer 130c opposite the FG electrode 134a. A lightly doped n-type drain (LDD) region 222a extends from the upper surface 122 into the semiconductor substrate 102 at a certain depth. The depth to which the n-type LDD 222a extends into the semiconductor substrate 102 is less than the depth to which the NSD region 228a extends into the semiconductor substrate 102. The n-type LDD 222a extends laterally from the NSD region 228a below the WLG dielectric layer 130c and the WLG electrode 184a.

[0030] The second flash memory bit structure includes an FG dielectric layer 130b above (e.g., on) the upper surface 122 of the semiconductor substrate 102. An FG electrode 134b is above the FG dielectric layer 130b. A CG dielectric layer is above the FG electrode 134b. The CG dielectric layer includes a first dielectric layer 160b above the FG electrode 134b, a second dielectric layer 162b above the first dielectric layer 160b, and a third dielectric layer 164b above the second dielectric layer 162b. In other embodiments, the CG dielectric layer may be or include one or more dielectric layers. A CG electrode 166b is above the CG dielectric layer (e.g., above the third dielectric layer 164b). A first dielectric cap layer 168b is above the CG electrode 166b, and a second dielectric cap layer 170b is above the first dielectric cap layer 168b.

[0031] First CG dielectric spacers 172c and 172d are on or along the opposite sidewalls of the CG electrode 166b and above the FG electrode 134b. The first CG dielectric spacers 172c and 172d are further on or along the opposite corresponding sidewalls of the CG dielectric layers (e.g., dielectric layers 160b, 162b, 164b) and dielectric cap layers 168b and 170b. Second CG dielectric spacers 174c and 174d are on or along the corresponding sidewalls of the respective first CG dielectric spacers 172c and 172d. The first CG dielectric spacer 172c is between the second CG dielectric spacer 174c and the CG electrode 166b, and the first CG dielectric spacer 172d is between the second CG dielectric spacer 174d and the CG electrode 166b.

[0032] The first WLG dielectric spacer 176b is on or along the respective sidewalls of the CG dielectric spacers 172c, 174c and the FG electrode 134b, and is above the FG dielectric layer 130b. The second WLG dielectric spacer 182b is on or along the sidewall of the first WLG dielectric spacer 176b, and is above the FG dielectric layer 130b. The first WLG dielectric spacer 176b is between (i) the second WLG dielectric spacer 182b and (ii) the CG dielectric spacers 172c, 174c and the FG electrode 134b. The WLG dielectric layer 130d extends laterally from the FG dielectric layer 130b and is above the upper surface 122 of the semiconductor substrate 102. The WLG electrode 184b is above the WLG dielectric layer 130d and is on or along the sidewall of the second WLG dielectric spacer 182b. The second WLG dielectric spacer 182b is located between the WLG electrode 184b and the first WLG dielectric spacer 176b. WLG dielectric spacers 176b, 182b and CG dielectric spacers 172c, 174c are located between the WLG electrode 184b and the CG electrode 166b. WLG dielectric spacers 176b, 182b are located between the WLG electrode 184b and the FG electrode 134b. The gate dielectric spacer 226f is located on or along the sidewall of the WLG electrode 184b on the side opposite to the second WLG dielectric spacer 182b.

[0033] NSD region 228b extends from the upper surface 122 into the semiconductor substrate 102 at a certain depth. NSD region 228b extends laterally from the WLG dielectric layer 130d opposite the FG electrode 134b. n-type cell LDD 222b extends from the upper surface 122 into the semiconductor substrate 102 at a certain depth. The depth to which the n-type cell LDD 222b extends into the semiconductor substrate 102 is less than the depth to which the NSD region 228b extends into the semiconductor substrate 102. The n-type cell LDD 222b extends laterally from the NSD region 228b below the WLG dielectric layer 130d and the WLG electrode 184b.

[0034] The first and second flash memory bit structures are contained within an isolation structure 180 located on the upper surface 122 of the semiconductor substrate 102. The isolation structure 180 is laterally positioned between the FG dielectric layers 130a and 130b. A shared NSD region 178 extends from the upper surface 122 into the semiconductor substrate 102 at a certain depth. The shared NSD region 178 is located below the isolation structure 180. A tunnel dielectric layer 182c is located on and along the sidewalls of the CG dielectric spacers 174b, 174d, 172b, and 172d, above the FG electrodes 134a and 134b, and above the isolation structure 180. A shared erase gate (EG) electrode 184c is located above the tunnel dielectric layer 182c. The protective dielectric layer 186 is located above the WLG electrodes 184a and 184b, the shared EG electrode 184c, and the second dielectric cap layers 170a and 170b.

[0035] FG electrodes 134a and 134b can be any material capable of trapping electrons. In some instances, FG electrodes 134a and 134b are or contain semiconductor materials, such as doped polycrystalline silicon. In instances where FG electrodes 134a and 134b contain doped semiconductor materials (e.g., polycrystalline silicon), FG electrodes 134a and 134b can be made of materials with a concentration of 1 × 10⁻⁶. 19 cm -3 Up to 1×10 21 cm -3 The n-type dopant within the range is used for doping. The CG electrodes 166a, 166b, WLG electrodes 184a, 184b, and shared EG electrode 184c can be or contain any conductive material, such as a doped semiconductor material, like doped polysilicon. In examples where the CG electrodes 166a, 166b, WLG electrodes 184a, 184b, and shared EG electrode 184c contain a doped semiconductor material (e.g., polysilicon), the CG electrodes 166a and 166b can be doped with an concentration of 1 × 10⁻⁶. 19 cm -3 Up to 1×10 21 cm -3 Doping is performed using n-type dopants within the specified range, and WLG electrodes 184a, 184b and the shared EG electrode 184c can be doped with concentrations of 5 × 10⁻⁶. 19 cm -3 Up to 5×10 21 cm -3 Doping can be performed with n-type dopants within the specified range. Alternatively, another dopant type and / or other doping concentrations can be implemented.

[0036] FG dielectric layers 130a, 130b, WLG dielectric layers 130c, 130d, and CG dielectric layers (e.g., including dielectric layers 160a, 160b, 162a, 162b, 164a, 164b) can be or contain any suitable dielectric material. In some instances, FG dielectric layers 130a, 130b and WLG dielectric layers 130c, 130d are oxides, such as silicon oxide. Additionally, in some instances, WLG dielectric layers 130c, 130d are oxides (e.g., silicon oxide) that have not undergone nitriding. As will be shown later, WLG dielectric layers 130c, 130d can be formed without undergoing nitriding (e.g., by oxidation and / or deposition), and WLG dielectric layers 130c, 130d can be masked and / or protected from any nitriding process during any nitriding process following the formation of WLG dielectric layers 130c, 130d. In some instances, the CG dielectric layers are all or comprise oxide-nitride-oxide stacks. For example, the first dielectric layers 160a and 160b are oxides, such as silicon oxide; the second dielectric layers 162a and 162b are nitrides, such as silicon nitride; and the third dielectric layers 164a and 164b are oxides, such as silicon oxide.

[0037] The first dielectric cap layers 168a and 168b, the second dielectric cap layers 170a and 170b, and the protective dielectric layer 186 may be or contain any suitable dielectric material. In some instances, the first dielectric cap layers 168a and 168b are or contain oxides, such as silicon oxide. In some instances, the second dielectric cap layers 170a and 170b are or contain nitrides, such as silicon nitride. In some instances, the protective dielectric layer 186 is or contains nitrides, such as silicon nitride.

[0038] The CG dielectric spacers 172a-172d, 174a-174d and the WLG dielectric spacers 176a, 176b, 182a, 182b can be any suitable dielectric material. In some instances, the first CG dielectric spacers 172a-172d and the WLG dielectric spacers 176a, 176b, 182a, 182b are or contain oxides, such as silicon oxide, and the second CG dielectric spacers 174a-174d are or contain nitrides, such as silicon nitride.

[0039] The isolation structure 180 and the tunnel dielectric layer 182c can be or contain any suitable dielectric material. In some instances, both the isolation structure 180 and the tunnel dielectric layer 182c are or contain oxides, such as silicon oxide. For example, the isolation structure 180 can be or contain a LOCOS structure, which is an oxide semiconductor material (e.g., silicon) of the semiconductor substrate 102. In some instances, the tunnel dielectric layer 182c is an oxide (e.g., silicon oxide) that has not undergone nitriding. As will be shown later, the tunnel dielectric layer 182c can be formed without undergoing nitriding (e.g., by deposition), and the tunnel dielectric layer 182c can be masked and / or protected from any nitriding process during any nitriding process following the formation of the tunnel dielectric layer 182c. Similarly, in some instances, the second WLG dielectric spacers 182a, 182b are oxides (e.g., silicon oxide) that have not undergone nitriding. As will be shown later, the second WLG dielectric spacers 182a, 182b can be formed without undergoing nitriding, and the second WLG dielectric spacers 182a, 182b can be masked and / or protected from any nitriding process during any nitriding process after the formation of the tunnel dielectric layer 182c.

[0040] The n-type cells LDDs 222a and 222b can be doped with n-type dopant. The concentration of the n-type dopant in the n-type cells LDDs 222a and 222b is greater than the concentration of the p-type dopant in the p-type doped semiconductor substrate 102. In some examples, the n-type cells LDDs 222a and 222b are doped with a concentration of 5 × 10⁻⁶. 19 cm -3 Up to 5×10 21 cm -3 Doping can be performed with n-type dopants within the specified range. Alternatively, another dopant type and / or other doping concentrations can be implemented.

[0041] Shared NSD regions 178 and 228a, 228b can be doped with n-type dopant. The concentration of n-type dopant in shared NSD regions 178 and 228a, 228b is greater than the corresponding concentration of n-type dopant in n-type cells LDD 222a, 222b and the concentration of p-type dopant in p-type doped semiconductor substrate 102. In some examples, shared NSD region 178 is doped with a concentration of 5 × 10⁻⁶. 19 cm -3 Up to 5×10 21 cm -3 Doping is performed using n-type dopants within a certain range. In some examples, NSD regions 228a and 228b are doped with dopants at a concentration of 5 × 10⁻⁶. 19 cm -3 Up to 5×10 21 cm -3Doping can be performed with n-type dopants within the specified range. Alternatively, another dopant type and / or other doping concentrations can be implemented.

[0042] The first pFET 114 includes a gate electrode 210a and a p-type source / drain (PSD) region on a laterally opposite side of the gate electrode 210a in the semiconductor substrate 102. An embedded stress source 224a is also located on a laterally opposite side of the gate electrode 210a in the semiconductor substrate 102, and the PSD region may be at least partially located within the corresponding embedded stress source 224a. The embedded stress source 224a and the PSD region are located within an n-type doped well 132a in the semiconductor substrate 102. The PSD region extends to a certain depth from the corresponding upper surface of the embedded stress source 224a into the embedded stress source 224a and / or the semiconductor substrate 102. The upper surface of the embedded stress source 224a may be located at, above, or below the upper surface 122 of the semiconductor substrate. A gate dielectric layer 202 is located above the upper surface 122 of the semiconductor substrate 102, and the gate electrode 210a is located above the gate dielectric layer 202. The channel region is located below the gate dielectric layer 202 and the gate electrode 210a in the semiconductor substrate 102. The channel region lies between the PSD regions and between the embedded stress sources 224a. p-type LDDs 214a are located on the laterally opposite sides of the gate electrode 210a in the semiconductor substrate 102. Each p-type LDD 214a is located between the channel region and the corresponding PSD region. A first gate dielectric spacer 212a is located on a corresponding opposite sidewall of the gate electrode 210a, and a second gate dielectric spacer 226a is located on a corresponding sidewall of the first gate dielectric spacer 212a.

[0043] Similarly, the second pFET 116 includes a gate electrode 210b and a PSD region on the laterally opposite side of the gate electrode 210b in the semiconductor substrate 102. An embedded stress source 224b is also on the laterally opposite side of the gate electrode 210b in the semiconductor substrate 102, and the PSD region may be at least partially located in the corresponding embedded stress source 224b. The embedded stress source 224b and the PSD region are in an n-type doped well 132b in the semiconductor substrate 102. The PSD region extends to a certain depth from the corresponding upper surface of the embedded stress source 224b into the embedded stress source 224b and / or the semiconductor substrate 102. The upper surface of the embedded stress source 224b may be located at, above, or below the upper surface 122 of the semiconductor substrate. The gate dielectric layer 204 is above the upper surface 122 of the semiconductor substrate 102, and the gate electrode 210b is above the gate dielectric layer 204. The channel region is below the gate dielectric layer 204 and the gate electrode 210b in the semiconductor substrate 102. The channel region lies between the PSD regions and between the embedded stress sources 224b. p-type LDDs 214b are located on the laterally opposite sides of the gate electrode 210a in the semiconductor substrate 102. Each p-type LDD 214b is located between the channel region and the corresponding PSD region. A first gate dielectric spacer 212b is located on a corresponding opposite sidewall of the gate electrode 210b, and a second gate dielectric spacer 226b is located on a corresponding sidewall of the first gate dielectric spacer 212b.

[0044] The first nFET 118 includes a gate electrode 210c and an NSD region 230a on the laterally opposite side of the gate electrode 210c in the semiconductor substrate 102. The NSD region 230a extends from the upper surface 122 of the semiconductor substrate 102 to a certain depth within the semiconductor substrate 102. A gate dielectric layer 206 is above the upper surface 122 of the semiconductor substrate 102, and the gate electrode 210c is above the gate dielectric layer 206. A channel region is located in the semiconductor substrate 102 below the gate dielectric layer 206 and the gate electrode 210c. The channel region is located between the NSD regions 230a. An n-type LDD 216a is located on the laterally opposite side of the gate electrode 210c in the semiconductor substrate 102. Each n-type LDD 216a is located between the channel region and the corresponding NSD region 230a. The first gate dielectric spacer 212c is on the corresponding opposite sidewall of the gate electrode 210c, and the second gate dielectric spacer 226c is on the corresponding sidewall of the first gate dielectric spacer 212c.

[0045] Similarly, the second nFET 120 includes a gate electrode 210d and an NSD region 230b on the laterally opposite side of the gate electrode 210d in the semiconductor substrate 102. The NSD region 230b extends from the upper surface 122 of the semiconductor substrate 102 to a certain depth within the semiconductor substrate 102. A gate dielectric layer 208 is above the upper surface 122 of the semiconductor substrate 102, and the gate electrode 210d is above the gate dielectric layer 208. A channel region is located in the semiconductor substrate 102 below the gate dielectric layer 208 and the gate electrode 210d. The channel region is located between the NSD regions 230b. An n-type LDD 216b is located on the laterally opposite side of the gate electrode 210d in the semiconductor substrate 102. Each n-type LDD 216b is located between the channel region and the corresponding NSD region 230b. The first gate dielectric spacer 212d is on the corresponding opposite sidewall of the gate electrode 210d, and the second gate dielectric spacer 226d is on the corresponding sidewall of the first gate dielectric spacer 212d.

[0046] p-type LDDs 214a and 214b can be doped with p-type dopant. The concentration of p-type dopant in p-type LDDs 214a and 214b is greater than the concentration of n-type dopant in n-type doped wells 132a and 132b, and the concentration of p-type dopant in p-type doped semiconductor substrate 102, respectively. In some examples, p-type LDDs 214a and 214b are doped with a concentration of 5 × 10⁻⁶ p-type dopant. 19 cm -3 Up to 5×10 21 cm -3 The n-type LDDs 216a and 216b are doped with p-type dopants within a certain range. The concentration of the n-type dopant in the n-type LDDs 216a and 216b is greater than the concentration of the p-type dopant in the p-type doped semiconductor substrate 102. In some examples, the n-type LDDs 216a and 216b are doped with dopant at a concentration of 5 × 10⁻⁶. 19 cm -3 Up to 5×10 21 cm -3 Doping can be performed using n-type dopants within a certain range. Other doping concentrations can also be implemented.

[0047] The PSD region can be doped with p-type dopant. The concentration of p-type dopant in the PSD region is greater than that of p-type LDDs 214a and 214b and the concentration of n-type dopant in n-type doped wells 132a and 132b, respectively. In some examples, the PSD region uses dopant with a concentration of 5 × 10⁻⁶. 19 cm -3 Up to 5×10 21 cm -3The NSD regions 230a and 230b are doped with p-type dopant within a certain range. NSD regions 230a and 230b can be doped with n-type dopant. The concentration of n-type dopant in NSD regions 230a and 230b is greater than the corresponding concentration of n-type dopant in n-type LDDs 216a and 216b and the concentration of p-type dopant in the p-type doped semiconductor substrate 102. In some examples, NSD regions 230a and 230b are doped with a concentration of 5 × 10⁻⁶ p-type dopant. 19 cm -3 Up to 5×10 21 cm -3 Doping can be performed using n-type dopants within a certain range. Other doping concentrations can also be implemented.

[0048] Embedded stress sources 224a and 224b can be or contain any suitable semiconductor material that applies appropriate stress to the respective channel regions of the pFETs 114 and 116. In some instances, embedded stress sources 224a and 224b apply compressive stress to the respective channel regions. When the semiconductor material of the semiconductor substrate 102 is silicon, embedded stress sources 224a and 224b can be, for example, silicon germanium (SiGe). In other instances, embedded stress sources can be implemented in nFETs, and tensile stress can be applied to the channel regions of the nFETs. In this example, and when the semiconductor material of the semiconductor substrate 102 is silicon, the embedded stress source can be, for example, silicon carbide (SiC).

[0049] Gate dielectric layers 202, 204, 206, and 208 can be or contain any suitable dielectric material. In some instances, gate dielectric layers 202-208 contain oxides, such as silicon oxide. Additionally, in some instances, gate dielectric layers 202-208 contain oxide nitrides, such as silicon oxide nitride. For example, as described later, silicon oxide can be formed for gate dielectric layers 202-208 using an oxidation process, and then the silicon oxide can undergo a nitriding process to nitride the silicon oxide. The formation of gate dielectric layers 202-208 can occur after the formation of WLG dielectric layers 130c and 130d, tunnel dielectric layer 182c, and second WLG dielectric spacers 182a and 182b; however, WLG dielectric layers 130c and 130d, tunnel dielectric layer 182c, and second WLG dielectric spacers 182a and 182b are masked and / or protected from undergoing the nitriding treatment of gate dielectric layers 202-208. Gate dielectric layer 204 is thicker than gate dielectric layer 202. Gate dielectric layer 206 is thicker than gate dielectric layer 204. Gate dielectric layer 208 is thicker than gate dielectric layer 206. The corresponding thicknesses of gate dielectric layers 202-208 can at least partially achieve the operating voltage ratings as described above.

[0050] Gate electrodes 210a, 210b, 210c, and 210d can be or contain any suitable conductive material, such as a doped semiconductor material, like doped polysilicon. In examples where gate electrodes 210a and 210b contain a doped semiconductor material (e.g., polysilicon), gate electrodes 210a and 210b can be made of a concentration of 5 × 10⁻⁶. 19 cm -3 Up to 5×10 21 cm -3 The p-type dopant is used for doping within a certain range. In examples where the gate electrodes 210c and 210d contain doped semiconductor materials (e.g., polycrystalline silicon), the gate electrodes 210c and 210d can be doped with a concentration of 5 × 10⁻⁶. 19 cm -3 Up to 5×10 21 cm -3 Doping can be performed with n-type dopants within the specified range. Alternatively, another dopant type and / or other doping concentrations can be implemented.

[0051] The first gate dielectric spacers 212a, 212b, 212c, 212d, the second gate dielectric spacers 226a, 226b, 226c, 226d, and the gate dielectric spacers 226e, 226f can be or contain any suitable dielectric material. For example, the gate dielectric spacers 212a-212d, 226a-226f can be or contain silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or combinations thereof.

[0052] For details, please refer to the following: Figure 1 A protective dielectric 200a is positioned above the isolation structure 150 in the transition region 106. The protective dielectric 200a is a protrusion that projects vertically from the upper surface 218 of the isolation structure 150. The protective dielectric 200a has a sidewall facing the flash memory region 104, on which residual dielectric spacers 226g are formed. The protective dielectric 200a (and possibly residual dielectric spacers 226g) can be formed along the flash memory region 104 perpendicular to... Figure 1A fence extending laterally in the direction of the cross-section. As described in detail below, the protective dielectric 200a may be caused by misalignment of the photoresist during processing. Additionally, as shown, the upper surface 220 of the isolation structure 150 on the lateral side of the protective dielectric 200a near the flash memory region 104 is at a lower level than the upper surface 122 of the semiconductor substrate 102 in the flash memory region 104. The upper surface 218 of the isolation structure 150 is located below the protective dielectric 200a and extends laterally from the protective dielectric 200a away from the flash memory region 104. The upper surface 218 is located at a level higher than the upper surface 220. The upper surface 218 may be above, at, or below the level of the upper surface 122 of the semiconductor substrate 102. The residual dielectric spacer 226g may be or contain the same material as the second gate dielectric spacers 226a-226d.

[0053] For details, please refer to the following: Figure 2 The groove 352 is located in the isolation structure 350 within the transition region 106. The groove 352 has a sidewall facing the flash memory region 104, on which residual dielectric spacers 226h are formed. The groove 352 (and possibly the residual dielectric spacers 226h) can extend along the flash memory region 104 perpendicular to... Figure 2 The groove 352 extends laterally in the direction of its cross-section. As described in detail below, the groove 352 may be created due to misalignment of the photoresist during processing. Additionally, as shown, the upper surface 360 ​​of the isolation structure 350 on the lateral side of the groove 352 near the flash memory region 104 is at a lower level than the upper surface 122 of the semiconductor substrate 102 in the flash memory region 104. The upper surface 362 of the isolation structure 350 extends laterally from the groove 352 away from the flash memory region 104. The upper surface 362 is located at a level higher than the upper surface 360. The upper surface 362 may be above, at, or below the level of the upper surface 122 of the semiconductor substrate 102. The residual dielectric spacer 226h may be or contain the same material as the second gate dielectric spacers 226a-226d.

[0054] For details, please refer to the following: Figure 3 The upper surface 122 of the semiconductor substrate 102 lies between the isolation structures 450 and 452 in the transition region 106. As described in detail below, in cases of some misalignment of the photoresist during processing, the semiconductor substrate 102 can act as an etch stop layer, preventing the formation of grooves in the semiconductor substrate 102 within the transition region 106. In cases of some misalignment, protrusions can be formed above the semiconductor substrate 102 in the transition region 106, for example... Figure 1The protective dielectric 200a is shown. Additionally, as shown, the upper surface 460 of the isolation structure 450 is at a lower level than the upper surface 122 of the semiconductor substrate 102 in the flash memory region 104. The upper surface 462 of the isolation structure 452 is located at a level higher than the upper surface 460. The upper surface 462 can be above, at, or below the level of the upper surface 122 of the semiconductor substrate 102. As shown, the residual n-type cell LDD 222c extends from the upper surface 122 into the semiconductor substrate 102 at a certain depth, and is located between the isolation structures 450 and 452 in the transition region 106. The residual n-type cell LDD 222c extends laterally from the isolation structure 450 away from the isolation structure 450.

[0055] Figure 1 , 2 Various aspects of transition region 106 of 3 can be implemented and combined in a semiconductor device. For example, for a given flash memory region having a first transition region on a first lateral side and a second transition region on an opposing second lateral side, both the first and second transition regions can include a protective dielectric 200a (e.g., if the photoresist overlaps on the two opposing sides, as described in detail below). Additionally, in some instances, both the first and second transition regions can have a recess 352 (e.g., if the photoresist has gaps on both opposing sides, as described in detail below). Furthermore, in some instances, the first transition region can include a protective dielectric 200a, while the second transition region can have a recess (e.g., if the photoresist is laterally offset, resulting in overlap on one side and gaps on the other).

[0056] Common Reference Figure 1 , 2 Metal-semiconductor compound 240a is located on the upper surface 122 of the semiconductor substrate 102 and on the NSD region 228a. Metal-semiconductor compound 240b is located on the upper surface 122 of the semiconductor substrate 102 and on the NSD region 228b. Metal-semiconductor compound 240c is located on the embedded stress source 224a. Metal-semiconductor compound 240d is located on the embedded stress source 224b. Metal-semiconductor compound 240e is located on the upper surface 122 of the semiconductor substrate 102 and on the NSD region 230a. Metal-semiconductor compound 240f is located on the upper surface 122 of the semiconductor substrate 102 and on the NSD region 230b. Metal-semiconductor compounds 240g, 240h, 240i, and 240j are located on the gate electrodes 210a, 210b, 210c, and 210d, respectively. The metal-semiconductor compounds 240a-240j can be silicides (e.g., NiSix, TiSix, CoSix, PtSix), germanides, etc.

[0057] Dielectric layer 242 is located above semiconductor substrate 102 (e.g., above the mirrored bit pairs 112, pFETs 114, 116, and nFETs 118, 120 of flash memory), and contact vias 244a, 244b, 244c, 244d, 244e, and 244f pass through dielectric layer 242. Dielectric layer 242 may comprise one or more dielectric layers. For example, dielectric layer 242 may comprise a conformal first dielectric layer above semiconductor substrate 102 and a second dielectric layer above the first dielectric layer. The conformal first dielectric layer may be a stress source layer, an etch stop layer, etc., and may be or comprise silicon nitride, silicon oxynitride, etc., or combinations thereof. The second dielectric layer may be or comprise silicon oxide, silicon nitride, etc. Dielectric layer 242 may be or comprise a front metal dielectric (PMD), an interlayer dielectric (ILD), etc.

[0058] Contact holes 244a, 244b, 244c, 244d, 244e, and 244f extend through dielectric layer 242 and contact corresponding metal-semiconductor compounds 240a, 240b, 240c, 240d, 240e, and 240f. Contact holes 244a-244f may each contain one or more barrier and / or adhesion layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc., or combinations thereof) conformally located in the corresponding openings through dielectric layer 242, and filler metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc., or combinations thereof) above and / or on the one or more barrier and / or adhesion layers.

[0059] Figures 4 to 23 Figures 24A, 24B, 24C, and 25 are corresponding cross-sectional views of semiconductor devices at intermediate manufacturing stages according to some examples. The treatment described with respect to these figures is generally aimed at... Figure 1 The semiconductor device 100 is unfolded. The same process can be performed to manufacture it. Figure 2 and 3 The semiconductor devices 300 and 400 may have misaligned photoresist and / or different isolation structures, as described below.

[0060] refer to Figure 4A semiconductor substrate 102 is provided. The semiconductor substrate 102 can be as described above. A gate dielectric layer 130 is formed over (e.g., on) the upper surface 122 of the semiconductor substrate. The gate dielectric layer 130 can be any material described above with respect to the FG dielectric layers 130a, 130b and the WLG dielectric layers 130c, 130d. The gate dielectric layer 130 can be formed using an oxidation process (e.g., in-situ vapor generation (ISSG) oxidation) or another deposition process (e.g., chemical vapor deposition (CVD)). In some instances, such as when the gate dielectric layer 130 is an oxide (e.g., silicon oxide), nitriding of the gate dielectric layer 130 is not required to form the gate dielectric layer 130.

[0061] n-type doped wells 132a and 132b are formed in the semiconductor substrate 102 within the pFET region 108. The n-type doped wells 132a and 132b can be formed by masking regions of the semiconductor substrate 102 where n-type doped wells are not formed (e.g., using photolithography with photoresist) and implanting n-type dopant into the semiconductor substrate 102. The concentration of the n-type dopant in the n-type doped wells 132a and 132b can be as described above.

[0062] An FG electrode layer 134 is formed over the gate dielectric layer 130. The FG electrode layer 134 can be any material described above with respect to FG electrodes 134a and 134b. The FG electrode layer 134 can be formed using any suitable deposition process (e.g., CVD, plasma-enhanced CVD (PECVD), etc.). The FG electrode layer 134 can be doped (e.g., by in-situ doping during deposition and / or implantation after deposition) to the concentrations described above with respect to FG electrodes 134a and 134b.

[0063] Isolation structures 140-148 and 150 (or 350 or 450, 452, depending on the manufacturing process) Figure 1 , 2The semiconductor device (and 3) is formed in the semiconductor substrate 102. As illustrated, the isolation structure 140-150 can be formed by depositing a hard mask layer over the FG electrode layer 134. The hard mask layer can be any suitable material (e.g., silicon nitride, silicon oxynitride, etc.) and can be deposited using any suitable deposition process (e.g., CVD). The hard mask layer is patterned, for example by using photolithography and etching processes (e.g., reactive ion etching (RIE)). Using the patterned hard mask layer as a mask, trenches (or more generally, recesses) are etched in the semiconductor substrate 102, for example, through the FG electrode layer 134 and the gate dielectric layer 130 via RIE. The liner layer can then be conformally deposited in the trench and over the patterned hard mask layer, for example by PECVD or atomic layer deposition (ALD), or formed on the exposed surface of the trench (e.g., by an oxidation process). For example, a filler material can be deposited on top of the liner layer using high aspect ratio CVD (HAR-CVD), flowable CVD (FCVD), etc. Excess filler material, liner layer, and hard mask layer can be removed by planarization processes (e.g., chemical mechanical polishing (CMP)). In other examples, the isolation structure 140-150 can be a field oxide structure, such as a LOCOS structure, at the upper surface 122 of the semiconductor substrate 102, which can be formed using a LOCOS process.

[0064] refer to Figure 5 The FG electrode layer 134 in flash memory region 104 is thinned. The thinning of the FG electrode layer 134 can be performed using photolithography and etching processes. For example, pFET region 108 and nFET region 110 can be masked (e.g., using photolithography with the aid of photoresist), and with pFET region 108 and nFET region 110 masked, the FG electrode layer 134 can be thinned by an etching process, which can include wet etching and / or dry etching. The etching process can etch any exposed isolation structures, such as isolation structures 140, 150, as shown.

[0065] A CG dielectric layer is formed over the FG electrode layer 134 and the isolation structures 140-150. As shown, the CG dielectric layer comprises a first dielectric layer 160 over the FG electrode layer 134, a second dielectric layer 162 over the first dielectric layer 160, and a third dielectric layer 164 over the second dielectric layer 162. As shown, the CG dielectric layer is conformally formed over the FG electrode layer 134 and the isolation structures 140-150. For example, the CG dielectric layer is formed along the sidewall of the FG electrode layer 134, from which any isolation structure (e.g., isolation structures 140, 150) is recessed. The CG dielectric layer (e.g., dielectric layers 160, 162, 164) can be any material described above regarding the CG dielectric layer (e.g., comprising dielectric layers 160, 162, 164). The CG dielectric layer (e.g., dielectric layers 160, 162, 164) can be formed using any suitable deposition process (e.g., CVD, low-pressure CVD (LPCVD), PECVD, etc.).

[0066] A CG electrode layer 166 is formed over the CG dielectric layer (e.g., over the third dielectric layer 164). A first dielectric cap layer 168 is formed over the CG electrode layer 166, and a second dielectric cap layer 170 is formed over the first dielectric cap layer 168. A dielectric cap buffer layer 502 is formed over the second dielectric cap layer 170. The CG electrode layer 166 can be any material described above with respect to CG electrodes 166a, 166b. The first dielectric cap layer 168 can be any material described above with respect to first dielectric cap layers 168a, 168b. The second dielectric cap layer 170 can be any material described above with respect to second dielectric cap layers 170a, 170b. The dielectric cap buffer layer 502 can be any suitable dielectric material. In some instances, the dielectric cap buffer layer 502 is or comprises an oxide, such as silicon oxide. The CG electrode layer 166, the first dielectric cap layer 168, the second dielectric cap layer 170, and the dielectric cap buffer layer 502 can be formed using any suitable deposition process (e.g., CVD, LPCVD, PECVD, etc.).

[0067] refer to Figure 6The CG electrode layer 166 is patterned into CG electrodes 166a and 166b. Additionally, the dielectric cap buffer layer 502, the second dielectric cap layer 170, the first dielectric cap layer 168, and the CG dielectric layers (e.g., dielectric layers 160-164) are patterned. These layers can be patterned using photolithography and etching processes (e.g., RIE). The CG dielectric layers (e.g., dielectric layers 160, 162, 164) are patterned into corresponding CG dielectric layers (e.g., dielectric layers 160a, 162a, 164a and dielectric layers 160b, 162b, 164b), with the corresponding CG electrodes 166a and 166b above the CG dielectric layers. The first dielectric cap layer 168 is patterned as the first dielectric cap layers 168a and 168b above the corresponding CG electrodes 166a and 166b, and the second dielectric cap layer 170 is patterned as the second dielectric cap layers 170a and 170b above the corresponding first dielectric cap layers 168a and 168b. The dielectric cap buffer layer 502 is patterned as the dielectric cap buffer layers 502a and 502b above the corresponding second dielectric cap layers 170a and 170b.

[0068] A first CG dielectric spacer layer 172 is formed over the semiconductor substrate 102, and a second CG dielectric spacer layer 174 is formed over the first CG dielectric spacer layer 172. The first CG dielectric spacer layer 172 is conformally formed over the FG electrode layer 134, the isolation structures 140-150, and the dielectric cap buffer layers 502a and 502b, and is located on and along the sidewalls of the CG electrodes 166a and 166b, the CG dielectric layers (e.g., dielectric layers 160a-164a and 160b-164b), the first dielectric cap layer 168a and 168b, the second dielectric cap layer 170a and 170b, and the dielectric cap buffer layers 502a and 502b. The second CG dielectric spacer layer 174 is conformally formed over the first CG dielectric spacer layer 172. The first CG dielectric spacer layer 172 can be any material described above with respect to the first CG dielectric spacers 172a-172d. The second CG dielectric spacer layer 174 can be any material described above with respect to the second CG dielectric spacers 174a-174d. The first CG dielectric spacer layer 172 and the second CG dielectric spacer layer 174 can be formed using any suitable deposition process (e.g., CVD, LPCVD, PECVD, etc.).

[0069] refer to Figure 7 The first CG dielectric spacer layer 172 and the second CG dielectric spacer layer 174 are patterned into first CG dielectric spacers 172a-172d and second CG dielectric spacers 174a-174d, respectively. Anisotropic etching can be used to pattern the first CG dielectric spacer layer 172 and the second CG dielectric spacer layer 174.

[0070] Dummy spacers 702a, 702b, 702c, and 702d are formed on the sidewalls of the second CG dielectric spacers 174b, 174d, 174a, and 174c, respectively. The dummy spacers 702a-702d can be formed by depositing a layer of dummy spacers 702a-702d (e.g., by CVD, LPCVD, PECVD, etc.) and patterning the layer into dummy spacers 702a-702d (e.g., by anisotropic etching). The dummy spacers 702a-702d can be any material that can be selectively etched. In some instances, the dummy spacers 702a-702d are or contain oxides, such as silicon oxide.

[0071] refer to Figure 8 The dummy spacers 702c and 702d are removed. Photoresist 802 (e.g., by spin coating) is deposited over the semiconductor substrate 102 and patterned using photolithography to have openings exposing the dummy spacers 702c and 702d. Using the photoresist 802 as a mask, an etching process is performed to selectively etch and remove the dummy spacers 702c and 702d. The etching process may include dry etching and / or wet etching. After the etching process, the photoresist 802 is removed, for example, by ashing.

[0072] refer to Figure 9 The FG electrode layer 134 is patterned into FG electrodes 134a and 134b. Using, for example, dummy spacers 702a and 702b, dielectric cap buffer layers 502a and 502b, first CG dielectric spacers 172a-172d, and second CG dielectric spacers 174a-174d as masks, the FG electrode layer 134 is patterned by an anisotropic etching process (e.g., RIE). FG electrodes 134a are located below, among other things, the dummy spacers 702a and the CG dielectric layers (e.g., dielectric layers 160a-164a), and FG electrodes 134b are located below, among other things, the dummy spacers 702b and the CG dielectric layers (e.g., dielectric layers 160b-164b). The etching process can also etch isolation structures 140-150, which can reduce the corresponding upper surfaces of isolation structures 140-150.

[0073] refer to Figure 10First WLG dielectric spacers 176a, 176b, 176c, and 176d are formed. The first WLG dielectric spacers 176a and 176b are formed on the corresponding sidewalls of the first CG dielectric spacers 172a and 172b, the second CG dielectric spacers 174a and 174b, and the FG electrodes 134a and 134b. The first WLG dielectric spacer 176c is formed on the corresponding sidewall of the dummy spacer 702a and the FG electrode 134a. The first WLG dielectric spacer 176d is formed on the corresponding sidewall of the dummy spacer 702b and the FG electrode 134b. The first WLG dielectric spacers 176a-176d can be formed by: depositing a layer of the first WLG dielectric spacers 176a-176d (e.g., by CVD, LPCVD, PECVD, etc.) and patterning the layer into the first WLG dielectric spacers 176a-176d (e.g., by anisotropic etching). The first WLG dielectric spacers 176a-176d can be any material described above with respect to the first WLG dielectric spacers 176a, 176b.

[0074] refer to Figure 11 A shared NSD region 178 is formed. Photoresist 1102 (e.g., by spin coating) is deposited over the semiconductor substrate 102 and patterned using photolithography to have openings exposing the first WLG dielectric spacers 176c, 176d, dummy spacers 702a, 702b, and the gate dielectric layer 130 between the first WLG dielectric spacers 176c, 176d. Using the photoresist 1102 as a mask, implantation is performed to implant dopant into the semiconductor substrate 102 to form the shared NSD region 178. The concentration of the n-type dopant in the shared NSD region 178 can be as described above.

[0075] Then, the first WLG dielectric spacers 176c, 176d, dummy spacers 702a, 702b, and the gate dielectric layer 130 laterally located between the FG electrodes 134a, 134b are removed. Using photoresist 1102 as a mask, an etching process is performed to selectively etch and remove the first WLG dielectric spacers 176c, 176d, dummy spacers 702a, 702b, and the exposed gate dielectric layer 130. The etching process may include dry etching and / or wet etching. After removing the exposed gate dielectric layer 130, the upper surface 122 of the semiconductor substrate 102 is exposed. After the etching process, the photoresist 1102 is removed, for example, by ashing.

[0076] refer to Figure 12An isolation structure 180 is formed on the upper surface 122 laterally located between the FG electrodes 134a and 134b. The upper surface 122 of the oxidized semiconductor substrate 102, laterally located between the FG electrodes 134a and 134b, forms the isolation structure 180. For example, the oxidation can be thermal oxidation. The oxidation may depend on implantation, thereby forming a shared NSD region 178. For example, implantation can amorphize the semiconductor substrate 102, which serves as the site for implantation. The degree of amorphization can determine the rate at which the semiconductor substrate 102 is oxidized.

[0077] refer to Figure 13 A spacer / tunnel dielectric layer 182 is formed over the semiconductor substrate 102. The spacer / tunnel dielectric layer 182 is conformally formed over dielectric cap buffer layers 502a, 502b, first CG dielectric spacers 172a-172d, second CG dielectric spacers 174a-174d, first WLG dielectric spacers 176a, 176b, FG electrodes 134a, 134b, and isolation structure 180. The spacer / tunnel dielectric layer 182 can be any material described above with respect to the second WLG dielectric spacers 182a, 182b, and tunnel dielectric layer 182c. The spacer / tunnel dielectric layer 182 can be formed using any suitable deposition process (e.g., CVD, LPCVD, PECVD, etc.). In some instances, such as when the spacer / tunnel dielectric layer 182 is an oxide (e.g., silicon oxide), the spacer / tunnel dielectric layer 182 can be formed without performing a nitriding process.

[0078] refer to Figure 14 The spacer / tunnel dielectric layer 182 is patterned as second WLG dielectric spacers 182a, 182b. The spacer / tunnel dielectric layer 182 extending laterally from the corresponding first WLG dielectric spacers 176a, 176b is removed over the gate dielectric layer 130. Photoresist 1402 (e.g., by spin coating) is deposited over the semiconductor substrate 102 and patterned using photolithography to have openings exposing the spacer / tunnel dielectric layer 182. Using the photoresist 1402 as a mask, an anisotropic etching process (e.g., RIE) is performed to pattern the second WLG dielectric spacers 182a, 182b and remove the lateral portions of the spacer / tunnel dielectric layer 182. The patterning of the spacer / tunnel dielectric layer 182 further results in the tunnel dielectric layer 182c being patterned typically starting from the spacer / tunnel dielectric layer 182.

[0079] The etching process can further etch the exposed gate dielectric layer 130 by removing the exposed lateral portions of the spacer / tunnel dielectric layer 182. Further etching of the gate dielectric layer 130 produces WLG dielectric layers 130c, 130d, which can be thinner than the FG dielectric layers 130a, 130b. In some instances, the etching process can completely etch the exposed gate dielectric layer 130 by removing the exposed lateral portions of the spacer / tunnel dielectric layer 182. Subsequently, the WLG dielectric layers 130c, 130d can be formed (e.g., grown) on the exposed upper surface 122 of the substrate 102. In such embodiments, the WLG dielectric layers 130c, 130d can be thinned or formed independently, such that the thickness of the WLG dielectric layers 130c, 130d can generally be optimized without constraints on, for example, the gate dielectric layers 202-208 of pFETs 114, 116 and nFETs 118, 120. The etching process can also etch other components formed of the same material, such as, as shown, the first WLG dielectric spacers 176a, 176b, the first CG dielectric spacers 172a, 172b, and the dielectric cap buffer layers 502a, 502b. After the etching process, the photoresist 1402 is removed, for example, by ashing.

[0080] refer to Figure 15 A conductive layer 184 is formed over the semiconductor substrate 102. The conductive layer 184 is formed over the spacer / tunnel dielectric layer 182, the second WLG dielectric spacers 182a, 182b, the tunnel dielectric layer 182c, the WLG dielectric layers 130c, 130d, and the dielectric cap buffer layers 502a, 502b, etc. The conductive layer 184 can be any material described above with respect to the WLG electrodes 184a, 184b, and the shared EG electrode 184c. The conductive layer 184 can be formed using any suitable deposition process (e.g., CVD, PECVD, physical vapor deposition (PVD), etc.). The conductive layer 184 can be doped (e.g., by in-situ doping during deposition and / or implantation after deposition) to the concentration described above with respect to the WLG electrodes 184a, 184b, and the shared EG electrode 184c.

[0081] The conductive layer 184 is planarized to have a top surface coplanar with the respective top surfaces of the second dielectric cap layers 170a, 170b. Planarizing the conductive layer 184 in this manner patterns a portion of the conductive layer 184 as a shared EG electrode 184c located laterally between the CG electrodes 166a, 166b and laterally between the FG electrodes 134a, 134b above the isolation structure 180. Planarization can be performed via CMP. Planarization may also remove portions of the dielectric cap buffer layers 502a, 502b, and the tunnel dielectric layer 182c, the first CG dielectric spacers 172a-172d, and the second CG dielectric spacers 174a-174d located at a level above the top surfaces of the second dielectric cap layers 170a, 170b. Although not shown, recesses may occur in the conductive layer 184, for example, in the pFET region 108 and the nFET region 110.

[0082] A protective dielectric layer 186 is formed over the conductive layer 184, the shared EG electrode 184c, and the dielectric cap buffer layers 502a, 502b, etc. The protective dielectric layer 186 can be any material described above regarding the protective dielectric layer 186. The protective dielectric layer 186 can be formed using any suitable deposition process (e.g., CVD, PECVD, PVD, etc.).

[0083] refer to Figure 16 The conductive layer 184 is further patterned as WLG electrodes 184a and 184b above the corresponding WLG dielectric layers 130c and 130d. Photoresist 1602 (e.g., by spin coating) is deposited on the semiconductor substrate 102 and patterned using photolithography to have openings 1604 and 1606 exposing the protective dielectric layer 186. The opening 1604 through the photoresist 1602 has sidewalls in the flash memory region 104 and sidewalls 1612 in the transition region 106, thus extending from the flash memory region 104 into the transition region 106. The opening 1606 through the photoresist 1602 has sidewalls in the flash memory region 104 and sidewalls in another region (e.g., another transition region), thus extending from the flash memory region 104 into the other region. Using photoresist 1602 as a mask, an anisotropic etching process (e.g., RIE) is performed to pattern the protective dielectric layer 186 and conductive layer 184. The etching process can further laterally remove the spacer / tunnel dielectric layer 182 and WLG dielectric layers 130c, 130d within openings 1604, 1606, exposing corresponding portions of the upper surface 122 of the semiconductor substrate 102, as shown. After the etching process, the photoresist 1602 is removed, for example, by ashing.

[0084] refer to Figure 17 ,exist Figure 16Protective dielectrics 200a and 200b are formed at the locations where conductive layer 184 is removed. Protective dielectric 200a is formed on and along the sidewalls of WLG electrode 184a, protective dielectric layer 186, and WLG dielectric layer 130c, and is formed above the portion of the upper surface 122 of the semiconductor substrate 102 laterally located between WLG dielectric layer 130c and isolation structure 150. Protective dielectric 200a is further formed above isolation structure 150, and is formed on and along the sidewalls of protective dielectric layer 186, conductive layer 184, and spacer / tunnel dielectric layer 182 in transition region 106. A protective dielectric 200b is formed on and along the sidewalls of the WLG electrode 184b, the protective dielectric layer 186, and the WLG dielectric layer 130d, and is formed laterally above the portion of the upper surface 122 of the semiconductor substrate 102 located between the WLG dielectric layer 130d and the isolation structure 140. Protective dielectrics 200a and 200b can be any material described above with respect to protective dielectric 200a. Protective dielectrics 200a and 200b can be formed by using any suitable deposition process (e.g., CVD, PECVD, PVD, etc.) and by using planarization techniques (e.g., CMP) to remove excess protective dielectric material from above the protective dielectric layer 186.

[0085] exist Figure 17 Following this process, various layers, electrodes, and spacers have been formed to form the bit-pair cells 112 mirrored from the flash memory. As shown subsequently, some implants for forming LDDs and NSDs can then be formed. Additionally, as detailed later, no layers, electrodes, or spacers for any FETs are formed. The process shown allows the formation of the bit-pair cells 112 mirrored from the flash memory to be generally independent of the formation of FETs 114-120. This makes the process more modular, thereby making it easier to insert or remove flash memory processing from, for example, CMOS processing.

[0086] refer to Figure 18The protective dielectric layer 186 and conductive layer 184 in the transition region 106, pFET region 108, and nFET region 110 are removed. Photoresist 1802 (e.g., by spin coating) is deposited over the semiconductor substrate 102 and patterned using photolithography to expose the protective dielectric layer 186 in the transition region 106, pFET region 108, and nFET region 110. Protective dielectrics 200a and 200b allow for misalignment tolerances to the patterning of the photoresist 1802. Using the photoresist 1802 as a mask, an etching process is performed to selectively remove the protective dielectric layer 186 and conductive layer 184 in the transition region 106, pFET region 108, and nFET region 110. The etching process may include dry etching and / or wet etching. After the etching process, the photoresist 1802 is removed, for example, by ashing.

[0087] Gate dielectric layers 202, 204, 206, and 208 are formed. Typically, in some instances, the spacer / tunnel dielectric layer 182 and gate dielectric layer 130 on the active region where the FET with the highest operating voltage rating will be formed are removed, followed by oxidation. The spacer / tunnel dielectric layer 182 and gate dielectric layer 130 on the active region where the FET has the second highest operating voltage rating are removed are subsequently oxidized after the respective removal. The active region where the spacer / tunnel dielectric layer 182 and gate dielectric layer 130 are removed first experiences the most oxidation, therefore, the gate dielectric layer formed on the active region is the thickest. The active region where the spacer / tunnel dielectric layer 182 and gate dielectric layer 130 are removed last experiences the least oxidation, therefore, the gate dielectric layer formed on the active region is the thinnest. In such instances, the gate dielectric layers 202, 204, 206, and 208 are or contain oxides, such as silicon oxide.

[0088] As shown in the figure, refer to Figure 19 Photoresist 1902 (e.g., by spin coating) is deposited over semiconductor substrate 102 and patterned using photolithography to form openings 1904 exposing spacer / tunnel dielectric layer 182, where a second nFET 120 will be formed. Using photoresist 1902 as a mask, an etching process is performed to selectively remove the spacer / tunnel dielectric layer 182 and gate dielectric layer 130 from the active regions where the second nFET 120 is formed. The etching process may include dry etching and / or wet etching. After the etching process, photoresist 1902 is removed, for example, by ashing.

[0089] Next, although not shown, an oxidation process, such as ISSG oxidation, is performed to oxidize the upper surface 122 of the semiconductor substrate 102. Then, similar to the previous removal of the spacer / tunnel dielectric layer 182 and gate dielectric layer 130, the spacer / tunnel dielectric layer 182 and gate dielectric layer 130 are removed from the active region where the first nFET 118 will be formed. Then, another oxidation process is performed to oxidize the upper surface 122 of the semiconductor substrate 102. Then, the spacer / tunnel dielectric layer 182 and gate dielectric layer 130 are removed from the active region where the second pFET 116 will be formed. Then, another oxidation process is performed to oxidize the upper surface 122 of the semiconductor substrate 102. Then, the spacer / tunnel dielectric layer 182 and gate dielectric layer 130 are removed from the active region where the first pFET 114 will be formed. Then, another oxidation process is performed to oxidize the upper surface 122 of the semiconductor substrate 102.

[0090] like Figure 20 As shown, as a result of the oxidation process, and after an oxidation process following the removal of the spacer / tunnel dielectric layer 182 and the gate dielectric layer 130 from the active region where the first pFET 114 is formed, gate dielectric layers 202, 204, 206, and 208 are formed. In the example shown, gate dielectric layer 208 is formed through four oxidation processes; gate dielectric layer 206 is formed through three oxidation processes; gate dielectric layer 204 is formed through two oxidation processes; and gate dielectric layer 202 is formed through one oxidation process. Therefore, gate dielectric layer 208 is thicker than gate dielectric layer 206; gate dielectric layer 206 is thicker than gate dielectric layer 204; and gate dielectric layer 204 is thicker than gate dielectric layer 202.

[0091] Following the oxidation process, a nitriding process is performed on the gate dielectric layers 202, 204, 206, and 208. The nitriding process may include decoupled plasma nitriding (DPN), followed by post-nitriding annealing (PNA). The nitriding process drives nitrogen-containing material into the gate dielectric layers 202, 204, 206, and 208 (e.g., in contrast to residual nitrogen-containing material remaining on the exposed surfaces of the gate dielectric layers 202, 204, 206, and 208, which may occur during annealing in a nitrogen-containing environment). Therefore, in such examples, the gate dielectric layers 202, 204, 206, and 208 may be or contain silicon oxide nitride.

[0092] During the nitriding process, WLG dielectric layers 130c and 130d, tunnel dielectric layer 182c, and second WLG dielectric spacers 182a and 182b, as well as other dielectric layers in flash memory region 104, are protected and / or masked to prevent them from undergoing the nitriding process. This protection and / or masking prevents the nitriding process from reaching the WLG dielectric layers 130c and 130d, tunnel dielectric layer 182c, and second WLG dielectric spacers 182a and 182b, as well as other dielectric layers in flash memory region 104. Therefore, after the nitriding process, the WLG dielectric layers 130c and 130d, tunnel dielectric layer 182c, and second WLG dielectric spacers 182a and 182b do not undergo nitriding. Furthermore, the protective dielectrics 200a, 200b, the protective dielectric layer 186, and the WLG electrodes 184a, 184b also prevent nitrogen-containing materials from reaching the WLG dielectric layers 130c, 130d and the second WLG dielectric spacers 182a, 182b during the nitriding process. Additionally, the protective dielectric layer 186 and the shared EG electrode 184c also prevent nitrogen-containing materials from reaching the tunnel dielectric layer 182c during the nitriding process. This processing allows the WLG dielectric layers 130c, 130d, the tunnel dielectric layer 182c, and the second WLG dielectric spacers 182a, 182b to have characteristics independent of any constraints on the gate electrodes 210a-210d, which allows for further optimization of the WLG dielectric layers 130c, 130d, the tunnel dielectric layer 182c, and the second WLG dielectric spacers 182a, 182b for the bit-pair cells 112 mirrored in flash memory.

[0093] For example Figure 20 As shown, protective dielectric 200a (and protective dielectric 200b, although not shown) can have rounded corners formed in the transition region 106 during semiconductor processing, thereby forming the gate dielectric layers 202-208. Regarding Figure 17 After the conductive layer 184 is removed from the transition region 106, during the formation of the gate dielectric layers 202-208, the sidewalls of the protective dielectric 200a previously adjacent to the sidewalls of the conductive layer 184 may be exposed to processes such as etching, cleaning, and / or ashing. Such processes can round off the corners formed by the sidewalls and top surface of the protective dielectric 200a.

[0094] refer to Figure 21A gate electrode layer 210 is formed over the semiconductor substrate 102 (e.g., over gate dielectric layers 202-208, protective dielectrics 200a, 200b, and protective dielectric layer 186). The gate electrode layer 210 can be any material described above with respect to gate electrodes 210a-210d. The gate electrode layer 210 can be formed using any suitable deposition process (e.g., CVD, PECVD, PVD, etc.). In some instances, the gate electrode layer 210 is or comprises a semiconductor material, such as polycrystalline silicon. In some instances, the semiconductor material can be doped in situ during deposition and / or implanted after deposition via dopant. In some instances, the gate electrode layer 210 in the pFET region 108 is formed after deposition and / or implantation with a concentration of 1×10⁻⁶. 19 cm -3 Up to 1×10 21 cm -3 The polysilicon is doped with p-type dopant within a certain range, and the gate electrode layer 210 in the nFET region 110 is doped with a concentration of 5 × 10⁻⁶ after implantation. 19 cm -3 Up to 5×10 21 cm -3 The polysilicon is doped with n-type dopants within the range of [specific types]. The flash memory region 104 can be masked during any implantation of the gate electrode layer 210 (e.g., by photoresist). Other materials (e.g., conductive materials) can also be implemented as the gate electrode layer 210, which can be formed by any deposition process.

[0095] A protective dielectric layer 2102 is formed above the gate electrode layer 210. In some instances, the protective dielectric layer 2102 is silicon oxide deposited by CVD, but in other instances other dielectric materials and / or other deposition processes may be used.

[0096] The hard mask layer 2104 is conformally formed over the protective dielectric layer 2102. In some instances, the hard mask layer 2104 is or contains silicon nitride deposited by CVD, but in other instances other hard mask (e.g., dielectric) materials and / or other deposition processes may be used.

[0097] The underlayer 2106 is formed over the hard mask layer 2104. The underlayer 2106 may comprise one or more sublayers, such as a filler layer (e.g., to provide a planarized surface on which photoresist will be formed) and an anti-reflective coating (ARC) layer. The underlayer 2106 may be or contain organic and / or inorganic materials (e.g., in a three-layer patterning scheme). The underlayer 2106 can be formed using spin coating or similar methods.

[0098] Photoresist 2108 (e.g., by spin coating) is deposited on or over the underlying layer 2106 and patterned using photolithography. The photoresist 2108 is patterned to remain at the locations where gate electrodes 210a-210d will form. Using the patterned photoresist 2108 as a mask, an etching process (e.g., RIE) is performed to pattern the hard mask layer 2104, the protective dielectric layer 2102, and the gate electrode layer 210, as shown below. Figure 22 As shown. Gate electrode layer 210 is patterned as gate electrodes 210a-210d. Protective dielectric layer 2102 is patterned as protective dielectric layers 2102a, 2102b, 2102c, and 2102d. Hard mask layer 2104 is patterned as hard mask layers 2104a, 2104b, 2104c, and 2104d. Protective dielectric layer 2102a is above gate electrode 210a, and hard mask layer 2104a is above protective dielectric layer 2102a. Protective dielectric layer 2102b is above gate electrode 210b, and hard mask layer 2104b is above protective dielectric layer 2102b. Protective dielectric layer 2102c is above gate electrode 210c, and hard mask layer 2104c is above protective dielectric layer 2102c. A protective dielectric layer 2102d is located above the gate electrode 210d, and a hard mask layer 2104d is located above the protective dielectric layer 2102d. After an etching process, the photoresist 2108 and the underlayer 2106 are removed, for example, by selectively ashing and / or etching processes (e.g., wet etching) of the materials of those layers.

[0099] refer to Figure 23 The first gate dielectric spacers 212a, 212b, 212c, and 212d are formed along the sidewalls of the gate electrodes 210a, 210b, 210c, and 210d. The first gate dielectric spacers 212a, 212b, 212c, and 212d can be formed by conformally depositing a material layer of the first gate dielectric spacers 212a, 212b, 212c, and 212d over the semiconductor substrate 102 and anisotropically etching the layer so that the first gate dielectric spacers 212a, 212b, 212c, and 212d remain. The first gate dielectric spacers 212a, 212b, 212c, and 212d can be any material described above with respect to those components. The layers can be deposited by CVD, PECVD, ALD, etc.

[0100] p-type LDDs 214a and 214b and n-type LDDs 216a and 216b are formed in the semiconductor substrate 102 in the pFET region 108 and the nFET region 110, respectively. The p-type LDD 214a is located on the laterally opposite side of the gate electrode 210a in the semiconductor substrate 102, and the p-type LDD 214b is located on the laterally opposite side of the gate electrode 210b in the semiconductor substrate 102. The n-type LDD 216a is located on the laterally opposite side of the gate electrode 210c in the semiconductor substrate 102, and the n-type LDD 216b is located on the laterally opposite side of the gate electrode 210d in the semiconductor substrate 102. The p-type LDDs 214a and 214b can be formed by masking the flash memory region 104, the transition region 106, and the nFET region 110 (e.g., using photolithography with the aid of photoresist) and implanting p-type dopants into the semiconductor substrate 102 in the pFET region 108. The n-type LDDs 216a and 216b can be formed by masking the flash memory region 104, the transition region 106, and the pFET region 108 (e.g., using photolithography with the aid of photoresist) and implanting an n-type dopant into the semiconductor substrate 102 in the nFET region 110. The concentration of the dopant can be as described above.

[0101] refer to Figure 24A , 24B At 24C, the protective dielectrics 200a and 200b are at least partially removed. Figure 24A , 24B In each of 24C, photoresist 2402 (e.g., by spin coating) is deposited over semiconductor substrate 102 and patterned using photolithography to expose protective dielectrics 200a, 200b and protective dielectric layer 186 in flash memory regions 104. Although Figure 24A , 24B The subsequent description of 24C focuses on the treatment of protective dielectric 200a, but this description can also be applied to protective dielectric 200b.

[0102] exist Figure 24A (which corresponds to) Figure 1 In the process of photolithography, misalignment leads to overlap 2412 between the photoresist 2402 and the protective dielectric 200a. The lateral edges of the protective dielectric 200a are typically formed by… Figure 16 The photoresist 1602 in the conductive layer 184 is patterned using the photoresist 1602 and has sidewalls corresponding to the sidewalls 1612 of the photoresist 1602. These sidewalls of the conductive layer 184 define sidewalls protecting the dielectric 200a, such as... Figure 17 As shown, it then proceeds as follows Figure 20 As shown, it unfolds as shown. Therefore, the overlap 2412 can be considered as the photoresist 2402 in Figure 24 and... Figure 16The overlap of photoresist 1602 in the photoresist is 2412. This overlap may be due to misalignment of one or both of the photoresist 2402 and 1602.

[0103] Using photoresist 2402 as a mask, an etching process is performed to selectively remove exposed portions of the protective dielectric 200a. The etching process may include dry etching and / or wet etching. The etching process removes the exposed portions of the protective dielectric 200a adjacent to the WLG electrode 184a and laterally located above the upper surface 122 of the semiconductor substrate 102 between the WLG dielectric layer 130c and the isolation structure 150. The photoresist 2402 masks portions of the protective dielectric 200a (e.g., in overlap 2412) away from the WLG electrode 184a and above the isolation structure 150 in the transition region 106. Therefore, the masked portion of the protective dielectric 200a remains after the etching process. The remaining protective dielectric 200a may form a protrusion that protrudes vertically from the isolation structure 150 and in the transition region 106.

[0104] In some instances, such as when the protective dielectric 200a is or contains the same material as the isolation structure 150 (e.g., silicon oxide), the etching process can also etch exposed portions of the isolation structure 150 (e.g., after the exposed portions of the protective dielectric 200a have been removed). Therefore, as shown, the upper surface 220 of the isolation structure 150 exposed to the etching process can be located at a level below the upper surface 122 of the semiconductor substrate 102. Additionally, the isolation structure 150 can have a masked upper surface 218, which can be located below any remaining portion of the protective dielectric 200a and / or near the pFET region 108 and / or the nFET region 110, i.e., at a level above the upper surface 220 of the isolation structure 150. The upper surface 218 can be above, at, or below the upper surface 122 of the semiconductor substrate 102.

[0105] exist Figure 24B (which corresponds to) Figure 2 In this process, misalignment in the photolithography process results in a gap 2422 between the photoresist 2402 and the protective dielectric 200a. The lateral edges of the protective dielectric 200a are typically formed by the process described above. Figure 16 The sidewalls 1612 of the photoresist 1602 in Figure 24 are formed. Therefore, the gap 2422 can be considered as the photoresist 2402 in Figure 24 and the gap between the photoresist 2402 and the gap between the photoresist 1602 in Figure 24 ... and the gap between the photoresist 16 Figure 16 The gap 2422 between the photoresist 1602. This gap may be formed due to misalignment of one or both of the photoresist 2402, 1602.

[0106] Using photoresist 2402 as a mask, an etching process is performed to selectively remove exposed portions of the protective dielectric 200a. The etching process may include dry etching and / or wet etching. The etching process removes the exposed portions of the protective dielectric 200a adjacent to the WLG electrode 184a and laterally located above the upper surface 122 of the semiconductor substrate 102 between the WLG dielectric layer 130c and the isolation structure 350. The photoresist 2402 further exposes portions of the isolation structure 350 (e.g., in gap 2422) in the transition region 106 away from the WLG electrode 184a. Therefore, no portion of the protective dielectric 200a remains after the etching process.

[0107] In some instances, such as when the protective dielectric 200a is or contains the same material as the isolation structure 350 (e.g., silicon oxide), the etching process can also etch exposed portions of the isolation structure 350. Thus, a recess 352 corresponding to the gap 2422 is formed in the isolation structure 350. The protective dielectric 200a can mask portions of the isolation structure 150 near the flash memory region 104 early in the etching process, and the etching process can therefore form recesses 352 in the isolation structure 150 that are not masked by the photoresist 2402 or the protective dielectric 200a early in the etching process. Additionally, as shown, the exposed upper surface 360 ​​of the isolation structure 350 in the etching process (e.g., after the exposed portions of the protective dielectric 200a have been removed) can be located at a level below the upper surface 122 of the semiconductor substrate 102. Additionally, the isolation structure 350 may have a masked upper surface 362, and said upper surface may be located below the photoresist 2402 and / or close to the pFET region 108 and / or the nFET region 110, i.e., at a level higher than the upper surface 360 ​​of the isolation structure 350. The upper surface 362 may be above, at, or below the upper surface 122 of the semiconductor substrate 102.

[0108] exist Figure 24C (which corresponds to) Figure 3In the photolithography process, misalignment may lead to overlap or gaps between the photoresist 2402 and the protective dielectric 200a, as described above. Using the photoresist 2402 as a mask, an etching process is performed to selectively remove exposed portions of the protective dielectric 200a. The etching process may include dry etching and / or wet etching. The etching process removes exposed portions of the protective dielectric 200a that are adjacent to the WLG electrode 184a and laterally located above the upper surface 122 of the semiconductor substrate 102 between the WLG dielectric layer 130c and the isolation structure 450. The upper surface 122 of the semiconductor substrate 102, laterally located between the isolation structures 450, 452, can act as an etch stop layer, such that no grooves are formed in the semiconductor material of the semiconductor substrate 102 in the transition region 106, for example when gaps (such as...) Figure 24B When (in the middle) appears. When overlapping (such as Figure 24A When the event occurs, the masking portion of the protective dielectric 200a may remain above the upper surface 122 of the semiconductor substrate 102 in the transition region 106.

[0109] In some instances, such as when the protective dielectric 200a is or contains the same material as the isolation structures 450, 452 (e.g., silicon oxide), the etching process can also etch the exposed portions of the isolation structure 450. Therefore, as shown, the upper surface 460 of the isolation structure 450 exposed to the etching process (e.g., after the exposed portions of the protective dielectric 200a have been removed) can be located at a level below the upper surface 122 of the semiconductor substrate 102. Additionally, the isolation structure 452 can have an upper surface 462 masked by photoresist 2402, located at a level above the upper surface 460 of the isolation structure 450. The upper surface 462 can be above, at, or below the upper surface 122 of the semiconductor substrate 102.

[0110] In relation to Figure 24A , 24B In the case of at least partially removing the protective dielectrics 200a and 200b as described in 24C, n-type cell LDDs 222a and 222b are formed. n-type cell LDDs 222a and 222b can be formed by implanting n-type dopants into the semiconductor substrate 102 in the flash memory region 104 using photoresist 2402 as a mask. See details. Figure 24C Residual n-type cells LDD 222c are formed in the transition region 106 between isolation structures 450 and 452. The residual n-type cells LDD 222c are formed in the semiconductor substrate 102 between the isolation structures 450 and 452 exposed by photoresist 2402. The dopant concentration can be as described previously. After implantation, the photoresist 2402 is removed, for example, by ashing.

[0111] refer to Figure 25Embedded stress sources 224a and 224b are subsequently formed in the semiconductor substrate 102 within the pFET region 108. To form the embedded stress sources 224a and 224b, corresponding grooves are formed in the semiconductor substrate 102. To form the grooves, a conformal hard mask layer is formed over the semiconductor substrate 102 in the flash memory region 104, transition region 106, and nFET region 110. The conformal hard mask layer may be or contains silicon nitride, silicon oxynitride, or combinations thereof. The conformal hard mask layer can be formed by conformally depositing and patterning the conformal hard mask layer. The conformal hard mask layer can be deposited using CVD, PECVD, ALD, etc. The conformal hard mask layer can be patterned using photolithography and etching processes. Then, grooves are formed in the semiconductor substrate 102 within the pFET region 108. Grooves are etched in the semiconductor substrate 102 at the locations where the embedded stress sources will be formed. Any suitable etching process can be used to form the grooves, and the etching process can be a wet or dry etching process. The etching process can be anisotropic and selective (e.g., preferential etching) on ​​the crystal planes of the semiconductor substrate 102. Next, embedded stress sources 224a and 224b are formed in the trenches. Selective epitaxial growth processes can be used to form the embedded stress sources 224a and 224b. Metal-organic CVD (MOCVD), molecular beam epitaxy (MBE), LPCVD, or another epitaxial process can be used to form the embedded stress sources 224a and 224b. After forming the embedded stress sources 224a and 224b, the conformal hard mask layer is removed. The conformal hard mask layer can be removed by an etching process selectively etching the material of the conformal hard mask layer, which can be a wet or dry etching process. Removing the conformal hard mask layer can also remove hard mask layers 2104a, 2104b, 2104c, and 2104d. For example, the conformal hard mask layer and the first hard mask layers 2104a-2104d can be the same material removed by the same etching process.

[0112] Next, second gate dielectric spacers 226a, 226b, 226c, and 226d are formed along the sidewalls of the first gate dielectric spacers 212a, 212b, 212c, and 212d. Second gate dielectric spacers 226a-226d can be formed by conformally depositing the material layer of the second gate dielectric spacers 226a-226d over the semiconductor substrate 102 and anisotropically etching the layer to leave the second gate dielectric spacers 226a-226d. Alternatively, other dielectric spacers can be formed on and along other sidewalls, for example, gate dielectric spacers 226e and 226f can be formed on and along the WLG electrodes 184a and 184b, respectively. Additionally, as... Figure 25 and Figure 1 As shown, residual dielectric spacers 226g can be formed on and along the sidewall of the protective dielectric 200a. Figure 2 As shown, residual dielectric spacers 226h can be formed on and along the sidewall of the recess 352 in the isolation structure 350. The second gate dielectric spacers 226a-226d can be any material described above regarding those components. The layers can be deposited by CVD, PECVD, ALD, etc.

[0113] NSD regions 228a, 228b, 230a, and 230b are formed in the semiconductor substrate 102. The formation of NSD regions 228a, 228b, 230a, and 230b can be achieved by masking the transition region 106 and the pFET region 108 (e.g., using photolithography with photoresist) and implanting n-type dopant into the semiconductor substrate 102 in the flash memory region 104 and the nFET region 110. The concentration of the dopant can be as described previously.

[0114] The PSD region is formed in the semiconductor substrate 102. The PSD region can be formed by masking the flash memory region 104, the transition region 106, and the nFET region 110 (e.g., by photolithography using photoresist) and implanting p-type dopant into the semiconductor substrate 102 in the pFET region 108. The concentration of the dopant can be as described above.

[0115] Stress memory technology can be implemented, for example, in nFET region 110. A stress source dielectric layer is formed over the semiconductor substrate 102, gate electrodes 210c, 210d, and gate dielectric spacers 212c, 212d, 226c, 226d in nFET region 110. The stress source dielectric layer can be or contains silicon nitride or a combination thereof. The stress source dielectric layer can be formed by conformally depositing and patterning it. The stress source dielectric layer can be deposited using CVD, PECVD, ALD, etc. The stress source dielectric layer can be patterned using photolithography and etching processes. An annealing process is performed on the stress source dielectric layer in nFET region 110. The annealing process allows the lattice structure of the semiconductor substrate 102 to deform due to stress induced by the stress source dielectric layer. The annealing process may also activate dopants implanted in previous processes. After the annealing process, the stress source dielectric layer is removed. The stress source dielectric layer can be removed by a selective etching process that targets the material of the stress source dielectric layer. The etching process can be a wet etching process or a dry etching process.

[0116] refer to Figure 1Metal-semiconductor compounds 240a, 240b, 240c, 240d, 240e, 240f, 240g, 240h, 240i, and 240j are formed. These compounds can be formed by depositing metals (e.g., Ni, Ti, Co, Pt) on the semiconductor substrate 102, for example, using PVD, CVD, or the like. The metal reacts with semiconductor materials (e.g., the semiconductor material of the semiconductor substrate 102, the semiconductor material of the embedded stress sources 224a and 224b, and the semiconductor material of the gate electrodes 210a, 210b, 210c, and 210d (e.g., silicon, such as polycrystalline silicon)). An annealing process can be used to react the metal with the semiconductor material. Any unreacted metal can be removed, for example, by selective etching of the metal.

[0117] A dielectric layer 242 is formed over a semiconductor substrate 102, and contact holes 244a, 244b, 244c, 244d, 244e, and 244f are formed through the dielectric layer 242. The dielectric layer 242 may contain any sublayers and / or materials as described above. The dielectric layer 242 can be deposited using CVD, PECVD, ALD, etc. The dielectric layer 242 can be planarized, for example, by CMP.

[0118] To form contact holes 244a-244f, appropriate photolithography and etching processes can be used to penetrate the dielectric layer 242 until the metal-semiconductor compounds 240a-240f form corresponding openings. The metal for contact holes 244a-244f is deposited in the openings penetrating the dielectric layer 242. Appropriate deposition processes such as CVD or PVD can be used to deposit the metal. Any excess metal can be removed, for example, by CMP and / or by patterning using photolithography and etching processes.

[0119] Although various examples have been described in detail, it should be understood that various changes, substitutions and alterations may be made to them without departing from the scope defined by the appended claims.

Claims

1. An integrated circuit (IC) comprising: A flash memory bit structure on a semiconductor substrate, the flash memory bit structure including a word line structure and a first oxide layer disposed between the semiconductor substrate and the word line structure, the first oxide layer not undergoing nitriding treatment; as well as A transistor structure on the semiconductor substrate, the transistor structure including a gate structure and a gate oxide layer containing a nitrided treatment, the gate oxide layer being above the semiconductor substrate, and the gate structure being above the gate oxide layer.

2. The IC according to claim 1, wherein the flash memory bit structure further comprises: A floating grid structure, wherein the word line structure is located on the first side of the floating grid structure; An eraser gate structure is located on the second side of the floating gate structure opposite to the first side; as well as A second oxide layer is disposed between the erase gate structure and the floating gate structure, and the second oxide layer has not undergone nitriding treatment.

3. The IC according to claim 1, wherein the flash memory bit structure further comprises: Floating gate structure; A control gate structure is located above the floating gate structure; A second oxide layer is disposed between the floating gate structure and the word line structure, and the second oxide layer has not undergone nitriding treatment; as well as A nitride layer is disposed above the floating gate structure and between the second oxide layer and the control gate structure.

4. The IC of claim 1, wherein the word line structure comprises polysilicon.

5. The IC of claim 1, further comprising a transition region between the flash memory bit structure and the transistor structure, the transition region comprising: The isolation structure in the semiconductor substrate; and An oxide protrusion extending vertically from the upper surface of the isolation structure above the isolation structure.

6. The IC of claim 1, further comprising a transition region between the flash memory bit structure and the transistor structure, the transition region comprising an isolation structure in the semiconductor substrate, the isolation structure having a groove recessed from the upper surface of the isolation structure.

7. The IC of claim 1, further comprising a transition region between the flash memory bit structure and the transistor structure, the transition region comprising: A first isolation structure in the semiconductor substrate, the first isolation structure being close to the transistor structure; A second isolation structure in the semiconductor substrate, the second isolation structure being close to the flash memory bit structure; as well as The portion of the semiconductor substrate extending between the first isolation structure and the second isolation structure, the portion of the semiconductor substrate surrounding the flash memory bit structure.

8. The IC of claim 1, wherein the transistor structure comprises a p-channel transistor having a SiGe structure.

9. A method comprising: Forming a flash memory bit structure on a semiconductor substrate, wherein forming the flash memory bit structure includes: A floating gate structure is formed above the semiconductor substrate; A first oxide layer is formed on the first side of the floating gate structure; as well as A word line structure is formed on the first oxide layer, the first oxide layer being between the word line structure and the semiconductor substrate; as well as After the word line structure is formed, a gate oxide layer of a transistor structure is formed on the semiconductor substrate.

10. The method of claim 9, wherein forming the word line structure comprises: A polycrystalline silicon layer is deposited over the semiconductor substrate and on the first oxide layer; and The polysilicon layer is patterned into the word line structure.

11. The method of claim 9, further comprising nitriding the gate oxide layer.

12. The method of claim 11, wherein the nitriding process is blocked from reaching the first oxide layer at least in part by the word line structure formed on the first oxide layer.

13. The method of claim 11, wherein the first oxide layer does not undergo nitriding after the gate oxide layer is nitrided.

14. The method of claim 9, wherein forming the gate oxide layer comprises oxidizing the upper surface of the semiconductor substrate.

15. The method of claim 9, wherein forming the flash memory bit structure further comprises: A control gate structure is formed above the floating gate structure; A nitride layer is formed along the sidewall of the control gate structure; and A second oxide layer is formed along the sidewall of the nitride layer, the second oxide layer being disposed between the word line structure and the nitride layer, wherein the second oxide layer does not undergo nitriding after the gate oxide layer has been nitrided.

16. The method of claim 9, wherein forming the flash memory bit structure further comprises: A second oxide layer is formed on a second side of the floating gate structure opposite to the first side of the floating gate structure; the second oxide layer is formed on the sidewall of the floating gate structure; and An erase gate structure is formed on the second oxide layer.

17. The method of claim 16, wherein the second oxide layer does not undergo nitriding after the gate oxide layer is nitrided.

18. The method of claim 9, further comprising: An isolation structure is formed in the transition region between the flash memory bit structure and the transistor structure in the semiconductor substrate, wherein forming the word line structure includes patterning the word line structure, and the isolation structure is exposed by patterning the word line structure; A protective oxide is formed on the sidewall of the letter line structure, and the protective oxide also extends over the isolation structure exposed by patterning the letter line structure; A gate structure is formed over the gate oxide layer; as well as After the gate structure is formed, the protective oxide is etched, wherein the photoresist used in the etching has an opening partially defined by a photoresist sidewall, the gap being laterally located between the photoresist sidewall and the laterally distal protective oxide, forming the word line structure, the opening exposing the protective oxide and a portion of the isolation structure, the etching forming a groove in the isolation structure.

19. The method of claim 9, further comprising: An isolation structure is formed in the transition region between the flash memory bit structure and the transistor structure in the semiconductor substrate, wherein forming the word line structure includes patterning the word line structure, and the isolation structure is exposed by patterning the word line structure; A protective oxide is formed on the sidewall of the letter line structure, and the protective oxide also extends over the isolation structure exposed by patterning the letter line structure; A gate structure is formed over the gate oxide layer; as well as After the gate structure is formed, the protective oxide is etched, wherein the photoresist used in the etching has an opening partially defined by photoresist sidewalls above the protective oxide, and the etching forms a protruding oxide protruding from the isolation structure, the protruding oxide remaining from the protective oxide after the etching.

20. A method comprising: A floating gate structure is formed above the semiconductor substrate; An oxide-nitride-oxide stack is formed above the floating gate structure; A control gate structure is formed above the oxide-nitride-oxide stack; A word line oxide layer is laterally formed on the first side of the floating gate structure above the semiconductor substrate; A word line structure is formed above the word line oxide layer; After the word line structure is formed, a gate oxide layer is formed; as well as A gate electrode is formed above the gate oxide layer.

21. The method of claim 20, further comprising nitriding the gate oxide layer before forming the gate electrode over the gate oxide layer.

22. The method of claim 21, wherein the word line oxide layer is not subjected to nitriding after the gate oxide layer is nitrided.

23. The method of claim 20, further comprising: A tunnel oxide layer is formed on the second side of the floating grid structure opposite to the first side; as well as An erase gate structure is formed on the tunnel oxide layer, wherein the gate oxide layer is formed after the erase gate structure is formed.

24. The method of claim 23, further comprising nitriding the gate oxide layer before forming the gate electrode over the gate oxide layer.

25. The method of claim 24, wherein the tunnel oxide layer does not undergo nitriding after the gate oxide layer is nitrided.

26. The method of claim 20, wherein: The gate oxide layer is the first gate oxide layer among a plurality of gate oxide layers; and The residual gate oxide layer in the plurality of gate oxide layers is formed simultaneously with at least a portion of the first gate oxide layer or is formed after the formation of the first gate oxide layer.

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