Display device

Abstract

The display device includes a CMOS wafer and a light emitting diode disposed in a first region of the CMOS wafer. The light emitting diode can include a first electrode structure, an emissive layer disposed on the first electrode structure, and a second electrode structure disposed on the semiconductor junction structure. The first electrode structure includes a metal layer, a reflective layer disposed on the metal layer, and a first transparent conductive oxide layer disposed on the reflective layer.

Description

Technical Field

[0001] The present invention relates to a display device, and more specifically, to a display device comprising a CMOS wafer and a light-emitting diode. Background Technology

[0002] Electronic devices such as smartphones, digital cameras, laptops, navigation systems, and smart TVs that provide images to users include display devices for displaying images. Augmented reality devices, virtual reality devices, and video projection devices may include microdisplay devices. Such microdisplay devices may include a CMOS wafer and light-emitting diodes disposed on the CMOS wafer to display high-brightness images while being driven at low power. Summary of the Invention

[0003] Technical issues The present invention provides a display device with reduced light loss and reduced defects.

[0004] Technical solution A display device according to an embodiment of the present invention includes a complementary metal-oxide-semiconductor (CMOS) wafer and a plurality of light-emitting diodes disposed on the CMOS wafer and planarly disposed in a first region of the CMOS wafer. Each of the light-emitting diodes may include a first electrode structure, an emitting layer disposed on the first electrode structure, and a second electrode structure disposed on the emitting layer. The first electrode structure may include a metal layer, a reflective layer disposed on the metal layer, and a first transparent conductive oxide layer disposed on the reflective layer.

[0005] Beneficial effects Based on the above, a first electrode structure with reduced defects can be provided. The first electrode structure can be provided through a bonding process between a CMOS wafer and a semiconductor substrate.

[0006] Side reflective layers can reflect light generated by the light-emitting diode to improve emission efficiency. Lenses can focus the emitted light to reduce light loss.

[0007] The auxiliary electrode located inside the trench can be connected to the common electrode as a whole to reduce the voltage drop that occurs in the common electrode. Attached Figure Description

[0008] Figure 1 This is a perspective view of a display device according to an embodiment of the inventive concept.

[0009] Figure 2 This is an example shown Figure 1 The cross-sectional view of the display device shown.

[0010] Figure 3aThis is a plan view showing the state in which the common electrode is disposed in the display area and non-display area of ​​the display device according to an embodiment of the inventive concept.

[0011] Figure 3b It is a plan view showing the arrangement relationship between the common electrode, voltage transmission electrode and auxiliary electrode according to an embodiment of the inventive concept.

[0012] Figure 4a It is shown Figure 3a An enlarged plan view of a portion of the first region.

[0013] Figure 4b It is a sectional view taken along line I-I' in Figure 4A.

[0014] Figure 4c This is an enlarged cross-sectional view showing the contact area between the second contact electrode and the first electrode structure.

[0015] Figure 4d This is an enlarged cross-sectional view showing the contact area between the passivation layer and the lens.

[0016] Figures 4e to 4f It is shown Figure 4b A detailed cross-sectional view of the first electrode structure.

[0017] Figure 4g It is shown Figure 4b A detailed cross-sectional view of a light-emitting diode.

[0018] Figure 5a It is shown Figure 3a An enlarged plan view of a portion of the second region; Figure 5b It is along Figure 5a The sectional view taken from line II-II'.

[0019] Figure 6a It is shown Figure 3a An enlarged plan view of a portion of the third-1 region.

[0020] Figure 6b It is along Figure 6a The sectional view taken from line III-III'.

[0021] Figure 7a It is shown Figure 3a An enlarged plan view of a portion of the third-2 region.

[0022] Figure 7b It is along Figure 7a A sectional view taken from line IV-IV'.

[0023] Figure 8aIt is a cross-sectional view corresponding to the second region according to an embodiment of the inventive concept.

[0024] Figure 8b It is a cross-sectional view corresponding to the third-2 region according to an embodiment of the inventive concept.

[0025] Figures 9a to 9s This is a cross-sectional view illustrating the process of manufacturing a display device according to an embodiment of the inventive concept.

[0026] Figure 10a It is a plan view showing the arrangement relationship between the common electrode, voltage transmission electrode and auxiliary electrode according to an embodiment of the inventive concept.

[0027] Figure 10b This is an enlarged plan view showing a portion of the third-2 region according to an embodiment of the inventive concept.

[0028] Figure 10c and Figure 10d It is along Figure 10b A sectional view taken by line V-V'.

[0029] Figure 10e This is an enlarged plan view showing a portion of the third-2 region according to an embodiment of the inventive concept.

[0030] Figure 10f It is a plan view showing the arrangement relationship between the common electrode and the auxiliary electrode according to an embodiment of the inventive concept.

[0031] Figure 11a This is a cross-sectional view showing a display device according to an embodiment of the inventive concept.

[0032] Figure 11b This is a cross-sectional view showing a light-emitting diode according to an embodiment of the inventive concept.

[0033] Figure 11c This is a detailed cross-sectional view showing a first electrode structure according to an embodiment of the inventive concept. Detailed Implementation

[0034] In this specification, it will be understood that when a component (or region, layer, portion) is referred to as being “set on”, “connected to”, or “combined to” another component, the component (or region, layer, portion) may be directly set on / directly connected to / directly combined with the other component, or there may be an intermediary third component.

[0035] Throughout this specification, the same reference numerals consistently denote the same elements. Additionally, for clarity, the thickness, scale, and dimensions of components are exaggerated in the drawings. In this specification, the term "and / or" encompasses any and all combinations of one or more of the related elements.

[0036] It will be understood that although terms such as “first” and “second” are used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one component from others. For example, an element referred to as a first element in one embodiment may be referred to as a second element in another embodiment without departing from the scope of the appended claims. Unless otherwise indicated, singular terms may include plural forms.

[0037] Additionally, terms such as "below," "under," "above," and "over" are used to explain the relationship between the elements shown in the accompanying drawings. The terms can be relative concepts and are described based on the directions indicated in the drawings.

[0038] The meaning of "includes" or "contains" is to describe an attribute, fixed quantity, process, operation, element, component or combination thereof, but does not exclude other attributes, fixed quantities, processes, operations, elements, components or combinations thereof.

[0039] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept pertains. Furthermore, terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with that in the context of the relevant art, and shall not be interpreted as having overly idealized or formalistic meanings unless explicitly defined herein.

[0040] In the following description, embodiments of the inventive concept will be illustrated with reference to the accompanying drawings.

[0041] Figure 1 This is a perspective view of a display device DD according to an embodiment of the inventive concept.

[0042] Reference Figure 1According to an embodiment of the inventive concept, the display device DD may have a rectangular shape having a long side extending in a first direction DR1 and a short side extending in a second direction DR2 intersecting the first direction DR1. However, embodiments of the inventive concept are not limited thereto. For example, the display device DD may have various shapes such as a circular shape or a polygonal shape other than a rectangular shape. Hereinafter, the direction that intersects substantially perpendicularly to the plane defined by the first direction DR1 and the second direction DR2 is defined as the third direction DR3. In this specification, "when viewed on a plane" means the state of viewing on the third direction DR3.

[0043] The top surface of the display device DD can be defined as a display surface DS, and has a plane defined by a first direction DR1 and a second direction DR2. An image generated in the display device DD can be provided to the user through the display surface DS.

[0044] The display surface DS may include a display area DA and a non-display area NDA surrounding the display area DA. The display area DA may display an image, and the non-display area NDA may not display an image. The non-display area NDA may surround the display area DA, but is not limited thereto, and the non-display area NDA may be located on one side of the display area DA.

[0045] Multiple pixels (PX) can be arranged in the display area (DA). The pixels (PX) can be arranged in a matrix. Each pixel (PX) may include pixel circuitry and a light-emitting diode (LED). All pixels (PX) can produce light of the same color. In embodiments of the inventive concept, the pixels (PX) may include multiple groups that produce light of different colors.

[0046] Figure 2 This is an example shown Figure 1 The cross-sectional view of the display device DD shown.

[0047] Reference Figure 2 The display device DD may include a circuit element layer 10, a light-emitting element layer 20, and a lens layer 30. However, embodiments of the inventive concept are not limited thereto, and in embodiments of the inventive concept, the lens layer 30 may be omitted, and another functional layer may be added.

[0048] Circuit element layer 10 may include pixel circuitry. The pixel circuitry can control the operation of the light-emitting diodes in light-emitting element layer 20, as will be described later. The pixel circuitry may include at least one transistor. Circuit element layer 10 may include a CMOS wafer. The CMOS wafer may include complementary nMOSFETs (NMOS) and pMOSFETs (PMOS). Multiple pixel regions are regularly arranged on the CMOS wafer, and pixel circuitry is disposed in each pixel region.

[0049] The light-emitting element layer 20 may include light-emitting diodes (LEDs) electrically connected to the pixel circuitry. An LED is a compound semiconductor and is an electrically driven LED containing gallium (Ga), phosphorus (P), and arsenic (As) as the primary semiconductor materials. When a forward current is applied to the pn junction structure, electrons and holes recombine at the junction surface to produce light with a specific wavelength corresponding to the band gap.

[0050] Lens layer 30 can be disposed on light-emitting element layer 20 and may include a lens. The lens can be configured to correspond to a light-emitting diode. The lens focuses the light emitted from the light-emitting diode. The light focused by the lens can be transmitted through the light guide unit.

[0051] Figure 3a This is a plan view illustrating the state in which the common electrode CME is disposed in the display area DA and non-display area NDA of the display device DD according to an embodiment of the inventive concept. The display area DA and non-display area NDA of the display device DD can be similarly applied to... Figure 2 The circuit element layer 10 described herein (i.e., applied to the CMOS wafer). In the following text, the circuit element layer 10 will be described as CMOS wafer 10 and will be referred to by the same reference numerals.

[0052] The common electrode CME can at least cover the display area DA. The common electrode CME can transmit the electrical voltage applied from the outside to the entire display area DA. In the following text, the display area DA will be described as the first area DA and will be referred to by the same reference numerals.

[0053] The non-display area NDA can be divided into multiple areas. In this embodiment, the non-display area NDA may include a second area NDA1 and a third area NDA2.

[0054] The second region NDA1 can be disposed outside the first region DA, and can be the region in which the dummy light-emitting diode (LED) is disposed, as will be described later. In this embodiment, the second region NDA1 can surround the first region DA, but is not limited thereto. The dummy LED can have the same stacked structure as the LED in the first region DA, but can be unconnected to the common electrode CME, and therefore can be undriven (or can be unemitting light). The structural features of the dummy LED will be described later.

[0055] When a light-emitting diode (LED) is formed in a specific region using the same process, the outer region can have different process conditions compared to the inner region. For example, the thickness of the deposited metal layer can be small, or the etching rate can be different. Therefore, defective LEDs may be formed in the outer region. Considering this structure, the LEDs located on the outer side may not be used as effective LEDs, but rather as dummy LEDs. If the process conditions and process efficiency are consistent regardless of the region, the dummy LEDs can be omitted; therefore, the second region NDA1 can be omitted in the embodiments of the inventive concept.

[0056] The third region NDA2 may include an inner region NDA21 (hereinafter referred to as the third-1 region) and an outer region NDA22 (hereinafter referred to as the third-2 region) divided according to the arrangement of the common electrode CME. The third-1 region NDA21 may be set to be closer to the first region DA than the third-2 region NDA22.

[0057] A common electrode CME can be provided in the third-1 region NDA21, but a light-emitting diode (LED) may not be provided or may be dummy. In this embodiment, the third-1 region NDA21 may surround the second region NDA1, but is not limited to it. The extent of the third-1 region NDA21 may be determined by the edge of the common electrode CME.

[0058] The third-2 region NDA22 can be a region in which the common electrode CME is not located. In this embodiment, the third-2 region NDA22 can surround the third-1 region NDA21, but is not limited to this. Multiple driving circuits can be arranged on the CMOS wafer 10 (see...). Figure 2 The first region DA is located in the third-2 region NDA22. For example, a scan driver can be disposed in the left and right regions of the third-2 region NDA22, with the first region DA in between. A data driver can be disposed in a portion of the third-2 region NDA22 located below the first region DA. Furthermore, analog circuitry, such as power circuitry, can be disposed in a portion of the third-2 region NDA22. The scan driver, data driver, and analog circuitry described above can be embedded in a CMOS wafer. That is, the scan driver, data driver, and analog circuitry can include transistors formed in the same manner as pixel circuitry.

[0059] The pad area PDA, which has multiple pad electrodes (PDs), can be located on one side of the third-2 region NDA22. The pad area PDA can correspond to a portion of the third-2 region NDA22. A circuit board can be connected to the pad area PDA. Although in Figure 3aOnly four pad electrodes (PDs) are shown in the diagram, receiving the electrical voltage applied to the common electrode CME; however, more pad electrodes can be placed in the pad area PDA. The pad electrodes can receive data image signals or control signals from the outside to provide signals to the data driver.

[0060] Reference Figure 3a The voltage transfer electrode (VTE) can be disposed in the third-2 region NDA22. Four voltage transfer electrodes (VTEs) corresponding to the four pad electrodes (PDs) are shown. The voltage transfer electrodes (VTEs) can extend from the common electrode (CME) toward the pad region PDA. The voltage transfer electrodes (VTEs) can be formed with the common electrode (CME) using the same process, can have the same stacked structure, and can have an integral shape. The voltage transfer electrodes (VTEs) and the common electrode (CME) can be different parts of a single electrode formed using the same process.

[0061] Figure 3b This is a plan view showing the arrangement of the common electrode CME, voltage transfer electrode VTE, and auxiliary electrode SE according to an embodiment of the inventive concept.

[0062] The auxiliary electrode SE can be stacked with the common electrode CME and the voltage transfer electrode VTE. On the third-direction DR3, the auxiliary electrode SE can be positioned below the common electrode CME and the voltage transfer electrode VTE.

[0063] The auxiliary electrode SE may include a plurality of first auxiliary electrodes SE1 extending in a first direction DR1 and a plurality of second auxiliary electrodes SE2 extending in a second direction DR2. The first auxiliary electrodes SE1 may be arranged in the second direction DR2, and the second auxiliary electrodes SE2 may be arranged in the first direction DR1.

[0064] A cell region UA ​​can be set within the area defined by the two most adjacent first auxiliary electrodes SE1 and the two most adjacent second auxiliary electrodes SE2. However, the cell region UA ​​can be set in... Figure 3a Within the display area DA. Figure 3b The image shows a representative cell region UA. At least one light-emitting diode (LED) can be disposed in cell region UA. This will be described in detail later.

[0065] A portion of the auxiliary electrode SE can be stacked with the common electrode CME, and the portion stacked with the common electrode CME can be entirely connected to the common electrode CME to reduce the voltage drop occurring in the common electrode CME. Another portion of the auxiliary electrode SE can be stacked with the voltage transfer electrode VTE, and the portion stacked with the voltage transfer electrode VTE can be entirely connected to the voltage transfer electrode VTE to reduce the pad electrode PD (see...). Figure 3aThe resistance in the voltage transfer path between the auxiliary electrode (SE) and the common electrode (CME). The auxiliary electrode (SE) can be formed using the same process regardless of the region and can have a monolithic shape.

[0066] Figure 4a It is shown Figure 3a An enlarged plan view of a portion of the first region, A1. Figure 4b It is along Figure 4a A sectional view taken by line I-I'. Figure 4c This is an enlarged cross-sectional view showing the contact area B1 between the second contact electrode 135 and the first electrode structure ES1 or the first electrode component. Figure 4d This is an enlarged cross-sectional view showing the contact area B2 between the passivation layer 150 and the lens LS. Figure 4e and Figure 4f It is shown Figure 4b A detailed cross-sectional view of the first electrode structure ES1. Figure 4g It is shown Figure 4b A detailed cross-sectional view of a light-emitting diode (LED).

[0067] Figure 4a A first auxiliary electrode SE1 and a second auxiliary electrode SE2, which intersect each other, are shown. The first auxiliary electrode SE1 can be disposed in the first trench TC1, and the second auxiliary electrode SE2 can be disposed in the second trench TC2.

[0068] The first region DA may include multiple unit regions UA and boundary regions BA between the unit regions UA. Each unit region UA ​​may be an internal region defined by two first trenches TC1 in the first trench TC1 and two second trenches TC2 in the second trench TC2. The boundary region BA may be a region in which the first trenches TC1 and the second trenches TC2 are disposed.

[0069] In this embodiment, the boundary region BA can be defined as the region in which the first trench TC1 and the second trench TC2 are provided, but it is not limited thereto. The plurality of cell regions UA can be defined as... Figure 4a The defined cell region UA ​​is narrow. Here, the width of the boundary region BA can be further increased; for example, the boundary region BA can be defined to have a width greater than the width of each of the first auxiliary electrode SE1 and the second auxiliary electrode SE2.

[0070] Figure 4a The diagram shows a light-emitting diode (LED), a lens (LS), and a first opening (COP1) disposed in the cell region UA. Figure 4b common electrode CME and Figure 4bThe light-emitting diodes (LEDs) are connected to each other through the first opening COP1. In the plan view, each of the first openings COP1 can be positioned inside the corresponding lens LS in the lens LS. In the plane, each of the lenses LS can be positioned inside the corresponding light-emitting diode (LED).

[0071] Figure 4b It shows Figure 2 A detailed view. The display device DD may include a CMOS wafer 10, a light-emitting element layer 20, and a lens layer 30.

[0072] The CMOS wafer 10 includes a silicon substrate 101. A plurality of source / drain regions 111 are defined in the silicon substrate 101. Each of the source / drain regions 111 may be a region doped with a dopant. The source / drain regions 111 may become the source or drain of a transistor depending on the signal flow. The pair of source / drain regions 111 may define a transistor together with a gate 121 or gate electrode, which will be described later.

[0073] A shallow trench isolation (STI) region 115 can also be defined in the silicon substrate 101. The STI region 115 can prevent leakage current by isolating the transistors. The STI region 115 can be configured differently depending on the design of the pixel circuit.

[0074] Gate 121 is disposed on silicon substrate 101. Each of gates 121 may include metal. Each of gates 121 is configured to correspond to a pair of source / drain regions 111. A first insulating layer 123 is disposed on silicon substrate 101. The first insulating layer 123 may include an oxide layer such as a silicon oxide layer or an aluminum oxide layer, a silicon nitride layer, or a silicon oxynitride layer. Although the first insulating layer 123 is shown as a single layer, the first insulating layer 123 is not limited to a single layer.

[0075] The CMOS wafer 10 includes a first contact electrode 125. The first contact electrode 125 can be connected to the source / drain region 111 through a first contact hole CH1 defined in a first insulating layer 123. The top surface of the first contact electrode 125 can be defined as a coplanar plane (or a flat surface) with the top surface of the first insulating layer 123. The first contact electrode 125 can be formed using a damascene method. The first contact electrode 125 can include a metal such as copper or tungsten.

[0076] A second insulating layer 130 is disposed on the first insulating layer 123. A second contact hole CH2 exposing the first contact electrode 125 may be defined in the second insulating layer 130. The second insulating layer 130 may include an oxide layer, a silicon nitride layer, or a silicon oxynitride layer, such as a silicon oxide layer or an aluminum oxide layer. Although the second insulating layer 130 is shown as a single layer, the second insulating layer 130 is not limited to a single layer.

[0077] The second contact electrode 135 may be disposed in the second contact hole CH2. The top surface of the second contact electrode 135 may be defined as a coplanar plane (or a flat surface) with the top surface of the second insulating layer 130. The second contact electrode 135 may include a metal structure 135-1 disposed inside the second contact hole and a barrier layer 135-2 disposed between the side surface of the metal structure 135-1 and the inner surface of the second contact hole CH2, and between the bottom surface of the metal structure 135-1 and the top surface of the first contact electrode 125 exposed through the second contact hole CH2.

[0078] The metal structure 135-1 may include a metal such as copper or tungsten. The barrier layer 135-2 is also conductive. The bonding strength between the second insulating layer 130 and the first contact electrode 125 can be increased by the barrier layer 135-2, and in addition, the barrier layer 135-2 can prevent metal atoms of the metal structure 135-1 from diffusing into the second insulating layer 130.

[0079] Barrier layer 135-2 may include a metal layer made of a barrier metal (hereinafter referred to as the barrier metal layer) and a nitride layer made of a barrier metal nitride (hereinafter referred to as the barrier metal nitride layer). The barrier metal nitride layer may be positioned closer to the second insulating layer 130 than the barrier metal layer. The barrier metal layer may improve adhesion, and the barrier metal nitride layer may prevent the diffusion of metal atoms in the metal structure 135-1. The barrier metal may include titanium or tantalum. Barrier layer 135-2 may include a titanium nitride layer and a titanium layer, or it may include a tantalum nitride layer and a tantalum layer.

[0080] In one embodiment of the inventive concept, the second contact electrode 135 may include a tungsten structure, a titanium layer surrounding the side and bottom surfaces of the tungsten structure, and a titanium nitride layer surrounding the titanium layer. In another embodiment of the inventive concept, the second contact electrode 135 may include a copper structure, a tantalum layer surrounding the side and bottom surfaces of the copper structure, and a tantalum nitride layer surrounding the tantalum layer.

[0081] like Figure 4c As shown, in an embodiment of the inventive concept, the top surface of the second contact electrode 135 may be concave. The first electrode structure ES1, described later, may contact the concave top surface of the second contact electrode 135. The second contact electrode 135 may be formed by a damascene method. In the chemical mechanical polishing (CMP) process of the damascene method, the second contact electrode 135 may be polished more than the second insulating layer 130, therefore, a dishing phenomenon may occur in the second contact electrode 135.

[0082] Refer again Figure 4b The light-emitting diode (LED) is disposed on the second insulating layer 130. Figure 4aThe light-emitting diode (LED) shown can produce light of the same color. In an embodiment of the inventive concept, Figure 4a One of the LEDs shown can produce red light, another can produce green light, and yet another can produce blue light. A third LED can produce one of red, green, blue, or white light.

[0083] Figure 4b A light-emitting diode (LED) may include a first electrode, a second electrode, and an emitting layer disposed between the first and second electrodes. In this embodiment, the first electrode is described as a first electrode structure ES1, and the second electrode is described as a second electrode structure ES2. Furthermore, the emitting layer includes a semiconductor junction structure SJS. In other words, the LED according to this embodiment may include a first electrode structure ES1, a semiconductor junction structure SJS disposed on the first electrode structure ES1, and a second electrode structure ES2 disposed on the semiconductor junction structure SJS. The first electrode structure ES1 may contact a second contact electrode 135 and may have a diameter larger than the diameter of each of the semiconductor junction structure SJS and the second electrode structure ES2. In this embodiment, the semiconductor junction structure SJS and the second electrode structure ES2 may have the same diameter. In a plan view, the semiconductor junction structure SJS and the second electrode structure ES2 may be disposed inside the first electrode structure ES1. In embodiments of the inventive concept, the first electrode structure ES1 may have the same diameter as each of the semiconductor junction structure SJS and the second electrode structure ES2.

[0084] When a light-emitting diode (LED) has the following characteristics Figure 4a When the first electrode structure ES1 is circular as shown, it can also be circular. However, the shape of the first electrode structure ES1 is not limited to this. The first electrode structure ES1 can be elliptical or polygonal, such as a square or octagon.

[0085] In this embodiment, the first electrode structure ES1 is described as an anode (or anode structure), and the second electrode structure ES2 is described as a cathode (or cathode structure), but is not limited thereto. In embodiments of the inventive concept, the first electrode structure ES1 may be a cathode, and the second electrode structure ES2 may be an anode. The stacked configuration of the semiconductor junction structure SJS can vary depending on whether the first electrode structure ES1 is an anode or a cathode.

[0086] The light-emitting element layer 20 may include a first side insulating layer SI1 disposed on the side surface of the first electrode structure ES1, the side surface of the semiconductor junction structure SJS, the side surface of the second electrode structure ES2, and the top surface of the second electrode structure ES2. Except for the first opening COP1 and the bottom surface of the first electrode structure ES1, the first side insulating layer SI1 surrounds the light-emitting diode LED.

[0087] The first insulating layer SI1 prevents the light-emitting diode (LED) and the side reflective layer SRL, which will be described later, from contacting each other. The first insulating layer SI1 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, an aluminum oxide layer, a zirconium oxide layer, a hafnium oxide layer, or a titanium oxide layer. In FIG. 4A, the first insulating layer SI1 is shown as a single layer, but is not limited thereto. The first insulating layer SI1 may have a single-layer structure of the aforementioned layers or a multilayer structure of any selection from the aforementioned layers.

[0088] A side reflective layer SRL is disposed outside the first side insulating layer SI1. The side reflective layer SRL can reflect light generated from the light-emitting diode (LED) to improve light efficiency, so that light generated from the LED is emitted into the first opening COP1. The side reflective layer SRL may include gold (Au), copper (Cu), silver (Ag), titanium (Ti), or aluminum (Al).

[0089] The side reflective layer SRL is configured to correspond at least to the side surface of the first electrode structure ES1, the side surface of the semiconductor junction structure SJS, and the side surface of the second electrode structure ES2. A portion of the side reflective layer SRL may also be disposed on the top surface of the second electrode structure ES2.

[0090] In this embodiment, the side reflective layer SRL can be configured to be spaced apart from each of the light-emitting diodes (LEDs). The side reflective layer SRL can be separated from and spaced apart from the boundary region BA. However, embodiments of the inventive concept are not limited thereto, and the side reflective layer SRL can have any shape. For example, the side reflective layer SRL can be... Figure 4a The first region DA has a monolithic shape.

[0091] The light-emitting element layer 20 may further include a second side insulating layer SI2 disposed inside the first side insulating layer SI1. The second side insulating layer SI2 is configured to protect a portion of the side surface of the light-emitting diode LED during the manufacturing process of the LED. This will be described in detail later.

[0092] The second insulating layer SI2 can contact the side surface of the semiconductor junction structure SJS and the side surface of the second electrode structure ES2. The second insulating layer SI2 can also be disposed on a portion of the top surface of the second electrode structure ES2. The second insulating layer SI2 can also be disposed on the portion of the top surface of the first electrode structure ES1 exposed by the semiconductor junction structure SJS. The second insulating layer SI2 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, an aluminum oxide layer, a zirconium oxide layer, a hafnium oxide layer, and a titanium oxide layer. Figure 4a In the diagram, the second insulating layer SI2 is shown as a single layer, but is not limited thereto. The second insulating layer SI2 may have a single-layer structure of the aforementioned layers or a multi-layer structure arbitrarily selected from the aforementioned layers.

[0093] The first opening COP1 corresponds to the emission region of the light-emitting diode (LED) and to the channel through which the second electrode structure ES2 is connected to the common electrode CME.

[0094] A planarization layer 140 is disposed on the second insulating layer 130. The planarization layer 140 is stacked with multiple unit regions UA and boundary regions BA, and is disposed on multiple light-emitting diodes (LEDs). The planarization layer 140 fills the regions where no LEDs are disposed. The planarization layer 140 may include an organic material.

[0095] The planarization layer 140 can be configured to correspond to the side surface of the first electrode structure ES1 and the side surface of the semiconductor junction structure SJS. A portion of the planarization layer 140 can be configured to correspond to the side surface of the second electrode structure ES2, and another portion can be configured on the second electrode structure ES2 to be stacked with the side reflection layer SRL. The planarization layer 140 can be in contact with the side reflection layer SRL. A second opening COP2 corresponding to the first opening COP1 can be configured in the planarization layer 140. The second opening COP2 can be aligned with the first opening COP1, but the second opening COP2 formed by a different process than the process used to form the first opening COP1 can have a larger area than the first opening COP1.

[0096] In embodiments of the inventive concept, the planarization layer 140 may not be disposed on the second electrode structure ES2. The top surface of the planarization layer 140 may be defined in the same plane as the top surface of the side reflective layer SRL. Here, the second opening COP2 may be omitted.

[0097] In planarization layer 140, the following are defined: Figure 4a The trenches TC1 and TC2, and in Figure 4b The second trench TC2 is shown as an example. The second auxiliary electrode SE2 is disposed in the second trench TC2. Figure 4a The first auxiliary electrode SE1 shown can be formed in the same process as the second auxiliary electrode SE2, and can have the same structure as the second auxiliary electrode SE2, which will be described later.

[0098] The second auxiliary electrode SE2 may include a metal structure SE2-1 disposed inside the second trench TC2 and a barrier layer SE2-2 disposed between the metal structure SE2-1 and the second trench TC2. The metal structure SE2-1 may include a metal such as copper or tungsten. The barrier layer SE2-2 is conductive, just like the metal structure SE2-1. The barrier layer SE2-2 can increase the adhesion to the planarization layer 140, and it can also prevent metal atoms from the metal structure SE2-1 from diffusing into the planarization layer 140.

[0099] The barrier layer SE2-2 may include a barrier metal layer and a barrier metal nitride layer. The barrier metal nitride layer may be positioned closer to the planarization layer 140 than the barrier metal layer. The barrier metal layer may include titanium or tantalum. The barrier metal nitride layer may include a titanium nitride layer or a tantalum nitride layer. The second auxiliary electrode SE2 may also be formed using an inlay method, similar to the second contact electrode 135, and the top surface of the second auxiliary electrode SE2 may be concave.

[0100] A common electrode CME is disposed on planarization layer 140. The common electrode CME can be stacked with cell region UA ​​and boundary region BA. The common electrode CME may include a transparent conductive material to emit light generated by a light-emitting diode (LED). The common electrode CME may include a transparent conductive oxide (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc tin oxide (ZTO), or indium gallium zinc oxide (IGZO)).

[0101] The common electrode CME is connected to the second electrode structure ES2 of the light-emitting diode (LED) through the first opening COP1 and the second opening COP2. The electrical voltage applied through the common electrode CME can be transmitted to the LED. Figure 4b A common electrode CME connected to two light-emitting diodes (LEDs) is shown as an example. One of the two LEDs can be defined as the first LED, and the other can be defined as the second LED.

[0102] The common electrode CME is in contact with the top surface of the second auxiliary electrode SE2. Because the top surface of the second auxiliary electrode SE2 is like... Figure 4a As shown, the common electrode CME is in contact with the second auxiliary electrode SE2 along the longitudinal direction of the second trench TC2, so the common electrode CME and the second auxiliary electrode SE2 can ensure sufficient contact area.

[0103] A passivation layer 150 is disposed on the common electrode CME. The passivation layer 150 protects the common electrode CME. The passivation layer 150 can be combined with... Figure 3a and Figure 3b The display area DA and the non-display area NDA are stacked to protect the voltage transfer electrode VTE. The passivation layer 150 may include organic or inorganic materials.

[0104] Lens LS is disposed on passivation layer 150. Two lenses LS corresponding to the first light-emitting diode (LED) and the second light-emitting diode (LED) are shown. Lens LS focuses the light emitted from the LED. Lens LS may comprise an organic material and have a hemispherical shape. Lens LS may have a diameter of about 1 micrometer or less.

[0105] like Figure 4b and Figure 4dAs shown, the passivation layer 150 may include a recessed region 150-c. The stepped portion may be located in conjunction with... Figure 4b The step portion is located in the region corresponding to the first opening COP1, and the step portion can extend to each of the common electrode CME and the passivation layer 150. The step portion can be removed depending on the material or thickness of the passivation layer 150.

[0106] In the following text, reference will be made to Figure 4e and Figure 4f The stacked structure of the first electrode structure ES1 is described in detail. Although not shown separately, in the first electrode structure ES1 according to an embodiment of the inventive concept, it can be seen from... Figure 4e and Figure 4f The structure shown omits some layers, or other functional layers can be added.

[0107] Reference Figure 4e The first electrode structure ES1 may include at least a metal layer ML, a reflective layer RL disposed on the metal layer ML, and a transparent conductive oxide layer TCO1 disposed on the reflective layer RL (hereinafter referred to as the first transparent conductive oxide layer). The metal layer ML, the reflective layer RL, and the first transparent conductive oxide layer TCO1 may be stacked sequentially, or additional functional layers may be further disposed between the metal layer ML, the reflective layer RL, and the first transparent conductive oxide layer TCO1.

[0108] The metal layer ML corresponds to the adhesive layer that bonds the CMOS wafer to the semiconductor substrate during the manufacturing process of a display device. In other words, the metal layer ML is a layer formed by bonding the metal layer of the CMOS wafer to the metal layer of the semiconductor substrate.

[0109] The metal layer ML may include at least one metal layer. The at least one metal layer may include any one of gold (Au), copper (Cu), silver (Ag), tin (Sn), titanium (Ti), zirconium (Zr), and tantalum (Ta), or may include an alloy of at least two of the metals mentioned above.

[0110] In this embodiment, a three-layer metal layer ML comprising a first metal layer ML1, a second metal layer ML2, and a third metal layer ML3 is illustrated as an example. The second metal layer ML2 may include any one of gold (Au), copper (Cu), silver (Ag), tin (Sn), titanium (Ti), zirconium (Zr), and tantalum (Ta), and may also include a metal different from the first metal layer ML1 and the third metal layer ML3. Each of the first metal layer ML1 and the third metal layer ML3 may include one of gold (Au), copper (Cu), silver (Ag), tin (Sn), titanium (Ti), zirconium (Zr), and tantalum (Ta). In embodiments of the inventive concept, the metal layer ML may include two consecutive metal layers from the first metal layer ML1, the second metal layer ML2, and the third metal layer ML3.

[0111] The reflective layer RL reflects light generated in the semiconductor junction structure SJS in the direction facing the semiconductor junction structure SJS. The reflective layer RL may include gold (Au), copper (Cu), silver (Ag), titanium (Ti), or aluminum (Al).

[0112] The first transparent conductive oxide layer TCO1 injects holes into the semiconductor junction structure SJS. The first transparent conductive oxide layer TCO1 can have a high work function that facilitates hole injection and can transmit light reflected from the reflective layer RL. The first transparent conductive oxide layer TCO1 includes at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc tin oxide (ZTO), and indium gallium zinc oxide (IGZO).

[0113] In this embodiment, the first electrode structure ES1 can be described as an anode and can have the structure described above. However, if the first electrode structure ES1 is a cathode, the structure of the first electrode structure ES1 can be changed. The electron injection functional layer and the reflective layer can be integrated into a single metal layer. That is, the metal layer serves as both the electron injection layer and the reflective layer. Therefore, the cathode structure can include two metal layers that are distinct from each other.

[0114] The first electrode structure ES1 can have a thickness of approximately 500 nm or less. Due to the increased thickness of the first electrode structure ES1, thickness-dependent process errors may occur. For example, the etching rate may vary depending on the thickness. When the first electrode structure ES1 is thick, it can be configured to have more inclined side surfaces. To form a first electrode structure ES1 with vertical side surfaces, it can have a thickness of approximately 500 nm or less.

[0115] according to Figure 4eThe first electrode structure ES1 may include a first barrier layer BRL1 disposed between the metal layer ML and the reflective layer RL, a second barrier layer BRL2 disposed between the reflective layer RL and the first transparent conductive oxide layer TCO1, and a third barrier layer BRL3 disposed below the metal layer ML. Each of the first barrier layer BRL1 to the third barrier layer BRL3 may include a barrier metal layer and a barrier metal nitride layer. The barrier metal layer can improve the adhesion between adjacent layers, and the barrier metal nitride layer can prevent the diffusion of metal atoms in adjacent layers.

[0116] In this embodiment, the first barrier layer BRL1 may include a barrier metal nitride layer BMLN comprising a barrier metal nitride (e.g., titanium nitride) and barrier metal layers BML disposed above and below the barrier metal nitride layer BMLN, respectively. The barrier metal layer BML comprises a barrier metal (e.g., titanium). For example, the titanium nitride layer can prevent electromigration in the reflective layer RL by allowing metal atoms of the barrier metal layer ML to move to the reflective layer RL.

[0117] In this embodiment, the second barrier layer BRL2 may include a barrier metal nitride layer BMLN containing titanium nitride. For example, the titanium nitride layer can block the movement of metal atoms between the first transparent conductive oxide layer TCO1 and the reflective layer RL to prevent voids from forming in the first transparent conductive oxide layer TCO1 or to prevent the reflective layer RL from being oxidized.

[0118] In this embodiment, the third barrier layer BRL3 may include a barrier metal nitride layer BMLN containing titanium nitride and barrier metal layers BML respectively disposed above and below the barrier metal nitride layer BMLN and containing titanium. This can prevent... Figure 4b Electromigration occurs between the second contact electrode 135 and the metal layer ML.

[0119] Figure 4f It shows the relationship with Figure 4e Compared to the first electrode structure ES1, which has a relatively simple stacked structure, the stacked structure in the first barrier layer ML can be a single metal layer. The first barrier layer BRL10 can include a barrier metal nitride layer BMLN and a barrier metal layer BML disposed on the barrier metal nitride layer BMLN. The third barrier layer BRL30 can include a barrier metal nitride layer BMLN and a barrier metal layer BML disposed below the barrier metal nitride layer BMLN and made of barrier metal. The barrier metal nitride layer BMLN of the first barrier layer BRL10 can be in contact with the top surface of the metal layer ML, and the barrier metal nitride layer BMLN of the third barrier layer BRL30 can be in contact with the bottom surface of the metal layer ML.

[0120] Figure 4f The stacked structure can be achieved by making specific layers have... Figure 4e The same material is used to form the laminated structure. For example, when Figure 4e When the metal layer ML has a single-layer structure of titanium (Ti), and the barrier metal layer BML of the first barrier layer BRL1 and the third barrier layer BRL3 includes titanium (Ti), the barrier metal layer BML of the first barrier layer BRL1 and the third barrier layer BRL3 adjacent to the metal layer ML, as well as the metal layer ML, can be set as a single metal layer.

[0121] Reference Figure 4g Provide a detailed description of a light-emitting diode (LED). Figure 4g In this diagram, the first electrode structure ES1 is briefly shown as a single layer, and the semiconductor junction structure SJS is shown in detail. Although a disk-shaped first electrode structure ES1 is shown as an example, the shape of the first electrode structure ES1 is not limited to this. In this embodiment, the light-emitting diode (LED) can have a cylindrical shape, but is not limited to this.

[0122] The semiconductor junction structure SJS may include an active layer ACT, a p-type semiconductor layer SP disposed on one side of the active layer ACT, and an n-type semiconductor layer SN disposed on the other side of the active layer ACT. In this embodiment, since the first electrode structure ES1, which serves as the anode, is disposed below the active layer ACT, the p-type semiconductor layer SP is disposed below the active layer ACT.

[0123] The active layer ACT can be configured as a single quantum well structure or a multi-quantum well structure. Light can be emitted by causing electron-hole pair recombination, based on an electrical signal applied through the p-type semiconductor layer SP and the n-type semiconductor layer SN. The active layer ACT can emit light with wavelengths from approximately 400 nm to approximately 900 nm, and a dual heterostructure can be used.

[0124] In embodiments of the inventive concept, the active layer ACT may have a structure in which semiconductor materials with large band gaps and semiconductor materials with small band gaps are alternately stacked, and may include group 3 to group 5 semiconductor materials selected according to the wavelength of the emitted light.

[0125] The p-type semiconductor layer SP may comprise at least one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may be doped with a first conductive dopant such as magnesium (Mg), zinc (Zn), calcium (Ca), or barium (Ba). For example, the p-type semiconductor layer SP may be p-GaN doped with magnesium (Mg). However, the materials forming the p-type semiconductor layer SP are not limited to these, and the p-type semiconductor layer SP may be formed from various other materials.

[0126] The n-type semiconductor layer SN may include at least one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may be doped with a second conductive dopant such as silicon (Si), germanium (Ge), or tin (Sn). However, the materials forming the n-type semiconductor layer SN are not limited to these, and the n-type semiconductor layer SN may be formed from various other materials.

[0127] Although not shown, the light-emitting diode (LED) may also include a cladding layer. The cladding layer may be disposed above and / or below the active layer ACT. The cladding layer may include an AlGaN layer or an InAlGaN layer. The LED may also include a tensile strain barrier reduction (TSBR) layer disposed above and / or below the active layer ACT. The TSBR layer may be a strain relaxation layer disposed between semiconductor layers with different lattice structures to buffer the difference in lattice constants. The TSBR layer may be a p-type semiconductor layer such as p-GaInP, p-AlInP, p-AlGaInP, etc., but embodiments of the inventive concept are not limited thereto.

[0128] In this embodiment, the second electrode structure ES2 may include a transparent conductive oxide layer (hereinafter referred to as the second transparent conductive oxide layer TCO2). The second transparent conductive oxide layer TCO2 may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc tin oxide (ZTO), or indium gallium zinc oxide (IGZO). The second transparent conductive oxide layer may correspond to a protective layer in the process of manufacturing a light-emitting diode (LED) and may inject electrons into the semiconductor junction structure SJS. A detailed description of the function of the second transparent conductive oxide layer as a protective layer will be described later with reference to the manufacturing method.

[0129] The second electrode structure ES2 may further include an electrode metal layer disposed between the second transparent conductive oxide layer and the semiconductor junction structure SJS. The electrode metal layer may include a metal having a work function smaller than that of the second transparent conductive oxide layer. The electrode metal layer can improve the electron injection performance of the second electrode structure ES2. The electrode metal layer may include aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), nickel (Ni), copper (Cu), their oxides, or alloys thereof.

[0130] Figure 5a It is shown Figure 3a An enlarged plan view of part of region A2 in the second region NDA1. Figure 5b It is along Figure 5a The sectional view taken from line II-II'. In the following description, the focus will be on the reference... Figures 4a to 4d The first region DA is described as having some differences from region A1.

[0131] Reference Figure 5a The first auxiliary electrode SE1 is disposed in the first trench TC1 within the second region NDA1, and the second auxiliary electrode SE2 is disposed in the second trench TC2 within the second region NDA1. The first auxiliary electrode SE1 is disposed in the second trench TC2 within the second region NDA1. Figure 4a The first auxiliary electrode SE1 extends, and the second auxiliary electrode SE2 extends from... Figure 4a The second auxiliary electrode SE2 is extended.

[0132] The second region NDA1 may include the unit region UA ​​and the boundary region BA between the unit regions UA. The arrangement relationship between the unit region UA ​​and the boundary region BA in the third region NDA2 may be the same as the arrangement relationship between the unit region UA ​​and the boundary region BA in the second region NDA1. A dummy light-emitting diode DED is disposed in the unit region UA ​​of the second region NDA1, and no lens LS and first opening COP1 are provided.

[0133] Figure 5b The dummy LED DED shown can have the same characteristics as... Figure 4b The dummy LED shown has essentially the same stacked structure as the LED. This is because the dummy LED (DED) is formed using the same process as the LED. The second electrode structure ES2 of the dummy LED (DED) is not exposed to the outside and is not connected to the common electrode CME. This is because the first opening COP1 is not defined within the first side insulating layer SI1, the second side insulating layer SI2, and the side reflective layer SRL. Therefore, the dummy LED (DED) may not be driven or may not emit light.

[0134] Figure 6a It is shown Figure 3a A magnified plan view of part of region A3 in the third-1 region NDA21. Figure 6b It is along Figure 6a The cross-sectional view taken by line III-III'. In the following, the differences between a portion A1 of the first region DA and a portion A2 of the second region NDA1 will be described, focusing on the above-mentioned first region DA.

[0135] Reference Figure 6a The first auxiliary electrode SE1 is disposed in the first trench TC1 within the third-1 region NDA21, and the second auxiliary electrode SE2 is disposed in the second trench TC2 within the third-1 region NDA21. The first auxiliary electrode SE1 is disposed in... Figure 5a The first auxiliary electrode SE1 extends, and the second auxiliary electrode SE2 extends from... Figure 5a The second auxiliary electrode SE2 is extended.

[0136] The third region NDA21 may include unit regions UA and boundary regions BA between unit regions UA. The arrangement relationship between unit regions UA and boundary regions BA in the third region NDA21 may be the same as the arrangement relationship between unit regions UA and boundary regions BA in the second region NDA1. Light-emitting diodes (LEDs) or dummy LEDs (DEDs) are not disposed in unit regions UA of the third region NDA21, and the lens LS and the first opening COP1 are not disposed in unit regions UA of the third region NDA21.

[0137] Reference Figure 6b The CMOS wafer 10 is schematically shown as comprising only a silicon substrate 101, a first insulating layer 123, and a second insulating layer 130. However, a scan driver may be formed in the third-1 region NDA21 of the CMOS wafer 10, and the scan driver may include... Figure 4b The transistor shown is a transistor-like circuit.

[0138] A common line CML can be disposed on the second insulating layer 130 within the third-1 region NDA21. The common line CML can be electrically connected to the common electrode CME within the third-1 region NDA21. Furthermore, the common line CML can not only be stacked with the third-1 region NDA21, but can also be extended to connect with, as will be referred to later... Figure 7b The voltage transfer electrode (VTE) is described as being stacked.

[0139] Common lines (CMLs) can include those with... Figure 4b The first conductive structure CS1 has the same stacked structure as the first electrode structure ES1. The common line CML may also include an insulating structure IC disposed on the top surface of the first conductive structure CS1. The insulating structure IC may include a first insulating patterned layer IC1 formed by the same process as the second side insulating layer SI2 and a second insulating patterned layer IC2 formed by the same process as the first side insulating layer SI1. The second insulating patterned layer IC2 may or may not contact the side surface of the first conductive structure CS1. The opening IC-OP may be defined in the insulating structure IC, and in embodiments of the inventive concept, the insulating structure IC may be omitted.

[0140] The common line CML may further include a second conductive structure CS2 disposed on and electrically connected to the first conductive structure CS1. The second conductive structure CS2 may be connected to the side surface of the first conductive structure CS1 and may be connected to the top surface of the first conductive structure CS1 through the opening IC-OP of the insulating structure IC. The second conductive structure CS2 may be connected to... Figure 4b The side reflective layer SRL is formed using the same process and can include the same materials. The second conductive structure CS2 can be formed with... Figure 4band Figure 5b The side reflective layers SRL are spaced apart and electrically insulated.

[0141] In this embodiment, a common line CML including a first conductive structure CS1, an insulating structure IC, and a second conductive structure CS2 is shown as an example; however, the common line CML is not limited to this. As described above, the common line CML may include only the first conductive structure CS1, or it may include both the first conductive structure CS1 and the insulating structure IC.

[0142] The public line CML can be accessed Figure 3b The auxiliary electrode SE (e.g., Figure 6b The second auxiliary electrode SE2 is connected to the common electrode CME. The second auxiliary electrode SE2 is disposed in the second trench TC2. A via TH extending from a region of the second trench TC2 can be defined in the planarization layer 140. The second auxiliary electrode SE2 can be connected to the common line CML through the via TH.

[0143] As an example, Figure 6a and Figure 6b The via TH is shown to be stacked with the second trench TC2, but embodiments of the inventive concept are not limited thereto. The via TH can be further defined with... Figure 6a The first trenches TC1 are stacked, and there are no particular restrictions on their number, shape and position.

[0144] Figure 7a It is shown Figure 3a A magnified plan view of part of region A4 of the third-2 region NDA22. Figure 7b It is along Figure 7a A cross-sectional view taken from line IV-IV'. The following description will focus on the differences between this region and a portion of region A3 of region NDA21 described above as part of region 3-1.

[0145] Figure 7a It shows Figure 3a The third-2 region NDA22 contains a portion A4 of which a pad electrode PD is disposed. A first auxiliary electrode SE1 is disposed within the first trench TC1 in the third-2 region NDA22, and a second auxiliary electrode SE2 is disposed within the second trench TC2 in the third-2 region NDA22. The first auxiliary electrode SE1... Figure 6a The first auxiliary electrode SE1 extends, and the second auxiliary electrode SE2 extends from... Figure 6a The second auxiliary electrode SE2 extends. The third-2 region NDA22 may include the cell region UA ​​and the boundary region BA between the cell regions UA. The pad electrode PD may be stacked with a portion of the cell region UA ​​and a portion of the boundary region BA.

[0146] In addition to pad electrode PD Figure 3a The third-2 region of NDA22, which is superimposed on the voltage transfer electrode VTE, can have the same characteristics as... Figure 7a and Figure 7b The structure is the same as that of a portion of region A4 shown in the diagram. However, the region of the third-2 region NDA22 that is not superimposed on the voltage transfer electrode VTE can have the same structure as... Figure 7a and Figure 7b The diagram shows different structures in a portion of region A4. The first auxiliary electrode SE1, the first trench TC1, the second auxiliary electrode SE2, and the second trench TC2 may not be located in the region of the third-2 region NDA22 that is not superimposed with the voltage transmission electrode VTE.

[0147] Figure 7b The common line CML runs along the voltage transfer electrode VTE from Figure 6a and Figure 6b The third-1 region NDA21 extends to the third-2 region NDA22. The common line CML can be connected to the voltage transmission electrode VTE via the second auxiliary electrode SE2. The second auxiliary electrode SE2, disposed in the second trench TC2, can be connected to the common line CML via the via TH defined in the planarization layer 140.

[0148] An opening 150-OP of a portion of the exposed voltage transmission electrode VTE (hereinafter referred to as the connection region) is defined in a passivation layer 150. A pad electrode PD disposed on the passivation layer 150 is connected to the connection region of the voltage transmission electrode VTE through the opening 150-OP.

[0149] Figure 8a It is a cross-sectional view corresponding to the second region NDA1 according to an embodiment of the inventive concept. Figure 8b This is a cross-sectional view corresponding to region NDA22 in area 3-2. Figure 8a Is with Figure 5b The sectional view corresponding to the sectional view, and Figure 8b Is with Figure 7b The sectional view corresponding to the sectional view.

[0150] Although not shown separately, it is formed in Figure 4b The second trench TC2 in the first region DA can also be like Figure 8a The second trench TC2 was modified in the same way and formed in Figure 7b The second trench TC2 in the third-1 region NDA21 can also be like Figure 8b The second trench TC2 was modified in the same way.

[0151] Figure 8a The second trench TC2 is formed more than Figure 4b and Figure 5bThe second trench TC2 shown is deep. Therefore, a portion of the side reflector layer SRL can be... Figure 8a The second trench TC2 is exposed. The second auxiliary electrode SE2 can contact the side reflective layer SRL.

[0152] Figure 8b The second trench TC2 in the middle is also formed more than Figure 6b and Figure 7b The second trench TC2 shown is deep. Therefore, the additional trenches already formed in some areas can be omitted. Figure 6b and Figure 7b The through-hole TH is included. Furthermore, the contact area between the second auxiliary electrode SE2 and the common line CML can be further increased.

[0153] Figures 9a to 9s This is a cross-sectional view illustrating the process of manufacturing a display device according to an embodiment of the inventive concept. Figures 9a to 9s In the middle, it is shown sequentially in one of the attached figures. Figure 4b , Figure 5b , Figure 6b and Figure 7b However, the first region DA, the second region NDA1, the third-1 region NDA21, and the third-2 region NDA22 can be discontinuous.

[0154] like Figure 9a As shown, a CMOS wafer 10 is provided. The CMOS wafer 10 includes a silicon substrate 101, a first insulating layer 123, and a second insulating layer 130. Except for the second contact electrode 135, Figure 9a The CMOS wafer 10 in the diagram is shown as being larger than... Figure 4b The CMOS wafer 10 is simple. The second contact electrode 135 disposed in the second contact hole CH2 can be formed by an damascene process. There are no particular limitations on the process for manufacturing the CMOS wafer 10.

[0155] like Figure 9a As shown, a first conductive layer CL1 can be disposed on the second insulating layer 130 of the CMOS wafer 10. The first conductive layer CL1 can be formed by a deposition process, and the type of deposition process used to form the first conductive layer CL1 is not particularly limited. The first conductive layer CL1 may include at least one metal layer. The first conductive layer CL1 may include... Figure 4e The first conductive layer CL1 may be a first metal layer ML1 or a first metal layer ML1 and a second metal layer ML2. The first conductive layer CL1 may further include a barrier layer disposed beneath the at least one metal layer. The barrier layer may be... Figure 4e The third barrier layer BRL3 or Figure 4f The third barrier layer, BRL30.

[0156] In this embodiment, the first conductive layer CL1 will be described as including... Figure 4e The structure of a third barrier layer BRL3 and a first metal layer ML1 and a second metal layer ML2 disposed on the third barrier layer BRL3.

[0157] Next, as Figure 9b As shown, a semiconductor substrate SUB-S is provided. Figure 9b The semiconductor substrate SUB-S aligned on CMOS wafer 10 is shown.

[0158] The semiconductor substrate SUB-S may include a silicon substrate 201, a buffer layer 202 disposed below the silicon substrate 201, a semiconductor junction layer 203 disposed below the buffer layer 202, and a second conductive layer CL2 disposed below the semiconductor junction layer 203. The buffer layer 202 may be an epitaxial layer grown from the silicon substrate 201.

[0159] The semiconductor junction layer 203 may include an active layer ACT, a p-type semiconductor layer SP disposed on one side of the active layer ACT, and an n-type semiconductor layer SN disposed on the other side of the active layer ACT. In this embodiment, the semiconductor junction layer 203 may have the same characteristics as the reference layer. Figure 4g The semiconductor junction structure SJS described has the same stacked structure. That is, the semiconductor junction layer 203 may include an n-type semiconductor layer SN, an active layer ACT disposed below the n-type semiconductor layer SN, and a p-type semiconductor layer SP disposed below the active layer ACT. The n-type semiconductor layer SN may have a higher density than... Figure 4g The n-type semiconductor layer SN shown has a large thickness. This is because a portion of it is removed during the polishing process, as will be described later.

[0160] The second conductive layer CL2 may include a transparent conductive oxide layer, a reflective layer disposed below the transparent conductive oxide layer, and at least one metal layer disposed above the reflective layer. The second conductive layer CL2 may include... Figure 4e The first transparent conductive oxide layer TCO1, the reflective layer RL, and one or more of the second metal layer ML2 and the third metal layer ML3. The second conductive layer CL2 may include the third metal layer ML3, or may include the second metal layer ML2 and the third metal layer ML3.

[0161] The second conductive layer CL2 may further include a barrier layer. The barrier layer may include... Figure 4e The first barrier layer BRL1 or Figure 4f The first barrier layer, BRL10. The barrier layer may also include... Figure 4e The second barrier layer BRL2, or may only include Figure 4e The second barrier layer, BRL2.

[0162] In this embodiment, the second conductive layer CL2 will be described as including... Figure 4e The structure includes a first transparent conductive oxide layer TCO1, a second barrier layer BRL2 disposed below the first transparent conductive oxide layer TCO1, a reflective layer RL disposed below the second barrier layer BRL2, a first barrier layer BRL1 disposed below the reflective layer RL, and a third metal layer ML3 disposed below the first barrier layer BRL1.

[0163] Next, as Figure 9c As shown, the semiconductor substrate SUB-S is bonded to the CMOS wafer 10. The second conductive layer CL2 can be adhered to the first conductive layer CL1 via a high-temperature, high-pressure process. In this embodiment, Figure 4e The second metal layer ML2 and Figure 4e The third metal layer ML3 can adhere to each other. Therefore, it is possible to form a structure with... Figure 4e The first electrode layer ESL1 has the same stacked structure as the first electrode structure ES1 described in the previous section. Figure 9d In the diagram, the first electrode layer ESL1 is shown as a single layer.

[0164] According to embodiments of the inventive concept, the uppermost metal layer of the first conductive layer CL1 and the lowermost metal layer of the second conductive layer CL2 may comprise the same metal, and the uppermost and lowermost metal layers may be formed into a single metal layer after the adhesion process of the first conductive layer CL1 and the second conductive layer CL2. For example, Figure 4e The second metal layer ML2 in Figure 7c can be a single metal layer formed after the adhesion process. The first conductive layer CL1 in Figure 7c can include Figure 4e The third barrier layer BRL3, the first metal layer ML1 on the third barrier layer BRL3, and the uppermost metal layer disposed on the first metal layer ML1, and the second conductive layer CL2 in FIG7c may include Figure 4e The structure includes a first transparent conductive oxide layer TCO1, a second barrier layer BRL2 below the first transparent conductive oxide layer TCO1, a reflective layer RL below the second barrier layer BRL2, a first barrier layer BRL1 below the reflective layer RL, a third metal layer ML3 below the first barrier layer BRL1, and a bottommost metal layer disposed below the third metal layer ML3. Figure 9c In the bonding process, the uppermost metal layer of the first conductive layer CL1 and the lowermost metal layer of the second conductive layer CL2 can form a single metal layer (i.e., Figure 4eThe second metal layer ML2). As described above, the uppermost metal layer of the first conductive layer CL1 and the lowermost metal layer of the second conductive layer CL2 may comprise the same metal. Each of the uppermost metal layer of the first conductive layer CL1 and the lowermost metal layer of the second conductive layer CL2 may comprise any one of gold (Au), copper (Cu), silver (Ag), tin (Sn), titanium (Ti), zirconium (Zr), and tantalum (Ta).

[0165] The following is a brief description of the method used to form a structure with... Figure 4f The first electrode structure is the same as the first electrode layer ESL1 of the first electrode structure. Figures 9a to 9c The first conductive layer CL1 in the middle includes Figure 4f The third barrier layer BRL30 and the first metal layer on the third barrier layer BRL30. Figure 9b and Figure 9c The second conductive layer CL2 in the middle includes Figure 4f The first transparent conductive oxide layer TCO1, the second barrier layer BRL2 disposed below the first transparent conductive oxide layer TCO1, the reflective layer RL disposed below the second barrier layer BRL2, the first barrier layer BRL10 disposed below the reflective layer RL, and the second metal layer disposed below the first barrier layer BRL10.

[0166] When the first conductive layer CL1 and the second conductive layer CL2 are as Figure 9c When combined as shown, it can form a structure with the characteristics of Figure 4f The first electrode layer ESL1 is the same as the first electrode structure ES1 in the stacked structure. Here, if the first metal layer and the second metal layer comprise the same metal, a structure like the one in the stacked structure can be formed. Figure 4f The diagram shows a single-layer metal layer ML comprising a single metal. If the first metal layer and the second metal layer comprise different metals, the metals of the first metal layer and the second metal layer can diffuse into each other to form an alloy layer.

[0167] Next, as Figure 9d As shown, remove Figure 9c A portion of the semiconductor substrate SUB-S is used to form the semiconductor junction structure layer SJSL. A semiconductor polishing process can be performed. This can completely remove... Figure 9c The silicon substrate 201 and buffer layer 202 are used, and a portion of the semiconductor junction layer 203 can be removed. Figure 9d The semiconductor junction structure layer SJSL formed by removing a portion of the semiconductor junction layer 203 is shown.

[0168] Semiconductor junction layer (SJSL) can have the same characteristics as... Figure 4f The semiconductor junction structure SJS has the same stacked structure. The corresponding layers of the semiconductor junction structure SJSL and the semiconductor junction structure SJS can have the same thickness.

[0169] Here, both the semiconductor junction structure layer SJSL and the first electrode layer ESL1 can be removed from a portion of the region (hereinafter referred to as the alignment bond region). The alignment bonds formed on the CMOS wafer 10 can be exposed to the outside through the alignment bond region. The alignment bonds can be used in photolithography processes performed in subsequent processes.

[0170] Next, as Figure 9e As shown, a second electrode layer ESL2 can be formed on the semiconductor junction structure layer SJSL. The second electrode layer ESL2 can have the same characteristics as... Figure 4g The second electrode structure ES2 described herein has the same stacked structure. A transparent conductive oxide layer for the second electrode layer ESL2 can be formed using a deposition process. The second electrode layer ESL2 may also include a metal layer disposed beneath the transparent conductive oxide layer. The metal layer in contact with the semiconductor junction structure layer SJSL can be formed using a primary deposition process. Alternatively, the transparent conductive oxide layer can be formed directly on the metal layer using a secondary deposition process.

[0171] According to an embodiment of the inventive concept, a second electrode layer ESL2 can be pre-formed between the buffer layer 202 and the semiconductor junction layer 203. Here, this step can be omitted. Figure 9d The process of removing a portion of the semiconductor junction layer 203 can remove only the silicon substrate 201 and the buffer layer 202.

[0172] Next, as Figure 9f As shown, the semiconductor junction structure layer SJSL and the second electrode layer ESL2 can be patterned. After forming the hard mask MSK through photolithography, the hard mask MSK can be used for etching. Figure 9e The semiconductor junction structure layer SJSL and the second electrode layer ESL2 are present. The hard mask MSK may include an insulating pattern. The semiconductor junction structure SJS, superimposed with the first region DA and the second region NDA1, is composed of... Figure 9e The semiconductor junction structure layer SJSL is formed. The second electrode structure ES2, superimposed on the semiconductor junction structure SJS, is composed of... Figure 9e The second electrode layer ESL2 is formed. The semiconductor junction structure layer SJSL and the second electrode layer ESL2 are removed from the third region NDA2.

[0173] During the etching process, the side surfaces of the semiconductor junction structure SJS and the second electrode structure ES2 may be damaged. However, the damage to the side surfaces of the semiconductor junction structure SJS and the second electrode structure ES2 can be repaired by a wet processing process.

[0174] Next, as Figure 9g As shown, remove Figure 9fA hard mask MSK is applied, and then a first insulating layer SI-1 is formed on the CMOS wafer 10. The first insulating layer SI-1 can be an inorganic layer and can be formed by a process of depositing inorganic materials. The first insulating layer SI-1 is disposed on the first electrode layer ESL1, surrounding the side surfaces of the semiconductor junction structure SJS and the second electrode structure ES2, and is disposed on the top surface of the second electrode structure ES2.

[0175] Next, as Figure 9h As shown, the first insulating layer SI-1 and the first electrode layer ESL1 are patterned. Therefore, a light-emitting diode (LED) superimposed on the first region DA and a dummy light-emitting diode (DED) superimposed on the second region NDA1 are formed.

[0176] Photolithography can be performed to create patterns. (See reference...) Figure 4b The second insulating layer SI2 described is formed from the first insulating layer SI-1, and the first electrode structure ES1, which is superimposed on the first region DA and the second region NDA1, is formed from the first electrode layer ESL1. (If omitted...) Figure 9g If the process of forming the first insulating layer SI-1 is used, the second insulating layer SI2 will not be formed.

[0177] The first conductive structure CS1, superimposed on the third region NDA2, is formed by the first electrode layer ESL1. The first conductive structure CS1 may have the same characteristics as the reference layer. Figure 6b and Figure 7b The first electrode structure ES1 described is the same stacked structure. The first insulating pattern layer IC1 disposed on the first conductive structure CS1 is composed of... Figure 9g The first insulating layer SI-1 is formed. The first insulating pattern layer IC1 may cover the top surface of the first conductive structure CS1.

[0178] because Figure 9h Photolithography and Figure 9f The process tolerances between the etching processes using the hard mask MSK can be mitigated, thus allowing the formation of a first electrode structure ES1 with a larger area than the second electrode structure ES2. Figure 9h In the photolithography process, the second insulating layer SI2 is protected by a photoresist (not shown). The first electrode structure ES1 is formed with a large area to protect the second insulating layer SI2 and the side surface of the semiconductor junction structure SJS protected by the second insulating layer SI2. Therefore, the second insulating layer SI2 can be disposed on a portion of the top surface of the first electrode structure ES1.

[0179] Next, as Figure 9i As shown, a second insulating layer SI-2 is formed on the CMOS wafer 10. The second insulating layer SI-2 can be an inorganic layer and can be formed by a process of depositing inorganic materials.

[0180] A second insulating layer SI-2 is disposed on the second insulating layer SI2 to cover the side surface of the first electrode structure ES1. The second insulating layer SI-2 covers the side surface of the first conductive structure CS1 and is disposed on the first insulating pattern layer IC1. The second insulating layer SI-2 is disposed on a portion of the top surface of the CMOS wafer 10.

[0181] Next, as Figure 9j As shown, the second insulating layer SI-2 is patterned. This can be performed within a single photolithography process. Figure 9i and 9j The process in.

[0182] Figure 9j The first side insulating layer SI1 can be made of Figure 9i A second insulating layer SI-2 is formed. Although the first side insulating layer SI1 is shown as having an integral shape in the first region DA and the second region NDA1, multiple first side insulating layers SI1 separated from each other can be formed on each of the light-emitting diode LED and the dummy light-emitting diode DED.

[0183] A second insulating pattern layer IC2 can be formed on the first insulating pattern layer IC1 in the third region NDA2. The stacked structure of the first insulating pattern layer IC1 and the second insulating pattern layer IC2 can be defined as follows: Figure 6b and Figure 7b An insulating structure IC. An opening IC-OP is defined within the insulating structure IC, exposing the top surface of the first conductive structure CS1. The shape of the opening IC-OP is not particularly limited. For example... Figure 9j As shown, the two edges of the first conductive structure CS1 can also be exposed by the insulating structure IC.

[0184] Next, as Figure 9k As shown, a metal layer ML-R is formed on CMOS wafer 10. The metal layer ML-R is formed by a deposition process. The metal layer ML-R is formed to be stacked with a first region DA, a second region NDA1, and a third region NDA2. The metal layer ML-R may include gold (Au), copper (Cu), silver (Ag), titanium (Ti), or aluminum (Al).

[0185] like Figure 9l As shown, the side reflective layer SRL and the second conductive structure CS2 can be formed from the metal layer ML-R by photolithography.

[0186] The side reflective layer SRL can be formed to overlap with the first region DA and the second region NDA1. The side reflective layer SRL is disposed outside the first side insulating layer SI1 and is in contact with the first side insulating layer SI1. Although multiple side reflective layers SRL are shown disposed on each of the plurality of second side insulating layers SI2, in embodiments of the inventive concept, the side reflective layer SRL can have an integral shape within the first region DA and the second region NDA1.

[0187] When the patterned metal layer ML-R is formed, a first opening COP1 can be formed. The first opening COP1 penetrates the first side insulating layer SI1, the second side insulating layer SI2, and the side reflective layer SRL of the light-emitting diode (LED) to expose a portion of the top surface of the second electrode structure ES2. The first opening COP1 is not formed in the dummy LED (DED). In the wet etching process that forms the first opening COP1, the transparent conductive oxide of the second electrode structure ES2 can protect the semiconductor junction structure SJS disposed beneath it from the etchant.

[0188] The second conductive structure CS2 can be formed to be stacked with the third region NDA2. The second conductive structure CS2 is disposed on the first conductive structure CS1 and the insulating structure IC, and is in contact with the portion of the first conductive structure CS1 exposed by the insulating structure IC. The second conductive structure CS2 can be connected to the first conductive structure CS1 at least through the open IC-OP. The stacked structure of the first conductive structure CS1, the insulating structure IC, and the second conductive structure CS2 can be defined as follows: Figure 6b and Figure 7b The common line described is CML.

[0189] like Figure 9m As shown, a planarization layer 140 is formed therein defining a second trench TC2. The planarization layer 140, which is configured as an organic layer, is formed on the CMOS wafer 10 using an inkjet printing process or a coating process. Subsequently, the second trench TC2 is formed in the planarization layer 140 using a first photolithography process. Although not shown separately, it is also possible to form [something else] when forming the second trench TC2. Figure 4a , Figure 5a , Figure 6a and Figure 7a The first trench TC1 is shown in the figure.

[0190] A via TH extending from the second trench TC2 can be further formed using a secondary photolithography process. The via TH is formed in the region superimposed on the common line CML of the third region NDA2.

[0191] In embodiments of the inventive concept, when the second trench TC2 is formed deeper using the first photolithography process, it is possible to form Figure 8a and Figure 8bThe second trench TC2 shown can be omitted. Figure 9m The secondary photolithography process is used to form the through-hole TH.

[0192] like Figure 9n As shown, a second auxiliary electrode SE2 is formed in the second trench TC2. When forming the second auxiliary electrode SE2, a second auxiliary electrode SE2 can also be formed... Figure 4a , Figure 5a , Figure 6a and Figure 7a The first auxiliary electrode SE1 is shown in the figure.

[0193] The second auxiliary electrode SE2 can be formed using an inlay method. After forming a thin barrier layer on the planarization layer 140 using a first deposition process, a metal layer thicker than the barrier layer is formed using a second deposition process. The metal layer with stepped portions is formed in the second trench TC2 and the surrounding region. The barrier layer and the metal layer disposed on the planarization layer 140 are removed using a CMP process. Therefore, a second auxiliary electrode SE2 comprising a barrier layer SE2-2 disposed only inside the second trench TC2 and a metal structure SE2-1 can be formed.

[0194] After that, as Figure 9o As shown, a second opening COP2 is formed in the planarization layer 140. The second opening COP2 is formed to correspond to the first opening COP1, and the second electrode structure ES2 is exposed to the outside. The second electrode structure ES2 of the dummy light-emitting diode (DED) is not exposed to the outside. As an example, a second opening COP2 with a diameter larger than that of the first opening COP1 is shown, but it is not limited thereto.

[0195] Next, as Figure 9p As shown, a common electrode CME is formed on the planarization layer 140 to be stacked with the first region DA, the second region NDA1, and the third-1 region NDA21. A voltage transfer electrode VTE is formed on the planarization layer 140 to be stacked with the third-2 region NDA22.

[0196] A common electrode CME and a voltage transfer electrode VTE with an integral shape are formed using a photolithography process. The common electrode CME is electrically connected to a light-emitting diode (LED) through a first opening COP1 and a second opening COP2. A transparent conductive oxide layer is formed on a planarization layer 140 using a deposition process, and then patterned to form a shape with... Figure 3a The common electrode CME and voltage transfer electrode VTE are shown in the diagram.

[0197] Next, as Figure 9qAs shown, a passivation layer 150 covering the common electrode CME is formed on the planarization layer 140. The passivation layer 150 covers the voltage transmission electrode VTE, and an opening 150-OP is formed in the passivation layer 150 to expose the connection region of the voltage transmission electrode VTE.

[0198] After that, as Figure 9r As shown, a pad electrode PD is formed on the planarization layer 140 to connect to the connection region of the voltage transmission electrode VTE. The pad electrode PD can be connected to the connection region of the voltage transmission electrode VTE through the opening 150-OP.

[0199] In addition, such as Figure 9s As shown, a lens LS can be formed on the planarization layer 140 to be stacked with a light-emitting diode (LED). The lens LS can be formed by patterning the organic layer via a photolithography process, or by dripping and drying organic material via an inkjet process.

[0200] Figure 10a This is a plan view showing the arrangement of the common electrode CME, voltage transfer electrode VTE, and auxiliary electrode SE according to an embodiment of the inventive concept. Figure 10b This is an enlarged plan view showing a portion of the third-2 region NDA22 according to an embodiment of the inventive concept. Figure 10c and Figure 10d It is along Figure 10b A sectional view taken by line V-V'. Figure 10e This is an enlarged plan view showing a portion of the third-2 region NDA21 according to an embodiment of the inventive concept. Figure 10f This is a plan view showing the arrangement relationship between the common electrode CME and the auxiliary electrode SE according to an embodiment of the inventive concept.

[0201] Figure 10a Corresponding to Figure 3b .according to Figure 10a The auxiliary electrode SE may include a cut region SE-C. In this embodiment, some of the second auxiliary electrode SE2 is shown as cut. The cut region SE-C of the auxiliary electrode SE may be superimposed on the voltage transmission electrode VTE.

[0202] The auxiliary electrode SE may include a first portion SE-1 superimposed on the common electrode CME and a portion superimposed on the voltage transfer electrode VTE and Figure 3a The second part SE-2 of the pad electrode PD stack. Figure 3a The pad electrode PD is not stacked with the first part SE-1. The first part SE-1 and the second part SE-2 may be spaced apart from each other on a plane.

[0203] Figure 10b yes Figure 10aAn enlarged view of the distal region of the voltage transfer electrode VTE is shown. A pad electrode PD superimposed on the second portion SE-2 is also shown. As described above, the first portion SE-1 and the second portion SE-2 of the auxiliary electrode SE are spaced apart from each other. The edge (or end) of the second portion SE-2 of the auxiliary electrode SE is shown aligned in a plane with the edge of the voltage transfer electrode VTE, but embodiments of the inventive concept are not limited thereto.

[0204] Reference Figure 10c Furthermore, a cutting region CML-C can be defined within the common line CML. The cutting region CML-C of the common line CML can be defined as substantially the same as, but not limited to, the cutting region SE-C of the auxiliary electrode SE. The common line CML includes a first common portion CML-1 and a second common portion CML-2 spaced apart from the first common portion CML-1. The first common portion CML-1 of the common line CML is disposed below and electrically connected to the first portion SE-1 of the auxiliary electrode SE. The second common portion CML-2 of the common line CML is disposed below and electrically connected to the second portion SE-2 of the auxiliary electrode SE.

[0205] The second contact electrode 135 and the connecting electrode 125-1 can be configured to electrically connect the pad electrode PD to the common electrode CME. The connecting electrode 125-1 can be connected via... Figure 4b The first contact electrode 125 is formed using the same process and can include the same stacked structure and the same material; that is, the second contact electrode 135 and the connecting electrode 125-1 can be disposed in the same layer. The connecting electrode 125-1 can be stacked with the cut region SE-C of the auxiliary electrode SE to replace the function of the cut auxiliary electrode SE and the cut common line CML. In other words, the electrical voltage applied through the pad electrode PD can be transmitted through the connecting electrode 125-1 to... Figure 10a The common electrode CME. (Refer to...) Figure 10c The electrical voltage can be transmitted in parallel through the voltage transfer electrode VTE to Figure 10a The common electrode CME.

[0206] Reference Figure 10dThe voltage transfer electrode VTE may also have a cut region VTE-C defined corresponding to the cut region SE-C of the auxiliary electrode SE. The width and length of the cut region SE-C of the auxiliary electrode SE and the cut region VTE-C of the voltage transfer electrode VTE are not necessarily the same. Here, the pad electrode PD and the common electrode CME may be electrically connected only through a channel defined by the second contact electrode 135 and the connecting electrode 125-1. In embodiments of the inventive concept, the first portion VTE-1 of the voltage transfer electrode VTE may be omitted. The second portion SE-2 of the voltage transfer electrode VTE may correspond to the first conductive layer of the pad electrode PD.

[0207] Reference Figure 10e The edge (or end) of the second part SE-2 of the auxiliary electrode SE may not be aligned with the edge of the voltage transmission electrode VTE in the plane. The distal ends of the first auxiliary electrode SE1 of the second part SE-2 and the second auxiliary electrode SE2 of the second part SE-2 may be disposed in the plane inside the voltage transmission electrode VTE.

[0208] Reference Figure 10f When compared with reference Figures 10a to 10e Compared to the described display device, the voltage transfer electrode VTE can be omitted. Because the voltage transfer electrode VTE is omitted, therefore... Figure 10c The first part SE-1 and the second part SE-2 can be electrically connected to each other only through the channel defined by the second contact electrode 135 and the connecting electrode 125-1.

[0209] Figure 11a This is a cross-sectional view showing a display device according to an embodiment of the inventive concept. Figure 11b This is a cross-sectional view showing a light-emitting diode LED-1 according to an embodiment of the inventive concept. Figure 11c This is a detailed cross-sectional view showing a first electrode structure ES10 according to an embodiment of the inventive concept.

[0210] Figure 11a Corresponding to Figure 4b And the same reference numerals are used for Figure 4b and Figure 11a The same components shown. In the following description, the focus will be on... Figure 4b and Figure 11a Different constructions are shown in the diagram.

[0211] exist Figure 11a In this embodiment, a light-emitting diode (LED-1) with an inverted structure can be used. In this embodiment, the first electrode structure ES10 is described as a cathode (or cathode structure), and the second electrode structure ES20 is described as an anode (or anode structure).

[0212] like Figure 11bAs shown, a semiconductor junction structure SJS-1 is disposed on a first electrode structure ES10, and the first electrode structure ES10 is disposed on the semiconductor junction structure SJS-1. The semiconductor junction structure SJS-1 may include an n-type semiconductor layer SN disposed on the first electrode structure ES10, an active layer ACT disposed on the n-type semiconductor layer SN, and a p-type semiconductor layer SP disposed on the active layer ACT. In an embodiment of the inventive concept, an electron blocking layer may also be disposed between the active layer ACT and the p-type semiconductor layer SP. In an embodiment of the inventive concept, the light-emitting diode LED-1 may also include a cladding layer or a TSBR layer.

[0213] The n-type semiconductor layer SN may include a first portion SN-P1 having a larger diameter (or horizontal length in cross-section) and positioned closer to the first electrode structure ES10, and a second portion SN-P2 having a smaller diameter (or horizontal length in cross-section) and positioned further away from the first electrode structure ES10. A stepped portion may be formed between the first portion SN-P1 and the second portion SN-P2. The side surface of the first portion SN-P1 may be an inclined surface ICS tilted relative to the first electrode structure ES10, and the side surface of the second portion SN-P2 may be substantially perpendicular to the first electrode structure ES10.

[0214] The second electrode structure ES20 may include a transparent conductive oxide layer. The second electrode structure ES20 may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc tin oxide (ZTO), and indium gallium zinc oxide (IGZO).

[0215] The first electrode structure ES10 can have Figure 11c The layered structure shown. When with Figure 4e Compared to the stacked structure, the first transparent conductive oxide layer TCO1 and the second barrier layer BRL2 can be omitted. The first electrode structure ES10 may include a metal layer ML-C disposed on the first barrier layer BRL1. The metal layer ML-C has Figure 4e The reflective layer RL and the electron injection layer are defined in the structure. The metal layer ML-C can have a multilayer structure and may include a first metal layer corresponding to the reflective layer. The metal layer ML-C may also include a second metal layer having a work function smaller than that of the reflective layer. The metal layer ML-C may include a magnesium alloy or an aluminum alloy. In an embodiment of the inventive concept, in the first electrode structure ES10, the reflective layer RL and the electron injection layer are defined in the structure. Figure 4f Compared to the stacked structure, the first transparent conductive oxide layer TCO1 and the second barrier layer BRL2 can be omitted. Furthermore, the aforementioned metal layer ML-C can be provided instead of the reflective layer RL.

[0216] Refer again Figure 11aThe second side insulating layer SI2 can contact a portion of each of the side surfaces of the semiconductor junction structure SJS-1 and the second electrode structure ES20. The second side insulating layer SI2 contacts the side surfaces of the p-type semiconductor layer SP, the active layer ACT, and the second portion SN-P2, and the second side insulating layer SI2 can be exposed. Figure 11b The inclined surface ICS described in the figure. The second side insulating layer SI2 can also be disposed on a portion of the top surface of the second electrode structure ES20.

[0217] A first insulating layer SI1 is disposed outside the second insulating layer SI2. The first insulating layer SI1 may contact the inclined surface ICS. A first opening COP1 is defined within the first insulating layer SI1 and the second insulating layer SI2.

[0218] A side reflective layer SRL is disposed outside the first side insulating layer SI1. In this embodiment, the side reflective layer SRL is shown as being continuously disposed on adjacent light-emitting diodes LED-1, but embodiments of the inventive concept are not limited thereto. Figure 4b As shown, the side reflective layers SRL can be separated and spaced apart in the boundary region BA. In this embodiment, unlike the first side insulating layer SI1, the side reflective layers SRL are not disposed on the top surface of the second electrode structure ES20, but are not limited thereto.

[0219] According to this embodiment, with Figure 4e Unlike other regions, the planarization layer 140 is omitted. The boundary region BA is defined by light-emitting diodes (LEDs) LED-1. Areas where LEDs LED-1 are not arranged or interspersed correspond to the boundary region BA. For example, when the LEDs LED-1 are arranged in a matrix, the boundary region BA between the LEDs LED-1 can have a grid shape on the plane. Figure 11a In the diagram, the boundary region BA is shown on the side surface based on the first electrode structure ES10.

[0220] The auxiliary electrode SE set in the boundary region BA can have the following characteristics: Figure 3b The grid shape shown. Figure 11a The diagram shows a second auxiliary electrode SE2 as part of the auxiliary electrode SE. The second auxiliary electrode SE2 may include a metal structure SE2-1 and a barrier layer SE2-2 disposed between the metal structure SE2-1 and the second trench TC2. Since the second auxiliary electrode SE2 is not formed on... Figure 4b Instead of being located in the second trench TC2, the second auxiliary electrode SE2 is disposed in the region between the light-emitting diodes LED-1, so the second auxiliary electrode SE2 can have different widths depending on the area in the cross-section.

[0221] During the manufacturing process, a planarization process, such as a grinding process, is performed, thus providing a flat top surface for the side reflective layer SRL and the auxiliary electrode SE. A portion of the first side insulating layer SI1 may also be removed during the planarization process. The common electrode CME is disposed on the top surface provided by the side reflective layer SRL and the auxiliary electrode SE, and can be electrically connected to the second electrode structure ES20 through the first opening COP1.

[0222] It will be apparent to those skilled in the art that various modifications and variations can be made to the inventive concept. Therefore, the inventive concept is intended to cover modifications and variations thereof, provided they fall within the scope of the appended claims and their equivalents. Thus, to the greatest extent permitted by law, the scope of the inventive concept will be determined by the broadest permissible interpretation of the appended claims and their equivalents, and should not be bound or limited by the foregoing detailed description.

[0223] Industrial applicability Various electronic devices are being developed, such as VR (virtual reality) devices, AR (augmented reality) devices, and MR (mixed reality) devices. These devices include high-resolution displays. This invention provides a high-resolution display device that can be applied to the aforementioned electronic devices.

Claims

1. A display device, the display device comprising: Complementary metal-oxide-semiconductor (CMOS) wafers; as well as Multiple light-emitting diodes are disposed on the CMOS wafer and are arranged in a plane in a first region of the CMOS wafer. Each of the plurality of light-emitting diodes includes: a first electrode structure; an emission layer disposed on the first electrode structure; and a second electrode structure disposed on the emission layer. The first electrode structure includes: a metal layer; a reflective layer disposed on the metal layer; and a first transparent conductive oxide layer disposed on the reflective layer.

2. The display device according to claim 1, wherein, The metal layer includes at least one of gold (Au), copper (Cu), silver (Ag), tin (SN), titanium (Ti), zirconium (Zr), and tantalum (Ta), or an alloy of at least two of the aforementioned metals.

3. The display device according to claim 1, wherein, The metal layer includes a first metal layer and a second metal layer disposed on the first metal layer. The first metal layer comprises any one of gold (Au), copper (Cu), silver (Ag), tin (SN), titanium (Ti), zirconium (Zr), and tantalum (Ta), and The second metal layer includes another of gold (Au), copper (Cu), silver (Ag), tin (SN), titanium (Ti), zirconium (Zr), and tantalum (Ta).

4. The display device according to claim 3, wherein, The metal layer further includes a third metal layer disposed on the second metal layer. The third metal layer comprises any one of gold (Au), copper (Cu), silver (Ag), tin (SN), titanium (Ti), zirconium (Zr), and tantalum (Ta), and The third metal layer comprises a metal different from that of the second metal layer.

5. The display device according to claim 1, wherein, The first electrode structure further includes: A first barrier layer is disposed between the metal layer and the reflective layer; and A second barrier layer is disposed between the reflective layer and the first transparent conductive oxide layer. Each of the first barrier layer and the second barrier layer includes a nitride layer made of a barrier metal nitride.

6. The display device according to claim 5, wherein, The first barrier layer further includes a barrier metal layer disposed on at least one of the upper and lower sides of the nitride layer made of the barrier metal nitride. The barrier metal layer includes titanium (Ti) or tantalum (Ta).

7. The display device according to claim 1, wherein, The first electrode structure also includes a barrier layer disposed beneath the metal layer. The barrier layer includes titanium nitride or tantalum nitride.

8. The display device according to claim 1, wherein, The CMOS wafer includes: A silicon substrate, in which an active region / drain region is defined; A gate is disposed on the silicon substrate; A first insulating layer covers the gate and is disposed on the silicon substrate; The first contact electrode is electrically connected to the source / drain region through a first contact hole defined in the first insulating layer; A second insulating layer covers the first contact electrode and is disposed on the first insulating layer; and The second contact electrode is electrically connected to the first contact electrode and to the first metal structure through a second contact hole passing through the second insulating layer.

9. The display device according to claim 8, wherein, The second contact electrode includes: A metal structure is disposed inside the second contact hole; and A barrier layer is disposed between the side surface of the metal structure and the inner surface of the second contact hole, and also between the bottom surface of the metal structure and the top surface of the first contact electrode exposed through the second contact hole. The barrier layer comprises a metal layer made of barrier metal and a nitride layer made of barrier metal nitride.

10. The display device according to claim 8, wherein, The top surface of the second contact electrode is concave.

11. The display device according to claim 1, wherein, The second electrode structure includes a second transparent conductive oxide layer.

12. The display device according to claim 11, wherein, The second electrode structure is the cathode of each of the plurality of light-emitting diodes, and The second electrode structure further includes an electrode metal layer disposed between the second transparent conductive oxide layer and the semiconductor junction structure.

13. The display device according to claim 11, wherein, The second electrode structure is the anode of each of the plurality of light-emitting diodes. The first electrode structure is the cathode of each of the plurality of light-emitting diodes. The emitter layer includes: an n-type semiconductor layer; an active layer disposed on the n-type semiconductor layer; and a p-type semiconductor layer disposed on the active layer. The n-type semiconductor layer includes a first portion and a second portion having a width smaller than that of the first portion in cross-section. The side surface of the second part is an inclined surface that is tilted relative to the first electrode structure.

14. The display device according to claim 1, wherein, On a plane, the emission layer is disposed inside the first electrode structure.

15. The display device according to claim 1, further comprising: A first insulating layer is disposed on the side surface of the first electrode structure, the side surface of the emission layer, the side surface of the second electrode structure, and the top surface of the second electrode structure; as well as A side reflective layer is disposed outside the first side insulating layer.

16. The display device according to claim 15, wherein, The side reflective layer corresponds at least to the side surface of the first electrode structure, the side surface of the emitting layer, and the side surface of the second electrode structure.

17. The display device according to claim 15, further comprising a second side insulating layer, in, A portion of the top surface of the first electrode structure is exposed by the emission layer. The second side insulating layer is disposed inside the first side insulating layer and corresponds to the top surface of the first electrode structure, the side surface of the emitter layer, the side surface of the second electrode structure, and the top surface of the second electrode structure. An opening is defined in the side reflective layer, the first side insulating layer, and the second side insulating layer, through which a portion of the top surface of the second electrode structure is exposed.

18. The display device according to claim 17, further comprising a common electrode, in, The plurality of light-emitting diodes includes a first light-emitting diode and a second light-emitting diode. The common electrode is configured to electrically connect the second electrode structure of the first light-emitting diode to the second electrode structure of the second light-emitting diode, and The common electrode is adhered to a portion of the top surface of the second electrode structure through the opening.

19. The display device according to claim 1, further comprising: A planarization layer is disposed on the CMOS wafer and is configured to correspond to the side surface of the first electrode structure and the side surface of the emitter layer; as well as A common electrode, comprising the second electrode structure disposed on the planarization layer and electrically connected to each of the plurality of light-emitting diodes. Wherein, on a plane, the first region of the CMOS wafer includes a plurality of unit regions in which the plurality of light-emitting diodes are disposed, and boundary regions between the plurality of unit regions, and The planarization layer is superimposed on the plurality of unit regions and the boundary regions.

20. The display device according to claim 19, further comprising auxiliary electrodes, in, The planarization layer defines a plurality of first trenches that overlap with the boundary region and extend in a first direction, and a plurality of second trenches that overlap with the boundary region and extend in a second direction that intersects the first direction. The auxiliary electrode is disposed inside the plurality of first trenches and the plurality of second trenches, and is electrically connected to the common electrode.

21. The display device according to claim 20, wherein, The auxiliary electrode includes: A metal structure is disposed inside the plurality of first trenches and the plurality of second trenches; and A barrier layer is disposed between the metal structure and the plurality of first trenches and the plurality of second trenches.

22. The display device according to claim 1, further comprising a plurality of dummy light-emitting diodes disposed on a plane in a second region outside the first region of the CMOS wafer. in, The plurality of dummy LEDs do not emit light.

23. The display device of claim 22, further comprising a common electrode, the common electrode being stacked with the first region and the second region and electrically connected to the second electrode structure of each of the plurality of light-emitting diodes. in, The common electrode is not electrically connected to the plurality of dummy LEDs.

24. The display device according to claim 22, wherein, The plurality of dummy LEDs have the same stacked structure as the plurality of LEDs.

25. The display device according to claim 22, further comprising: A common electrode, superimposed on the first region and the second region, and electrically connected to the second electrode structure of each of the plurality of light-emitting diodes; A voltage transfer electrode extends from the common electrode to a third region outside the second region of the CMOS wafer; as well as A pad electrode is electrically connected to the voltage transmission electrode in the third region.

26. The display device of claim 25, further comprising a passivation layer stacked with the first region, the second region, and the third region, covering the common electrode and the voltage transmission electrode, and having an opening through which a connection region of the voltage transmission electrode is exposed. in, The pad electrode is electrically connected to the connection region of the voltage transmission electrode through the opening in the passivation layer.

27. The display device according to claim 25, further comprising a common line disposed below the voltage transmission electrode and electrically connected to the voltage transmission electrode.

28. The display device according to claim 27, wherein, The common line includes a first conductive structure having the same stacked structure as the first electrode structure.

29. The display device according to claim 28, wherein, The common line includes: An insulating structure is disposed on the top surface of the first conductive structure; and A second conductive structure is disposed on at least the first conductive structure and electrically connected to the first conductive structure.

30. The display device according to claim 29, further comprising: A planarization layer is disposed between the common line and the voltage transmission electrode, and a plurality of trenches are defined in the planarization layer; as well as An auxiliary electrode is disposed in the plurality of trenches and configured to electrically connect the common line to the voltage transmission electrode.

31. The display device according to claim 30, wherein, The auxiliary electrode extends from a region of each of the plurality of trenches and is electrically connected to the common line through a via through the planarization layer.

32. The display device according to claim 30, wherein, The third region of the CMOS wafer includes an inner region in which the common electrode is disposed and an outer region in which the common electrode is not disposed. The auxiliary electrode is configured to electrically connect the common electrode to the common line in the inner region.

33. The display device according to claim 1, further comprising: A common electrode, electrically connected to the second electrode structure of each of the plurality of light-emitting diodes to be superimposed on the first region; A pad electrode is disposed in the outer region of the first region to receive electrical voltage; An auxiliary electrode includes a first portion disposed below the common electrode and electrically connected to the common electrode, and a second portion spaced apart from the first portion, disposed below the pad electrode and electrically connected to the pad electrode; as well as The common line includes a first portion disposed below and electrically connected to the first portion of the auxiliary electrode, and a second portion disposed below and electrically connected to the second portion of the auxiliary electrode. The CMOS wafer includes a connection electrode that is electrically connected to each of the first portion and the second portion of the common line.

34. The display device according to claim 33, wherein, The CMOS wafer includes: A silicon substrate, in which an active region / drain region is defined; A gate is disposed on the silicon substrate; A first insulating layer covers the gate and is disposed on the silicon substrate; The first contact electrode is electrically connected to the source / drain region through a first contact hole defined in the first insulating layer; A second insulating layer covers the first contact electrode and is disposed on the first insulating layer; and The second contact electrode is electrically connected to the first contact electrode and to the first metal structure through a second contact hole passing through the second insulating layer. The connecting electrode and the first contact electrode are disposed on the same layer.

35. The display device according to claim 1, further comprising a plurality of lenses disposed on the plurality of light-emitting diodes to respectively correspond to the plurality of light-emitting diodes.

Images