FPGA-based multi-path printing nozzle driving circuit and system

Abstract

The application belongs to the field of printing drive circuit, and specifically discloses a multi-channel printing nozzle drive circuit and system based on FPGA. The application provides a unified reference voltage signal for all voltage regulating modules through a power supply module, ensures the consistency of the source of the multi-channel drive voltage, effectively avoids the initial voltage difference caused by the drift of multiple independent power supplies, and lays a stable foundation for printing uniformity. On this basis, each voltage regulating module accurately and independently adjusts the unified reference voltage according to the independent voltage regulating signal sent by the FPGA, thereby generating customized drive voltage. This architecture combines system stability and channel-level flexibility, effectively suppresses the fluctuation of ink drop shape and flight trajectory caused by inconsistent power supply, and realizes the ability to dynamically adjust the driving energy according to different nozzle characteristics or printing task requirements. Therefore, the scheme significantly improves the output consistency and stability of the multi-channel nozzle under long-time work.

Description

Technical Field

[0001] This application belongs to the field of print driver circuits, specifically relating to a multi-channel print head driver circuit and system based on FPGA. Background Technology

[0002] In an FPGA-based multi-channel printhead drive system, to achieve high-precision and high-efficiency printing, it is necessary to simultaneously meet core requirements such as stable data transmission, differentiated drive voltage signal supply, and precise synchronization of movement position.

[0003] However, existing technical solutions face several common bottlenecks in the architecture and implementation of such systems. First, there is a lack of a unified interface and signal connection structure between the FPGA and the printhead to adapt to the driving requirements of multiple printheads, making it difficult to transmit multiple control signals, power signals, and jet signals stably. Second, the high-voltage power supply required for printhead driving is often generated in a decentralized manner or has insufficient power supply stability, making it difficult to meet the high-voltage power supply consistency requirements when multiple printheads are working simultaneously. Third, based on a unified high-voltage power supply, existing systems often cannot provide independently adjustable drive voltage signals for different printhead channels, making it difficult to adapt to the differentiated needs of multiple printheads in terms of jet energy, printing density, or operating parameters. Fourth, there is usually a lack of a unified position closed-loop and timing coordination mechanism between the slide rail motion control and the multi-printhead jet control, which can easily lead to problems such as position deviation, synchronization error, and splicing inconsistency during continuous scanning and printing of multiple printheads.

[0004] Therefore, during high-speed reciprocating or long-stroke continuous printing, problems such as nozzle position deviation, scanning splicing misalignment between different printheads, and inconsistency in repeated areas of the image are likely to occur. Summary of the Invention

[0005] In view of the shortcomings of the existing technology, the purpose of this application is to provide a multi-channel printhead driving circuit and system based on FPGA, which aims to solve the problem that the current multi-channel printhead printing has poor accuracy in long-term working scenarios due to the limitations of voltage regulation and driving scheme.

[0006] The first aspect of this application relates to an FPGA-based multi-channel printhead driving circuit. In one embodiment, it includes: a first interface module, a power supply module, multiple voltage regulation modules, and a second interface module. Multiple first output terminals of the first interface module are respectively connected to the first input terminals of the multiple voltage regulation modules. Multiple output terminals of the power supply module are respectively connected to the second input terminals of the multiple voltage regulation modules. The output terminals of the multiple voltage regulation modules are respectively connected to the multiple first input terminals of the second interface module. The second output terminal of the first interface module is connected to the second input terminal of the second interface module. The first interface module is configured to receive input signals from an FPGA control unit and output voltage regulation signals from the input signals to the multiple voltage regulation modules, and output ink dot control signals from the input signals to the second interface module. The power supply module is configured to provide the same reference voltage signal to the multiple voltage regulation modules based on an external power supply signal. The voltage regulation modules are configured to adjust the reference voltage signal based on the voltage regulation signal to generate a driving voltage signal required by the printhead corresponding to the current voltage regulation module and output it to the second interface module. The second interface module is configured to distribute the multiple driving voltage signals and ink dot control signals to the corresponding printheads to achieve driving.

[0007] In one embodiment, the power supply module includes: an input unit and a boost unit; the input terminal of the input unit is connected to an external power supply, and the output terminal of the input unit is connected to the input terminal of the boost unit; multiple output terminals of the boost unit are respectively connected to the second input terminals of multiple voltage regulation modules; the input unit is configured to receive an externally input power supply voltage signal and filter it to output it to the boost unit; the boost unit is configured to boost the power supply voltage signal to a reference voltage signal that meets the back-end voltage regulation requirements.

[0008] In one embodiment, the input unit includes a first parallel network consisting of a fuse and a plurality of capacitors; wherein an external power supply is connected to the input terminal of the first parallel network through the fuse; and the output terminal of the first parallel network is connected to the input terminal of the boost unit.

[0009] In one embodiment, the boost unit includes: a second parallel network consisting of a high-frequency switching boost chip and a plurality of capacitors; the input terminal of the high-frequency switching boost chip is connected to the output terminal of the first parallel network; the input terminal of the high-frequency switching boost chip is connected to the input terminal of the second parallel network; and the output terminal of the second parallel network is connected to the input terminal of the voltage regulation module.

[0010] In one embodiment, the voltage regulation signal is a PWM signal; the voltage regulation module includes: a voltage regulation chip based on the PWM signal, a first capacitor, and a second capacitor; the output terminal of the power supply module is connected to the input terminal of the voltage regulation chip through the first capacitor; the output terminal of the voltage regulation chip is connected to the second interface module through the second capacitor.

[0011] In one embodiment, the FPGA-based multi-channel printhead driving circuit further includes: a position feedback module and a motor drive module; the output of the position feedback module is connected to the FPGA control unit; the input of the motor drive module is connected to the FPGA control unit; the position feedback module is configured to collect the current position information of the slide rail motor and output it to the FPGA control unit; the motor drive module is configured to receive the slide rail motor drive signal generated by the FPGA control unit based on the position information to execute the slide rail motor drive.

[0012] In one embodiment, the position feedback module includes an absolute encoder; the absolute encoder is mounted on a slide rail and is used to acquire the absolute position information of multiple printheads.

[0013] In one embodiment, the FPGA-based multi-channel printhead drive circuit further includes: an FPGA control unit; the FPGA control unit is configured to determine the printhead that should currently perform the jetting action based on the absolute position information, so as to generate a slide rail motor drive signal output to the motor drive module.

[0014] The second aspect of this application relates to an FPGA-based multi-channel printhead driving system, including the FPGA-based multi-channel printhead driving circuit of the first aspect.

[0015] In one embodiment, the FPGA-based multi-channel printhead driving system includes: an FPGA control unit, a first interface module, a power supply module, multiple voltage regulation modules, a second interface module, multiple printheads, a position feedback module, a motor drive module, and a slide rail motor; multiple first output terminals of the FPGA control unit are connected to the input terminals of the first interface module; multiple first output terminals of the first interface module are respectively connected to the first input terminals of the multiple voltage regulation modules; the input terminal of the power supply module is used to connect to an external power supply, and multiple output terminals of the power supply module are respectively connected to the second input terminals of the multiple voltage regulation modules; the output terminals of the multiple voltage regulation modules are respectively connected to the multiple first input terminals of the second interface module; the second output terminal of the first interface module is connected to the second input terminal of the second interface module; multiple output terminals of the second interface module are respectively connected to the input terminals of the multiple printheads; the detection terminal of the position feedback module is coupled to the slide rail motor structure, and the output terminal of the position feedback module is connected to the input terminal of the FPGA control unit; the second output terminal of the FPGA control unit is connected to the input terminal of the motor drive module; and the output terminal of the motor drive module is connected to the control terminal of the slide rail motor.

[0016] Overall, the technical solution of this application solves the printing accuracy problem and achieves significant technical effects through the synergistic effect of the following technical means: First, a single reference voltage signal is provided to all voltage regulation modules via a power supply module, ensuring the initial consistency and stability of the multi-path drive voltage from the source and avoiding differences in base voltage caused by drift of multiple independent power supply parameters. Based on this, multiple independent voltage regulation modules receive voltage regulation signals from the FPGA and independently and precisely adjust this unified reference voltage, thereby generating the required, independently adjustable drive voltage for each printhead. This design combines a unified and stable high-voltage source with independent and flexible voltage regulation. On the one hand, it fundamentally suppresses differences in droplet shape and flight trajectory caused by inconsistent power supplies; on the other hand, it enables the system to dynamically and precisely adjust the drive energy for different printheads or printing needs, thus significantly improving the output uniformity and stability of multiple printheads under long-term operation and achieving highly consistent print quality.

[0017] Secondly, by introducing a position feedback module containing an absolute encoder and sending its real-time feedback of the slide rail position information to the FPGA control unit, the FPGA can generate a synchronous injection control signal in real time.

[0018] This closed-loop collaborative mechanism ensures that the spraying action of each nozzle corresponds precisely to the instantaneous physical position of the slide rail, effectively eliminating the cumulative position error and synchronization deviation caused by open-loop control or inaccurate feedback. This enables precise control of the spray point position during dynamic continuous printing, solving the problems of image misalignment and inconsistent stitching, and ultimately achieving stable printing with long-term, high precision. Attached Figure Description

[0019] Figure 1 This is one of the structural block diagrams of the FPGA-based multi-channel printhead driving circuit provided in the embodiments of this application; Figure 2 This is a schematic diagram of the first interface module provided in an embodiment of this application; Figure 3 This is a schematic diagram of the second interface module provided in an embodiment of this application; Figure 4 This is a circuit topology diagram of the power supply module provided in the embodiments of this application; Figure 5 This is a circuit topology diagram of the voltage regulation module provided in the embodiments of this application; Figure 6 This is the second structural block diagram of the FPGA-based multi-channel printhead driving circuit provided in the embodiments of this application; Figure 7 This is a schematic diagram of position feedback provided in an embodiment of this application.

[0020] In all the accompanying drawings, the same reference numerals are used to denote the same elements or structures, wherein: 10 is the first interface module; 20 is the power supply module; 30 is the voltage regulation module; 40 is the second interface module. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0022] In this application, the term "and / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A existing alone, A and B existing simultaneously, and B existing alone. In this application, the symbol " / " indicates that the related objects are in an "or" relationship, for example, A / B means A or B.

[0023] In this application, the terms "first" and "second," etc., are used to distinguish different objects, not to describe a specific order of objects. For example, "first response message" and "second response message," etc., are used to distinguish different response messages, not to describe a specific order of response messages. The term "electrical connection" in this application can refer to a direct circuit connection or signal transmission via a communication protocol.

[0024] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0025] In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more, for example, multiple processing units means two or more processing units, multiple elements means two or more elements, etc.

[0026] Currently, due to limitations in voltage regulation and drive solutions, FPGA-based multi-head printers suffer from poor accuracy in long-term working scenarios.

[0027] Based on this, this application proposes a multi-channel printhead driving circuit based on FPGA. Please refer to... Figure 1 , Figure 1 This is one of the structural block diagrams of the FPGA-based multi-channel printhead driving circuit provided in the embodiments of this application.

[0028] In this embodiment, the FPGA-based multi-channel printhead driving circuit includes: a first interface module 10, a power supply module 20, multiple voltage regulation modules 30, and a second interface module 40.

[0029] It should be noted that the electrical connection relationship between the modules is as follows: The first interface module 10 has multiple first output terminals and one second output terminal. Its multiple first output terminals are respectively connected to the control input terminals of each voltage regulating module 30, that is, the first input terminals of the voltage regulating module 30, for transmitting independent control commands; its second output terminal is connected to the instruction input terminal of the second interface module 40, that is, the second input terminal of the second interface module 40, for transmitting another type of control signal.

[0030] It should be noted that the power supply module 20 has multiple output voltage terminals, which are connected one-to-one with the power input terminals of each voltage regulation module 30, i.e., the second input terminals of the voltage regulation module 30, to provide an energy source for each voltage regulation module. The output terminal of each voltage regulation module 30 is connected one-to-one with the corresponding drive voltage input terminal of the second interface module 40, i.e., the multiple first input terminals of its second interface module 40.

[0031] Understandably, this one-to-one connection means that on the physical line or logical channel, a designated port of one module is directly connected to a designated port of another module, forming a point-to-point signal or power transmission path, ensuring the independence and isolation of signals in each channel.

[0032] In addition, the input of the first interface module 10 should be connected to the FPGA control unit; the output of the second interface module 40 should be connected to the print head.

[0033] It should be noted that the first interface module 10 is configured to receive the input signal from the FPGA control unit, output the voltage regulation signal in the input signal to multiple voltage regulation modules 30, and output the ink dot control signal in the input signal to the second interface module 40.

[0034] Understandably, the core function of the first interface module 10 in the circuit is to receive digital signals from the upper-level FPGA control unit and decouple and distribute the composite signal. Specifically, the input signals issued by the FPGA typically include two types: one is a voltage regulation signal used to set the amplitude of the driving voltage, and the other is an ink droplet control signal, or jet timing signal, that controls when the printhead nozzle generates ink droplets. The first interface module 10 is configured to identify and separate these two types of signals, sending the voltage regulation signal in parallel to the corresponding voltage regulation modules 30 through its multiple first output terminals, while sending the ink droplet control signal to the second interface module 40 through its second output terminal. Physically, this module can be a circuit board or connector assembly that integrates level conversion, buffer driving, and signal routing functions.

[0035] It should be noted that the power supply module 20 is configured to provide the same reference voltage signal to multiple voltage regulation modules 30 based on an external power supply signal.

[0036] Understandably, the core function of the power supply module 20 is to generate a stable and clean common high-voltage DC power supply, i.e., a common reference voltage signal. Its workflow is as follows: it receives a lower voltage power signal from outside the system, and through internal power conversion and conditioning circuitry, boosts and stabilizes it to a high voltage level required for all printhead drives. For example, a fixed value within the range of 20V to 50V. This common reference voltage signal means that at any given time, the voltage supplied by the power supply module 20 to the power input terminals of all voltage regulation modules 30 has a highly consistent nominal value and static accuracy. This provides a unified and stable reference starting point for differentiated voltage regulation in the backend. One possible implementation of the power supply module 20 includes: an input filtering unit, such as a filter composed of a fuse, common-mode inductor, and filter capacitor; and a DC-DC boost converter unit. For example, a boost circuit composed of a high-efficiency switching regulator chip and its peripheral inductors, capacitors, and diodes.

[0037] It should be noted that the voltage regulating module 30 is configured to adjust the reference voltage signal based on the voltage regulating signal, and generate a drive voltage signal corresponding to the print head required by the current voltage regulating module 30, which is then output to the second interface module 40.

[0038] Understandably, the voltage regulating module 30 is the core unit for achieving independent adjustment of the drive voltage. Each voltage regulating module 30 operates independently, receiving two inputs: one is the same reference voltage signal from the power supply module 20, serving as its input power; the other is a dedicated voltage regulating signal from the first interface module 10, serving as a setting command for its output voltage. The voltage regulating module 30 is configured to reduce or linearly adjust the input reference voltage in real time according to the received voltage regulating signal, thereby generating a drive voltage signal corresponding to the printhead required by the current voltage regulating module.

[0039] For example, if the voltage regulation signal is a pulse width modulation (PWM) signal, the voltage regulation module 30 may include a PWM-to-analog voltage conversion circuit and a low dropout regulator (LDO) or a switching buck regulator, such as a Buck circuit. The feedback reference voltage of the LDO or Buck circuit is changed by adjusting the PWM duty cycle, thereby achieving continuous regulation of the output voltage. If the voltage regulation signal is a digital signal, such as an I2C or SPI command, the voltage regulation module 30 may include a programmable power management chip with a digital interface, allowing direct setting of the output voltage value via digital commands. The output voltage of each voltage regulation module can be independently set to different values ​​to suit the optimal operating voltage requirements of the specific printhead it is connected to.

[0040] It should be noted that the second interface module 40 is configured to distribute multiple drive voltage signals and ink dot control signals to the corresponding printheads to achieve drive.

[0041] Understandably, the second interface module 40 is a signal and power distribution hub. It receives inputs from two sources: one is a multi-channel drive voltage signal that has been independently regulated from each voltage regulating module 30; the other is an ink dot control signal from the first interface module 10. The second interface module 40 is configured to correctly route and distribute these signals to each physical printhead connected to it.

[0042] Specifically, it transmits the Nth drive voltage signal and the Nth ink dot control signal, typically consisting of multiple timing and data lines, to the corresponding pins of the Nth printhead. This achieves synchronized delivery of power and control logic. This functionality can be achieved through careful PCB routing design, isolating the signal lines of different channels to different output ports. Physically, the second interface module 40 typically manifests as one or more high-density, multi-pin connectors for reliable connection to the printhead.

[0043] In this embodiment, a unified reference voltage signal is provided to all voltage regulation modules through the power supply module, ensuring the consistency of the source of the multi-channel drive voltage. This effectively avoids initial voltage differences caused by the drift of multiple independent power supplies, laying a stable foundation for printing uniformity. Based on this, each voltage regulation module precisely and independently adjusts this unified reference voltage according to the independent voltage regulation signal sent by the FPGA, thereby generating a customized drive voltage. This architecture combines system stability with channel-level flexibility, fundamentally suppressing fluctuations in droplet shape and flight trajectory caused by inconsistent power supplies, and also enabling dynamic adjustment of drive energy according to different printhead characteristics or printing task requirements. Therefore, this solution significantly improves the output consistency and stability of multiple printheads under long-term operation.

[0044] Based on this, this application provides a specific implementation method. Please refer to the following in sequence. Figures 2 to 5 .

[0045] It should be noted that, Figure 2 This is a schematic diagram of the first interface module provided in an embodiment of this application; Figure 3 This is a schematic diagram of the second interface module provided in an embodiment of this application.

[0046] Understandably, the custom printed circuit board is equipped with an FPGA interface J1 and a printhead interface J2, which corresponds to the specific selection of the first interface module 10 and the second interface module 40; these are used to realize the signal and power connections between the FPGA control unit, the printhead execution unit, and related auxiliary circuits. Through the functional division and signal planning of the above interfaces, the multiple PWM voltage regulation signals and ink droplet signals required for printhead driving can be stably transmitted on a unified circuit platform, meeting the engineering application requirements of multi-channel printhead driving and motion coordinated control.

[0047] The FPGA interface J1 connects to the FPGA control board and serves as the primary input interface for control signals and low-voltage logic signals in the printhead drive system. This interface introduces multiple logic power and ground signals to provide stable operating power for the control, voltage regulation, and interface-related circuits on the board. Simultaneously, the J1 interface receives multiple PWM voltage regulation signals and ink droplet signals output from the FPGA. The multiple PWM voltage regulation signals are fed into various voltage regulation branches on the PCB board to separately adjust the high-voltage power supply formed after centralized voltage boosting, thereby creating a drive voltage suitable for different printheads or different ink droplet concentrations. The ink droplet signals, after signal transmission and distribution on the board, are sent to the printhead interface side as printhead ejection control-related signals. By centrally integrating multiple voltage regulation controls and ejection data controls into the FPGA interface side, unified programmable management of printhead drive parameter configuration, ejection timing control, and coordination with the slide rail movement is achieved.

[0048] The printhead interface J2 is directly connected to the printhead electrical interface, used to output printhead data and ignition signals processed by the PCB board to multiple printheads. Specifically, the J2 interface receives the printhead drive voltage output from each voltage regulation module and sends it to the corresponding printhead channel to achieve independent setting of the operating voltage of different printheads. On the other hand, it receives the ink droplet signal transmitted, matched, and distributed by the PCB board and outputs it to the corresponding printhead according to the printhead interface specification. Through the above settings, the printhead interface J2 realizes the unified output of power supply and jet control signals for multiple printheads, enabling each printhead to perform differentiated jetting tasks according to its own voltage regulation results in the same system. In addition, a ground terminal and auxiliary pins can be set in the interface to improve the stability of the power circuit and improve the operational reliability of the entire board under the condition of simultaneous operation of multiple channels.

[0049] In this embodiment, the power supply module 20 includes an input unit and a boost unit; the input terminal of the input unit is connected to an external power supply, and the output terminal of the input unit is connected to the input terminal of the boost unit; multiple output terminals of the boost unit are respectively connected to the second input terminals of multiple voltage regulation modules 30; the input unit is configured to receive externally input power supply voltage signals and filter them to output to the boost unit; the boost unit is configured to boost the power supply voltage signals to a reference voltage signal that meets the back-end voltage regulation requirements.

[0050] Understandably, the above connections constitute a two-stage power generation architecture. The input unit is configured to perform primary power reception and preprocessing functions. The external power input voltage signal here typically refers to DC power supplied by the system host or an external adapter, such as 12V or 24V. Filtering is a critical signal conditioning process designed to eliminate or suppress noise, surges, and electromagnetic interference from the mains or power lines, and to provide overcurrent protection for subsequent circuits.

[0051] Understandably, the boost unit is the core of the power supply module 20, configured to perform voltage conversion. This means that the boost unit needs to efficiently and stably boost the relatively low DC input voltage, which has been pre-processed by the input unit, to a higher, fixed voltage value. This voltage value needs to serve as a common reference for all subsequent independent voltage regulation by the voltage regulation modules 30. The reference voltage signal is a stable DC voltage, the value of which needs to be determined based on the drive voltage range of the printhead used, for example, it may be 20V, 30V, or 40V.

[0052] With this design, the stable and consistent "reference voltage signal" generated by the boost unit is distributed in parallel to each voltage regulation module 30 through its multiple outputs. This ensures that the initial power reference of all voltage regulation channels is exactly the same, providing a crucial prerequisite for achieving independent, accurate, and highly consistent voltage regulation in the back end.

[0053] Specifically, Figure 4 This is a circuit topology diagram of the power supply module provided in the embodiments of this application.

[0054] The input unit includes a first parallel network consisting of a fuse and multiple capacitors; an external power supply is connected to the input terminal of the first parallel network through the fuse; the output terminal of the first parallel network is connected to the input terminal of the boost unit.

[0055] It is understandable that an external main power supply, preferably a 48V DC power supply, is used as the input. After the main power supply is introduced into the printed circuit board via the interface, it is first pre-processed by a protection and filtering circuit. The filtering circuit consists of multiple sets of capacitors connected in parallel to suppress ripple and transient interference at the power input terminal, reduce the impact of external power fluctuations on the subsequent boost circuit, and thus improve the stability and reliability of the system power supply. The filtered DC power supply is then input to the boost unit.

[0056] The boost unit includes a second parallel network consisting of a high-frequency switching boost chip and multiple capacitors; the input terminal of the high-frequency switching boost chip is connected to the output terminal of the first parallel network; the input terminal of the high-frequency switching boost chip is connected to the input terminal of the second parallel network; and the output terminal of the second parallel network is connected to the input terminal of the voltage regulation module 30.

[0057] Understandably, the boost unit elevates the input low-to-medium voltage DC to the high-voltage DC level required by the subsequent nozzle drive circuit. The boost unit employs a high-frequency switching boost structure, using energy storage and release to stably convert the input voltage into a higher-voltage DC output.

[0058] In this embodiment, the boost unit output forms two high-voltage buses, positive and negative, corresponding to BUS+ and BUS respectively. This system provides a symmetrical and stable high-voltage power supply foundation for subsequent voltage regulation circuits. At the output of the boost unit, multiple sets of energy storage and filtering capacitors are installed on the printed circuit board to smooth the high-voltage bus, reducing voltage fluctuations and high-frequency noise in the high-voltage output, thereby improving the power supply stability during subsequent voltage regulation and printhead drive processes. This structure ensures that the boost circuit maintains a stable high-voltage output even when multiple printheads are operating simultaneously, preventing bus voltage dips or fluctuations from affecting the consistency and reliability of subsequent drive voltages.

[0059] By setting the aforementioned boost module circuit on the PCB board, the centralized generation and unified distribution of the high-voltage power required by the print head drive system are realized. This enables subsequent voltage regulation modules to form drive voltages adapted to the working requirements of different print heads on the basis of a unified high-voltage bus, thereby providing a power foundation for the synchronous, stable, and reliable operation of multiple print heads during the slide rail movement.

[0060] Specifically, Figure 5 This is a circuit topology diagram of the voltage regulation module provided in the embodiments of this application.

[0061] The voltage regulation signal is a PWM signal; the voltage regulation module 30 includes: a voltage regulation chip based on the PWM signal, a first capacitor and a second capacitor; the output terminal of the power supply module 20 is connected to the input terminal of the voltage regulation chip through the first capacitor; the output terminal of the voltage regulation chip is connected to the second interface module 40 through the second capacitor.

[0062] Understandably, the custom printed circuit board also includes multiple voltage regulation module circuits, used to independently adjust the drive voltage required by each printhead based on the high-voltage bus output from the boost module. This multiple voltage regulation module circuit, as a downstream unit in the PCB power supply and drive architecture, is responsible for distributing and converting the uniformly generated high-voltage bus according to channels into printhead drive voltages of different amplitudes. It is a key circuit structure for enabling multiple printheads to operate collaboratively at different working voltages.

[0063] It should be noted that the multi-channel voltage regulation module circuit uses the output of the BUS+ high-voltage bus and the BUS from the previous stage boost module. The high-voltage bus serves as the input power source and receives multiple PWM voltage regulation signals output from the FPGA. Each PWM voltage regulation signal corresponds to a voltage regulation branch, used to independently control the high-voltage bus level in the corresponding branch, thereby forming a drive voltage adapted to the working requirements of different printheads. In the specific implementation, each voltage regulation module can adopt a voltage regulation structure controlled by the PWM signal. By modulating the conduction timing, duty cycle, or equivalent output energy, the printhead drive voltage output by the corresponding branch can be continuously or steppedly adjusted within a preset range. Thus, multiple independent printhead drive voltages can be simultaneously formed on the same printed circuit board to meet the differentiated control requirements of different printhead channels in terms of jet density, working energy, or printing parameters.

[0064] In this embodiment, the multi-channel voltage regulation module is preferably composed of multiple independent voltage regulation branches connected in parallel. The diagram shows a single-channel voltage regulation circuit, which can be further combined by stacking. In practical applications, it can be expanded into a multi-channel structure according to the number of printheads and system design requirements. Each voltage regulation branch shares the high-voltage bus provided by the front-stage boost module electrically, but is driven by an independent PWM voltage regulation signal for control, thereby ensuring that the output voltage of each channel can be set independently. The output signals processed by each voltage regulation module are further sent to the printhead interface and cooperate with the ink droplet signals transmitted from the FPGA to the PCB board to form the data and drive signal outputs corresponding to each printhead, so as to realize the synchronous jetting control of multiple printheads on the same platform.

[0065] Understandably, to improve the stability and consistency of the voltage regulation outputs, the output of the voltage regulation module can also be equipped with filtering, energy storage, or voltage stabilization circuits to suppress voltage ripple, switching noise, and transient fluctuations generated during PWM regulation, thereby improving the stability of each drive voltage under continuous printing conditions. Through this structure, the multi-channel voltage regulation module can maintain the relative independence and stability of the output voltage of each branch even when multiple printheads are operating simultaneously, avoiding the impact of inter-channel coupling, voltage fluctuations, or load changes on the consistency and reliability of printhead ejection.

[0066] Understandably, by setting the aforementioned multi-channel voltage regulation module circuit on the PCB board, independent voltage regulation of each channel is achieved on the basis of a unified high-voltage bus. This allows the multi-channel PWM voltage regulation signals output by the FPGA to control the driving voltage of each printhead separately, and to work in conjunction with the ink droplet signal to form printhead data and ignition signal output that meet the printhead interface requirements. This provides a key driving voltage foundation for the synchronous, stable, and reliable operation of multiple printheads with different printhead voltages during the slide rail movement.

[0067] Furthermore, this application specifically improves the slide rail motor drive and position synchronization mechanism to achieve precise real-time correspondence between the printing action and the mechanical position. Please refer to... Figure 6 , Figure 6 This is the second structural block diagram of the FPGA-based multi-channel printhead driving circuit provided in the embodiments of this application.

[0068] In this embodiment, in addition to the above, the FPGA-based multi-channel printhead drive circuit also includes a position feedback module and a motor drive module.

[0069] The position feedback module's output is connected to the FPGA control unit; the motor drive module's input is connected to the FPGA control unit; the position feedback module is configured to collect the current position information of the slide rail motor and output it to the FPGA control unit; the motor drive module is configured to receive the slide rail motor drive signal generated by the FPGA control unit based on the position information, so as to execute the slide rail motor drive.

[0070] Understandably, the position feedback module's output is directly connected to the dedicated input port of the FPGA control unit. Its core function is to acquire the current motion position information of the slide rail motor in real time and convert this information into an electrical signal output that the FPGA can recognize. This position information typically includes direction, relative displacement, and absolute reference zero point.

[0071] Understandably, the input of the motor drive module is connected to the control signal output of the FPGA control unit. Its core function is to receive the slide rail motor drive signal generated by the FPGA control unit based on the aforementioned real-time position information and execute the drive of the motor. This slide rail motor drive signal is typically a combined signal containing direction, enable, and speed / position control commands. The role of the motor drive module is to convert and amplify the low-voltage logic control signals from the FPGA into current and voltage sufficient to drive the slide rail motor.

[0072] In this architecture, the FPGA control unit forms the core of a closed-loop control system. Its workflow is as follows: the position feedback module continuously acquires the actual position and feeds it back to the FPGA; the control logic inside the FPGA (such as a PID controller) compares the target position with the feedback position, calculates the control quantity, and generates the corresponding slide rail motor drive signal, which is then sent to the motor drive module; the motor drive module drives the slide rail motor to move, thus eliminating position errors. Simultaneously, the FPGA synchronously matches the real-time, high-precision position information with the printed image data, triggering the ink droplet control signal of the printhead at the most precise moment. This deeply integrated hardware closed-loop control fundamentally solves the problem of positioning error accumulation caused by the disconnect between motion and inkjet printing, ensuring the absolute accuracy of the ink droplet position and the consistency of multi-pass printing during high-speed continuous scanning printing.

[0073] In one feasible implementation, please refer to Figure 7 , Figure 7 This is a schematic diagram of position feedback provided in an embodiment of this application.

[0074] In one feasible implementation, the core component of the position feedback module is an absolute encoder. This absolute encoder is directly mounted on the slide rail, or on a transmission component that moves synchronously with the slide rail. Its detection end is mechanically coupled to the printhead carrier carrying multiple printheads, and is used to acquire and output the absolute position information of the printhead carrier in the slide rail direction in real time. The acquisition mentioned here refers to the encoder reading the position encoding pattern on the code disk or code ruler that moves relative to it through its internal sensing elements, such as an optical reader, magnetic element, or capacitive sensing unit. The absolute position information refers to a digital encoded value that corresponds one-to-one with the physical position of the slide rail and is independent of historical motion data.

[0075] Specifically, an absolute encoder is a multi-bit precision encoder. Taking the attached diagram as an example, a 3-bit precision absolute encoder divides its code disk into 2^3 = 8 unique sectors along the circumference. Each sector has a specific coding pattern consisting of 3 binary digits. When the printhead carrier moves, the encoder reader reads the 3-bit code of the current sector in real time. This code directly corresponds to a specific absolute position on the slide rail. An absolute encoder reads a fixed, globally unique code value at any given time. The system can determine its exact position immediately upon power-up, fundamentally avoiding the accumulation of position errors caused by pulse loss, interference, or power outages, thus providing higher system reliability.

[0076] In particular, the circular feedback structure of this absolute encoder can improve position accuracy by increasing the number of bits. In this way, the FPGA can obtain the precise position of the nozzle carrier in the slide rail direction in real time, and perform precise nozzle control based on this position data, providing a solid foundation for synchronous spraying of multiple nozzles.

[0077] It should be noted that the FPGA control unit is configured to determine the printhead that should perform the jetting action based on the absolute position information, so as to generate a slide rail motor drive signal output to the motor drive module.

[0078] Specifically, the processing unit first analyzes the signal output by the encoder to obtain the current absolute position encoding value. Then, through pre-calibration or calculation, an accurate mapping relationship is established between the absolute position encoding value and the coordinate system of the printing job. This mapping relationship forms the basis of the control logic, enabling the system to clearly determine whether the printhead carrier has entered the predetermined target printing area.

[0079] Understandably, when the processing unit determines that the printhead carrier has reached the target printing area, it further determines which printhead(s) should perform the spraying action at that moment based on the preset printing data and the layout parameters of the multi-head printhead.

[0080] Understandably, in a multi-head system, the physical installation positions of each printhead along the slide rail have a fixed offset. Therefore, the processing unit stores an independent position compensation value for each printhead. This compensation value represents the installation offset of the printhead relative to a unified positional reference point. During actual control, the processing unit combines the unified absolute position of the slide rail with the individual position compensation values ​​of each printhead in real time to generate an independent ink jet timing control signal for each printhead, precisely aligned with its physical position. This mechanism ensures that although the multiple printheads are not mechanically aligned, the ink droplets they eject are arranged strictly according to the relative positional relationship required by the target pattern on the printing medium, laying a crucial foundation for position synchronization in achieving high-quality multicolor printing, multifunction printing, or high-speed parallel printing.

[0081] It should be noted that in terms of multi-head control, the FPGA can perform unified scheduling and individual control of multiple printheads. For scenarios requiring simultaneous printing, the FPGA can control multiple printheads to spray synchronously at their corresponding positions based on a unified position reference. For scenarios requiring reduced interference, reduced power surges, or adaptation to different printhead response characteristics, the FPGA can also implement time-sharing spray control for multiple printheads. Regardless of whether synchronous or time-sharing methods are used, each printhead uses the actual position of the slide rail as the triggering basis, thereby avoiding the spray deviation problem caused by simply relying on fixed time interval control.

[0082] In this embodiment, the slide rail position feedback is directly introduced into the multi-head control logic, and the FPGA performs unified management and independent compensation for the multiple printheads. Compared with the traditional approach where slide rail motion control and individual printhead drive are separated, managing slide rail position information and multi-head control simultaneously through the same FPGA allows each printhead to share a unified clock reference in the time dimension and a unified position coordinate in the spatial dimension. This significantly reduces synchronization deviation, relative position drift, and splicing errors when multiple printheads are working in parallel. Especially in multi-color printing, multi-array printhead printing, or large-format scanning printing scenarios, this method can effectively ensure the boundary continuity, splicing consistency, and repeatability accuracy between the output patterns of different printheads.

[0083] In addition, this application proposes an FPGA-based multi-channel printhead driving system, including the FPGA-based multi-channel printhead driving circuit of the first aspect.

[0084] Specifically, the FPGA-based multi-channel printhead drive system includes: an FPGA control unit, a first interface module, a power supply module, multiple voltage regulation modules, a second interface module, multiple printheads, a position feedback module, a motor drive module, and a slide rail motor; multiple first output terminals of the FPGA control unit are connected to the input terminals of the first interface module; multiple first output terminals of the first interface module are respectively connected to the first input terminals of the multiple voltage regulation modules; the input terminal of the power supply module is used to connect to an external power supply, and multiple output terminals of the power supply module are respectively connected to the second input terminals of the multiple voltage regulation modules; the output terminals of the multiple voltage regulation modules are respectively connected to the multiple first input terminals of the second interface module; the second output terminal of the first interface module is connected to the second input terminal of the second interface module; multiple output terminals of the second interface module are respectively connected to the input terminals of the multiple printheads; the detection terminal of the position feedback module is coupled to the slide rail motor structure, and the output terminal of the position feedback module is connected to the input terminal of the FPGA control unit; the second output terminal of the FPGA control unit is connected to the input terminal of the motor drive module; and the output terminal of the motor drive module is connected to the control terminal of the slide rail motor.

[0085] It is understandable that this drive system integrates the drive circuit with the FPGA control unit, print head, position feedback module and slide rail motor to form a complete closed-loop control system, thereby achieving a technical effect at the system level that surpasses the simple superposition of individual components.

[0086] First, the system employs a unified power supply and independent voltage regulation architecture to provide a stable and consistent driving voltage for multiple printheads, allowing for precise independent adjustment. This fundamentally ensures the consistency of multi-channel output, significantly improving the uniformity and color / density stability of the overall printed image. Second, the system innovatively integrates high-precision position feedback, real-time FPGA position calculation, and printhead ejection control, achieving strict synchronization between ejection motion and the spatial position of the slide rail. This completely solves the problems of position accumulation error and image stitching misalignment in continuous motion printing, achieving extremely high positioning accuracy. Finally, through the close collaboration of the aforementioned hardware and closed-loop logic, the system seamlessly connects power management, independent multi-channel drive, precision motion control, and ejection timing generation. This not only significantly improves the reliability and consistency of print quality during long-term operation but also enhances its adaptability to different printing tasks and complex processes.

[0087] Compared with the prior art, the beneficial effects of the FPGA-based multi-channel printhead driving system provided in this application are the same as those of the FPGA-based multi-channel printhead driving circuit provided in the above embodiments, and will not be repeated here.

[0088] It should be understood that expressions such as “comprising” and “may include” used in this application indicate the existence of the disclosed functions, operations, or constituent elements, and do not limit one or more additional functions, operations, and constituent elements. In this application, terms such as “comprising” and / or “having” are to be interpreted as indicating a particular characteristic, number, operation, constituent element, component, or combination thereof, but not to exclude the existence or possibility of adding one or more other characteristics, numbers, operations, constituent elements, components, or combinations thereof.

[0089] Furthermore, in this application, the expression "and / or" includes any and all combinations of the associated listed words. For example, the expression "A and / or B" may include A, may include B, or may include both A and B.

[0090] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A multi-channel printhead driving circuit based on FPGA, characterized in that, include: The system comprises a first interface module, a power supply module, multiple voltage regulation modules, and a second interface module. The first output terminals of the first interface module are respectively connected to the first input terminals of the multiple voltage regulating modules; the multiple output terminals of the power supply module are respectively connected to the second input terminals of the multiple voltage regulating modules; the output terminals of the multiple voltage regulating modules are respectively connected to the multiple first input terminals of the second interface module; the second output terminal of the first interface module is connected to the second input terminal of the second interface module. The first interface module is configured to receive the input signal from the FPGA control unit, output the voltage regulation signal in the input signal to multiple voltage regulation modules, and output the ink dot control signal in the input signal to the second interface module; The power supply module is configured to provide the same reference voltage signal to multiple voltage regulation modules based on an external power supply signal; The voltage regulation module is configured to adjust the reference voltage signal based on the voltage regulation signal, and generate a drive voltage signal required by the print head corresponding to the current voltage regulation module, which is then output to the second interface module. The second interface module is configured to distribute multiple drive voltage signals and ink dot control signals to the corresponding printheads to achieve drive.

2. The FPGA-based multi-channel printhead driving circuit as described in claim 1, characterized in that, The power supply module includes: an input unit and a boost unit; The input terminal of the input unit is connected to an external power supply, and the output terminal of the input unit is connected to the input terminal of the boost unit; the multiple output terminals of the boost unit are respectively connected to the second input terminals of the multiple voltage regulating modules one by one. The input unit is configured to receive an externally input power voltage signal and filter it for output to the boost unit; The boost unit is configured to boost the power supply voltage signal to a reference voltage signal that meets the back-end voltage regulation requirements.

3. The FPGA-based multi-channel printhead driving circuit as described in claim 2, characterized in that, The input unit includes: a fuse, and a first parallel network consisting of multiple capacitors; The external power supply is connected to the input terminal of the first parallel network via a fuse; the output terminal of the first parallel network is connected to the input terminal of the boost unit.

4. The FPGA-based multi-channel printhead driving circuit as described in claim 3, characterized in that, The boost unit includes: a high-frequency switching boost chip and a second parallel network composed of multiple capacitors; The input terminal of the high-frequency switching boost chip is connected to the output terminal of the first parallel network; the input terminal of the high-frequency switching boost chip is connected to the input terminal of the second parallel network; the output terminal of the second parallel network is connected to the input terminal of the voltage regulation module.

5. The FPGA-based multi-channel printhead driving circuit as described in claim 1, characterized in that, The voltage regulation signal is a PWM signal; The voltage regulation module includes: a voltage regulation chip based on a PWM signal, a first capacitor, and a second capacitor; The output terminal of the power supply module is connected to the input terminal of the voltage regulator chip through the first capacitor; the output terminal of the voltage regulator chip is connected to the second interface module through the second capacitor.

6. The FPGA-based multi-channel printhead driving circuit as described in claim 1, characterized in that, The FPGA-based multi-channel printhead drive circuit also includes: a position feedback module and a motor drive module; The output of the position feedback module is connected to the FPGA control unit; the input of the motor drive module is connected to the FPGA control unit. The position feedback module is configured to collect the current position information of the slide rail motor and output it to the FPGA control unit; The motor drive module is configured to receive the slide rail motor drive signal generated by the FPGA control unit based on the position information, so as to execute the slide rail motor drive.

7. The FPGA-based multi-channel printhead drive circuit as described in claim 6, characterized in that, The position feedback module includes: an absolute encoder; The absolute encoder is mounted on the slide rail and is used to collect the absolute position information of multiple printheads.

8. The FPGA-based multi-channel printhead driving circuit according to claim 7, characterized in that, The FPGA-based multi-channel printhead drive circuit also includes: an FPGA control unit; The FPGA control unit is configured to determine the printhead that should perform the jetting action based on the absolute position information, so as to generate a slide rail motor drive signal and output it to the motor drive module.

9. A multi-channel printhead driving system based on FPGA, characterized in that, Includes an FPGA-based multi-channel printhead drive circuit as described in any one of claims 1 to 8.

10. The FPGA-based multi-channel printhead driving system as described in claim 9, characterized in that, The FPGA-based multi-channel printhead drive system includes: an FPGA control unit, a first interface module, a power supply module, multiple voltage regulation modules, a second interface module, multiple printheads, a position feedback module, a motor drive module, and a slide rail motor; The FPGA control unit has multiple first output terminals connected to the input terminals of the first interface module; the multiple first output terminals of the first interface module are respectively connected to the first input terminals of the multiple voltage regulation modules; the input terminal of the power supply module is used to connect to an external power supply, and the multiple output terminals of the power supply module are respectively connected to the second input terminals of the multiple voltage regulation modules. The output terminals of the multiple voltage regulating modules are respectively connected to the multiple first input terminals of the second interface module; the second output terminal of the first interface module is connected to the second input terminal of the second interface module; the multiple output terminals of the second interface module are respectively connected to the input terminals of the multiple printheads. The detection end of the position feedback module is coupled to the slide rail motor structure, and the output end of the position feedback module is connected to the input end of the FPGA control unit; the second output end of the FPGA control unit is connected to the input end of the motor drive module; and the output end of the motor drive module is connected to the control end of the slide rail motor.

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