A direct current system insulation resistance monitoring method based on time sequence phase locking

Abstract

This application provides a DC system insulation resistance monitoring method based on time-phase locking, relating to the field of DC system monitoring technology. The method includes the following steps: injecting a sinusoidal voltage into the DC system at a preset frequency and acquiring the sampling voltage across a sampling resistor in real time; using a digital phase-locked loop (PLL) to track the phase difference between the injected voltage and the sampling voltage in real time, and based on the phase information output by the PLL, acquiring the maximum value and the corresponding first injected voltage value when the sampling voltage reaches its maximum value, and acquiring the corresponding second injected voltage value when the sampling voltage crosses zero; calculating the current insulation resistance value based on the acquired maximum sampling voltage value, the corresponding first injected voltage value, and the second injected voltage value corresponding to the zero-crossing point of the sampling voltage. This solution achieves precise alignment between the sampling time and the characteristic points of the sampling voltage, improves the accuracy and repeatability of insulation resistance measurement, and also possesses adaptive compensation capabilities.

Description

Technical Field

[0001] This invention belongs to the field of DC system monitoring technology, specifically relating to a DC system insulation resistance monitoring method based on time-phase locking. Background Technology

[0002] DC systems are widely used in photovoltaic power generation, electric vehicles, DC charging piles, lithium battery energy storage, and other fields. The insulation resistance between the positive and negative terminals and ground is a key indicator for measuring system safety. When the insulation resistance decreases, it may cause leakage, short circuits, or even fires. Therefore, real-time online monitoring of the insulation resistance is necessary.

[0003] An existing technology provides a method for monitoring the insulation resistance of a DC system via AC voltage injection. This method injects a sinusoidal AC signal between the positive and negative terminals of the DC system and the ground, and uses an RC DC blocking circuit to sample the ground current. The insulation resistance is calculated using the maximum value of the sampled voltage and the injected voltage value corresponding to the zero-crossing point. Compared to the traditional square wave injection method, this method effectively reduces the impact of ground capacitance and DC voltage on measurement accuracy.

[0004] However, this method has a key problem in practical applications: the accuracy of the sampling time is difficult to guarantee. Because the measurement circuit contains components such as DC blocking capacitors and sampling resistors, the RC circuit formed by these components introduces a fixed phase shift, causing the maximum value and zero-crossing points of the sampled voltage to deviate from their theoretical positions. Furthermore, this phase shift changes with variations in system operating temperature, component aging, and dynamic adjustments to the injection frequency. Existing methods lack a mechanism for identifying and compensating for this phase shift, resulting in a persistent deviation in the sampling time that cannot be automatically corrected. This leads to systematic errors in the insulation resistance calculation results, affecting monitoring accuracy and long-term stability. Summary of the Invention

[0005] In view of the above-mentioned defects or deficiencies in the prior art, a method for monitoring the insulation resistance of a DC system based on timing phase locking is provided, which adopts the following measurement circuit: a bridge resistor is connected to the positive and negative terminals of the DC system respectively, the common terminal of the two bridge resistors is connected to the first terminal of the first resistor, the second terminal of the first resistor is connected to the negative terminal of the injected voltage source, the positive terminal of the injected voltage source is grounded, and the DC blocking capacitor is connected in series with the sampling resistor and then in parallel across the two terminals of the first resistor. The method includes the following steps: A sinusoidal voltage is injected into the DC system at a preset frequency, and the sampling voltage across the sampling resistor is collected in real time. A digital phase-locked loop is used to track the phase difference between the injected voltage and the sampled voltage in real time. Based on the phase information output by the digital phase-locked loop, the maximum value and the corresponding first injected voltage value are collected when the sampled voltage reaches its maximum value, and the corresponding second injected voltage value is collected when the sampled voltage crosses zero. Based on the maximum value of the sampled voltage and the corresponding first injection voltage value, and the second injection voltage value corresponding to the zero-crossing point of the sampled voltage, the current insulation resistance value is calculated.

[0006] According to the technical solution provided in this application, the method of using a digital phase-locked loop to track the phase difference between the injected voltage and the sampled voltage in real time includes the following steps: The injected voltage is used as a reference signal input to the digital phase-locked loop. The phase detector of the digital phase-locked loop detects the phase difference between the injected voltage and the sampled voltage, and generates a phase error signal. The phase error signal is filtered by a loop filter and then input to a voltage-controlled oscillator or a numerically controlled oscillator to generate a synchronization reference signal that is synchronized with the injected voltage. The analog-to-digital converter is triggered by the rising or falling edge of the synchronization reference signal to sample the maximum value point and the zero crossing point of the sampled voltage, respectively. Specifically, when the phase difference between the synchronization reference signal and the sampling voltage is locked to zero, the sampling time is precisely aligned with the characteristic point of the sampling voltage.

[0007] According to the technical solution provided in this application, before triggering the analog-to-digital converter with the rising or falling edge of the synchronization reference signal to sample the maximum value point and zero-crossing point of the sampled voltage, the method further includes the following steps: After system startup or injection frequency adjustment, perform phase offset self-calibration: Inject a sinusoidal voltage into the DC system at the current injection frequency, continuously collect the sampled voltage waveform for multiple cycles, determine the true phase position of the maximum value point of the sampled voltage, and determine the first phase offset between the true phase position and the rising or falling edge of the synchronization reference signal. Determine the true phase position of the zero-crossing point of the sampled voltage, and determine the second phase offset between the true phase position and the rising or falling edge of the synchronization reference signal; The phase offset is stored in the calibration parameter table, which records the first phase offset between the maximum value point of the sampled voltage and the synchronization reference signal at different injection frequencies, and the second phase offset between the zero crossing point of the sampled voltage and the synchronization reference signal. During subsequent normal measurements, the corresponding first phase offset and second phase offset are retrieved from the calibration parameter table according to the current injection frequency. The sampling of the maximum value point of the sampling voltage is triggered after the first phase offset is superimposed on the rising or falling edge of the synchronization reference signal, and the sampling of the zero-crossing point of the sampling voltage is triggered after the second phase offset is superimposed.

[0008] According to the technical solution provided in this application, the method further includes dynamically adjusting the injection frequency of the sinusoidal voltage; The dynamic adjustment of the injection frequency of the sinusoidal voltage includes the following steps: Based on the calculated insulation resistance value, combined with the ratio of the maximum value of the sampling voltage at the current injection frequency to the corresponding first injection voltage value, and the second injection voltage value corresponding to the zero crossing point of the sampling voltage, the current value of the capacitance to ground is estimated by solving the impedance equation containing the capacitance to ground parameter. The current value of the capacitance to ground is compared with a preset capacitance threshold range. If the current capacitance to ground value falls within the first threshold range, the injection frequency is adjusted to the first frequency; if the current capacitance to ground value falls within the second threshold range, the injection frequency is adjusted to the second frequency. The first frequency and the second frequency correspond to the operating points where the sensitivity of the sampling voltage amplitude to capacitance changes is zero or close to zero, so that at the adjusted frequency, the maximum value of the sampling voltage and the corresponding injection voltage value, as well as the injection voltage value corresponding to the zero-crossing point of the sampling voltage, are minimally affected by the fluctuation of the capacitance to ground.

[0009] According to the technical solution provided in this application, the calculation of the current insulation resistance value includes the following steps: Multiple measurement cycles are executed continuously. In each cycle, a set of sampling data is collected. Each set of sampling data includes a maximum value of the sampling voltage and the corresponding first injection voltage value, and a second injection voltage value corresponding to a zero-crossing point of the sampling voltage. Phase consistency verification is performed on multiple sets of sampling data collected within multiple cycles, and abnormal cycle data whose phase difference is not locked within the preset threshold range are removed; The maximum value of the sampled voltage in each group of sampled data retained after verification is compared with the corresponding first injection voltage value to obtain multiple ratio data, and the second injection voltage value in each group of sampled data retained after verification is used as multiple voltage data. Statistical processing is performed on multiple ratio data to obtain the first statistical value, and statistical processing is performed on multiple voltage data to obtain the second statistical value; The first and second statistical values ​​are used as the final input values ​​for the insulation resistance calculation. They are then substituted into the insulation resistance solution equation pre-constructed based on the circuit parameters, injection frequency, and the topology of the measurement circuit to obtain the current insulation resistance value.

[0010] According to the technical solution provided in this application, the step of performing phase consistency verification on multiple sets of sampled data collected within multiple periods includes the following steps: During each measurement cycle, the phase error signal output by the digital phase-locked loop is continuously monitored; When the absolute value of the phase error signal is continuously less than the first error threshold within a preset time window, the current period is determined to be a valid phase-locking period, and the sampled data collected in the current period is marked as valid data. When the absolute value of the phase error signal is greater than or equal to the first error threshold within a preset time window, the current period is determined to be a phase unlocking period, and the sampled data collected in the current period is marked as invalid data and discarded. The number of cycles marked as invalid data in multiple consecutive measurement cycles is counted. If the number of invalid data cycles exceeds the preset threshold, it is determined that there is continuous interference or circuit abnormality in the current measurement environment, the insulation resistance calculation is paused and an alarm signal is output. If the number of invalid data periods does not exceed the preset threshold, only invalid data will be removed, and valid data will continue to be used for subsequent ratio calculations and statistical processing.

[0011] According to the technical solution provided in this application, after dynamically adjusting the injection frequency of the sinusoidal voltage, the method further includes the following steps: When the injection frequency is switched from the current frequency to the adjusted new frequency, the first measurement period after the switching time is marked as the transition period; During the transition period, the digital phase-locked loop re-establishes phase lock with the new frequency as a reference, and before the phase lock is established, it pauses the acquisition of the maximum value of the sampling voltage and the corresponding first injection voltage value, and the second injection voltage value corresponding to the zero crossing point of the sampling voltage. The system detects whether the digital phase-locked loop has completed phase locking. When the phase difference is locked within a preset error range, the phase locking is determined to be complete. Starting from the next measurement cycle after phase lock is established, resume the acquisition of the maximum value of the sampled voltage and the corresponding first injection voltage value, and the second injection voltage value corresponding to the zero crossing point of the sampled voltage, and mark the first measurement cycle after the acquisition is resumed as the valid start cycle; Data collected during the transition period is not included in subsequent multi-period statistical processing, while data from the effective starting period and its subsequent periods are included in the calculation window of multi-period statistical processing.

[0012] According to the technical solution provided in this application, after the injection frequency is switched from the current frequency to the adjusted new frequency, the following steps are also included: Retrieve the last measurement result before frequency adjustment, including the injection frequency, maximum sampling voltage, first injection voltage value, second injection voltage value, and calculated insulation resistance value at that time; After frequency adjustment, multiple measurement cycles are performed continuously at the new injection frequency to obtain the insulation resistance value at the new frequency. Based on the ratio of the maximum value of the sampled voltage to the first injected voltage value at the two frequencies before and after frequency adjustment, and the second injected voltage value corresponding to the zero-crossing point of the sampled voltage, a frequency normalization mapping relationship is constructed. The insulation resistance value measured after frequency adjustment is converted to the equivalent insulation resistance value before frequency adjustment according to the frequency normalization mapping relationship, so as to generate a normalized insulation resistance value that is consistent with historical data. The normalized insulation resistance value is stored in a historical trend database for continuous trend analysis and comparison with historical data before frequency adjustment.

[0013] According to the technical solution provided in this application, the following steps are also included: During continuous monitoring, the phase error signal in each measurement cycle is recorded to form a phase error history sequence, and the normalized insulation resistance value corresponding to each measurement cycle is recorded to form an insulation resistance history sequence. The phase error history sequence and the insulation resistance history sequence are time-aligned, and their correlation coefficient is calculated. Based on the correlation coefficient and the trend changes in the historical sequence of insulation resistance, the corresponding diagnostic results are output; the diagnostic results include whether the change in the insulation resistance measurement value is caused by a change in the insulation state of the measured system or by a decline in the performance of the measurement system itself.

[0014] According to the technical solution provided in this application, the following steps are also included: After the injection frequency is switched, online adaptive phase drift compensation is triggered; The online adaptive phase drift compensation includes: Within the peak range of the injected voltage, the sampling voltage waveform across the sampling resistor is acquired using an oversampling method, and the dynamic zero-crossing phase value and dynamic peak phase value under the current actual physical phase are extracted. The dynamic zero-crossing phase value is compared with the second phase offset corresponding to the current injection frequency in the calibration parameter table to obtain the pure hardware phase drift. The pure hardware phase drift is superimposed on the synchronization reference signal output by the digital phase-locked loop to generate a dynamically corrected sampling trigger signal; Simultaneously, the pure hardware phase drift is superimposed with the first phase offset and the second phase offset corresponding to the current injection frequency in the calibration parameter table to form an updated phase offset, which is then stored in the calibration parameter table.

[0015] Compared with the prior art, the beneficial effects of this application are as follows: First, it achieves precise alignment between the sampling time and the characteristic points of the sampling voltage: the phase difference between the injected voltage and the sampling voltage is tracked in real time by a digital phase-locked loop, and the sampling time is precisely controlled according to the phase information output by the phase-locked loop, ensuring that the maximum value and zero crossing point of the sampling voltage are accurately acquired, thus eliminating the sampling deviation caused by the phase shift and parameter drift of the RC circuit.

[0016] Secondly, it improves the accuracy and repeatability of insulation resistance measurement: Since the maximum value of the sampling voltage and the zero crossing point are directly involved in the calculation of insulation resistance, the precise alignment of the sampling time ensures the accuracy of the input data for each measurement, resulting in good consistency of the insulation resistance value between different measurement cycles.

[0017] Third, it has adaptive compensation capability: The closed-loop characteristic of the digital phase-locked loop enables it to automatically track the phase change between the injected voltage and the sampled voltage. When the injection frequency is adjusted or the circuit parameters change due to temperature drift or component aging, the phase-locked loop can adjust and relock in real time to ensure that the sampling time is always accurately aligned. Attached Figure Description

[0018] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 A flowchart illustrating the steps of the DC system insulation resistance monitoring method based on timing phase locking provided in this application; Figure 2 A schematic diagram of the measurement circuit provided in this application; Detailed Implementation The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0019] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0020] As mentioned in the background section, this application proposes a DC system insulation resistance monitoring method based on timing phase locking, using the following measurement circuit: a bridge resistor is connected to the positive and negative terminals of the DC system respectively, the common terminal of the two bridge resistors is connected to the first terminal of the first resistor, the second terminal of the first resistor is connected to the negative terminal of the injected voltage source, the positive terminal of the injected voltage source is grounded, and the DC blocking capacitor is connected in series with the sampling resistor and then in parallel across the two terminals of the first resistor. like Figure 1 As shown, the method includes the following steps: S1. Inject a sinusoidal voltage into the DC system at a preset frequency, and collect the sampling voltage across the sampling resistor in real time; S2. A digital phase-locked loop is used to track the phase difference between the injected voltage and the sampled voltage in real time. Based on the phase information output by the digital phase-locked loop, the maximum value and the corresponding first injected voltage value are collected when the sampled voltage reaches its maximum value, and the corresponding second injected voltage value is collected when the sampled voltage crosses zero. S3. Based on the maximum value of the sampled voltage and the corresponding first injection voltage value, and the second injection voltage value corresponding to the zero-crossing point of the sampled voltage, the current insulation resistance value is calculated.

[0021] Specifically, this method employs the following... Figure 2 The measurement circuit shown has DC+ representing the positive bus of the DC system, which is the positive terminal of the DC power supply being measured and represents the high potential terminal of the output DC voltage. DC- representing the negative bus of the DC system, which is the negative terminal of the DC power supply being measured and represents the low potential terminal of the output DC voltage. O represents the two bridge resistors R. a The common connection point of the bridge, called the midpoint, is the node where the AC injection signal is connected to the measurement circuit. fP This represents the positive-to-ground capacitance, which is the distributed capacitance between the positive bus DC+ of a DC system and the ground. It is one of the inherent stray capacitances to ground in a DC system and can shunt the AC injected signal. C fN This represents the negative terminal-to-ground capacitance, which is the distributed capacitance between the negative bus DC- of the DC system and the ground. It is one of the inherent stray capacitances to ground in the DC system, and is related to C. fP Together they constitute the system's capacitance to ground. R fP R represents the insulation resistance between the positive terminal and ground, which is the insulation resistance between the positive bus DC+ of the DC system and the ground. It is one of the insulation parameters that needs to be monitored in this method. fN This represents the insulation resistance between the negative pole and ground, specifically the insulation resistance between the DC- negative busbar (DC-) of the DC system and the ground. It is one of the insulation parameters that needs to be monitored in this method. eThis represents the grounding current, an alternating current flowing from the sampling node to the ground. It is the loop current formed by the injected AC signal throughout the circuit, and its magnitude reflects the combined impedance characteristics of the system's insulation and capacitance to ground. In this circuit, the positive terminal of the DC system is connected to one end of the first bridge resistor, and the negative terminal of the DC system is connected to one end of the second bridge resistor. The resistance values ​​of the first and second bridge resistors are equal, and their other ends are connected together to form a common terminal, which serves as the midpoint of the bridge. The midpoint of the bridge is connected to the first end of the first resistor. The second end of the first resistor is connected to the negative terminal of the injected voltage source, and the positive terminal of the injected voltage source is directly connected to the ground. The DC blocking capacitor is connected in series with the sampling resistor and then connected in parallel across the two ends of the first resistor. That is, one end of the DC blocking capacitor is connected to the first end of the first resistor, the other end of the DC blocking capacitor is connected to the first end of the sampling resistor, and the second end of the sampling resistor is connected to the second end of the first resistor.

[0022] Based on this circuit, this method is implemented according to the following steps.

[0023] Step 1: Inject a sinusoidal voltage into the DC system at a preset frequency. The operator generates a sinusoidal voltage signal with a preset frequency and amplitude using a signal generator. The output of the signal generator is connected to the system according to the circuit connection method: the positive terminal of the signal generator is connected to ground, and the negative terminal is connected to the second end of the first resistor. The preset frequency is usually selected between 10 Hz and 100 Hz, and the amplitude is usually selected between 10 V and 50 V. The specific values ​​can be preset according to the voltage level and ground capacitance range of the DC system being tested. For example, for a DC system with a rated voltage of 1000 V, the injection frequency can be set to 50 Hz and the amplitude to 30 V.

[0024] Step two: Real-time acquisition of the sampling voltage across the sampling resistor. An analog-to-digital converter (ADC) input channel is connected in parallel across the sampling resistor. The ADC operates continuously at a fixed sampling rate, which should satisfy the Nyquist sampling theorem, i.e., at least 10 times the injection frequency, to ensure accurate waveform reproduction of the sampled voltage. For example, when the injection frequency is 50 Hz, the sampling rate can be set to 5 kHz, acquiring 100 points per cycle. The ADC converts the acquired analog voltage signal into a digital value, storing it in the processor's memory buffer for subsequent calculations.

[0025] Step three involves using a digital phase-locked loop (PLL) to track the phase difference between the injected voltage and the sampled voltage in real time. The processor runs a PLL algorithm. The algorithm's input includes two signals: one is the sampled value of the injected voltage, and the other is the sampled value of the voltage across the sampling resistor. Internally, the algorithm maintains a numerically controlled oscillator (CNC), which outputs a synchronization reference signal with the same frequency as the injected voltage. In each sampling cycle, the algorithm first calculates the phase difference between the injected and sampled voltages. This phase difference is then processed by a loop filter and used to adjust the output phase of the CNC oscillator. Through repeated iterations, the output phase of the CNC oscillator gradually approaches the phase of the injected voltage, ultimately achieving synchronization. When the phase difference is locked within a preset error range (e.g., ±0.5 degrees), the PLL is considered locked.

[0026] Step four: Based on the phase information output by the digital phase-locked loop (PLL), when the sampling voltage reaches its maximum value, the maximum value and the corresponding first injection voltage value are acquired; when the sampling voltage crosses zero, the corresponding second injection voltage value is acquired. Specifically, the PLL algorithm outputs a synchronization reference signal, which is a square wave or pulse sequence in phase with the injection voltage. The processor's timer module is configured in external trigger mode, using the rising edge of the synchronization reference signal as the trigger source. When the rising edge of the synchronization reference signal arrives, the timer triggers the analog-to-digital converter (ADC) to perform one sampling. The sampled voltage value acquired at this time is not used directly but needs to be compensated according to a pre-calibrated offset. Specifically, the acquisition time of the maximum sampling voltage point lags behind the rising edge of the synchronization reference signal by a fixed offset, which is obtained through pre-calibration. Similarly, the acquisition time of the zero-crossing sampling voltage point also lags behind the rising edge of the synchronization reference signal by another fixed offset. The processor looks up these two offsets from the calibration table based on the current injection frequency, and after the rising edge of the synchronization reference signal arrives, delays by the corresponding offset, triggering two analog-to-digital conversion samplings. The first sampling obtains the maximum value of the sampled voltage, and at the same time, the output voltage value of the injected voltage source is recorded as the first injected voltage value; the second sampling obtains the sampled voltage value corresponding to the zero-crossing point of the sampled voltage (theoretically zero), and at the same time, the output voltage value of the injected voltage source is recorded as the second injected voltage value.

[0027] Step five: Based on the maximum value of the sampled voltage and the corresponding first injection voltage value, and the second injection voltage value corresponding to the zero-crossing point of the sampled voltage, the current insulation resistance value is calculated. The processor substitutes these three voltage values ​​into a pre-constructed insulation resistance solution equation. This equation is derived based on circuit theory and includes known circuit parameters: the resistance of the bridge resistor, the resistance of the first resistor, the resistance of the sampling resistor, the frequency of the injection voltage, and the amplitude of the injection voltage source. The processor substitutes these known values ​​and the three sampled voltage values ​​into the equation and solves for the insulation resistance value through arithmetic operations. The calculated insulation resistance value is stored in memory and can also be output to a host computer or displayed on a screen via a communication interface.

[0028] Furthermore, the processor reads the current injection frequency f from memory and converts it to an angular frequency ω = 2πf. Simultaneously, it reads known circuit parameters: bridge resistance R. a First resistor R e Sampling resistor R ex DC blocking capacitor C x The processor also reads the maximum value v of the sampled voltage acquired in this measurement. ex_max The corresponding first injection voltage value v g_x And the second injection voltage value v corresponding to the zero-crossing point of the sampling voltage. g_y ;R e Let the voltage across the terminals be v es The grounding current is set as i e DC voltage is set to v dc The injected voltage value is set to v. g R ex Let the voltage across the terminals be v ex Real-time sampling v ex When v ex At the moment of maximum, v ex The voltage sampling value is v ex_max When v ex The moment when v reaches its maximum g The voltage sampling value is v g_x When v ex At the moment of zero, the corresponding v g The voltage sampling value is v g_y ; The sampled voltage value v ex_max v g_x v g_y Substituting into the following formula, we can obtain the parameters. and

[0029]

[0030] Will and Substituting into the following formula, the insulation resistance value R can be obtained. fm :

[0031] It should be noted that parameters A, B, E, and F are intermediate substitution variables introduced to simplify the impedance expression. The relevant parameters A, B, E, F, and R in the above equation are... o The definition is as follows:

[0032] R o It is the parallel value of the two bridge resistors Ra, that is...

[0033] It is the angular velocity of the sinusoidal AC injection voltage, and its frequency. The correspondence is as follows:

[0034] For resistors The resistance value, Sampling resistor The resistance value, Cx is the capacitance value of the DC blocking capacitor Cx.

[0035] The technical principle of this method lies in the fact that a digital phase-locked loop (PLL) maintains a fixed phase relationship between the synchronization reference signal and the injected voltage through closed-loop control. Since a deterministic phase relationship exists between the sampled voltage and the injected voltage, determined by the measurement circuit, a fixed correspondence exists between the edge position of the synchronization reference signal and the characteristic point position of the sampled voltage. After calibrating and determining this correspondence, sampling can be completed at precise moments, avoiding errors caused by phase drift during open-loop sampling.

[0036] The technical effects achieved by this method are: the sampling time is precisely aligned with the maximum value and zero crossing point of the sampling voltage, eliminating the sampling deviation introduced by the phase shift and parameter drift of the RC circuit; the insulation resistance measurement accuracy is improved, and the results of different measurement cycles have good repeatability; the automatic tracking characteristics of the phase-locked loop enable the system to adapt to changes in injection frequency and circuit parameter drift; the entire scheme does not require additional hardware and is easy to implement on existing equipment.

[0037] In a preferred embodiment, the step of using a digital phase-locked loop to track the phase difference between the injected voltage and the sampled voltage in real time includes the following steps: The injected voltage is used as a reference signal input to the digital phase-locked loop. The phase detector of the digital phase-locked loop detects the phase difference between the injected voltage and the sampled voltage, and generates a phase error signal. The phase error signal is filtered by a loop filter and then input to a voltage-controlled oscillator or a numerically controlled oscillator to generate a synchronization reference signal that is synchronized with the injected voltage. The analog-to-digital converter is triggered by the rising or falling edge of the synchronization reference signal to sample the maximum value point and the zero crossing point of the sampled voltage, respectively. Specifically, when the phase difference between the synchronization reference signal and the sampling voltage is locked to zero, the sampling time is precisely aligned with the characteristic point of the sampling voltage.

[0038] Specifically, within the processor, the digital phase-locked loop (PLL) is implemented using a software algorithm. This algorithm has two input signals: one is a real-time sampled value of the injected voltage, designated as the reference signal; the other is a real-time sampled value of the voltage across the sampling resistor, designated as the feedback signal. The algorithm outputs a synchronization reference signal to trigger subsequent sampling operations.

[0039] The first step involves inputting the injected voltage as a reference signal into the digital phase-locked loop (PLL). The phase detector of the PLL detects the phase difference between the injected voltage and the sampled voltage, generating a phase error signal. The phase detector employs a multiplicative phase detector structure. Specifically, the processor multiplies the current sampled value of the reference signal with the sampled value of the feedback signal to obtain the product. Since both the reference and feedback signals are sinusoidal, their product contains a DC component related to the phase difference and a second harmonic component. To extract the DC component, the algorithm passes the product through a low-pass filter to remove high-frequency components, obtaining a DC signal proportional to the sine of the phase difference; this signal is the phase error signal. When the reference and feedback signals are perfectly in phase, the phase error signal is zero; when a phase difference exists, the phase error signal is either positive or negative.

[0040] The second step involves filtering the phase error signal through a loop filter before inputting it to a voltage-controlled oscillator (VCO) or a numerically controlled oscillator (CNC). The loop filter employs a first-order low-pass filter structure, with a transfer function containing proportional and integral terms. In practice, the processor multiplies the phase error signal by a proportional coefficient to obtain the proportional term, and simultaneously accumulates the phase error signal into an integrator to obtain the integral term. The proportional and integral terms are then added to obtain the filtered control quantity. The values ​​of the proportional and integral coefficients determine the response speed and stability of the phase-locked loop (PLL). For example, the proportional coefficient can be set to 0.1, and the integral coefficient to 0.01; the specific values ​​can be determined through simulation based on the system response requirements. The filtered control quantity serves as the input to the CNC oscillator.

[0041] The third step involves the CNC oscillator adjusting the frequency and phase of its output signal based on the filtered input control quantity, generating a synchronization reference signal synchronized with the injected voltage. Internally, the CNC oscillator maintains a phase accumulator, which increments by a step size each sampling period, determined by the control quantity. The phase accumulator's output is converted into a sine wave signal using a sine lookup table, while the most significant bit or carry signal of the phase accumulator serves as the edge output of the synchronization reference signal. Specifically, when the phase accumulator increases from a value less than π to a value greater than π, a rising edge signal is generated; this signal is the synchronization reference signal. By adjusting the step size, the increment rate of the phase accumulator can be controlled, thereby changing the frequency of the output signal. Under closed-loop control, the output frequency of the CNC oscillator gradually approaches the frequency of the reference signal, and the phase difference gradually decreases.

[0042] The fourth step involves triggering the analog-to-digital converter (ADC) using the rising or falling edge of the synchronization reference signal to sample the maximum value and zero-crossing point of the sampled voltage, respectively. The processor connects the rising edge of the synchronization reference signal to the external trigger pin of the ADC. When the rising edge of the synchronization reference signal arrives, the ADC is triggered to perform a conversion. Since the synchronization reference signal is synchronized with the injected voltage, and there is a circuit-determined phase relationship between the injected voltage and the sampled voltage, the rising edge of the synchronization reference signal corresponds to a fixed phase point on the sampled voltage waveform. To achieve sampling at the maximum value and zero-crossing point, the processor adds two different delays to the rising edge of the synchronization reference signal. The first delay is used to align with the maximum value of the sampled voltage, and the second delay is used to align with the zero-crossing point. The values ​​of these two delays are obtained through pre-calibration and stored in memory. The processor configures a timer, which starts counting when the rising edge of the synchronization reference signal arrives, triggering the first sampling when the first delay arrives and the second sampling when the second delay arrives. The result of the first sampling is the maximum value of the sampled voltage, and the result of the second sampling is the voltage value corresponding to the zero-crossing point of the sampled voltage. When the phase difference between the synchronization reference signal and the sampling voltage is locked to zero, these two delays ensure that the sampling time falls precisely on the characteristic point of the sampling voltage.

[0043] The technical principle of this method is as follows: a digital phase-locked loop (PLL) detects the phase difference through a phase detector, controls the dynamic response through a loop filter, and adjusts the output phase through a numerically controlled oscillator (CNC oscillator), forming a negative feedback system. When the system is stable, the phase difference between the synchronization reference signal output by the CNC oscillator and the injected voltage approaches zero. By using the edge of the synchronization reference signal to trigger sampling, it is possible to ensure that the sampling time maintains a fixed phase relationship with the injected voltage, and then align the sampling voltage to the characteristic points through a calibrated delay.

[0044] The technical effects achieved by this method are as follows: it combines the standard digital phase-locked loop structure with the sampling requirements of insulation resistance monitoring, realizing closed-loop control of the sampling time; the automatic tracking characteristics of the phase-locked loop enable it to adapt to changes in injection frequency and drift of circuit parameters; the edge triggering method of the synchronization reference signal is simple and reliable, and easy to interface with analog-to-digital converters; the entire phase-locked loop is implemented through software algorithms in the processor without increasing hardware complexity.

[0045] In a preferred embodiment, before triggering the analog-to-digital converter with the rising or falling edge of the synchronization reference signal to sample the maximum value point and zero-crossing point of the sampled voltage, the method further includes the following steps: After system startup or injection frequency adjustment, perform phase offset self-calibration: Inject a sinusoidal voltage into the DC system at the current injection frequency, continuously collect the sampled voltage waveform for multiple cycles, determine the true phase position of the maximum value point of the sampled voltage, and determine the first phase offset between the true phase position and the rising or falling edge of the synchronization reference signal. Determine the true phase position of the zero-crossing point of the sampled voltage, and determine the second phase offset between the true phase position and the rising or falling edge of the synchronization reference signal; The phase offset is stored in the calibration parameter table, which records the first phase offset between the maximum value point of the sampled voltage and the synchronization reference signal at different injection frequencies, and the second phase offset between the zero crossing point of the sampled voltage and the synchronization reference signal. During subsequent normal measurements, the corresponding first phase offset and second phase offset are retrieved from the calibration parameter table according to the current injection frequency. The sampling of the maximum value point of the sampling voltage is triggered after the first phase offset is superimposed on the rising or falling edge of the synchronization reference signal, and the sampling of the zero-crossing point of the sampling voltage is triggered after the second phase offset is superimposed.

[0046] Specifically, in the measurement circuit, the DC blocking capacitor, sampling resistor, and first resistor form an RC network. When an AC signal passes through this network, a phase shift occurs. Even if the digital phase-locked loop locks the phase difference between the synchronization reference signal and the injected voltage to zero, the actual waveform of the sampled voltage still has a fixed phase shift relative to the injected voltage. The magnitude of this phase shift depends on the time constant of the RC network and the frequency of the injected signal. When the injection frequency changes, the phase shift also changes. To eliminate the impact of this phase shift on sampling accuracy, this method performs phase shift self-calibration after system startup or injection frequency adjustment.

[0047] The system's self-calibration during startup occurs after the device is initially powered on or reset. At this time, the measurement circuit has not yet begun formal monitoring, and the processor enters calibration mode. Self-calibration after injection frequency adjustment is performed after each dynamic adjustment of the injection frequency to ensure that the phase shift at the new frequency is accurately recorded.

[0048] The specific steps for phase offset self-calibration are as follows.

[0049] The first step involves injecting a sinusoidal voltage into the DC system at the current injection frequency and continuously acquiring multiple cycles of sampled voltage waveforms. The processor is configured to operate the analog-to-digital converter (ADC) at a high sampling rate, at least 100 times the injection frequency, to ensure accurate capture of waveform details. For example, if the injection frequency is 50 Hz, the sampling rate is set to 10 kHz, with 200 points acquired per cycle. The ADC continuously acquires sampled voltage data for 10 cycles and stores the acquired data in a memory buffer.

[0050] The second step is to determine the true phase position of the maximum value point of the sampled voltage. The processor performs peak detection on the acquired waveform data. Specifically, it iterates through the sampling points of each cycle, compares the amplitudes of adjacent sampling points, and finds the point with the largest amplitude. Since the waveform may contain noise, the processor uses a sliding window averaging method to smooth the waveform before performing peak detection. After finding the peak point of each cycle, the processor records the sampling sequence number of that point in the entire waveform. The processor also records the sampling sequence number of the rising edge of the synchronization reference signal. Since the sampling rate is fixed, the difference between sampling sequence numbers can be converted into a time difference, and then into a phase difference based on the injection frequency. The processor calculates the phase difference between the peak point and the rising edge of the synchronization reference signal, denoted as the first phase offset. This offset represents the offset angle of the actual maximum value point of the sampled voltage relative to the rising edge of the synchronization reference signal.

[0051] The third step is to determine the true phase position of the zero-crossing point of the sampled voltage. The processor performs zero-crossing detection on the acquired waveform data. Specifically, it iterates through the sampling points of each cycle, finding the point where the sampled voltage changes from negative to positive—that is, the position where the previous sampling point was negative and the next sampling point is positive. Since the waveform may have a DC bias, the processor first calculates the average value of the waveform and then uses this average value as a reference for zero-crossing detection. After finding the zero-crossing point of each cycle, the sampling number of that point is recorded. The processor calculates the phase difference between the zero-crossing point and the rising edge of the synchronization reference signal, denoted as the second phase offset. This offset represents the offset angle of the actual zero-crossing point of the sampled voltage relative to the rising edge of the synchronization reference signal.

[0052] The fourth step involves storing the first and second phase offsets in the calibration parameter table. The calibration parameter table is a data area allocated in the processor's memory, stored using an array structure. The array index is either the injection frequency value or a frequency range number. Each entry contains two floating-point numbers: the first phase offset and the second phase offset. For example, if the injection frequency is 50 Hz, an entry for 50 Hz is found or created in the calibration parameter table, and the calculated first and second phase offsets are written to that entry. If an entry for that frequency already exists, the newly calculated value overwrites the old value, or a moving average is used to update the value, thus enhancing calibration stability.

[0053] Fifth, during subsequent normal measurements, the corresponding first and second phase offsets are retrieved from the calibration parameter table based on the current injection frequency. During normal measurement, the processor first obtains the currently used injection frequency value, and then uses this frequency value as an index to search for the corresponding entry in the calibration parameter table. If a matching entry is found, the first and second phase offsets are read; if not found, the default value (e.g., zero) is used, and a new self-calibration is triggered.

[0054] Step 6: Sampling at the maximum value of the sampled voltage is triggered by superimposing a first phase offset on the rising or falling edge of the synchronization reference signal. Sampling at the zero-crossing point of the sampled voltage is triggered by superimposing a second phase offset. The processor is configured with a timer that supports multiple comparison channels. When the rising edge of the synchronization reference signal arrives, the timer starts counting. The first comparison channel of the timer is set to the count value corresponding to the first phase offset. When the count value reaches this value, the first analog-to-digital conversion sampling is triggered, at which point the maximum value of the sampled voltage is acquired. The second comparison channel of the timer is set to the count value corresponding to the second phase offset. When the count value reaches this value, the second analog-to-digital conversion sampling is triggered, at which point the voltage value corresponding to the zero-crossing point of the sampled voltage is acquired. In this way, the actual sampling time is precisely adjusted to coincide with the true characteristic point of the sampled voltage.

[0055] The technical principle of this method is as follows: The actual phase shift introduced by the RC circuit is measured through self-calibration, and this phase shift is superimposed as a compensation amount on the sampling trigger moment, thereby offsetting the system error introduced by the circuit itself. Since this phase shift depends only on the circuit parameters and the injection frequency, and is independent of the external environment, it can be used for a long time at that frequency after a single calibration. When the injection frequency changes, the corresponding compensation amount can be quickly retrieved because the calibration parameter table records the offset at each frequency, eliminating the need for recalibration.

[0056] The technical effects achieved by this method are: it completely eliminates the influence of the fixed phase shift introduced by the RC circuit on the sampling accuracy; it realizes adaptive compensation at different frequencies through the calibration parameter table; the self-calibration process is only executed after system startup or frequency adjustment, without occupying normal measurement time; the compensated sampling time accurately corresponds to the real characteristic point of the sampling voltage, providing high-quality input data for insulation resistance calculation.

[0057] In a preferred embodiment, the method further includes dynamically adjusting the injection frequency of the sinusoidal voltage; The dynamic adjustment of the injection frequency of the sinusoidal voltage includes the following steps: Based on the calculated insulation resistance value, combined with the ratio of the maximum value of the sampling voltage at the current injection frequency to the corresponding first injection voltage value, and the second injection voltage value corresponding to the zero crossing point of the sampling voltage, the current value of the capacitance to ground is estimated by solving the impedance equation containing the capacitance to ground parameter. The current value of the capacitance to ground is compared with a preset capacitance threshold range. If the current capacitance to ground value falls within the first threshold range, the injection frequency is adjusted to the first frequency; if the current capacitance to ground value falls within the second threshold range, the injection frequency is adjusted to the second frequency. The first frequency and the second frequency correspond to the operating points where the sensitivity of the sampling voltage amplitude to capacitance changes is zero or close to zero, so that at the adjusted frequency, the maximum value of the sampling voltage and the corresponding injection voltage value, as well as the injection voltage value corresponding to the zero-crossing point of the sampling voltage, are minimally affected by the fluctuation of the capacitance to ground.

[0058] Specifically, during fixed-frequency injection, changes in the capacitance to ground affect the amplitude and phase of the sampling voltage, thus impacting the accuracy of insulation resistance calculations. To address this issue, this method estimates the capacitance to ground value based on the current measurement data after each insulation resistance calculation and adjusts the injection frequency for subsequent measurements based on the estimation results.

[0059] The first step is to estimate the current value of the capacitance to ground.

[0060] The processor reads the current injection frequency f from memory and converts it to an angular frequency ω = 2πf. Simultaneously, it reads known circuit parameters: bridge resistance R. a First resistor R e Sampling resistor R ex DC blocking capacitor C x The processor also reads the maximum value v of the sampled voltage acquired in this measurement. ex_max The corresponding first injection voltage value v g_x And the second injection voltage value v corresponding to the zero-crossing point of the sampling voltage. g_y .

[0061] The processor first calculates the ratio K = v ex_max / v g_x , and then calculates the real part x zx = K·R ex .

[0062] According to circuit theory, the real part of the equivalent impedance, the insulation resistance R fm , the capacitance to ground C fm , and the circuit parameters satisfy the following relationship: ; The processor substitutes the known R fm , ω, R e , R ex into the above formula to solve for the unknown C fm . When specifically solving, the processor rewrites the equation as: ; The processor performs the above arithmetic operations to calculate the current value C fm of the capacitance to ground.

[0063] Second step, select the injection frequency according to the capacitance to ground value.

[0064] The processor compares the calculated C fm with the preset capacitance threshold range. The preset threshold range is stored in the memory and includes two boundary values Cth1 and Cth2. For example, Cth1 = 0.1 μF and Cth2 = 1 μF. If C fm < Cth1, the processor determines that it falls into the first threshold range and adjusts the injection frequency to the first frequency f1; if Cth1 ≤ C fm ≤ Cth2, the processor determines that it falls into the second threshold range and adjusts the injection frequency to the second frequency f2; if C fm > Cth2, the processor determines that it falls into the third threshold range and adjusts the injection frequency to the third frequency f3.

[0065] The values of the first frequency f1, the second frequency f2, and the third frequency f3 are determined in advance through theoretical calculations and correspond to the operating points where the sensitivity of the sampled voltage amplitude to capacitance to capacitance change is zero or close to zero. For example, for typical circuit parameters, f1 = 100 Hz, f2 = 50 Hz, and f3 = 20 Hz can be set.

[0066] Third step, re-measure the insulation resistance value at the adjusted frequency.

[0067] The processor writes the new frequency into the signal generator, and the signal generator generates a sine wave voltage according to the new frequency and injects it into the system. Subsequently, the processor performs the injection, sampling, acquisition, and calculation steps at the new frequency according to the前述 method to obtain the updated insulation resistance value.

[0068] The technical principle of this method lies in the fact that the magnitude of the capacitance to ground affects the amplitude of the sampled voltage, but this effect is related to the injection frequency. By selecting a specific frequency, the relationship between the sampled voltage amplitude and changes in the capacitance to ground can be made insensitive. Specifically, when the injection frequency equals a certain value, the derivative of the sampled voltage amplitude with respect to the capacitance is zero, and at this point, small fluctuations in the capacitance will not cause changes in the sampled voltage amplitude. By estimating the current capacitance to ground value and adjusting the injection frequency to near the insensitive frequency corresponding to that capacitance value, the impact of capacitance fluctuations on the measurement results can be minimized.

[0069] The technical effects achieved by this method are as follows: it realizes adaptive optimization of the injection frequency, enabling the measurement system to maintain high accuracy under different ground capacitance conditions; by selecting an insensitive frequency, it fundamentally reduces the interference of ground capacitance, rather than correcting it through algorithms afterward; the frequency adjustment and phase-locked sampling work together to form a complete adaptive monitoring closed loop; this method is applicable to various DC systems, including photovoltaic power generation, electric vehicles, DC charging piles, lithium battery energy storage, and other scenarios, and is also applicable to offline insulation resistance monitoring without DC voltage.

[0070] In a preferred embodiment, the calculation of the current insulation resistance value includes the following steps: Multiple measurement cycles are executed continuously. In each cycle, a set of sampling data is collected. Each set of sampling data includes a maximum value of the sampling voltage and the corresponding first injection voltage value, and a second injection voltage value corresponding to a zero-crossing point of the sampling voltage. Phase consistency verification is performed on multiple sets of sampling data collected within multiple cycles, and abnormal cycle data whose phase difference is not locked within the preset threshold range are removed; The maximum value of the sampled voltage in each group of sampled data retained after verification is compared with the corresponding first injection voltage value to obtain multiple ratio data, and the second injection voltage value in each group of sampled data retained after verification is used as multiple voltage data. Statistical processing is performed on multiple ratio data to obtain the first statistical value, and statistical processing is performed on multiple voltage data to obtain the second statistical value; The first and second statistical values ​​are used as the final input values ​​for the insulation resistance calculation. They are then substituted into the insulation resistance solution equation pre-constructed based on the circuit parameters, injection frequency, and the topology of the measurement circuit to obtain the current insulation resistance value.

[0071] Specifically, after completing the phase locking and sampling trigger settings, the processor begins to execute the multi-cycle measurement process.

[0072] First, the processor configures a cycle counter and sets the number of measurement cycles to a preset value, such as 10 cycles. Each measurement cycle performs one complete sampling process. Within each measurement cycle, the processor acquires a set of sampled data according to the previously described method. This set of sampled data contains three values: the maximum sampled voltage, the first injection voltage value corresponding to that maximum value, and the second injection voltage value corresponding to the zero-crossing point of the sampled voltage. The processor stores this data in an array structure, where each element of the array is a structure containing three floating-point numbers. Simultaneously, the processor records the cycle number corresponding to that measurement cycle.

[0073] Secondly, after completing a preset number of measurement cycles, the processor performs phase consistency verification on the acquired multiple sets of sampled data. The purpose of phase consistency verification is to eliminate cycle data that are not fully locked by the phase-locked loop (PLL) or are subject to interference. The processor reads the phase error signal record for each measurement cycle from the digital PLL module. The digital PLL continuously outputs a phase error value in each cycle, which reflects the phase difference between the synchronization reference signal and the injected voltage. The processor presets a first error threshold, for example, 0.5 degrees. For each measurement cycle, the processor checks whether the absolute value of the phase error signal within that cycle is continuously less than the first error threshold within a preset time window. The time window can be set to half a cycle or the entire cycle. In specific operation, the processor iterates through all phase error sampling points within the cycle. If the absolute values ​​of multiple consecutive sampling points (e.g., 10 consecutive sampling points) exceed the first error threshold, the cycle is determined to be an abnormal cycle. If the absolute values ​​of all phase error sampling points within the cycle are less than the first error threshold, the cycle is determined to be a valid cycle. The processor marks the sampled data of valid periods as valid and marks the sampled data of abnormal periods as invalid and discards them, excluding them from subsequent calculations.

[0074] Then, the processor processes each set of sampled data retained after verification. For each set of valid sampled data, the processor calculates the ratio of the maximum sampled voltage to the corresponding first injection voltage value. Specifically, the processor reads the v value of that set. ex_max and v g_x Perform division operation v ex_max Divide by v g_x The ratio data is obtained and stored in a ratio array. Simultaneously, the processor directly extracts the second injection voltage value v of this group. g_y The values ​​are stored in a voltage array. After the above processing, the ratio array stores N ratio data, and the voltage array stores N voltage data, where N is the number of valid periods to be retained.

[0075] Next, the processor performs statistical processing on multiple ratio data to obtain the first statistical value. The statistical processing method can be arithmetic mean, median, or weighted average. Taking the arithmetic mean as an example, the processor iterates through the ratio array, sums all ratio data, obtains the sum, and then divides it by the number of effective periods N to obtain the average ratio, which is the first statistical value. Similarly, the processor performs statistical processing on the voltage array, sums all voltage data, divides it by N, and obtains the average voltage, which is the second statistical value. If the median is used, the processor first sorts the ratio array and the voltage array separately, and then takes the value at the middle position as the statistical value. If a weighted average is used, the processor assigns weights according to the phase error of each period, with periods having smaller phase errors receiving higher weights.

[0076] Finally, the processor uses the first and second statistical values ​​as input values ​​for the final insulation resistance calculation, substituting them into the pre-constructed insulation resistance solution equation based on circuit parameters, injection frequency, and the topology of the measurement circuit. This solution equation, stored in the processor as code, is a mathematical expression containing multiple known parameters and two input variables. The processor substitutes the known bridge resistance, first resistance, sampling resistance, injection voltage frequency, and the first and second statistical values ​​into the equation, solving for the insulation resistance value through arithmetic operations. This insulation resistance value is the final result of the current multi-cycle measurement, stored in memory for output or trend analysis.

[0077] The technical effects achieved by this method are as follows: multi-cycle measurement reduces the impact of random errors in single sampling; phase consistency verification eliminates abnormal data and ensures the quality of data involved in the calculation; statistical processing provides robust input values ​​and improves the stability of insulation resistance calculation; the entire process is completed automatically without manual intervention.

[0078] In a preferred embodiment, the phase consistency verification of multiple sets of sampled data collected within multiple periods includes the following steps: During each measurement cycle, the phase error signal output by the digital phase-locked loop is continuously monitored; When the absolute value of the phase error signal is continuously less than the first error threshold within a preset time window, the current period is determined to be a valid phase-locking period, and the sampled data collected in the current period is marked as valid data. When the absolute value of the phase error signal is greater than or equal to the first error threshold within a preset time window, the current period is determined to be a phase unlocking period, and the sampled data collected in the current period is marked as invalid data and discarded. The number of cycles marked as invalid data in multiple consecutive measurement cycles is counted. If the number of invalid data cycles exceeds the preset threshold, it is determined that there is continuous interference or circuit abnormality in the current measurement environment, the insulation resistance calculation is paused and an alarm signal is output. If the number of invalid data periods does not exceed the preset threshold, only invalid data will be removed, and valid data will continue to be used for subsequent ratio calculations and statistical processing.

[0079] Specifically, the processor continuously monitors the phase error signal output by the digital phase-locked loop (PLL) during each measurement cycle. When the PLL is running, it outputs a phase error value each sampling cycle, which is stored in a register of the processor. The processor reads this register at fixed time intervals to obtain the phase error signal.

[0080] The processor pre-sets two parameters: a first time window and a first error threshold. The length of the first time window can be set to half a cycle or a full cycle. For example, for an injection frequency of 50 Hz, a cycle is 20 milliseconds, so the time window can be set to 20 milliseconds. The first error threshold is set to an angle value, such as 0.5 degrees. Within each measurement cycle, the processor monitors the phase error signal within that cycle. Specifically, the processor continuously samples the phase error value within the time window, and after each sampling, it determines whether the absolute value of the sampled value is less than the first error threshold.

[0081] When the absolute value of the phase error signal remains below the first error threshold for a preset time window, the processor determines that the current period is a valid phase-locked period. "Remaining below" means that the absolute value of the phase error does not exceed the first error threshold at any of the sampling points within the time window. The processor marks the sampled data collected in the current period as valid data and stores it in a dedicated valid data buffer. Simultaneously, the processor increments the valid period counter.

[0082] When the absolute value of the phase error signal is greater than or equal to the first error threshold within a preset time window, the processor determines the current period as a phase lockout period. This means that at some point in this period, the tracking accuracy of the phase-locked loop exceeds the allowable range. The processor marks the sampled data acquired in the current period as invalid data and discards it, not storing it in the valid data buffer. At the same time, the processor increments the invalid period counter and records the relevant information for this period in the log for subsequent analysis.

[0083] After completing multiple consecutive measurement cycles, the processor counts the number of cycles marked as invalid data within those cycles. The consecutive cycles can be set to the most recent 10 or 20 cycles, with the specific value preset according to system response speed requirements. The processor reads the invalid cycle counter value from memory to obtain the number of invalid data cycles.

[0084] The processor compares the number of invalid data periods with a preset threshold. The preset threshold is an integer, for example, set to 5. If the number of invalid data periods exceeds the preset threshold, the processor determines that there is continuous interference or circuit abnormality in the current measurement environment. At this time, the processor performs an alarm operation: suspends the insulation resistance calculation, stops subsequent sampling and data processing, and outputs an alarm signal through the communication interface or display screen. The alarm signal can be a status code or a text message, such as "Measurement environment abnormal, please check the system".

[0085] If the number of invalid data periods does not exceed a preset threshold, the processor determines that the current measurement environment is normal, removes only the invalid data, and continues to use the valid data for subsequent ratio calculation and statistical processing. Specifically, the processor passes the data in the valid data buffer to the ratio calculation module, while invalid data is not passed.

[0086] The technical principle of this method lies in the fact that the phase error signal of the phase-locked loop (PLL) directly reflects the accuracy of synchronous tracking. When there is strong interference in the measurement environment, signal quality deteriorates, or circuit abnormalities occur, the tracking capability of the PLL will decrease, manifested as an increase in phase error or aggravated fluctuations. By continuously monitoring the phase error and comparing it with a threshold, the data quality of each cycle can be judged in real time. When quality problems occur in multiple consecutive cycles, it indicates that the problem is not sporadic but continuous, requiring a system alarm.

[0087] The technical effects achieved by this method are: real-time monitoring of the measurement process quality; ability to distinguish between occasional interference and continuous faults, avoiding misjudgment due to single interference; proactive suspension of calculation and alarm in case of continuous faults, preventing the output of unreliable data; and separation of valid and invalid data, ensuring the quality of data involved in the calculation.

[0088] In a preferred embodiment, after dynamically adjusting the injection frequency of the sinusoidal voltage, the method further includes the following steps: When the injection frequency is switched from the current frequency to the adjusted new frequency, the first measurement period after the switching time is marked as the transition period; During the transition period, the digital phase-locked loop re-establishes phase lock with the new frequency as a reference, and before the phase lock is established, it pauses the acquisition of the maximum value of the sampling voltage and the corresponding first injection voltage value, and the second injection voltage value corresponding to the zero crossing point of the sampling voltage. The system detects whether the digital phase-locked loop has completed phase locking. When the phase difference is locked within a preset error range, the phase locking is determined to be complete. Starting from the next measurement cycle after phase lock is established, resume the acquisition of the maximum value of the sampled voltage and the corresponding first injection voltage value, and the second injection voltage value corresponding to the zero crossing point of the sampled voltage, and mark the first measurement cycle after the acquisition is resumed as the valid start cycle; Data collected during the transition period is not included in subsequent multi-period statistical processing, while data from the effective starting period and its subsequent periods are included in the calculation window of multi-period statistical processing.

[0089] Specifically, after the processor completes the injection frequency adjustment, the signal generator begins to output a sinusoidal voltage at the new frequency. At this time, the digital phase-locked loop needs to switch from the old frequency to the new frequency and re-establish phase lock. During this transition period, the sampled data may be unstable and cannot be used for insulation resistance calculations.

[0090] The processor marks the first measurement cycle after the switching moment as a transition cycle. Specifically, when issuing the frequency adjustment instruction, the processor sets a transition cycle flag. This flag indicates whether the processor is currently in a transition cycle. The processor also initializes the transition cycle counter to 1.

[0091] During the transition period, the processor performs the following operations: The digital phase-locked loop (PLL) re-establishes phase lock with the new frequency as a reference. After detecting a change in the injection frequency, the PLL algorithm automatically resets its internal state and begins tracking the phase relationship at the new frequency. Before phase lock is fully established, the processor pauses the acquisition of the maximum sampled voltage value and its corresponding first injection voltage value, as well as the second injection voltage value corresponding to the zero-crossing point of the sampled voltage. Specifically, when the transition period flag is valid, the processor skips the sampling trigger and analog-to-digital conversion steps and does not perform any sampling operations. This means that no new sampled data is acquired and stored during the transition period.

[0092] The processor continuously monitors whether the digital phase-locked loop (PLL) has achieved phase locking. This is done by reading the PLL's lock status flag. During operation, the PLL algorithm continuously calculates the phase difference between the synchronization reference signal and the injected voltage. When the absolute value of the phase difference is less than a preset error range for multiple consecutive sampling periods, the PLL sets the lock status flag to 1, indicating successful locking. The preset error range can be set to 0.5 degrees. The processor reads this flag in each sampling period; once the flag becomes 1, it determines that phase locking has been successfully established.

[0093] When the phase difference is detected to be locked within the preset error range, the processor determines that phase locking has been successfully established. At this point, the processor clears the transition period flag and resets the transition period counter to zero. Simultaneously, the processor prepares to enter the normal measurement state.

[0094] Starting from the next measurement cycle after phase-locked acquisition is established, the processor resumes acquiring the maximum value of the sampled voltage and the corresponding first injection voltage value, as well as the second injection voltage value corresponding to the zero-crossing point of the sampled voltage. Specifically, the processor marks the first measurement cycle after resuming acquisition as the valid start cycle. The valid start cycle is marked by setting a start cycle flag and recording the cycle number in memory.

[0095] In subsequent multi-cycle statistical processing, the processor performs data acquisition and verification. Data acquired during the transition period is not included in subsequent multi-cycle statistical processing. This is because no data is acquired during the transition period, or even if a small amount of data is acquired, it is explicitly excluded. Data from the valid start period and subsequent periods are included in the calculation window of the multi-cycle statistical processing. Starting from the valid start period, the processor continuously acquires a preset number of cycle data, and then performs phase consistency verification, statistical processing, and insulation resistance calculation.

[0096] The technical principle of this method is as follows: After a frequency switch, the phase-locked loop (PLL) needs a certain amount of time to recapture the phase information at the new frequency. During the capture process, the synchronization reference signal output by the PLL is not yet stable, and the phase relationship between the sampled data and the injected voltage is uncertain, making it unusable for insulation resistance calculation. By setting a transition period and pausing acquisition, unstable data contamination of the statistical window is avoided. After the PLL relocks, acquisition resumes from the next cycle, ensuring that the data used in subsequent calculations are stable and reliable.

[0097] The technical effects achieved by this method are: no invalid or unreliable measurement data are generated during frequency switching; the setting of the transition period ensures the purity of the data within the statistical window; the detection of the phase-locked loop locking state ensures the accuracy of the sampling recovery timing; and the marking of the effective start period provides a clear starting point for subsequent multi-cycle statistics.

[0098] In a preferred embodiment, after the injection frequency is switched from the current frequency to the adjusted new frequency, the following steps are further included: Retrieve the last measurement result before frequency adjustment, including the injection frequency, maximum sampling voltage, first injection voltage value, second injection voltage value, and calculated insulation resistance value at that time; After frequency adjustment, multiple measurement cycles are performed continuously at the new injection frequency to obtain the insulation resistance value at the new frequency; Based on the ratio of the maximum value of the sampled voltage to the first injected voltage value at the two frequencies before and after frequency adjustment, and the second injected voltage value corresponding to the zero-crossing point of the sampled voltage, a frequency normalization mapping relationship is constructed. The insulation resistance value measured after frequency adjustment is converted to the equivalent insulation resistance value before frequency adjustment according to the frequency normalization mapping relationship, so as to generate a normalized insulation resistance value that is consistent with historical data. The normalized insulation resistance value is stored in a historical trend database for continuous trend analysis and comparison with historical data before frequency adjustment.

[0099] Specifically, after the processor completes the injection frequency adjustment, there may be systematic differences between the measurement results at the new frequency and the historical data at the old frequency. In order to maintain the continuity of historical trends, the processor performs historical data normalization processing.

[0100] First, the processor retrieves the last measurement result before the frequency adjustment. Before the frequency adjustment command is issued, the processor has already completed a full insulation resistance calculation and stored the result in the historical data buffer. This measurement result includes: the injection frequency f_old at the time of measurement, and the maximum sampled voltage v. ex_max_old First injection voltage value v g_x_old Second injection voltage value v g_y_old and the calculated insulation resistance value R fm_old The processor reads this data from the buffer and stores it in a temporary variable for the current operation.

[0101] Secondly, after the frequency adjustment is completed, the processor continuously executes multiple measurement cycles at the new injection frequency f_new to obtain the insulation resistance value at the new frequency. Specifically, the processor samples and calculates at the new frequency to obtain the insulation resistance value R. fm_new At the same time, the processor also recorded the maximum value v of the sampled voltage at the new frequency. ex_max_new First injection voltage value v g_x_new Second injection voltage value v g_y_new .

[0102] Then, the processor constructs a frequency normalization mapping relationship based on the ratio of the maximum value of the sampled voltage to the first injected voltage value at the two frequencies before and after frequency adjustment, and the second injected voltage value corresponding to the zero-crossing point of the sampled voltage. The specific construction process is as follows: The processor calculates the ratio K_old=v at the old frequency. ex_max_old / v g_x_old And the ratio K_new=v at the new frequency ex_max_new / v g_x_new Simultaneously, the processor records the second injection voltage value v at the old frequency. g_y_old and the second injection voltage value v at the new frequency g_y_newAccording to circuit theory, there is a definite relationship between the insulation resistance value and these measured quantities. For the same insulation resistance value, the K value and v measured at different frequencies will have different values. g_y There is a functional relationship between the values. The processor derives this functional relationship through theoretical formulas or establishes a mapping function through numerical fitting methods. For example, the processor can establish the following mapping relationship: when the insulation resistance value remains unchanged, the measurement results at the new frequency and the measurement results at the old frequency satisfy R... fm_new = F(R fm_old The specific form of the mapping function F can be derived from the circuit equations, including known circuit parameters and frequency parameters.

[0103] Finally, the processor converts the insulation resistance value measured after frequency adjustment to the equivalent insulation resistance value before frequency adjustment according to the frequency normalization mapping relationship, generating a normalized insulation resistance value that is consistent with historical data. Specifically, the processor converts the insulation resistance value R measured at the new frequency... fm_new Substituting the inverse function of the mapping function, we can calculate the insulation resistance value that should be obtained if the old frequency is still used for measurement. This value is denoted as R. fm_normalized For example, if the mapping function is R... fm_new =j×R fm_old Where j is the frequency normalization ratio correction coefficient, which is an inherent conversion ratio constant determined solely by the measurement circuit topology, fixed hardware parameters, and the new and old injection frequencies when the actual insulation state of the measured DC system remains unchanged. It characterizes the proportional relationship between the theoretical measured response of the insulation resistance at the new injection frequency and the original reference injection frequency; then the converted equivalent insulation resistance value is R. fm_normalized =R fm_new / j. The normalized insulation resistance value is stored in the historical trend database for continuous trend analysis and comparison with historical data before frequency adjustment.

[0104] The processor will normalize the insulation resistance value R fm_normalized Stored in the historical trend database. The historical trend database is a structure that stores time-series data, with each record containing a timestamp and a normalized insulation resistance value. The database can be a circular buffer in memory or a file on an external storage device. During storage, the processor stores the current timestamp and the normalized insulation resistance value. fm_normalized It is written to the database as a record.

[0105] During subsequent monitoring, the processor uses normalized insulation resistance values ​​for continuous trend analysis and comparison. When it is necessary to display historical trend curves, the processor reads all normalized insulation resistance values ​​from the database and plots the curves in chronological order. Because all data is converted to the same frequency reference, the curves accurately reflect the changing trend of insulation resistance and are unaffected by frequency adjustments.

[0106] The technical principle of this method lies in the fact that the measured insulation resistance value is related to the injection frequency; the same insulation resistance may yield different values ​​at different frequencies. To eliminate the influence of frequency on the measured value, a frequency normalization mapping relationship needs to be established to convert the measurement results at different frequencies to the same reference frequency. This mapping relationship is based on circuit theory and is constructed using known circuit parameters and frequency parameters, enabling accurate compensation for the effects of frequency variations.

[0107] The technical effects achieved by this method are: the measurement data before and after frequency adjustment are comparable, and the historical trend curve remains continuous; the normalized data truly reflects the changing trend of insulation resistance and is not affected by frequency switching; the mapping relationship is based on theoretical derivation, and the compensation is accurate and reliable; the normalized data is stored in the historical database, which facilitates long-term trend analysis and fault early warning.

[0108] In a preferred embodiment, the following steps are also included: During continuous monitoring, the phase error signal in each measurement cycle is recorded to form a phase error history sequence, and the normalized insulation resistance value corresponding to each measurement cycle is recorded to form an insulation resistance history sequence. The phase error history sequence and the insulation resistance history sequence are time-aligned, and their correlation coefficient is calculated. Based on the correlation coefficient and the trend changes in the historical sequence of insulation resistance, the corresponding diagnostic results are output; the diagnostic results include whether the change in the insulation resistance measurement value is caused by a change in the insulation state of the measured system or by a decline in the performance of the measurement system itself.

[0109] Specifically, during continuous monitoring, the processor performs data recording at the end of each measurement cycle. The processor reads the phase error signal record for that measurement cycle from the digital phase-locked loop (PLL) module. The PLL outputs a phase error value in each sampling cycle, reflecting the instantaneous phase difference between the synchronization reference signal and the injected voltage. The processor iterates through all phase error sampling points within that cycle, calculates the arithmetic mean of these sampling points, and obtains the average phase error value for that cycle. Alternatively, the processor scans all sampling points, finds the maximum phase error value, and obtains the peak phase error value for that cycle. The processor writes the representative phase error value calculated for that cycle into a pre-allocated phase error history sequence array in memory. This array is a circular buffer that stores the phase error values ​​of the most recent M cycles in chronological order, where M can be set to 100 or 200.

[0110] Simultaneously, the processor records the normalized insulation resistance value corresponding to each measurement cycle. The normalized insulation resistance value is the insulation resistance value after frequency normalization. The processor writes the normalized insulation resistance value of that cycle into a pre-allocated insulation resistance history sequence array in memory. This array has the same length and time correspondence as the phase error history sequence array, and the elements in the two arrays correspond one-to-one according to the same cycle number, forming time-aligned historical data.

[0111] After completing a preset number of measurement cycles, the processor performs joint diagnostic calculations. The preset number can be set to 50 or 100 cycles to ensure the historical data has sufficient statistical significance. The processor takes the historical phase error sequence array and the historical insulation resistance sequence array as input and calculates their correlation coefficient. The correlation coefficient is calculated using the Pearson correlation coefficient formula. Specifically, the processor first calculates the average value of the phase error sequence and the average value of the insulation resistance sequence. Then, the processor iterates through each pair of data points in the sequence, calculates the deviation of each data point from the average value, multiplies the phase error deviation by the insulation resistance deviation, and sums the products. Simultaneously, the processor calculates the sum of squares of the phase error deviation and the sum of squares of the insulation resistance deviation, respectively. Finally, the processor divides the sum of products by the square root of the product of the sum of squares of the phase error deviation and the sum of squares of the insulation resistance deviation to obtain the correlation coefficient. The correlation coefficient ranges from -1 to +1, where a negative value indicates a negative correlation between the two sequences, a positive value indicates a positive correlation, and the closer the absolute value is to one, the stronger the correlation.

[0112] The processor stores the calculated correlation coefficients in memory and, combined with the trend changes in the historical insulation resistance sequence, outputs the corresponding diagnostic results. The diagnostic results include two types: changes in the insulation resistance measurement are caused by changes in the insulation state of the tested system, or by a degradation in the performance of the measuring system itself. The processor makes this judgment using the following logic.

[0113] The processor first detects whether the historical sequence of insulation resistance shows a downward trend. The downward trend is detected using linear regression or a sliding window comparison method. Taking sliding window comparison as an example, the processor takes the insulation resistance values ​​of the most recent 10 periods, calculates the average of these 10 values, and then takes the average of the previous 10 periods. If the current average is less than the average of the previous 10 periods, and the difference exceeds a preset downward threshold, a downward trend is determined. If a downward trend is detected, the processor obtains the corresponding correlation coefficient. If the correlation coefficient is negative and its absolute value is greater than a first preset threshold, such as 0.6, the processor determines that the decrease in the insulation resistance measurement is caused by actual aging or fault in the insulation of the tested system and outputs an insulation warning signal. This warning signal can be sent to a host computer via a communication interface or displayed on a local screen as "Insulation resistance decreased, please check equipment insulation."

[0114] If the correlation coefficient is positive and its absolute value is greater than the second preset threshold, for example, 0.6, the processor determines that the decrease in the insulation resistance measurement value is caused by a decline in the performance of the measurement system itself, and outputs a measurement system health alarm signal. This alarm signal indicates "Measurement system performance has declined; please check the phase-locked loop or circuit components."

[0115] If the absolute value of the correlation coefficient is less than the third preset threshold, for example, 0.3, the processor determines that the measurement result is affected by random factors, maintains the current monitoring state, and does not output a warning signal. At this time, the processor only records the data and waits for more periods of data accumulation before making a judgment.

[0116] In addition, the processor independently monitors the trend of the historical phase error sequence. The processor continuously calculates the mean or peak value of the historical phase error sequence. Specifically, after each measurement cycle, the processor updates the average phase error of the most recent 10 cycles. If this average value continues to rise and exceeds a preset health threshold—for example, if the average phase error exceeds 1 degree for five consecutive cycles—the processor outputs a measurement system health alarm signal regardless of the correlation coefficient. This is because the continuous increase in phase error itself indicates a decline in the phase-locked loop tracking performance; even if the insulation resistance value remains unchanged, it indicates a problem with the measurement system.

[0117] The technical principle of this method is as follows: When the insulation resistance of the measured system actually decreases, the change in the measured insulation resistance value is caused by the measured quantity itself. At this time, the performance of the measurement system has not changed, therefore the phase error signal of the phase-locked loop (PLL) should remain stable and there is no positive correlation between it and the insulation resistance value; it may even show a negative correlation. When the performance of the measurement system itself deteriorates, the tracking accuracy of the PLL will be affected, and the phase error signal will increase. This decrease in tracking accuracy will also affect the calculated insulation resistance, leading to an abnormal decrease in the insulation resistance value. Therefore, there is a positive correlation between the phase error and the insulation resistance value. These two situations can be distinguished by calculating the correlation coefficient between two historical sequences.

[0118] In a preferred embodiment, the following steps are also included: After the injection frequency is switched, online adaptive phase drift compensation is triggered; The online adaptive phase drift compensation includes: Within the peak range of the injected voltage, the sampling voltage waveform across the sampling resistor is acquired using an oversampling method, and the dynamic zero-crossing phase value and dynamic peak phase value under the current actual physical phase are extracted. The dynamic zero-crossing phase value is compared with the second phase offset corresponding to the current injection frequency in the calibration parameter table to obtain the pure hardware phase drift. The pure hardware phase drift is superimposed on the synchronization reference signal output by the digital phase-locked loop to generate a dynamically corrected sampling trigger signal; Simultaneously, the pure hardware phase drift is superimposed with the first phase offset and the second phase offset corresponding to the current injection frequency in the calibration parameter table to form an updated phase offset, which is then stored in the calibration parameter table.

[0119] Specifically, phase offset self-calibration is performed after system startup or injection frequency adjustment, recording the static phase offset. However, during long-term system operation, temperature changes cause resistance and capacitance values ​​to drift, and component aging also alters circuit parameters; these factors all contribute to the slow change in phase offset. To compensate for this dynamic drift, this method triggers online adaptive phase drift compensation after each injection frequency switch.

[0120] After the processor completes the injection frequency switch, it first performs phase offset self-calibration to obtain the static phase offset at the current frequency, including the first phase offset (peak point offset) and the second phase offset (zero crossing point offset), and stores these offsets in the calibration parameter table. Subsequently, the processor enters online adaptive compensation mode.

[0121] Within the peak range of the injected voltage, the processor acquires the sampled voltage waveform across the sampling resistor using an oversampling method. Oversampling refers to a sampling rate much higher than the signal frequency, for example, setting the sampling rate to 256 times the injection frequency. In practice, the processor configures the analog-to-digital converter to operate continuously at this high sampling rate, acquiring sampled voltage data for multiple cycles. The processor locates the peak region of the injected voltage within the acquired data. Since the injected voltage is a known sine wave, its peak position can be determined using the synchronization reference signal output by the phase-locked loop. The processor extracts a window of data near the peak position corresponding to the synchronization reference signal, for example, 10 sampling points before and after the peak point, for a total of 21 sampling points.

[0122] The processor performs waveform analysis on these sampling points to extract the dynamic zero-crossing phase value and dynamic peak phase value under the current actual physical phase. The dynamic peak phase value is extracted by finding the maximum value of the sampled voltage in the captured window of data and recording its sampling number within the entire waveform. Since the sampling rate is known, the sampling number can be converted to time, and then converted to a phase value based on the injection frequency; this phase value is the dynamic peak phase value. The dynamic zero-crossing phase value is extracted by capturing a window of data near the zero-crossing point, finding the point where the sampled voltage changes from negative to positive, recording its sampling number, converting it to a phase value, and obtaining the dynamic zero-crossing phase value.

[0123] The processor reads the second phase offset corresponding to the current injection frequency from the calibration parameter table. This second phase offset is the static zero-crossing offset obtained through self-calibration. The processor compares the dynamic zero-crossing phase value with the static second phase offset, calculates the difference, and obtains the pure hardware phase drift. The pure hardware phase drift reflects the change in actual phase offset relative to the static calibration value caused by factors such as temperature variations and component aging. Specifically, the processor performs a subtraction operation: the pure hardware phase drift equals the dynamic zero-crossing phase value minus the static second phase offset.

[0124] The processor superimposes the pure hardware phase drift onto the synchronization reference signal output by the digital phase-locked loop (PLL) to generate a dynamically corrected sampling trigger signal. Specifically, the processor configures the timer's compare channel, using the rising edge of the original synchronization reference signal as a reference, and superimposes the delay corresponding to the pure hardware phase drift onto the reference time to obtain a new trigger moment. When the timer count reaches the new trigger moment, it triggers the analog-to-digital converter (ADC) to perform sampling. In this way, the sampling trigger moment can follow the dynamic changes in the hardware phase in real time.

[0125] Simultaneously, the processor superimposes the pure hardware phase drift with the first and second phase offsets corresponding to the current injected frequency in the calibration parameter table to form an updated phase offset, which is then stored in the calibration parameter table. Specifically, the processor reads the first phase offset corresponding to the current frequency from the calibration parameter table, adds the pure hardware phase drift to obtain the updated first phase offset, and reads the second phase offset, adds the pure hardware phase drift to obtain the updated second phase offset. The processor writes the updated two offsets back to the corresponding entries in the calibration parameter table, overwriting the original values. In this way, the offsets in the calibration parameter table are no longer static values, but dynamic values ​​that are updated in real time as the system runs, continuously tracking changes in hardware parameters.

[0126] During subsequent normal measurements, the processor directly uses the updated phase offset from the calibration parameter table for sampling triggering, without needing to re-execute the complete self-calibration process. Static self-calibration and online adaptive compensation are only re-triggered when the injection frequency is readjusted.

[0127] The technical principle of this method lies in the fact that the resistance and capacitance values ​​in a circuit drift with temperature changes, and this drift is slow and continuous. Static self-calibration is only performed during system startup or frequency adjustment, and cannot cover the slow drift during long-term operation. Through online adaptive compensation, after each measurement cycle or frequency switch, the change in actual phase relative to the static calibration value is detected in real time, and this change is superimposed on the sampling trigger signal, thus achieving real-time compensation for dynamic drift.

[0128] The technical effects achieved by this method are: real-time compensation for dynamic phase drift caused by factors such as temperature changes and component aging, ensuring that the sampling time is always precisely aligned with the true characteristic point of the sampling voltage; the calculation of the pure hardware phase drift is based on actual measurement, without the need for additional temperature sensors or aging models; the dynamic updating of the calibration parameter table enables adaptive maintenance of parameters, significantly improving long-term operational stability; the entire compensation process is completed automatically in the background without affecting the normal measurement process.

[0129] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for monitoring the insulation resistance of a DC system based on time-phase locking, characterized in that, The following measurement circuit is used: a bridge resistor is connected to the positive and negative terminals of the DC system respectively. The common terminal of the two bridge resistors is connected to the first terminal of the first resistor. The second terminal of the first resistor is connected to the negative terminal of the injected voltage source. The positive terminal of the injected voltage source is grounded. The DC blocking capacitor is connected in series with the sampling resistor and then in parallel across the two terminals of the first resistor. The method includes the following steps: A sinusoidal voltage is injected into the DC system at a preset frequency, and the sampling voltage across the sampling resistor is collected in real time. A digital phase-locked loop is used to track the phase difference between the injected voltage and the sampled voltage in real time. Based on the phase information output by the digital phase-locked loop, the maximum value and the corresponding first injected voltage value are collected when the sampled voltage reaches its maximum value, and the corresponding second injected voltage value is collected when the sampled voltage crosses zero. Based on the maximum value of the sampled voltage and the corresponding first injection voltage value, and the second injection voltage value corresponding to the zero-crossing point of the sampled voltage, the current insulation resistance value is calculated.

2. The DC system insulation resistance monitoring method based on time-phase locking according to claim 1, characterized in that, The method of using a digital phase-locked loop to track the phase difference between the injected voltage and the sampled voltage in real time includes the following steps: The injected voltage is used as a reference signal input to the digital phase-locked loop. The phase detector of the digital phase-locked loop detects the phase difference between the injected voltage and the sampled voltage, and generates a phase error signal. The phase error signal is filtered by a loop filter and then input to a voltage-controlled oscillator or a numerically controlled oscillator to generate a synchronization reference signal that is synchronized with the injected voltage. The analog-to-digital converter is triggered by the rising or falling edge of the synchronization reference signal to sample the maximum value point and the zero crossing point of the sampled voltage, respectively. Specifically, when the phase difference between the synchronization reference signal and the sampling voltage is locked to zero, the sampling time is precisely aligned with the characteristic point of the sampling voltage.

3. The DC system insulation resistance monitoring method based on time-phase locking according to claim 2, characterized in that, Before triggering the analog-to-digital converter with the rising or falling edge of the synchronization reference signal to sample the maximum value point and zero-crossing point of the sampled voltage, the following steps are also included: After system startup or injection frequency adjustment, perform phase offset self-calibration: Inject a sinusoidal voltage into the DC system at the current injection frequency, continuously collect the sampled voltage waveform for multiple cycles, determine the true phase position of the maximum value point of the sampled voltage, and determine the first phase offset between the true phase position and the rising or falling edge of the synchronization reference signal. Determine the true phase position of the zero-crossing point of the sampled voltage, and determine the second phase offset between the true phase position and the rising or falling edge of the synchronization reference signal; The phase offset is stored in the calibration parameter table, which records the first phase offset between the maximum value point of the sampled voltage and the synchronization reference signal at different injection frequencies, and the second phase offset between the zero crossing point of the sampled voltage and the synchronization reference signal. During subsequent normal measurements, the corresponding first phase offset and second phase offset are retrieved from the calibration parameter table according to the current injection frequency. The sampling of the maximum value point of the sampling voltage is triggered after the first phase offset is superimposed on the rising or falling edge of the synchronization reference signal, and the sampling of the zero-crossing point of the sampling voltage is triggered after the second phase offset is superimposed.

4. The method for monitoring the insulation resistance of a DC system based on time-phase locking according to claim 1, characterized in that, The method also includes dynamically adjusting the injection frequency of the sinusoidal voltage; The dynamic adjustment of the injection frequency of the sinusoidal voltage includes the following steps: Based on the calculated insulation resistance value, combined with the ratio of the maximum value of the sampling voltage at the current injection frequency to the corresponding first injection voltage value, and the second injection voltage value corresponding to the zero crossing point of the sampling voltage, the current value of the capacitance to ground is estimated by solving the impedance equation containing the capacitance to ground parameter. The current value of the capacitance to ground is compared with a preset capacitance threshold range. If the current capacitance to ground value falls within the first threshold range, the injection frequency is adjusted to the first frequency; if the current capacitance to ground value falls within the second threshold range, the injection frequency is adjusted to the second frequency. The first frequency and the second frequency correspond to the operating points where the sensitivity of the sampling voltage amplitude to capacitance changes is zero or close to zero, so that at the adjusted frequency, the maximum value of the sampling voltage and the corresponding injection voltage value, as well as the injection voltage value corresponding to the zero-crossing point of the sampling voltage, are minimally affected by the fluctuation of the capacitance to ground.

5. The method for monitoring the insulation resistance of a DC system based on time-phase locking according to claim 1, characterized in that, The calculation to obtain the current insulation resistance value includes the following steps: Multiple measurement cycles are executed continuously. In each cycle, a set of sampling data is collected. Each set of sampling data includes a maximum value of the sampling voltage and the corresponding first injection voltage value, and a second injection voltage value corresponding to a zero-crossing point of the sampling voltage. Phase consistency verification is performed on multiple sets of sampling data collected within multiple cycles, and abnormal cycle data whose phase difference is not locked within the preset threshold range are removed; The maximum value of the sampled voltage in each group of sampled data retained after verification is compared with the corresponding first injection voltage value to obtain multiple ratio data, and the second injection voltage value in each group of sampled data retained after verification is used as multiple voltage data. Statistical processing is performed on multiple ratio data to obtain the first statistical value, and statistical processing is performed on multiple voltage data to obtain the second statistical value; The first and second statistical values ​​are used as the final input values ​​for the insulation resistance calculation. They are then substituted into the insulation resistance solution equation pre-constructed based on the circuit parameters, injection frequency, and the topology of the measurement circuit to obtain the current insulation resistance value.

6. The DC system insulation resistance monitoring method based on time-phase locking according to claim 5, characterized in that, The phase consistency verification of multiple sets of sampled data collected over multiple periods includes the following steps: During each measurement cycle, the phase error signal output by the digital phase-locked loop is continuously monitored; When the absolute value of the phase error signal is continuously less than the first error threshold within a preset time window, the current period is determined to be a valid phase-locking period, and the sampled data collected in the current period is marked as valid data. When the absolute value of the phase error signal is greater than or equal to the first error threshold within a preset time window, the current period is determined to be a phase unlocking period, and the sampled data collected in the current period is marked as invalid data and discarded. The number of cycles marked as invalid data in multiple consecutive measurement cycles is counted. If the number of invalid data cycles exceeds the preset threshold, it is determined that there is continuous interference or circuit abnormality in the current measurement environment, the insulation resistance calculation is paused and an alarm signal is output. If the number of invalid data periods does not exceed the preset threshold, only invalid data will be removed, and valid data will continue to be used for subsequent ratio calculations and statistical processing.

7. The DC system insulation resistance monitoring method based on time-phase locking according to claim 4, characterized in that, After dynamically adjusting the injection frequency of the sinusoidal voltage, the method further includes the following steps: When the injection frequency is switched from the current frequency to the adjusted new frequency, the first measurement period after the switching time is marked as the transition period; During the transition period, the digital phase-locked loop re-establishes phase lock with the new frequency as a reference, and before the phase lock is established, it pauses the acquisition of the maximum value of the sampling voltage and the corresponding first injection voltage value, and the second injection voltage value corresponding to the zero crossing point of the sampling voltage. The system detects whether the digital phase-locked loop has completed phase locking. When the phase difference is locked within a preset error range, the phase locking is determined to be complete. Starting from the next measurement cycle after phase lock is established, resume the acquisition of the maximum value of the sampled voltage and the corresponding first injection voltage value, and the second injection voltage value corresponding to the zero crossing point of the sampled voltage, and mark the first measurement cycle after the acquisition is resumed as the valid start cycle; Data collected during the transition period is not included in subsequent multi-period statistical processing, while data from the effective starting period and its subsequent periods are included in the calculation window of multi-period statistical processing.

8. The method for monitoring the insulation resistance of a DC system based on time-phase locking according to claim 7, characterized in that, After switching the injection frequency from the current frequency to the adjusted new frequency, the following steps are also included: Retrieve the last measurement result before frequency adjustment, including the injection frequency, maximum sampling voltage, first injection voltage value, second injection voltage value, and calculated insulation resistance value at that time; After frequency adjustment, multiple measurement cycles are performed continuously at the new injection frequency to obtain the insulation resistance value at the new frequency; Based on the ratio of the maximum value of the sampled voltage to the first injected voltage value at the two frequencies before and after frequency adjustment, and the second injected voltage value corresponding to the zero-crossing point of the sampled voltage, a frequency normalization mapping relationship is constructed. The insulation resistance value measured after frequency adjustment is converted to the equivalent insulation resistance value before frequency adjustment according to the frequency normalization mapping relationship, so as to generate a normalized insulation resistance value that is consistent with historical data. The normalized insulation resistance value is stored in a historical trend database for continuous trend analysis and comparison with historical data before frequency adjustment.

9. The DC system insulation resistance monitoring method based on time-phase locking according to claim 1, characterized in that, It also includes the following steps: During continuous monitoring, the phase error signal in each measurement cycle is recorded to form a phase error history sequence, and the normalized insulation resistance value corresponding to each measurement cycle is recorded to form an insulation resistance history sequence. The phase error history sequence and the insulation resistance history sequence are time-aligned, and their correlation coefficient is calculated. Based on the correlation coefficient and the trend changes in the historical sequence of insulation resistance, the corresponding diagnostic results are output; the diagnostic results include whether the change in the insulation resistance measurement value is caused by a change in the insulation state of the measured system or by a decline in the performance of the measurement system itself.

10. The method for monitoring the insulation resistance of a DC system based on time-phase locking according to claim 3, characterized in that, It also includes the following steps: After the injection frequency is switched, online adaptive phase drift compensation is triggered; The online adaptive phase drift compensation includes: Within the peak range of the injected voltage, the sampling voltage waveform across the sampling resistor is acquired using an oversampling method, and the dynamic zero-crossing phase value and dynamic peak phase value under the current actual physical phase are extracted. The dynamic zero-crossing phase value is compared with the second phase offset corresponding to the current injection frequency in the calibration parameter table to obtain the pure hardware phase drift. The pure hardware phase drift is superimposed on the synchronization reference signal output by the digital phase-locked loop to generate a dynamically corrected sampling trigger signal; Simultaneously, the pure hardware phase drift is superimposed with the first phase offset and the second phase offset corresponding to the current injection frequency in the calibration parameter table to form an updated phase offset, which is then stored in the calibration parameter table.

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