A method for optimizing the parameters of a high-voltage generating circuit of an X-ray tube

Abstract

The present application relates to the technical field of high-voltage power supply control, and discloses a high-voltage generation circuit parameter optimization design method of an X-ray tube, comprising the following steps: step one, constructing a three-stage cascaded boost topology architecture composed of a first-stage flyback conversion circuit, a second-stage full-bridge LLC resonant conversion circuit and a third-stage 24 times voltage multiplier rectifier circuit; step two, establishing a charge dynamic flow transfer model based on the 24 times voltage multiplier rectifier circuit, and calculating an estimated ripple voltage at an output end of the 24 times voltage multiplier rectifier circuit by using the charge dynamic flow transfer model. The three-stage cascaded boost topology architecture is adopted, and through multi-stage gain distribution and high-frequency conversion technology, the technical effect of replacing a traditional giant power-frequency transformer with a miniaturized high-frequency transformer and a charge pump component is achieved, the high integration of an internal high-voltage power supply system of a handheld X-ray device is realized, and the deficiency that the existing technology is difficult to realize lightweight and miniaturized operation of the device due to the huge size of the transformer and the cascaded component is solved.

Description

Technical Field

[0001] This invention relates to the field of high-voltage power supply control technology, specifically to a method for optimizing the design of high-voltage generating circuit parameters for X-ray tubes. Background Technology

[0002] In handheld X-ray imaging equipment, the high-voltage generation circuit, as a core functional component, directly determines the X-ray quality and imaging quality of the X-ray tube through the stability and conversion efficiency of its output voltage. With the increasing demands for portability and image resolution in fields such as aerospace non-destructive testing, mobile healthcare, and field operations, achieving stable high-rate voltage conversion within a compact space, and precisely optimizing parameters based on dynamic load characteristics, has become a highly challenging and novel technical problem in this field.

[0003] Currently, the industry typically uses methods such as power frequency transformer step-up, single-stage high-frequency conversion circuits, or conventional pulse voltage multiplier circuits to generate high voltage. This approach establishes tens of thousands of volts of DC high voltage at the output terminal through the switching control of power transistors and the induction boost of magnetic components. A simple closed-loop feedback mechanism is used to capture voltage fluctuations at the end to maintain the constancy of the high voltage output.

[0004] In existing technologies, most high-voltage generators are designed under conditions of large heat sinks, thick insulating media, or fixed grid power supply, resulting in circuit schemes that are often bulky and have high power loss. Due to battery voltage fluctuations, limited space for heat dissipation, and the charge pumping effect of the 24x voltage multiplier circuit during high-current exposure in actual handheld processing, these factors can cause instantaneous drops in output voltage and dynamic ripple oscillations, leading to a discrepancy between the detected tube voltage and the actual exposure requirements. This disconnect significantly reduces the imaging consistency of handheld devices during high-frequency continuous exposure, making it difficult to accurately reflect the dynamic performance of the system during operation and easily causing localized overheating. Therefore, this invention proposes a method for optimizing the design parameters of the high-voltage generation circuit of an X-ray tube to solve the aforementioned problems. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a method for optimizing the design of high-voltage generating circuit parameters for X-ray tubes, thereby solving the problems mentioned in the background section.

[0006] To achieve the above objectives, the present invention provides the following technical solution: a method for optimizing the design of high-voltage generating circuit parameters for an X-ray tube, comprising: Step 1: Construct a three-stage cascaded boost topology consisting of a first-stage flyback converter circuit, a second-stage full-bridge LLC resonant converter circuit, and a third-stage 24x voltage multiplier rectifier circuit. Step 2: Establish a charge dynamic flow model based on the 24x voltage multiplier rectifier circuit, and use the charge dynamic flow model to calculate the estimated ripple voltage at the output terminal of the 24x voltage multiplier rectifier circuit; Step 3: Set the bus voltage feedforward control strategy according to the estimated ripple voltage, and adjust the switching duty cycle of the first-stage flyback converter circuit through the bus voltage feedforward control strategy. Step 4: Acquire the output voltage and current signals of the adjusted second-stage full-bridge LLC resonant converter circuit to determine the optimal resonant frequency point of the second-stage full-bridge LLC resonant converter circuit under the current load impedance; Step 5: Calculate the voltage change rate of the second-stage full-bridge LLC resonant converter circuit at the moment of power switching when it is at the optimal resonant frequency point, and adjust the dead time of the power transistor according to the voltage change rate. Step 6: Use the digital dual closed-loop algorithm to sample the high-voltage signal at the end of the circuit after adjusting the dead time in real time, and correct the control parameters of the first-stage flyback converter circuit and the second-stage full-bridge LLC resonant converter circuit based on the verification results obtained from the sampling.

[0007] Preferably, the three-stage cascaded boost topology is encapsulated in a metal shielded cavity with electromagnetic shielding characteristics, and an electrical isolation feedback circuit is provided between the first-stage flyback converter circuit and the second-stage full-bridge LLC resonant converter circuit. The 24x voltage multiplier rectifier circuit adopts an asymmetric capacitor arrangement structure, wherein the capacitor near the output terminal of the second-stage full-bridge LLC resonant converter circuit has a higher capacitance than the terminal capacitor.

[0008] Preferably, the algorithm formula for estimating the ripple voltage is as follows: , in, To predict ripple voltage, This is the output current of the third-stage 24x voltage multiplier rectifier circuit. For switching frequency, This refers to the capacitance value of a single-stage capacitor. This is the voltage multiplier stage.

[0009] Preferably, the bus voltage feedforward control strategy specifically involves converting the estimated ripple voltage into a voltage compensation increment and superimposing the voltage compensation increment into the original duty cycle control signal of the first-stage flyback converter circuit.

[0010] Preferably, in step four, when acquiring the output voltage and current signals of the second-stage full-bridge LLC resonant converter circuit, a weighted average filtering process is performed on the sampled data to eliminate high-frequency spurious interference. The method for determining the optimal resonant frequency point is as follows: establish a voltage gain model of the second-stage full-bridge LLC resonant converter circuit, and search for the lowest operating frequency that enables the power transistor to achieve zero-voltage turn-on under the current load impedance. The process of determining the optimal resonant frequency point includes dynamic correction of the resonant cavity parameters: real-time monitoring of the resonant current waveform of the second-stage full-bridge LLC resonant converter circuit, identification of the inductance drift value of the transformer core at different temperatures through waveform feature extraction; updating the parameters of the voltage gain model based on the inductance drift value, recalculating the current theoretical resonant frequency using the updated voltage gain model, and searching for the optimal resonant frequency point using the theoretical resonant frequency as the central reference value.

[0011] Preferably, the dead time of the adjusted power transistor satisfies the following calculation criteria: , in, Dead time, For the power transistor output capacitor, This refers to the bus voltage output from the first-stage flyback converter circuit. This represents the peak current of the resonant cavity.

[0012] Preferably, the digital dual closed-loop algorithm includes an inner current control loop and an outer voltage control loop, and the sampling frequency of the inner current control loop is set to be more than five times the sampling frequency of the outer voltage control loop. Step six includes an anomaly determination process: when the verification result shows that the high voltage signal output at the end continuously deviates from the preset threshold, the main control unit blocks the drive pulses of the first-stage flyback converter circuit and the second-stage full-bridge LLC resonant converter circuit.

[0013] Preferably, the correction process of the control parameters includes a step-by-step compensation logic for the nonlinear drop of the third-stage 24x voltage multiplier rectifier circuit: establishing a nonlinear mapping function between the terminal output high voltage signal and the bus voltage output by the first-stage flyback converter circuit, and calculating the instantaneous voltage drop slope of the terminal output high voltage signal based on the verification result; When the instantaneous voltage drop slope exceeds the preset rate of change threshold, the switching duty cycle gain of the first-stage flyback converter circuit and the pulse frequency offset of the second-stage full-bridge LLC resonant converter circuit are simultaneously adjusted by the digital dual closed-loop algorithm.

[0014] Preferably, the three-stage cascaded boost topology is controlled by an AMR processor, which establishes a real-time communication connection with an external host computer. The AMR processor has a pre-stored database of impedance characteristics of X-ray tubes of different specifications. The AMR processor receives exposure parameter instructions from the host computer and extracts the corresponding initial control vector from the impedance characteristic database according to the exposure parameter instructions. The initial control vector includes the preset duty cycle of the first-stage flyback converter circuit and the starting operating frequency of the second-stage full-bridge LLC resonant converter circuit. The AMR processor performs segmented pre-excitation on the three-stage cascaded boost topology based on the initial control vector to shorten the steady-state settling time for the terminal output high-voltage signal to reach the set value.

[0015] Preferably, the process by which the AMR processor performs the adjustment of the dead time of the power transistor includes jitter processing of the electromagnetic interference frequency band: after determining a reference value for the dead time based on the voltage change rate, the AMR processor superimposes pulse jitter generated by a pseudo-arbitrary frequency within a narrow frequency band centered on the optimal resonant frequency point on the basis of the reference value. The AMR processor synchronizes the circuit operation status data after pulse jitter to the host computer in real time. The host computer performs closed-loop optimization on the disturbance amplitude of the pseudo-arbitrary sequence based on the smoothness of the received high voltage waveform, and suppresses the high-frequency interference of the three-stage cascaded boost topology to the sensitive pins of the AMR processor by dispersing the spectral energy distribution of switching noise.

[0016] This invention provides a method for optimizing the design parameters of a high-voltage generating circuit for an X-ray tube. It offers the following advantages: 1. This invention adopts a three-stage cascaded boost topology architecture. Through multi-stage gain distribution and high-frequency conversion technology, it achieves the technical effect of replacing traditional giant power frequency transformers with miniaturized high-frequency transformers and charge pump components. This realizes the high integration of the internal high-voltage power supply system of handheld X-ray equipment and solves the shortcomings of existing technologies, which make it difficult to achieve lightweight and miniaturized operation of equipment due to the huge size of transformers and cascaded components.

[0017] 2. This invention employs an adaptive frequency control method that searches for the optimal resonant frequency point and dynamically adjusts the dead time of the power transistor based on the voltage change rate. This achieves the technical effect of keeping the full-bridge LLC resonant converter circuit in the inductive region at all times, thus realizing zero-voltage turn-on. This minimizes switching losses and electromagnetic losses, significantly reduces the instantaneous temperature rise inside the system, and extends battery life. It also solves the shortcomings of traditional converter circuits, such as compromised electronic component reliability and limited heat dissipation due to severe switching losses.

[0018] 3. This invention employs a predictive ripple voltage calculation based on a charge dynamic flow model, combined with a bus voltage feedforward control strategy and a digital dual closed-loop algorithm. This achieves the technical effect of predicting charge pumping demand through the AMR processor at the moment of exposure and cross-stage linkage compensation. It realizes extremely small ripple interference and high-precision dynamic adjustment of the 70kV high-voltage signal at the output end, solving the problems of output voltage drift and oscillation caused by the significant nonlinear characteristics of the voltage multiplier circuit, as well as the blurring or severe noise in the X-ray tube imaging at the back end. Attached Figure Description

[0019] Figure 1 This is a flowchart of the present invention; Figure 2 This is a schematic diagram of the overall power supply design structure of the present invention; Figure 3 The flyback circuit of this invention; Figure 4 This is a diagram showing the current variation in the flyback circuit of the present invention. Detailed Implementation

[0020] To enable those skilled in the art to understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort should fall within the scope of protection of the present invention.

[0021] The present invention will now be described in detail with reference to the accompanying drawings: Please see the appendix Figure 1-4 This invention provides a method for optimizing the design of high-voltage generating circuit parameters for an X-ray tube, comprising: Step 1: Construct a three-stage cascaded boost topology consisting of a first-stage flyback converter circuit, a second-stage full-bridge LLC resonant converter circuit, and a third-stage 24x voltage multiplier rectifier circuit. The three-stage cascaded boost topology is packaged in a metal shielded cavity with electromagnetic shielding properties, and an electrical isolation feedback circuit is provided between the first-stage flyback converter circuit and the second-stage full-bridge LLC resonant converter circuit. The 24x voltage multiplier rectifier circuit adopts an asymmetrical capacitor arrangement structure, in which the capacitance of the capacitor near the output terminal of the second-stage full-bridge LLC resonant converter circuit is higher than that of the terminal capacitor. Step 2: Establish a charge dynamic flow model based on the 24x voltage multiplier rectifier circuit, and use the charge dynamic flow model to calculate the estimated ripple voltage at the output of the 24x voltage multiplier rectifier circuit. The algorithm formula for estimating ripple voltage is as follows: , in, To predict ripple voltage, This is the output current of the third-stage 24x voltage multiplier rectifier circuit. For switching frequency, This refers to the capacitance value of a single-stage capacitor. This refers to the voltage multiplier stage; Step 3: Set the bus voltage feedforward control strategy according to the estimated ripple voltage, and adjust the switching duty cycle of the first-stage flyback converter circuit through the bus voltage feedforward control strategy. The bus voltage feedforward control strategy is as follows: the estimated ripple voltage is converted into a voltage compensation increment, and the voltage compensation increment is superimposed on the original duty cycle control signal of the first-stage flyback converter circuit. Step 4: Acquire the output voltage and current signals of the adjusted second-stage full-bridge LLC resonant converter circuit to determine the optimal resonant frequency point of the second-stage full-bridge LLC resonant converter circuit under the current load impedance; In step four, when acquiring the output voltage and current signals of the second-stage full-bridge LLC resonant converter circuit, a weighted average filtering process is performed on the sampled data to eliminate high-frequency spurious interference. The method for determining the optimal resonant frequency is as follows: establish a voltage gain model of the second-stage full-bridge LLC resonant converter circuit, and search for the lowest operating frequency that enables the power transistor to achieve zero-voltage turn-on under the current load impedance. The process of determining the optimal resonant frequency point includes dynamic correction of the resonant cavity parameters: real-time monitoring of the resonant current waveform of the second-stage full-bridge LLC resonant converter circuit, identification of the inductance drift value of the transformer core at different temperatures through waveform feature extraction; updating the parameters of the voltage gain model based on the inductance drift value, recalculating the current theoretical resonant frequency using the updated voltage gain model, and searching for the optimal resonant frequency point using the theoretical resonant frequency as the central reference value. Step 5: Calculate the voltage change rate of the second-stage full-bridge LLC resonant converter circuit at the moment of power switching when it is at the optimal resonant frequency point, and adjust the dead time of the power transistor according to the voltage change rate. The dead time of the power transistor should be adjusted to meet the following calculation criteria: , in, Dead time, For the power transistor output capacitor, This refers to the bus voltage output from the first-stage flyback converter circuit. This represents the peak current of the resonant cavity. Step 6: Use the digital dual closed-loop algorithm to sample the high-voltage signal at the end output after adjusting the dead time in real time, and correct the control parameters of the first-stage flyback converter circuit and the second-stage full-bridge LLC resonant converter circuit based on the verification results obtained from the sampling. The digital dual closed-loop algorithm includes an inner current control loop and an outer voltage control loop, and the sampling frequency of the inner current control loop is set to be more than five times the sampling frequency of the outer voltage control loop. Step six includes an anomaly detection process: when the verification result shows that the high voltage signal output at the end continuously deviates from the preset threshold, the main control unit blocks the drive pulses of the first-stage flyback converter circuit and the second-stage full-bridge LLC resonant converter circuit.

[0022] The process of correcting the control parameters includes a step-by-step compensation logic for the nonlinear drop of the third-stage 24x voltage multiplier rectifier circuit: establishing a nonlinear mapping function between the terminal output high voltage signal and the bus voltage output of the first-stage flyback converter circuit, and calculating the instantaneous voltage drop slope of the terminal output high voltage signal based on the verification results. When the instantaneous voltage drop slope exceeds the preset rate of change threshold, the switching duty cycle gain of the first-stage flyback converter circuit and the pulse frequency offset of the second-stage full-bridge LLC resonant converter circuit are adjusted simultaneously through a digital dual closed-loop algorithm.

[0023] The three-stage cascaded boost topology is controlled by an AMR processor, which establishes a real-time communication connection with an external host computer. The AMR processor has a database of impedance characteristics for X-ray tubes of different specifications pre-stored inside. The AMR processor receives exposure parameter commands from the host computer and extracts the corresponding initial control vector from the impedance characteristic database according to the exposure parameter commands. The initial control vector includes the preset duty cycle of the first-stage flyback converter circuit and the starting operating frequency of the second-stage full-bridge LLC resonant converter circuit. The AMR processor performs segmented pre-excitation on the three-stage cascaded boost topology based on the initial control vector to shorten the steady-state settling time of the terminal output high-voltage signal to reach the set value.

[0024] The process of adjusting the dead time of the power transistor by the AMR processor includes jitter processing of the electromagnetic interference frequency band: After determining the reference value of the dead time based on the voltage change rate, the AMR processor superimposes pulse jitter generated by pseudo-arbitrary frequency in a narrow frequency band centered on the optimal resonant frequency point on the reference value. The AMR processor synchronizes the circuit operation status data after pulse jitter to the host computer in real time. The host computer performs closed-loop optimization on the disturbance amplitude of the pseudo-arbitrary sequence based on the smoothness of the received high voltage waveform. It suppresses high-frequency interference of the three-stage cascaded boost topology to the sensitive pins of the AMR processor by dispersing the spectral energy distribution of switching noise.

[0025] The first-stage flyback converter circuit, as the primary boost and voltage regulation unit, effectively boosts the input voltage through the periodic energy storage and release mechanism of the transformer. At the same time, it provides a stable and flexibly adjustable intermediate bus voltage for the subsequent power conversion stage, and is the basic power supply stage of the high-voltage power supply system. The second-stage full-bridge LLC resonant converter circuit serves as the core power conversion unit. It makes full use of passive components such as resonant inductors and resonant capacitors to achieve zero-voltage or zero-current soft-switching of power switching devices. It can complete high-efficiency energy transfer and secondary boosting processes under high-frequency operating conditions, significantly reducing switching losses and electromagnetic interference. The third-stage 24x voltage multiplier rectifier circuit adopts a structure in which multi-stage diodes and capacitors are cascaded alternately in the form of a charge pump. It converts the high-frequency AC power output from the previous stage into high-voltage DC power at the tens of thousands of volts level through the accumulation of charge and the superposition of voltage at each stage. This is the key topology for achieving ultra-high voltage output. The charge dynamic flow model is used to accurately describe the charge transfer and redistribution behavior of each capacitor in a voltage multiplier circuit during the periodic charging and discharging process. This model is an important mathematical tool and theoretical basis for analyzing system output impedance, calculating voltage ripple, and evaluating dynamic performance. As an active disturbance suppression method, the bus voltage feedforward control strategy monitors the changes in input or intermediate voltage in real time and predicts the voltage drop trend at the end, thereby adjusting the output of the upstream converter in advance to effectively offset the system response delay caused by the cascading of multiple circuits. The optimal resonant frequency point refers to the specific frequency at which the full-bridge LLC resonant circuit operates in the ideal soft-switching state where the primary-side switching transistor achieves zero-voltage turn-on and the secondary-side rectifier diode achieves zero-current turn-off. This frequency can maximize the conversion efficiency and reduce electromagnetic noise. The asymmetric capacitor arrangement structure is based on the physical characteristics that each stage of the voltage multiplier circuit has a different degree of influence on the output ripple. By selectively configuring capacitors of different capacities, a better distribution of voltage stress can be achieved, thereby reducing the system size and total capacitance while maintaining performance. The digital dual closed-loop control algorithm is a cascaded control structure consisting of a fast-response current inner loop and a high-precision voltage outer loop. The inner loop is responsible for dynamically adjusting and stabilizing the power, while the outer loop ensures the steady-state accuracy of the output voltage, together improving the control quality of the system. The host computer user interface and remote monitoring terminal provide a graphical operating environment for sending control commands to the high-voltage system, displaying output waveforms and parameters in real time, and enabling advanced settings and optimizations of the adjustment parameters of the underlying controller, thereby improving the system's controllability and observability.

[0026] A three-stage cascaded boost topology is constructed by decomposing the total boost ratio into flyback, resonant, and voltage multiplier stages, significantly reducing voltage stress on power devices at each stage and avoiding leakage inductance losses and insulation problems associated with single-stage high-ratio boosting. The metal-shielded enclosure, combined with an electrically isolated feedback circuit, effectively cuts off the conduction path of high-voltage discharge noise to the low-voltage control side, ensuring the purity of the control signal under extreme high-voltage environments. The asymmetric capacitor arrangement, based on the physical characteristic that current stress increases closer to the source in a voltage multiplier link, precisely allocates energy storage resources, significantly reducing the space occupied by the capacitor bank while ensuring output rigidity.

[0027] Establishing a dynamic charge flow model enables in-depth analysis of the complex energy transfer logic within a multi-stage voltage multiplier circuit, accurately quantifying the impact of the charging and discharging time constants of each capacitor on the final output voltage fluctuations. Utilizing a specific algorithmic formula to calculate and estimate the ripple voltage allows for digital prediction of high-voltage quality, providing a precise data reference for subsequent control algorithms. This mathematical model-based prediction method overcomes the shortcomings of traditional control methods, which passively adjust after ripple generation, providing a theoretical basis for the system to fundamentally compensate for the physical defects of the voltage multiplier circuit.

[0028] A bus voltage feedforward control strategy is implemented to directly feed back the predicted voltage fluctuation information to the first-stage converter circuit, enabling advanced scheduling of the voltage compensation signal across different stages. By superimposing the voltage compensation increment onto the original duty cycle signal, the first-stage flyback circuit can increase the energy supply in advance when the load changes, thus compensating for the voltage trap caused by the charging and discharging lag in the subsequent voltage multiplier circuit. This control method significantly shortens the system's dead zone for voltage fluctuation regulation, ensuring that the high voltage output at the end remains at a stable set level during high-speed pulse exposure.

[0029] Acquiring the output signal and searching for the optimal resonant frequency ensures that the full-bridge LLC circuit always operates within the golden range of highest conversion efficiency and lowest electromagnetic interference. A dynamic correction mechanism for resonant cavity parameters is introduced, monitoring the current waveform to detect changes in the physical characteristics of the transformer caused by temperature rise over long-term operation, and updating the voltage gain model in real time accordingly. This adaptive frequency search logic eliminates the negative impact of ambient temperature drift on the resonant state, enabling the circuit to accurately maintain the soft-switching characteristics of the power transistors even under continuous high-intensity operation, completely avoiding the risk of transistor burnout due to detuning.

[0030] Calculating the voltage change rate during power switching accurately captures subtle dynamics during circuit commutation, providing real-time feedback for dead-time optimization. Dynamic adjustments based on dead-time calculation criteria ensure that the power transistor turns on the moment its parasitic capacitance is completely discharged, eliminating overlapping losses during switching at the source. This precise timing control improves the overall energy conversion efficiency of the power system and effectively reduces the self-generated heat of the power transistor during high-frequency switching.

[0031] By utilizing a digital dual-loop algorithm combined with a high-frequency sampling current inner loop, the system achieves rapid capture and millisecond-level correction of minute disturbances in the high-voltage output, ensuring the rigor of the system control logic. The anomaly detection process, through continuous monitoring of the output status by the main control unit, provides reliable software protection for the equipment, instantly shutting down the drive in the event of arcing or load short circuits to protect sensitive electronic components from damage. The stepped compensation logic addresses the inherent gain drop problem of the voltage multiplier circuit through a nonlinear mapping function, enabling the system to output highly linear and precise high voltage across the entire load range, providing a stable physical foundation for high-quality X-ray imaging.

[0032] Employing an AMR processor and host computer-linked control mode, and utilizing a pre-stored impedance characteristic database and segmented pre-excitation technology, personalized drive configurations are achieved for different X-ray tube models, significantly accelerating the response rate of high voltage rising from zero to the set value. Pseudo-arbitrary frequency pulse jitter technology, through algorithm-level spectrum shaping, successfully disperses the spike interference energy generated by the switching circuit evenly, reducing the intensity of electromagnetic radiation emitted by the system. The host computer's closed-loop optimization strategy for jitter amplitude based on waveform smoothness constructs a deeply integrated hardware and software anti-interference defense system, fundamentally solving the crosstalk problem of high-voltage power supply to microprocessor communication pins.

[0033] Example 1: When performing handheld non-destructive testing on oil pipelines and bridge steel structures in extremely cold or high-temperature regions, the equipment needs to be... to Under extreme temperature differences, it can instantly output a stable 70kV high voltage, and due to the limitation of battery power supply, it has almost demanding requirements for power conversion efficiency.

[0034] This embodiment employs a three-stage cascaded topology. The first-stage flyback converter initially boosts the 24V voltage of the lithium battery to an intermediate bus voltage of 150V. This circuit uses a planar transformer design to minimize vertical height. The second-stage full-bridge LLC resonant converter is responsible for the main power conversion, with the resonant slot parameters configured based on a center frequency of 100kHz. The third-stage 24x voltage multiplier rectifier circuit uses an asymmetrical capacitor arrangement, with the four capacitors near the front end using 22nF high-voltage ceramic capacitors, while the capacitors at the end decrease to 4.7nF. This arrangement utilizes the characteristics of high current at the front end and high voltage at the back end to reduce size while ensuring ripple suppression capability. The entire system is encapsulated within a 1.5mm thick aluminum-magnesium alloy electromagnetic shielding cavity.

[0035] When detection begins, the AMR processor activates the charge dynamic flow model. Because the 24x voltage multiplier circuit generates significant charge pumping at the moment of load application, the processor uses the formula... The estimated ripple voltage under the current 2mA tube current is approximately 350V.

[0036] Instead of waiting for the high voltage drop at the end of the circuit to occur before adjusting, the system converts the estimated 350V deviation into a voltage compensation increment. The AMR processor directly adjusts the switching duty cycle of the first-stage flyback circuit, instantly boosting the output bus voltage from 150V to 158V. This feedforward control strategy replenishes energy before the charge is depleted, keeping the instantaneous voltage drop at the 70kV output terminal below 0.2%.

[0037] Increased operating time leads to a rise in transformer core temperature, causing a change in permeability. The AMR processor monitors the resonant current waveform of the second-stage LLC circuit in real time using a high-speed ADC. By extracting the zero-crossing and peak characteristics of the current waveform, the system identifies an 8% drift in the resonant inductor. At this point, the AMR processor performs dynamic correction of the resonant cavity parameters: updating the voltage gain model based on the offset, recalculating the theoretical resonant frequency, and adjusting it from 100kHz to 94kHz. Then, it calculates the rate of voltage change at the moment of power transistor switching. The output capacitance of the power transistor is affected by temperature. The charging and discharging speed slows down, and the processor follows... The standard is to precisely compensate the dead time from 300ns to 345ns.

[0038] This operation ensures that even with core inductance drift, the power transistor can achieve perfect zero-voltage turn-on, and the overall conversion efficiency is always maintained above 93%, effectively solving the system protection shutdown problem caused by limited heat dissipation in handheld devices.

[0039] Example 2: In mobile ambulance emergency scenarios, X-ray tubes require rapid, continuous, and high-precision pulse exposure control for different anatomical locations. This demands that the high-voltage generating circuit possess not only extremely high transient response speed and control precision, but also the ability to effectively handle real-time adjustment pressures and system disturbances caused by nonlinear changes in X-ray tube impedance. Especially during chest thickness detection exposure, the spatial electromagnetic field environment generated by the high-voltage circuit is extremely complex and subject to strong interference. The AMR processor acquires the output signal of the full-bridge LLC inverter circuit in real time. To overcome the distortion of sampling data caused by high-frequency switching noise, the system performs weighted moving average filtering on the raw voltage and current data. This algorithm selects the 16 most recent sample values ​​as the filtering window, assigning different weight coefficients based on time proximity to enhance the tracking ability of the latest voltage change trends. Simultaneously, it effectively suppresses instantaneous spike pulses caused by transformer leakage inductance, extracting a clean, stable, and reliable feedback reference signal. The processor core runs a digital dual-loop control algorithm: the inner current loop monitors and regulates the dynamic changes of the transformer primary current in real time with a high sampling rate; the outer voltage loop operates at a slightly lower frequency, aiming to maintain high-precision high-voltage stability in the final output.

[0040] When the X-ray tube is operating at high voltage and shows signs of minor arcing, or when there are severe nonlinear fluctuations in impedance, the system automatically triggers a stepped real-time compensation mechanism for the voltage multiplier circuit. The processor first calculates the instantaneous drop slope of the high-voltage signal based on real-time verification data. If this slope exceeds a safety threshold, the traditional unidirectional linear adjustment strategy is no longer used. Instead, a nonlinear mapping function is used to simultaneously adjust the duty cycle gain of the first-stage flyback converter circuit and the switching frequency offset of the second-stage resonant circuit in a composite and coordinated manner. This linkage adjustment mechanism effectively solves the inherent control disconnect problem in multi-stage cascaded power topologies where "pre-stage control cannot respond to changes in the load of subsequent stages," significantly improving the static accuracy of the high-voltage output. Even under conditions of strong vibration and harsh electromagnetic environments in mobile emergency rescue, the system can still ensure consistent grayscale performance in X-ray imaging, completely resolving common image quality defects in traditional systems such as high image noise and insufficient contrast, providing stable and reliable image support for emergency diagnosis.

[0041] Example 3: In high-end digital operating rooms, the high-voltage generating circuit must perform the voltage boosting task and synchronize status data to the doctor's AR glasses or remote diagnostic host computer via a wireless network. The circuit must not generate any broadband noise that interferes with wireless communication during operation.

[0042] Before the surgery begins, the host computer sends an "interventional guided exposure" command via WiFi. Upon receiving the command, the AMR processor immediately retrieves the internally stored "special X-ray tube impedance characteristic database." Based on the initial control vector provided by the database, the AMR processor executes segmented pre-excitation: within the first 5ms before the doctor presses the foot switch, the duty cycle of the first-stage flyback circuit is locked at 35%, while the LLC circuit operates at a safe frequency far from the resonant point. At this time, the capacitors of the voltage multiplier circuit begin to charge in an orderly manner.

[0043] When the formal exposure command is issued, the time for the high voltage to climb from 0 to the set value is shortened by 15ms compared to the traditional method, which greatly improves the real-time performance of dynamic interventional imaging.

[0044] During continuous high-voltage output, to protect the sensitive ADC pins of the AMR processor and the wireless communication within the operating room from interference, the system activates an electromagnetic interference jitter processing mode. The AMR processor introduces a perturbation generated by a pseudo-random sequence based on the determined optimal dead-time reference. This perturbation causes the switching frequency of the LLC circuit to rapidly "jump" between 98.5kHz and 101.5kHz, rather than being fixed at 100kHz. The host computer receives the synchronously transmitted operating data from the AMR in real time and provides feedback optimization instructions based on the observed high-voltage waveform smoothness. If the host computer detects impaired waveform smoothness, it adjusts the perturbation distribution density of the pseudo-random sequence.

[0045] Through "spectral energy dissipation" technology, the spike electromagnetic interference originally concentrated at a specific frequency point is evenly distributed across a wide frequency band. Tests show that the system's conducted and radiated interference are reduced by more than 15dB, ensuring that expensive surgical robots, ECG monitors, and host computer wireless links can operate stably under 70kV high voltage, and solving the interference problem caused by the inability to install complex hardware filters in handheld devices due to limited space.

[0046] Embodiments of the present invention have been presented and described. It will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for optimizing the design parameters of a high-voltage generating circuit for an X-ray tube, characterized in that, include: Step 1: Construct a three-stage cascaded boost topology consisting of a first-stage flyback converter circuit, a second-stage full-bridge LLC resonant converter circuit, and a third-stage 24x voltage multiplier rectifier circuit. Step 2: Establish a charge dynamic flow model based on the 24x voltage multiplier rectifier circuit, and use the charge dynamic flow model to calculate the estimated ripple voltage at the output terminal of the 24x voltage multiplier rectifier circuit; Step 3: Set the bus voltage feedforward control strategy according to the estimated ripple voltage, and adjust the switching duty cycle of the first-stage flyback converter circuit through the bus voltage feedforward control strategy. Step 4: Acquire the output voltage and current signals of the adjusted second-stage full-bridge LLC resonant converter circuit to determine the optimal resonant frequency point of the second-stage full-bridge LLC resonant converter circuit under the current load impedance; Step 5: Calculate the voltage change rate of the second-stage full-bridge LLC resonant converter circuit at the moment of power switching when it is at the optimal resonant frequency point, and adjust the dead time of the power transistor according to the voltage change rate. Step 6: Use the digital dual closed-loop algorithm to sample the high-voltage signal at the end of the circuit after adjusting the dead time in real time, and correct the control parameters of the first-stage flyback converter circuit and the second-stage full-bridge LLC resonant converter circuit based on the verification results obtained from the sampling.

2. The method for optimizing the design of high-voltage generating circuit parameters for an X-ray tube according to claim 1, characterized in that, The three-stage cascaded boost topology is encapsulated in a metal shielded cavity with electromagnetic shielding characteristics, and an electrical isolation feedback circuit is provided between the first-stage flyback converter circuit and the second-stage full-bridge LLC resonant converter circuit. The 24x voltage multiplier rectifier circuit adopts an asymmetric capacitor arrangement structure, wherein the capacitor near the output terminal of the second-stage full-bridge LLC resonant converter circuit has a higher capacitance than the terminal capacitor.

3. The method for optimizing the design of high-voltage generating circuit parameters for an X-ray tube according to claim 1, characterized in that, The algorithm formula for estimating the ripple voltage is as follows: ， in, To predict ripple voltage, This is the output current of the third-stage 24x voltage multiplier rectifier circuit. For switching frequency, This refers to the capacitance value of a single-stage capacitor. This is the voltage multiplier stage.

4. The method for optimizing the design of high-voltage generating circuit parameters for an X-ray tube according to claim 1, characterized in that, The bus voltage feedforward control strategy specifically involves converting the estimated ripple voltage into a voltage compensation increment and superimposing the voltage compensation increment into the original duty cycle control signal of the first-stage flyback converter circuit.

5. The method for optimizing the design of high-voltage generating circuit parameters for an X-ray tube according to claim 1, characterized in that, In step four, when acquiring the output voltage and current signals of the second-stage full-bridge LLC resonant converter circuit, the sampled data is subjected to weighted average filtering to eliminate high-frequency spurious interference. The method for determining the optimal resonant frequency point is as follows: establish a voltage gain model of the second-stage full-bridge LLC resonant converter circuit, and search for the lowest operating frequency that enables the power transistor to achieve zero-voltage turn-on under the current load impedance. The process of determining the optimal resonant frequency point includes dynamic correction of the resonant cavity parameters: real-time monitoring of the resonant current waveform of the second-stage full-bridge LLC resonant converter circuit, identification of the inductance drift value of the transformer core at different temperatures through waveform feature extraction; updating the parameters of the voltage gain model based on the inductance drift value, recalculating the current theoretical resonant frequency using the updated voltage gain model, and searching for the optimal resonant frequency point using the theoretical resonant frequency as the central reference value.

6. The method for optimizing the design of high-voltage generating circuit parameters for an X-ray tube according to claim 1, characterized in that, The dead time of the adjusted power transistor satisfies the following calculation criteria: ， in, Dead time, For the power transistor output capacitor, This refers to the bus voltage output from the first-stage flyback converter circuit. This represents the peak current of the resonant cavity.

7. The method for optimizing the design of high-voltage generating circuit parameters for an X-ray tube according to claim 1, characterized in that, The digital dual closed-loop algorithm includes an inner current control loop and an outer voltage control loop, and the sampling frequency of the inner current control loop is set to be more than five times the sampling frequency of the outer voltage control loop. Step six includes an anomaly determination process: when the verification result shows that the high voltage signal output at the end continuously deviates from the preset threshold, the main control unit blocks the drive pulses of the first-stage flyback converter circuit and the second-stage full-bridge LLC resonant converter circuit.

8. The method for optimizing the design of high-voltage generating circuit parameters for an X-ray tube according to claim 1, characterized in that, The correction process for the control parameters includes a step-wise compensation logic for the nonlinear drop of the third-stage 24x voltage multiplier rectifier circuit: establishing a nonlinear mapping function between the terminal output high voltage signal and the bus voltage output by the first-stage flyback converter circuit, and calculating the instantaneous voltage drop slope of the terminal output high voltage signal based on the verification results. When the instantaneous voltage drop slope exceeds the preset rate of change threshold, the switching duty cycle gain of the first-stage flyback converter circuit and the pulse frequency offset of the second-stage full-bridge LLC resonant converter circuit are simultaneously adjusted by the digital dual closed-loop algorithm.

9. The method for optimizing the design of high-voltage generating circuit parameters for an X-ray tube according to claim 1, characterized in that, The three-stage cascaded boost topology is controlled by an AMR processor, which establishes a real-time communication connection with an external host computer. The AMR processor has a database of impedance characteristics of X-ray tubes of different specifications pre-stored inside. The AMR processor receives exposure parameter instructions from the host computer and extracts the corresponding initial control vector from the impedance characteristic database according to the exposure parameter instructions. The initial control vector includes the preset duty cycle of the first-stage flyback converter circuit and the starting operating frequency of the second-stage full-bridge LLC resonant converter circuit. The AMR processor performs segmented pre-excitation on the three-stage cascaded boost topology based on the initial control vector to shorten the steady-state settling time for the terminal output high-voltage signal to reach the set value.

10. The method for optimizing the design of high-voltage generating circuit parameters for an X-ray tube according to claim 9, characterized in that, The process by which the AMR processor performs the adjustment of the dead time of the power transistor includes jitter processing of the electromagnetic interference frequency band: after determining the reference value of the dead time based on the voltage change rate, the AMR processor superimposes pulse jitter generated by a pseudo-arbitrary frequency in a narrow frequency band centered on the optimal resonant frequency point on the basis of the reference value. The AMR processor synchronizes the circuit operation status data after pulse jitter to the host computer in real time. The host computer performs closed-loop optimization on the disturbance amplitude of the pseudo-arbitrary sequence based on the smoothness of the received high voltage waveform, and suppresses the high-frequency interference of the three-stage cascaded boost topology to the sensitive pins of the AMR processor by dispersing the spectral energy distribution of switching noise.

Images