A novel bandgap reference start-up circuit with degenerate state detection

Abstract

A novel bandgap reference startup circuit with degeneracy state detection is disclosed, particularly relating to the design of integrated circuit power control chips. The circuit includes a novel bandgap reference startup circuit and a bias voltage and enable signal generation circuit. The novel bandgap reference startup circuit comprises a startup circuit and an inverter, a degeneracy-removal current generation circuit, a bandgap core and process corner adaptive compensation circuit, and a Schmitt trigger circuit. This invention utilizes the on / off characteristics of MOSFETs to achieve startup. By detecting the difference in degeneracy state between the core devices of the second-order compensated bandgap circuit (such as BJTs and MOSFETs) at the degeneracy point and in normal operating conditions, it can accurately identify and effectively remove the bandgap reference circuit from the degeneracy state. Simultaneously, it adapts to the spurious operating point detection requirements of first-order bandgap circuits, accurately identifying the operating state of the reference circuit and effectively solving problems such as unreliable startup, high power consumption, inaccurate judgment, and poor adaptability in existing circuits.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design technology, and particularly relates to the design of integrated circuit power control chips. Background Technology

[0002] Bandgap reference circuits are the core modules of analog and mixed-signal integrated circuits. They can provide stable reference voltage or current, and are not significantly affected by power supply voltage, temperature and process parameters. They are widely used in circuits such as ADCs, DACs, LDOs and voltage comparators. Their performance directly determines the accuracy and reliability of integrated circuit systems.

[0003] The core topologies of bandgap reference circuits (such as BJT differential pairs and resistive feedback networks) possess inherent symmetry, making them prone to falling into metastable states (i.e., spurious operating points) with zero current or non-target voltage during power-up, thus failing to start normally. This problem is particularly pronounced in high-voltage applications. For second-order compensated bandgap circuits, the topological symmetry is further enhanced by the introduction of compensation structures, leading to additional degenerate states. The probability of degenerate states occurring is significantly increased under high-voltage conditions, further exacerbating the risk of startup failure. These abnormal states can directly cause the integrated circuit system to malfunction. Therefore, a startup circuit is an essential module for bandgap reference circuits. It must force the reference circuit out of abnormal states and guide it to a stable operating point during the power-up phase, automatically shutting off after the reference stabilizes to avoid introducing additional power consumption and performance interference.

[0004] The performance of the startup circuit directly determines the startup reliability and overall stability of the bandgap reference circuit. Therefore, its design must meet multiple stringent requirements: accurate abnormal state identification capability, rapid disengagement capability, while also considering low power consumption and small area. However, existing startup circuits generally cannot fully cover these requirements, especially in terms of high-voltage scenario adaptation and degenerate state handling of second-order compensated bandgap circuits, where there are significant shortcomings. Summary of the Invention

[0005] To address the aforementioned shortcomings of existing technologies, this patent proposes an optimized bandgap reference startup circuit. The proposed startup scheme, based on degeneracy state detection, utilizes the on / off characteristics of MOSFETs to achieve startup. By detecting the degeneracy state difference between the core components of the second-order compensated bandgap circuit (such as BJTs and MOSFETs) at the degeneracy point and in normal operating conditions, it can accurately identify and effectively remove the bandgap reference circuit from the degeneracy state. Simultaneously, it adapts to the spurious operating point detection requirements of first-order bandgap circuits, accurately identifying the operating state of the reference circuit and effectively solving problems such as unreliable startup, high power consumption, inaccurate judgment, and poor adaptability in existing circuits.

[0006] The present invention is achieved through the following technical solution:

[0007] A novel bandgap reference startup circuit with degenerate state detection includes a novel bandgap reference startup circuit and a bias voltage and enable signal generation circuit.

[0008] The novel bandgap reference start-up circuit includes a start-up circuit and an inverter, a degenerate current generation circuit, a bandgap core and process angle adaptive compensation circuit, and a Schmitt trigger circuit.

[0009] In the bandgap core and process angle adaptive compensation circuit:

[0010] The sources of PMOS transistors MP12, MP14, MP16, MP17, MP18, and MP19 are connected to VDD. The source of PMOS transistor MP13 is connected to the drain of MP12. The source of PMOS transistor MP15 is connected to the drain of MP14. The drain of PMOS transistor MP13 is connected to VIN-. The drain of MP15 is connected to one end of resistors R3 and R5. The other end of R3 is connected to the emitter of PNP2. The ratio of m between PNP1 and PNP2 is 1:8. The other end of resistor R5 is connected to VSS. The drain of MP16 is connected to the drain of MN6. The NMOS transistor MN8... The drain of MN6 is connected to the gate of MN7. The source of MN6, MN7, and MN8 is connected to VSS. The drain of MN7 is connected to the source of MN5. MN5 is connected to the drain of MP17. The drain of MP18 is connected to the source of MP28. The drain of MP28 is connected to the drain of MN11, the drain of MN12, and one end of resistor R1. The other end of R1 is connected to one end of R2. The other end of R2 is connected to VSS. The source of MN11 and MN12 is connected to VSS. The drain of MP19 is connected to the source of MP20. The drain of MP20 is connected to one end of R4. The other end of R4 is connected to VSS.

[0011] In the aforementioned startup circuit and inverter:

[0012] An inverter is formed by connecting PMOS transistors MP1, MP2, MP3, MP4, MP5 and NMOS transistor MN0 in series. The source of MP1 is connected to VDD, the drain of MP5 is connected to the drain of MN0, and the source of MN0 is connected to VSS.

[0013] The gates of NMOS transistors MN1 and MN2 are connected to the drains of MP5 and MN0, respectively. The sources of MN1 and MN2 are connected to VSS. The sources of PMOS transistors MP6 and MP7 are connected to VDD. The drain of MP6 is connected to the drain of MN1, and the drain of MP7 is connected to the drain of MN2. The drain of NMOS transistor MN19 is connected to the gates of MN1 and MN2, and the source of MN19 is connected to the drain of NMOS transistor MN20. The source of MN20 is connected to VSS.

[0014] In the aforementioned degenerate current generation circuit:

[0015] The source of NMOS transistor MN3 is connected to VSS, and the drain of MN3 is connected to the drain of MP8. The source of PMOS transistor MP8 is connected to VDD, the source of MP9 is connected to VDD, and the drain of MP9 is connected to the source of MP10. The drain of MP10 is connected to the source of MP11 and to the drain of MN4. The drain of MP11 is connected to VIN-, and the source of MN4 is connected to VBP0.

[0016] In the Schmitt trigger circuit described above:

[0017] NMOS transistors MP29 and MP30 are connected in series, and MN21 and MN22 are connected in series. The drain of PMOS transistor MP30 is connected to the drain of MN21, the source of MP21 is connected to the drain of MP29 and the source of MP30, and the drain of MP21 is connected to VSS. The drain of MN13 is connected to the source of MN21 and the drain of MN22, the source of MN13 is connected to VDD, the source of MP22 is connected to VDD, the drain of MP22 is connected to the drain of MN14, and the source of MN14 is connected to VSS.

[0018] The bias voltage and enable signal generation circuit is a self-biased current source structure, which provides VBP1 voltage for the new bandgap reference startup circuit, and serves as the bias voltage for the conduction transistor in the bandgap reference and the cascode amplifier.

[0019] The significant advantages and beneficial effects of this invention are as follows:

[0020] 1. A degenerate state detection and decoupling mechanism is designed for second-order and higher-order compensated bandgap circuits. Through the synergistic effect of the SENSE signal and the switching transistor, the circuit can be quickly driven out of the abnormal state, completely avoiding startup failures in high-voltage scenarios, while also being compatible with the false operating point identification requirements of first-order bandgap circuits.

[0021] 2. MN10 operates in the subthreshold region, and its output current achieves second-order temperature compensation for the bandgap reference. At the same time, under different process angles such as SS / FF, its gate voltage can be dynamically adjusted to follow the threshold voltage, avoiding the shift of the operating region caused by PVT fluctuations and ensuring the accuracy of the reference voltage.

[0022] 3. After the reference circuit stabilizes, the startup circuit is automatically shut down via MN19 and MN20, with no additional power consumption; the pre-amplifier signal can trigger dedicated switching transistors such as MP6 and MP7 to quickly shut down the entire circuit, adapting to low-power design requirements.

[0023] 4. Strong adaptability to various scenarios: It is compatible with a wide temperature range, does not require a complex voltage divider resistor network, has a simple structure and is easy to integrate on-chip, and can be widely used in various precision integrated circuits that rely on bandgap references, such as ADCs, DACs, and LDOs.

[0024] 5. Through the precise coordination of the Schmitt trigger and the switching transistor, false triggering caused by small fluctuations in the reference voltage is avoided, ensuring the stability of the subsequent circuit and minimizing the impact of power supply voltage fluctuations and process deviations. Attached Figure Description

[0025] Figure 1 A novel bandgap reference start-up circuit for degenerate state detection;

[0026] Figure 2 This is a circuit for generating bias voltage and enable signal. Detailed Implementation

[0027] A novel bandgap reference startup circuit with degenerate state detection includes a novel bandgap reference startup circuit and a bias voltage and enable signal generation circuit.

[0028] I. Circuit Connection:

[0029] The novel bandgap reference start-up circuit includes a start-up circuit and an inverter, a degenerate current generation circuit, a bandgap core and process angle adaptive compensation circuit, and a Schmitt trigger circuit.

[0030] In the bandgap core and process angle adaptive compensation circuit:

[0031] The sources of PMOS transistors MP12, MP14, MP16, MP17, MP18, and MP19 are connected to VDD. The source of PMOS transistor MP13 is connected to the drain of MP12. The source of PMOS transistor MP15 is connected to the drain of MP14. The drain of PMOS transistor MP13 is connected to VIN-. The drain of MP15 is connected to one end of resistors R3 and R5. The other end of R3 is connected to the emitter of PNP2. The ratio of m between PNP1 and PNP2 is 1:8. The other end of resistor R5 is connected to VSS. The drain of MP16 is connected to the drain of MN6. The NMOS transistor MN8... The drain of MN6 is connected to the gate of MN7. The sources of MN6, MN7, and MN8 are connected to VSS. The drain of MN7 is connected to the source of MN5. MN5 is connected to the drain of MP17. The drain of MP18 is connected to the source of MP28. The drain of MP28 is connected to the drains of MN11 and MN12, and one end of resistor R1. The other end of R1 is connected to one end of R2, and the other end of R2 is connected to VSS. The sources of MN11 and MN12 are connected to VSS. The drain of MP19 is connected to the source of MP20. The drain of MP20 is connected to one end of R4, and the other end of R4 is connected to VSS. In this circuit, INT_BG serves as the second-order compensated bandgap reference output voltage of the current-mode architecture. In this circuit, MN10 operates in the subthreshold region, and its output subthreshold current exhibits a trend opposite to the VBE curvature with temperature. As temperature changes, the nonlinearity of VBE is canceled out by the nonlinearity of the subthreshold current, achieving the effect of second-order compensation. The resistance values ​​of R1 and R2 are consistent with the trend of the threshold voltage of MN10 under different process corners. Through negative feedback, the gate voltage of MN10 follows the change of its threshold voltage under different process corners, so that MN10 always works in the subthreshold region.

[0032] In the aforementioned startup circuit and inverter:

[0033] An inverter is formed by connecting PMOS transistors MP1, MP2, MP3, MP4, MP5 and NMOS transistor MN0 in series. The source of MP1 is connected to VDD, the drain of MP5 is connected to the drain of MN0, and the source of MN0 is connected to VSS.

[0034] NMOS transistors MN1 and MN2 have their gates connected to the drains of MP5 and MN0, respectively. The sources of MN1 and MN2 are connected to VSS. PMOS transistors MP6 and MP7 have their sources connected to VDD. The drain of MP6 is connected to the drain of MN1, and the drain of MP7 is connected to the drain of MN2. NMOS transistor MN19 has its drain connected to the gates of MN1 and MN2, and its source is connected to the drain of NMOS transistor MN20. The source of MN20 is connected to VSS. MP6, MP7, MP10, MN8, MN9, MN12, and MP27 act as switches, enabling either POR_5V_IN or ENA_5V_IN by setting one of these signals to 0. Figure 1 2. Circuit 2 shuts off quickly.

[0035] In the aforementioned degenerate current generation circuit:

[0036] The source of NMOS transistor MN3 is connected to VSS. The drain of MN3 is connected to the drain of PMOS transistor MP8. The source of MP8 is connected to VDD. The source of MP9 is connected to VDD. The drain of MP9 is connected to the source of MP10. The drain of MP10 is connected to the source of MP11 and to the drain of MN4. The drain of MP11 is connected to VIN-. The source of MN4 is connected to VBP0.

[0037] In the Schmitt trigger circuit described above:

[0038] NMOS transistors MP29 and MP30 are connected in series, and MN21 and MN22 are connected in series. The drain of PMOS transistor MP30 is connected to the drain of MN21, the source of MP21 is connected to the drain of MP29 and the source of MP30, and the drain of MP21 is connected to VSS. The drain of MN13 is connected to the source of MN21 and the drain of MN22, the source of MN13 is connected to VDD, the source of MP22 is connected to VDD, the drain of MP22 is connected to the drain of MN14, and the source of MN14 is connected to VSS. By designing the width-to-length ratio of MP21 and MN13, different hysteresis voltages are generated, and the upper and lower trigger voltages are precisely designed to adapt to the INT_BG fluctuations under the PVT process corner, generating a SENSE signal. The current mirror circuit composed of MN3, MN8, MP9, MP10, MP11, and MN4 generates a current that is degenerate from the degeneracy state.

[0039] The bias voltage and enable signal generation circuit is a self-biased current source structure, providing VBP1 voltage for the novel bandgap reference startup circuit, serving as the bias voltage for the bandgap reference and the transistors in the cascode amplifier. The enable signal EN_B forces the startup circuit to start. MN0 and MP1~MP5 form an inverter structure, with MP1~MP4 operating in the linear region to reduce the current in this branch. MN1 and MN2 pull down VBP0 and VBP1 voltages, starting the bandgap core circuit. At this time, VBN0 rises. If INT_BG is at its normal operating value, MN19 and MN20 are turned on, setting the gate voltages of MN1 and MN2 to 0, thus turning off MN1 and MN2, and consequently shutting down the startup circuit.

[0040] II. Working Principle:

[0041] Figure 1In the circuit, after power-on, EN_B is set to 0, MP1~MP5 are turned on, and MP1~MP4 operate in the linear region to reduce the current in this branch. At this time, the gate voltages of MN1 and MN2 rise, and MN1 and MN2 are turned on, causing VBP0 and VBP1 voltages to drop. MP13~MP20 and MP23~MP26 are turned on, and the circuit begins to operate normally, with VBN0 rising. If INT_BG is at its normal operating value, MN19 and MN20 are turned on, setting the gate voltages of MN1 and MN2 to 0, turning off MN1 and MN2, and shutting down the startup circuit. When INT_BG is in a low degenerate state, INT_BG does not turn on MN20, so MN20 is off. At this time, MN1 and MN2 are still on. The Schmitt trigger composed of MP29~MP32, MP21, MP22, MN13, and MN14, connected to INT_BG, generates a SENSE signal. When the SENSE signal is set to 0, the other end of the OR gate is set to 1, so MN3 is on, and current is generated in this branch. Current is also generated in the MP9 branch, so MP10 is on. Because SENSE is set to 0, MP11 is on, MN4 is off, and the VIN- voltage rises. It decreases through the cascode operational amplifier VBP0, and at this time, INT_BG rises, breaking the low degenerate state. When INT_BG is in a high degenerate state, MN1 and MN2 remain off, the SENSE signal is set to 1, and the other end of the OR gate is also set to 1, thus MN3 conducts, generating current in this branch. The MP9 branch also generates current, causing MP10 to conduct. Because SENSE is set to 1, MP11 is off, MN4 conducts, VBP0 voltage rises, and INT_BG falls, breaking the high degenerate state. Both utilize the SENSE signal to generate a negative feedback detection mechanism for INT_BG. MN10 operates in subthreshold mode, and its output subthreshold current exhibits a trend opposite to the VBE curvature with temperature. As temperature increases, the nonlinear decay of VBE is offset by the nonlinear increase of the subthreshold current, achieving a second-order compensation effect: VBG = (VBE / R5 + VT * lnN / R3 + Isub) * R4. At this time, the value of INT_BG will change under different process corners, and the threshold voltage of MN10 will also change. Under the SS process corner, the threshold voltages of MN10 and MN5 will increase, the values ​​of R1 and R2 will increase, the gate voltage of MP28 will decrease, and the drain voltage of MP28 will increase. Therefore, the gate voltage of MN10 will increase, following the change in the threshold voltage of MN10. The principle is similar under the FF process corner, to avoid MN10 entering other operating regions due to the change in the threshold voltage under the PVT process corner. When one of the signals POR_5V_IN and ENA_5V_IN is set to 0, MP6, MP7, MP10, MN8, MN9, MN12, and MP27 act as switching transistors. Figure 1 The circuit shuts down rapidly. When a higher-order compensation is used in the circuit, a degenerate state point will be added, and this startup circuit can still be used.

[0042] Figure 2 The structure is a self-biased current source that provides bias voltage for the bandgap reference and the cascode amplifier. By changing the width-to-length ratio of MN17 and MN18, a voltage drop is generated in resistor R12, thus producing current. The resulting current is (VGS). MN18 -VGS MN17 ) / R12.

Claims

1. A novel bandgap reference start-up circuit with degenerate state detection, characterized in that, This includes a novel bandgap reference startup circuit and a bias voltage and enable signal generation circuit; The novel bandgap reference start-up circuit includes a start-up circuit and an inverter, a degenerate current generation circuit, a bandgap core and process angle adaptive compensation circuit, and a Schmitt trigger circuit. In the bandgap core and process angle adaptive compensation circuit: The sources of PMOS transistors MP12, MP14, MP16, MP17, MP18, and MP19 are connected to VDD. The source of PMOS transistor MP13 is connected to the drain of MP12. The source of PMOS transistor MP15 is connected to the drain of MP14. The drain of PMOS transistor MP13 is connected to VIN-. The drain of MP15 is connected to one end of resistors R3 and R5. The other end of R3 is connected to the emitter of PNP2. The ratio of m between PNP1 and PNP2 is 1:

8. The other end of resistor R5 is connected to VSS. The drain of MP16 is connected to the drain of MN6. The NMOS transistor MN8... The drain of MN6 is connected to the gate of MN7. The source of MN6, MN7, and MN8 is connected to VSS. The drain of MN7 is connected to the source of MN5. MN5 is connected to the drain of MP17. The drain of MP18 is connected to the source of MP28. The drain of MP28 is connected to the drain of MN11, the drain of MN12, and one end of resistor R1. The other end of R1 is connected to one end of R2. The other end of R2 is connected to VSS. The source of MN11 and MN12 is connected to VSS. The drain of MP19 is connected to the source of MP20. The drain of MP20 is connected to one end of R4. The other end of R4 is connected to VSS.

2. The novel bandgap reference start-up circuit with degenerate state detection according to claim 1, characterized in that, In the aforementioned startup circuit and inverter: An inverter is formed by connecting PMOS transistors MP1, MP2, MP3, MP4, MP5 and NMOS transistor MN0 in series. The source of MP1 is connected to VDD, the drain of MP5 is connected to the drain of MN0, and the source of MN0 is connected to VSS. The gates of NMOS transistors MN1 and MN2 are connected to the drains of MP5 and MN0, respectively. The sources of MN1 and MN2 are connected to VSS. The sources of PMOS transistors MP6 and MP7 are connected to VDD. The drain of MP6 is connected to the drain of MN1, and the drain of MP7 is connected to the drain of MN2. The drain of NMOS transistor MN19 is connected to the gates of MN1 and MN2, and the source of MN19 is connected to the drain of NMOS transistor MN20. The source of MN20 is connected to VSS.

3. The novel bandgap reference start-up circuit with degenerate state detection according to claim 1, characterized in that, In the aforementioned degenerate current generation circuit: The source of NMOS transistor MN3 is connected to VSS. The drain of MN3 is connected to the drain of PMOS transistor MP8. The source of MP8 is connected to VDD. The source of MP9 is connected to VDD. The drain of MP9 is connected to the source of MP10. The drain of MP10 is connected to the source of MP11 and to the drain of MN4. The drain of MP11 is connected to VIN-. The source of MN4 is connected to VBP0.

4. A novel bandgap reference start-up circuit with degenerate state detection according to claim 1, characterized in that, In the Schmitt trigger circuit described above: NMOS transistors MP29 and MP30 are connected in series, and MN21 and MN22 are connected in series. The drain of PMOS transistor MP30 is connected to the drain of MN21, the source of MP21 is connected to the drain of MP29 and the source of MP30, and the drain of MP21 is connected to VSS. The drain of MN13 is connected to the source of MN21 and the drain of MN22, the source of MN13 is connected to VDD, the source of MP22 is connected to VDD, the drain of MP22 is connected to the drain of MN14, and the source of MN14 is connected to VSS.

5. A novel bandgap reference start-up circuit with degenerate state detection according to claim 1, characterized in that, The bias voltage and enable signal generation circuit is a self-biased current source structure, which provides VBP1 voltage for the new bandgap reference startup circuit, and serves as the bias voltage for the conduction transistor in the bandgap reference and the cascode amplifier.

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