A method for suppressing noise introduction in a mirror current source circuit and a mirror current source circuit

Abstract

This invention provides a method for suppressing noise introduction in a current mirror circuit, comprising: sampling the gate voltage of the voltage-to-current conversion module in the current mirror on a first capacitor between the gate and the power supply to avoid introducing noise from the reference current source and the current-to-voltage conversion module; when external noise affects the output current of the current mirror, compensating for the charge of the parasitic capacitance between the gate and ground to suppress voltage changes in the first capacitor between the gate and the power supply, thereby reducing the impact of noise on the output current. This invention allows the gate-source voltage of the current source to remain constant when the power supply voltage or the voltage to ground changes, thus keeping the current source current constant. In other words, this auxiliary structure can greatly enhance the current source's immunity to power supply or ground interference and significantly reduce power supply noise and ground noise.

Description

Technical Field

[0001] This invention relates to the field of electronic circuits, and in particular to a method for suppressing noise introduction in a mirror current source circuit and a mirror current source circuit. Background Technology

[0002] A current mirror is a common biasing circuit that provides current bias to other subsystems by mirroring the input current to the output branch. The process of replicating the input current to the output branch is typically accomplished using devices that map current to control voltage; that is, current-to-voltage conversion units and voltage-to-current conversion units are used to replicate the current from the reference current source to the output branch. For example... Figure 1 As shown, the reference current source converts the current signal into a voltage signal through transistor A and sends it to the gate of transistor B. At transistor B, the voltage signal is converted back into a current signal and output from port P1.

[0003] However, in this circuit structure, noise interference is inevitable between the current source and the mirror transistor. To avoid this problem, such as... Figure 2 As shown, existing technologies include sampling the gate voltage VG1 of the output branch and maintaining it on capacitor C1. In this case, VG1 follows changes in the power supply voltage, ensuring the gate-source voltage of the current source remains constant, thus ensuring the output current of the current source remains constant. However, in actual circuits, parasitic capacitances between metal lines or vias, and parasitic capacitances C1 between the VG1 port and ground, exist. p Such issues are difficult to avoid. Therefore, after sampling, if the power supply voltage or ground potential changes, the gate-source voltage of the current source will undergo an undesirable change, causing the current source output current to change and generating additional power supply-ground noise.

[0004] Generally, the gate-source voltage change ΔV of the current source gs1 for

[0005] The larger ΔVgs1 is, the greater the current change in the current source. To reduce this voltage change, a common practice is to increase the capacitance of C1. For example, if the parasitic capacitance C... p The capacitor is 1pF. To ensure a -40dB power supply rejection effect for the current source, C1 needs to be increased to over 100pF, but this would consume a significant amount of chip area. If even higher power supply rejection requirements are needed, increasing the value of C1 becomes impractical. Therefore, the parasitic capacitance C... p The presence of [something] will greatly affect power supply noise, leading to a decrease in circuit performance noise. Summary of the Invention

[0006] The purpose of this invention is to provide a method for suppressing noise introduction in a mirror current source circuit, comprising: The gate voltage of the voltage-to-current conversion module in the mirror current source is sampled on the first capacitor between the gate and the power supply to avoid introducing noise from the reference current source and the current-to-voltage conversion module. When external noise affects the output current of the mirror current source, the charge of the parasitic capacitance between the gate and ground is compensated to suppress the voltage change of the first capacitor between the gate and the power supply, thereby reducing the impact of noise on the output current.

[0007] Preferably, the compensation for the charge of the parasitic capacitance between the gate and ground includes: A programmable gain amplifier is provided between the power supply voltage and the gate of the voltage-to-current conversion module, and the output voltage of the programmable gain amplifier is coupled to the gate voltage of the output branch through a second capacitor. By adjusting the gain of the programmable gain amplifier and the coupling coefficient of the second capacitor, the parasitic capacitance between the gate and ground is compensated.

[0008] Preferably, compensating for the parasitic capacitance between the gate and ground includes: The capacitance value of the second capacitor is set according to the transfer function of the programmable gain amplifier and the capacitance value of the parasitic capacitor, so that when the power supply voltage and / or the potential of the ground point change, the charge change of the second capacitor is compensated to the parasitic capacitance between the gate and ground.

[0009] Preferably, the capacitance value C2 of the second capacitor is: C2 = C p / (K-1) Where K is the transfer function, C p The capacitance value is the parasitic capacitance between the gate and ground.

[0010] Preferably, the programmable gain amplifier includes a first transistor, a second transistor, a third capacitor, and a fourth capacitor, wherein: One end plate of the third capacitor is electrically connected to the gate of the first transistor, and the other end plate is electrically connected to the first capacitor. One end plate of the fourth capacitor is electrically connected to the gate of the first transistor, and the other end plate is electrically connected to the ground point. The transfer function K is: K = 1 + C3 / C4 Wherein, C3 is the capacitance value of the third capacitor, and C4 is the capacitance value of the fourth capacitor.

[0011] Preferably, the capacitance values ​​of the third capacitor and the fourth capacitor are not less than 1pF.

[0012] Preferably, the capacitance value of the third capacitor is equal to the capacitance value of the fourth capacitor, and the capacitance value of the second capacitor is equal to the capacitance value of the parasitic capacitance between the gate and ground.

[0013] Preferably, sampling the gate voltage of the voltage-to-current conversion module in the mirror current source onto the first capacitor between the gate and the power supply includes: A switch is provided between the current-to-voltage conversion module and the voltage-to-current conversion module in the mirror current source. During the sampling process, the switch is closed so that the output voltage of the current-to-voltage conversion module is connected to the gate of the voltage-to-current conversion module and sampled onto the first capacitor between the gate and the power supply. After the sampling is completed, the switch is opened to avoid introducing noise from the reference current source and the current-to-voltage conversion module.

[0014] The present invention also provides a mirror current source circuit, including: a reference current source, a current-to-voltage conversion module, and a voltage-to-current conversion module, and further including: The sampling module includes at least a first capacitor between the gate and the power supply, used to sample the gate voltage of the voltage-to-current conversion module in the mirror current source onto the first capacitor, so as to avoid introducing noise from the reference current source and the current-to-voltage conversion module; The charge compensation module is used to compensate the charge of the parasitic capacitance between the gate and ground when external noise affects the output current of the mirror current source, so as to suppress the voltage change of the first capacitor between the gate and the power supply and reduce the impact of noise on the output current.

[0015] Preferably, the charge compensation module includes: A programmable gain amplifier, wherein the input terminal of the programmable gain amplifier is connected to a power supply voltage; The second capacitor has one end plate connected to the output terminal of the programmable gain amplifier and the other end plate connected to the gate of the voltage-to-current conversion module.

[0016] Preferably, the capacitance value of the second capacitor is set according to the transfer function of the programmable gain amplifier and the capacitance value of the parasitic capacitor, so that when the power supply voltage and / or the potential of the ground point change, the charge change of the second capacitor is compensated to the parasitic capacitance between the gate and ground.

[0017] Preferably, the capacitance value C2 of the second capacitor is: C2 = C p / (K-1) Where K is the transfer function, C p The capacitance value of the parasitic capacitance.

[0018] Preferably, the programmable gain amplifier includes a first transistor, a second transistor, a third capacitor, and a fourth capacitor, wherein: One end plate of the third capacitor is electrically connected to the gate of the first transistor, and the other end plate is electrically connected to the first capacitor. One end plate of the fourth capacitor is electrically connected to the gate of the first transistor, and the other end plate is electrically connected to the ground point. The transfer function K is: K = 1 + C3 / C4 Wherein, C3 is the capacitance value of the third capacitor, and C4 is the capacitance value of the fourth capacitor.

[0019] Preferably, the capacitance values ​​of the third capacitor and the fourth capacitor are not less than 1pF.

[0020] Preferably, the capacitance value of the third capacitor is equal to the capacitance value of the fourth capacitor, and the capacitance value of the first capacitor is equal to the capacitance value of the parasitic capacitor.

[0021] Preferably, the sampling module further includes: A switch is disposed between the current-to-voltage conversion module and the voltage-to-current conversion module. The switch is closed during the sampling process so that the output voltage of the current-to-voltage conversion module is connected to the gate of the voltage-to-current conversion module and sampled onto the first capacitor. After the sampling is completed, the switch is opened to avoid introducing noise from the reference current source and the current-to-voltage conversion module.

[0022] The present invention also provides a ramp generator that uses a circuit of a mirror current source as described above to generate a ramp signal.

[0023] The present invention also provides an image sensor employing the aforementioned ramp generator, wherein the ramp generator is used to convert the analog signals output by the pixel units of the image sensor into digital signals.

[0024] The present invention proposes a new noise suppression scheme for a mirror current source circuit through the above-described solution. When the power supply voltage or the voltage to ground changes, the gate-source voltage of the current source can remain unchanged, thereby keeping the current source current constant. That is, this auxiliary structure can greatly enhance the current source's anti-interference capability against the power supply or to ground, and can greatly reduce the power supply noise and ground noise of the current source. Attached Figure Description

[0025] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings.

[0026] Figure 1 , Figure 2This is a schematic diagram of a current mirror source circuit in the prior art; Figure 3 , Figure 4 This is a schematic diagram of a mirror current source noise suppression circuit in different embodiments of the present invention.

[0027] Throughout the figures, the same or similar reference numerals denote the same or similar devices (modules) or steps. Detailed Implementation

[0028] The purpose of this invention is to provide a method for suppressing noise introduction in a current mirror circuit. First, the gate voltage of the voltage-to-current conversion module in the current mirror is sampled onto a first capacitor C1 between the gate and the power supply to avoid introducing noise from the reference current source and the current-to-voltage conversion module. When external noise affects the output current of the current mirror, the parasitic capacitance C1 between the gate and ground is... p The charge is compensated to suppress voltage changes in the first capacitor C1 between the gate and the power supply, thereby reducing the impact of noise on the output current.

[0029] This invention, based on the existing scheme of sampling the gate voltage of the voltage-to-current conversion module in the mirror current source at the first capacitor C1 between the gate and the power supply, addresses the parasitic capacitance C. p The charge can be compensated, for example, by setting a feedforward circuit to suppress the voltage change of the first capacitor C1 between the gate and the power supply.

[0030] In an alternative implementation, the parasitic capacitance C can be controlled by setting a programmable gain amplifier (PGA). p To compensate for the charge, specifically, a programmable gain amplifier (PGA) is placed between the power supply voltage Vdd and the gate of the voltage-to-current conversion module, and the output voltage Vdd of the programmable gain amplifier (PGA) is set to... o The second capacitor C2 is coupled to the gate voltage VG1 of the output branch, such as... Figure 3 As shown, by adjusting the gain of the programmable gain amplifier (PGA) and the coupling coefficient of the second capacitor C2, the parasitic capacitance C between the gate and ground can be controlled. p Compensation will be provided.

[0031] Preferably, in this embodiment, the transfer function of the programmable gain amplifier (PGA) and the parasitic capacitance C can be used as the basis. p The capacitance value of the second capacitor C2 is set such that when the power supply voltage Vdd and / or the potential of the ground point GND change, the charge change of the second capacitor C2 is compensated for the parasitic capacitance C between the gate and ground.p .

[0032] For example, the capacitance value C2 of the second capacitor is set as: C2 = C p / (K-1) Where K is the transfer function of the programmable gain amplifier (PGA), and C p The capacitance value is the parasitic capacitance between the gate and ground.

[0033] In this implementation, if the power supply voltage Vdd increases by ΔV as shown in the figure, VG1 also needs to increase by ΔV to keep the current of the current source constant. Therefore, the parasitic capacitance C... p The required positive charge value should be C. p ×ΔV, and at this time, due to the effect of PGA, the voltage V on the lower plate of the second capacitor C2 is... o For the same increase of K×ΔV, the positive charge output of C2, C2×(K-1)×ΔV, is exactly equal to Cp×ΔV. Therefore, charge exchange only occurs between C2 and C. p During this period, no charge change occurs on C1. Therefore, VG1 changes in tandem with Vdd, increasing by ΔV. Consequently, the gate-source voltage Vgs of the current source remains unchanged, and the current of the current source also remains constant. It can be seen that the current source's anti-interference capability is effectively improved when Vdd changes, thus suppressing power supply noise.

[0034] Similarly, if the voltage to ground GND changes by ΔV, VG1 needs to remain constant in order to keep the current source current constant, then C p Requires output of positive charge C p At this point, due to the effect of the programmable gain amplifier, the voltage Vo of the lower plate of C2 decreases by (K-1)×ΔV, while the voltage VG1 of the upper plate remains unchanged. The positive charge C2×(K-1)×ΔV required for C2 is exactly equal to the parasitic capacitance Cp×ΔV. Therefore, charge exchange only occurs between C2 and C. p During this period, there is no change in charge on C1, so the gate-source voltage Vgs of the current source remains unchanged. It can be seen that when the voltage to ground (GND) changes, the current source current does not change, thus enhancing the current source's immunity to ground interference and reducing its noise to ground.

[0035] Preferably, as shown in the figure, the programmable gain amplifier (PGA) includes a first transistor MP1, a second transistor MP2, a third capacitor C3, and a fourth capacitor C4, wherein: One end of the third capacitor C3 is electrically connected to the gate of the first transistor MP1, and the other end is electrically connected to the first capacitor C1. One end of the fourth capacitor C4 is electrically connected to the gate of the first transistor MP1, and the other end is electrically connected to the ground point (GND). In this embodiment, the transfer function K is: K = 1 + C3 / C4 Wherein, C3 is the capacitance value of the third capacitor, and C4 is the capacitance value of the fourth capacitor.

[0036] Preferably, the capacitance values ​​of the third capacitor C3 and the fourth capacitor C4 are both not less than 1pF.

[0037] In a preferred embodiment, the capacitance value of the third capacitor C3 is equal to the capacitance value of the fourth capacitor C4, and the capacitance value of the second capacitor C2 is equal to the parasitic capacitance C between the gate and ground. p The capacitance values ​​are equal.

[0038] Preferably, sampling the gate voltage of the voltage-to-current conversion module in the mirror current source onto the first capacitor C1 between the gate and the power supply includes: A switch sw1 is installed between the current-to-voltage conversion module and the voltage-to-current conversion module in the mirror current source, as follows: Figure 4 As shown, during the sampling process, the switch sw1 is closed, so that the output voltage of the current-to-voltage conversion module is connected to the gate of the voltage-to-current conversion module and sampled onto the first capacitor C1 between the gate and the power supply. After the sampling is completed, the switch sw1 is opened to avoid introducing noise from the reference current source and the current-to-voltage conversion module.

[0039] The present invention also provides a mirror current source circuit, including: a reference current source, a current-to-voltage conversion module, and a voltage-to-current conversion module, and further including: The sampling module includes at least a first capacitor C1 between the gate and the power supply, used to sample the gate voltage of the voltage-to-current conversion module in the mirror current source onto the first capacitor C1, so as to avoid introducing noise from the reference current source and the current-to-voltage conversion module. The charge compensation module is used to compensate for the parasitic capacitance C between the gate and ground when external noise affects the output current of the mirror current source. p The charge is compensated to suppress voltage changes in the first capacitor C1 between the gate and the power supply, thereby reducing the impact of noise on the output current.

[0040] Preferably, the charge compensation module includes: A programmable gain amplifier (PGA) with its input terminal connected to a power supply voltage; The second capacitor C2 has one end plate connected to the output terminal of the programmable gain amplifier PGA, and the other end plate connected to the gate of the voltage-to-current conversion module.

[0041] Preferably, the capacitance value of the second capacitor C2 is determined based on the transfer function of the programmable gain amplifier PGA and the parasitic capacitance C. p The capacitance value is set such that when the power supply voltage and / or the potential of the ground point change, the charge change of the second capacitor C2 is compensated for the parasitic capacitance C between the gate and ground. p .

[0042] Preferably, the capacitance value C2 of the second capacitor is: C2 = C p / (K-1) Where K is the transfer function, C p The capacitance value of the parasitic capacitance.

[0043] Preferably, such as Figure 3 As shown, the programmable gain amplifier (PGA) includes a first transistor MP1, a second transistor MP2, a third capacitor C3, and a fourth capacitor C4, wherein: One end plate of the third capacitor is electrically connected to the gate of the first transistor, and the other end plate is electrically connected to the first capacitor C1. One end plate of the fourth capacitor is electrically connected to the gate of the first transistor, and the other end plate is electrically connected to the ground point. The transfer function K is: K = 1 + C3 / C4 Wherein, C3 is the capacitance value of the third capacitor, and C4 is the capacitance value of the fourth capacitor.

[0044] Preferably, the capacitance values ​​of the third capacitor C3 and the fourth capacitor C4 are not less than 1pF.

[0045] Preferably, the capacitance value of the third capacitor C3 is equal to the capacitance value of the fourth capacitor C4, and the capacitance value of the first capacitor C1 is equal to the capacitance value of the parasitic capacitor C. p The capacitance values ​​are equal.

[0046] Preferably, the sampling module further includes: Switch sw1, such as Figure 4 As shown, a switch is positioned between the current-to-voltage conversion module and the voltage-to-current conversion module. It is used to close the switch during the sampling process, so that the output voltage of the current-to-voltage conversion module is connected to the gate of the voltage-to-current conversion module and sampled onto the first capacitor C1. After the sampling is completed, the switch sw1 is opened to avoid introducing noise from the reference current source and the current-to-voltage conversion module.

[0047] The present invention also provides a ramp generator that uses a circuit of a mirror current source as described above to generate a ramp signal.

[0048] The present invention also provides an image sensor employing the aforementioned ramp generator, wherein the ramp generator is used to convert the analog signals output by the pixel units of the image sensor into digital signals.

[0049] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered exemplary and not restrictive in any way. Furthermore, it is clear that the word "comprising" does not exclude other elements and steps, and the word "a" does not exclude a plural. Multiple elements recited in the apparatus claims may also be implemented by a single element. The terms "first," "second," etc., are used to denote names and do not indicate any particular order.

Claims

1. A method for suppressing noise introduction in a mirror current source circuit, characterized in that, include: The gate voltage of the voltage-to-current conversion module in the mirror current source is sampled on the first capacitor between the gate and the power supply to avoid introducing noise from the reference current source and the current-to-voltage conversion module. When external noise affects the output current of the mirror current source, the charge of the parasitic capacitance between the gate and ground is compensated to suppress the voltage change of the first capacitor between the gate and the power supply, thereby reducing the impact of noise on the output current.

2. The method for suppressing noise introduction in a mirror current source circuit as described in claim 1, characterized in that, The compensation for the charge of the parasitic capacitance between the gate and ground includes: A programmable gain amplifier is provided between the power supply voltage and the gate of the voltage-to-current conversion module, and the output voltage of the programmable gain amplifier is coupled to the gate voltage of the output branch through a second capacitor. By adjusting the gain of the programmable gain amplifier and the coupling coefficient of the second capacitor, the parasitic capacitance between the gate and ground is compensated.

3. The method for suppressing noise introduction in a mirror current source circuit as described in claim 2, characterized in that, The compensation for the parasitic capacitance between the gate and ground includes: The capacitance value of the second capacitor is set according to the transfer function of the programmable gain amplifier and the capacitance value of the parasitic capacitor, so that when the power supply voltage and / or the potential of the ground point change, the charge change of the second capacitor is compensated to the parasitic capacitance between the gate and ground.

4. The method for suppressing noise introduction in a mirror current source circuit as described in claim 3, characterized in that, The capacitance value C2 of the second capacitor is: C2 = C p / (K-1) Where K is the transfer function, C p The capacitance value is the parasitic capacitance between the gate and ground.

5. The method for suppressing noise introduction in a mirror current source circuit as described in claim 3, characterized in that, The programmable gain amplifier includes a first transistor, a second transistor, a third capacitor, and a fourth capacitor, wherein: One end plate of the third capacitor is electrically connected to the gate of the first transistor, and the other end plate is electrically connected to the first capacitor. One end plate of the fourth capacitor is electrically connected to the gate of the first transistor, and the other end plate is electrically connected to the ground point. The transfer function K is: K = 1 + C3 / C4 Wherein, C3 is the capacitance value of the third capacitor, and C4 is the capacitance value of the fourth capacitor.

6. The method for suppressing noise introduction in a mirror current source circuit as described in claim 5, characterized in that, The capacitance values ​​of the third capacitor and the fourth capacitor are not less than 1pF.

7. The method for suppressing noise introduction in a mirror current source circuit as described in claim 5, characterized in that, The capacitance value of the third capacitor is equal to the capacitance value of the fourth capacitor, and the capacitance value of the second capacitor is equal to the capacitance value of the parasitic capacitance between the gate and ground.

8. The method for suppressing noise introduction in a mirror current source circuit as described in claim 1, characterized in that, The step of sampling the gate voltage of the voltage-to-current conversion module in the mirror current source onto the first capacitor between the gate and the power supply includes: A switch is provided between the current-to-voltage conversion module and the voltage-to-current conversion module in the mirror current source. During the sampling process, the switch is closed so that the output voltage of the current-to-voltage conversion module is connected to the gate of the voltage-to-current conversion module and sampled onto the first capacitor between the gate and the power supply. After the sampling is completed, the switch is opened to avoid introducing noise from the reference current source and the current-to-voltage conversion module.

9. A current mirror circuit, comprising: The reference current source, current-to-voltage conversion module, and voltage-to-current conversion module are characterized by further comprising: The sampling module includes at least a first capacitor between the gate and the power supply, used to sample the gate voltage of the voltage-to-current conversion module in the mirror current source onto the first capacitor, so as to avoid introducing noise from the reference current source and the current-to-voltage conversion module; The charge compensation module is used to compensate the charge of the parasitic capacitance between the gate and ground when external noise affects the output current of the mirror current source, so as to suppress the voltage change of the first capacitor between the gate and the power supply and reduce the impact of noise on the output current.

10. The mirror current source circuit as described in claim 9, characterized in that, The charge compensation module includes: A programmable gain amplifier, wherein the input terminal of the programmable gain amplifier is connected to a power supply voltage; The second capacitor has one end plate connected to the output terminal of the programmable gain amplifier and the other end plate connected to the gate of the voltage-to-current conversion module.

11. The mirror current source circuit as described in claim 10, characterized in that, The capacitance value of the second capacitor is set according to the transfer function of the programmable gain amplifier and the capacitance value of the parasitic capacitor, so that when the power supply voltage and / or the potential of the ground point change, the charge change of the second capacitor is compensated to the parasitic capacitance between the gate and ground.

12. The mirror current source circuit as described in claim 11, characterized in that, The capacitance value C2 of the second capacitor is: C2 = C p / (K-1) Where K is the transfer function, C p The capacitance value of the parasitic capacitance.

13. The mirror current source circuit as described in claim 11, characterized in that, The programmable gain amplifier includes a first transistor, a second transistor, a third capacitor, and a fourth capacitor, wherein: One end plate of the third capacitor is electrically connected to the gate of the first transistor, and the other end plate is electrically connected to the first capacitor. One end plate of the fourth capacitor is electrically connected to the gate of the first transistor, and the other end plate is electrically connected to the ground point. The transfer function K is: K = 1 + C3 / C4 Wherein, C3 is the capacitance value of the third capacitor, and C4 is the capacitance value of the fourth capacitor.

14. The mirror current source circuit as described in claim 13, characterized in that, The capacitance values ​​of the third capacitor and the fourth capacitor are not less than 1pF.

15. The mirror current source circuit as described in claim 13, characterized in that, The capacitance value of the third capacitor is equal to the capacitance value of the fourth capacitor, and the capacitance value of the first capacitor is equal to the capacitance value of the parasitic capacitor.

16. The mirror current source circuit as described in claim 9, characterized in that, The sampling module further includes: A switch is disposed between the current-to-voltage conversion module and the voltage-to-current conversion module. The switch is closed during the sampling process so that the output voltage of the current-to-voltage conversion module is connected to the gate of the voltage-to-current conversion module and sampled onto the first capacitor. After the sampling is completed, the switch is opened to avoid introducing noise from the reference current source and the current-to-voltage conversion module.

17. A ramp generator, characterized in that, A ramp signal is generated using the mirror current source circuit described in claims 9-16.

18. An image sensor, characterized in that, The ramp generator as described in claim 17 is used to convert the analog signal output by the image sensor pixel unit into a digital signal.

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