Clock peak-shaving control device, control method and chip
By introducing selection and delay modules into the chip design to control the timing of the register group, clock peak shifting is achieved, solving the problem of high peak power consumption during DFT and improving power consumption and stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- KTMICRO ELECTRONICS
- Filing Date
- 2026-03-04
- Publication Date
- 2026-06-09
Smart Images
Figure CN122172932A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of testing technology, and more specifically, to a clock stagger control device, control method, and chip. Background Technology
[0002] As chips continue to evolve, the power consumption requirements are becoming increasingly stringent. Therefore, Design for Testability (DFT) testing is necessary during the chip design phase. DFT is a technique that considers testing needs in advance during the chip design stage. Its core purpose is to improve chip testability by embedding special test logic and structures into the design, effectively detecting potential defects during manufacturing and reducing testing costs. DFT consists of two processes: shift and capture. The shift process involves serially shifting test data into the scan chain through the scan input. The capture process follows immediately after the shift process, where the chip operates on its normal function clock pulses, and the combinational logic's response is captured in the scan register. The peak clock power consumption during the DFT process is a significant power consumption issue in chip design. Because the scan chain operations during the shift process cause frequent clock signal switching, the instantaneous peak clock power consumption increases significantly, resulting in higher dynamic power consumption than in normal operating mode. Summary of the Invention
[0003] The purpose of some embodiments of this application is to provide a clock peak shaving control device, control method, and chip. According to the technical solution of the embodiments of this application, the device includes a first selection module, a first delay module, a second selection module, and a first latch module. The first delay module is connected to the first selection module, and the first selection module is connected to a first register group through the second selection module. The first latch module is connected to two different register groups, including a first register group and a second register group, each register group including at least one or more registers. The first delay module is used to generate a target delayed clock signal. The first selection module is used to select between a test clock signal and the target delayed clock signal. The second selection module... The chip is used to switch between different operating modes to obtain a driving clock signal; the latch module is used to control the timing of register signals in different groups. The driving clock signal is used to provide a clock signal for each register in each register group. In this embodiment, by adding a first selection module, a second selection module, a first delay module, and a first latch module, the test clock signal is delayed. Then, based on the generated target delayed clock signal and the first latch module, the timing of register signals in different groups is controlled. The driving clock signal is used to provide a clock signal for each register in each register group, so that the registers in each group do not flip at the same time. The flip time of the registers is controlled reasonably to effectively reduce the peak power consumption of the shift process.
[0004] In a first aspect, some embodiments of this application provide a clock stagger control device, including: a first selection module, a first delay module, a second selection module, and a first latch module, wherein the first delay module is connected to the first selection module, the first selection module is connected to a first register group through the second selection module, and the first latch module is connected to two different register groups respectively, the different register groups including a first register group and a second register group, and the register group includes at least one or more registers; The first delay module is used to generate the target delay clock signal; The first selection module is used to select between the test clock signal and the target delay clock signal; The second selection module is used to switch between different operating modes of the chip to obtain the drive clock signal; The latch module is used to control the timing of register signals in different groups, and the drive clock signal is used to provide a clock signal for each register in each register group.
[0005] Some embodiments of this application delay the test clock signal by adding a first selection module, a second selection module, a delay module, and a latch module. Then, based on the generated target delayed clock signal and the latch module, the latch module is used to control the timing of register signals in different groups. The driving clock signal is used to provide a clock signal for each register in each register group, so that the registers in each group do not flip at the same time. This reasonably staggers the peak control of the register flip time and effectively reduces the peak power consumption of the shift process.
[0006] Optionally, the input terminal of the delay module receives a test clock signal, the output terminal of the delay module is connected to the input terminal of the first selection module, the output terminal of the first selection module is connected to the input terminal of the second selection module, and the first selection module is also connected to a first enable terminal, which is used to switch the clock signals of different stages of the DFT.
[0007] Some embodiments of this application provide two signals: a test clock signal of the original phase and a target delay clock signal generated by a delay module. The two clock signals are selected by a first selection module, which is controlled by an enable signal to switch the clock signal used in different test stages.
[0008] Optionally, the input of the second selection module is also connected to a function clock signal, and the output of the second selection module is connected to the clock terminal of the first register group.
[0009] Optionally, the second selection module further includes a second enable terminal, which is used to switch the clock signal in different modes.
[0010] In some embodiments of this application, the clock signal output by the first selection module is then selected by the respective functional clock func_clk through the second selection module. The selection signal of the second selection module is controlled by the enable terminal, thereby selecting different clock sources in functional mode and scan test mode, and finally forming the clock signal driving each group of DFF (registers).
[0011] Optionally, the relative delay between the test clock signal and the target delay clock signal is less than or equal to half a clock cycle.
[0012] Some embodiments of this application adjust the delay signal of the delay module to adjust the relative delay value of each clock signal to the optimal value that meets the expected peak power consumption index, so that the register flipping is fully spread out on the time axis, thereby significantly reducing the instantaneous peak power consumption of the shift phase.
[0013] Optionally, the output of the second selection module is also connected to the clock terminal of the first latch module via an inverter, and the output of the first latch module is connected to the SI pin of the register in the second register group.
[0014] Some embodiments of this application use opposite-edge triggered latches (LATs) inserted between cross-group scan chains to prevent timing issues during data transfer between different register groups during the shift process.
[0015] Secondly, some embodiments of this application provide a clock stagger control method, applied to any of the clock stagger control devices described in the first aspect, the method comprising: Obtain the target delay clock signal; When the first enable signal is a first preset value and the second enable signal is a second preset value, a drive clock signal for the register is generated based on the test clock signal and the target delay clock signal. The drive clock signal is used to provide a clock signal for each register in the register group so that the peak power consumption of each register group meets the optimal solution.
[0016] Optionally, the method further includes: The target delay clock signal is obtained by adjusting the delay clock signal of the delay module.
[0017] Optionally, the method further includes: When the second enable signal is the second preset value, the control chip is in test mode.
[0018] Optionally, the method further includes: When the second enable signal is a third preset value, the control chip is in a functional mode, which is used to control the chip to perform a preset function.
[0019] Thirdly, some embodiments of this application provide a chip including one or more sets of clock misalignment control devices as described in any of the first aspects.
[0020] Optionally, the chip includes two sets of clock shaving control devices as described in any of the first aspects, including: a first control device and a second control device, wherein the first control device includes a first delay module, a first selection module, a second selection module and a first latch module; the second control device includes a second delay module, a third selection module, a fourth selection module and a second latch module; The first selection module is connected to the first register group through the second selection module; the output of the first register group is connected to the input of the first latch module, and the output of the second selection module is connected to the clock terminal of the first latch module through an inverter. The third selection module is connected to the clock terminal of the second register group through the fourth selection module, and the output terminal of the first latch module is connected to the SI terminal of the register in the second register group. Attached Figure Description
[0021] To more clearly illustrate the technical solutions of some embodiments of this application, the accompanying drawings used in some embodiments of this application will be briefly described below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0022] Figure 1 A structural block diagram of a clock stagger control device provided in an embodiment of this application; Figure 2 This is a structural block diagram of another clock stagger control device provided in an embodiment of this application. Detailed Implementation
[0023] The technical solutions of some embodiments of this application will now be described with reference to the accompanying drawings.
[0024] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0025] As chips continue to evolve, the power consumption requirements are becoming increasingly stringent. Therefore, Design for Testability (DFT) testing is necessary during the chip design phase. DFT is a technique that considers testing needs in advance during the chip design stage. Its core purpose is to improve chip testability by embedding special test logic and structures into the design, effectively detecting potential defects during manufacturing and reducing testing costs. DFT consists of two processes: shift and capture. The shift process involves serially shifting test data into the scan chain through the scan input. The capture process follows immediately after the shift process, where the chip operates on its normal function clock pulses, and the combinational logic's response is captured in the scan register. The peak clock power consumption during the DFT process is a significant power consumption issue in chip design. Because the scan chain operations during the shift process cause frequent clock signal switching, the instantaneous peak clock power consumption increases significantly, resulting in higher dynamic power consumption than in normal operating mode.
[0026] In view of this, some embodiments of this application provide a clock peak shaving control device, which includes a first selection module, a first delay module, a second selection module, and a first latch module. The first delay module is connected to the first selection module, the first selection module is connected to a first register group via the second selection module, and the first latch module is connected to two different register groups, including a first register group and a second register group, each register group including at least one or more registers. The first delay module is used to generate a target delayed clock signal. The first selection module is used to select between a test clock signal and the target delayed clock signal. The second selection module is used to select between different working states of the chip. The operating mode is switched to obtain the driving clock signal; the latch module is used to control the timing of the register signals of different groups, and the driving clock signal is used to provide a clock signal for each register in each register group. In this embodiment, by adding a first selection module, a second selection module, a delay module and a latch module, the test clock signal is delayed, and then according to the generated target delay clock signal and the latch module, the latch module is used to control the timing of the register signals of different groups, and the driving clock signal is used to provide a clock signal for each register in each register group, so that the registers of each group do not flip at the same time, and the flip time of the registers is reasonably staggered to effectively reduce the peak power consumption of the shift process.
[0027] like Figure 1 As shown, an embodiment of this application provides a clock stagger control device, which includes: a first selection module 102, a first delay module 101, a second selection module 103, and a first latch module 105. The first delay module 101 is connected to the first selection module 102, the first selection module 102 is connected to the first register group 104 through the second selection module 102, and the first latch module 105 is connected to two different register groups, including the first register group 104 and the second register group 109. Each register group includes at least one or more registers. The first delay module 101 is used to generate the target delay clock signal; The first selection module 102 is used to select the test clock signal and the target delay clock signal, i.e., MUX1; The second selection module 103 is used to switch between different operating modes of the chip to obtain a drive clock signal. The drive clock signal is used to provide clock signals for each register in the register group, namely MUX2. The first latch module 105 is used to process the timing violations introduced by the interaction of different groups of test clocks. That is, the latch is added to avoid the hold time violation caused by the delay problem of the signals of different groups of registers. The clock signal output by the second selection module is the driving clock signal, and it is opposite to the clock edge of the first latch module (latch).
[0028] The first and second selection modules are MUX modules. The latch module is a latch (LAT).
[0029] Specifically, a chip may contain multiple func clocks, such as func1 / func2. The second selector (second selection module) is used to switch between func and scan modes, but for different groups of second selectors, they are used to distinguish between func1 / func2 / func3.
[0030] During the scan shift phase, all registers in the chip are serially loaded with the target test vector through the SI terminal. At this time, the clock terminals (CK) of all registers continuously toggle, causing large-scale charging and discharging activities to occur in a very short time. Compared with the toggle behavior limited by data changes and clock gating in the normal functional mode, the overall toggle rate of registers in the scan shift phase is significantly increased, forming an instantaneous switching density much higher than that in the functional mode within a time window of about 1 ns. This causes significant peak power consumption and power supply noise risks. Based on this, this application provides a clock peak control device. The first selection module inputs two clock signals: an original clock signal and a delayed signal set by the delay module. The first selection module selects the original clock signal and the delayed signal through the enable terminal. The second selection module selects the functional mode or the test mode through the enable terminal. The clock signal output by the second selection module is input to the first register group and input to the first latch module through an inverter, thereby realizing the input of different phase drive clock signals to different register groups, so that the registers in each group will not toggle at the same time, reducing the peak value at the same time. In this embodiment, a single scan clock is internally divided into multiple scan clocks, so that the flip times of all internal registers are staggered. Without affecting the function and timing convergence, by distributing a single scan clock into multiple paths and programmably adjusting the delay of each scan clock, the register flip times are staggered, thereby significantly reducing the peak power consumption during the scan shift stage.
[0031] Some embodiments of this application delay the test clock signal by adding a first selection module, a second selection module, a first delay module, and a first latch module. Then, based on the generated target delayed clock signal and the first latch module, the first latch module is used to control the timing of register signals in different groups. The driving clock signal is used to provide a clock signal for each register in each register group, so that the registers in each group do not flip at the same time. This reasonably staggers the peak control of the register flip time and effectively reduces the peak power consumption of the shift process.
[0032] Another embodiment of this application further illustrates the clock stagger control device provided in the above embodiments.
[0033] Specifically, such as Figure 2 As shown, DFF is a register, MUX is a selector, and LAT is a latch; the input terminal of the first delay module receives the test clock signal, the output terminal of the first delay module is connected to the input terminal of the first selector module, the output terminal of the first selector module is connected to the input terminal of the second selector module, and the first selector module is also connected to a first enable terminal, which is used to switch the clock signals of different stages of the DFT.
[0034] Specifically, during the design phase, only one external scan_clk pad is retained. The corresponding scan clock (test clock signal) is divided into multiple groups inside the chip. Each group of clocks consists of two signals: one is the original phase scan clock, and the other is the delayed clock scan_clock_delay_0 generated by the buffer (delay module). The two clocks are selected by the first selection module MUX1. The enable signal of the first selection module MUX1 is controlled by the first enable terminal scan_en, which is used to switch the scan clock used in different test stages, that is, to switch between the shift and capture stages.
[0035] Some embodiments of this application provide two signals: a test clock signal of the original phase and a target delay clock signal generated by a first delay module. The two clock signals are selected by a first selection module, which is controlled by an enable signal to switch the clock signal used in different test stages.
[0036] Optionally, the input of the second selection module is also connected to a function clock signal, and the output of the second selection module is connected to the clock terminal of the first register group.
[0037] Optionally, the second selection module further includes a second enable terminal, which is used to switch the clock signal in different modes.
[0038] Subsequently, the scan clock output by the first selection module MUX1 is selected by the second selection module MUX2 along with their respective functional clocks func_clk. The selection signal of MUX2 is controlled by the second enable terminal scan_mode, thereby selecting different clock sources in functional mode and scan test mode, and finally forming the clock signal driving each group of DFFs (registers).
[0039] This application embodiment obtains the number of registers in each module and allocates the registers reasonably and evenly to different register groups (scan clock groups) to achieve a balanced distribution of clock load and flip-flop activity over time.
[0040] In some embodiments of this application, the clock signal output by the first selection module is then selected by the respective functional clock func_clk through the second selection module. The selection signal of the second selection module is controlled by the enable terminal, thereby selecting different clock sources in functional mode and scan test mode, and finally forming the clock signal driving each group of DFF (registers).
[0041] Optionally, the relative delay between the test clock signal and the target delay clock signal is less than or equal to half a clock cycle.
[0042] Specifically, because the internal multiple scan clocks are intentionally phase-shifted, a significant skew (relative delay) occurs between the clock groups. If scan chains are directly established between different register groups, such as... Figure 2 The DFF2 to DFF4 path in the circuit may cause serious hold issues that are difficult to fix through conventional routing adjustments. Therefore, during the DFT stage, a latch (LAT) triggered by the falling edge of the clock needs to be inserted between registers across scan clock groups, allowing scan data to be re-latched during cross-group transfers. As long as the skew between two adjacent scan clock groups does not exceed half a clock cycle, the hold time risk caused by cross-group scan chains can be effectively eliminated, ensuring timing reliability during the shift stage and guaranteeing timing under off-peak clock conditions.
[0043] Some embodiments of this application adjust the delay signal of the delay module to adjust the relative delay value of each clock signal to the optimal value that meets the expected peak power consumption index, so that the register flipping is fully spread out on the time axis, thereby significantly reducing the instantaneous peak power consumption of the shift phase.
[0044] Optionally, the output of the second selection module is also connected to the clock terminal of the first latch module via an inverter, and the output of the first latch module is connected to the SI pin of the register in the second register group.
[0045] Some embodiments of this application use opposite-edge triggered latches (LATs) inserted between cross-group scan chains to prevent timing issues during data transfer between different register groups during the shift process.
[0046] This application provides a structure and method for generating multiple scan clocks with different timing phases within the chip, relying only on a single external scan clock pad. This is used to group and drive different registers during the shift phase, thereby distributing the register toggle times. It also provides a clock architecture that combines MUX selection, scan_en, and scan_mode control to achieve seamless switching between the functional clock and multiple scan clocks, optimizing power consumption in test mode while ensuring that the timing of the functional mode is unaffected. Furthermore, it provides a clock optimization method that adjusts the scan clock delay units (such as buffer link delay) during the physical implementation phase to achieve the target peak power consumption, improving IR drop, reducing decap requirements, and thus comprehensively optimizing power consumption and area.
[0047] It should be noted that each of the implementable methods in this embodiment can be implemented individually or in any combination without conflict. This application does not limit this.
[0048] Another embodiment of this application provides a clock stagger control method for executing the clock stagger control device provided in the above embodiment, including: Obtain the target delay clock signal; When the first enable signal is a first preset value and the second enable signal is a second preset value, a drive clock signal for the register is generated based on the test clock signal and the target delay clock signal. The drive clock signal is used to provide a clock signal for each register in the register group so that the peak power consumption of each register meets the optimal solution.
[0049] Optionally, the method further includes: The target delay clock signal is obtained by adjusting the delay clock signal of the delay module.
[0050] Optionally, the method further includes: When the second enable signal is the second preset value, the control chip is in test mode.
[0051] Optionally, the method further includes: When the second enable signal is a third preset value, the control chip is in a functional mode, which is used to control the chip to perform a preset function.
[0052] Specifically, in the testing phase of this application embodiment, by adjusting the delay module, i.e. the buffer delay, the relative delay value skew of each test clock signal scan clock is adjusted to the optimal value that meets the expected peak power consumption index, so that the register flipping is fully spread out on the time axis, thereby significantly reducing the instantaneous peak power consumption of the shift phase.
[0053] The testing process is as follows: Shift phase: scan_en = 1 (first preset value). At this time, each group of clocks enters the corresponding register group through its own delay path, and completes the loading of test vectors at staggered times. Register flips are distributed across different time slices.
[0054] Because a latch (LAT) triggered by the opposite edge is inserted between cross-group scan chains, data transfer between different scan clock groups will not cause timing problems during the shift process.
[0055] Capture stage: scan_en=0. At this time, MUX1 selects the original scan clock without delay, and all registers resume using the clock with the same phase as the functional mode. This does not affect the functional path from the register Q terminal to the subsequent logic cloud, ensuring that the timing of the capture stage is not affected by the control device of this application.
[0056] Some embodiments of this application provide a chip including one or more sets of clock misalignment control devices as described above.
[0057] like Figure 1 As shown, the chip includes two sets of clock shaving control devices as described above, including: a first control device and a second control device. The first control device includes a first delay module 101, a first selection module 102, a second selection module 103, and a first latch module 105. The second control device includes a second delay module 106, a third selection module 107, a fourth selection module 108, and a second latch module 110. The first selection module 102 is connected to the first register group 104 through the second selection module 103; the output terminal of the first register group 104 is connected to the input terminal of the first latch module 105, and the output terminal of the second selection module 103 is connected to the clock terminal of the first latch module 105 through an inverter. The third selection module 107 is connected to the clock terminal of the second register group 109 through the fourth selection module 108, and the output terminal of the first latch module 105 is connected to the SI terminal of the register in the second register group 109.
[0058] Specifically, addressing the problems encountered in reducing power consumption during the DFT shift process in existing technologies, this application proposes a clock dispersion method based on the shift and capture working principles of DFT. This method divides the clock signal into n required time periods and reasonably staggers the toggle time of the register, effectively reducing the peak power consumption during the shift process. Compared to existing technologies, this application does not require additional chip package pins (pads) and avoids the timing convergence problems caused by clock phase adjustment, balancing power optimization and design complexity, and improving the stability and reliability of DFT testing.
[0059] By internally distributing the scan clock through multiple paths, the number of registers flipping simultaneously is significantly reduced, thereby effectively lowering the peak power consumption of the instantaneous clock during the scan shift phase. The staggered distribution of register flips on the time axis helps reduce the instantaneous current surge in the power network, improves IR drop convergence capability, and reduces the pressure on power integrity design.
[0060] With peak power consumption suppressed, the chip's need for decoupling capacitors is significantly reduced, allowing for a corresponding reduction in the size of the power decoupling unit, thereby saving chip area and related wiring resources. Simultaneously, since no additional decoupling capacitor pads are added and the impact on the functional clock path is minimal, better overall power consumption, area, and reliability metrics can be achieved while ensuring test coverage and timing convergence.
[0061] The above are merely embodiments of this application and are not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application. It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0062] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
[0063] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
Claims
1. A clock peak-shaving control device, characterized in that, The device includes: a first selection module, a first delay module, a second selection module, and a first latch module, wherein the first delay module is connected to the first selection module, the first selection module is connected to a first register group through the second selection module, and the first latch module is connected to two different register groups respectively, the different register groups including a first register group and a second register group, and the register group includes at least one or more registers. The first delay module is used to generate the target delay clock signal; The first selection module is used to select between the test clock signal and the target delay clock signal; The second selection module is used to switch between different operating modes of the chip to obtain the drive clock signal; The latch module is used to control the timing of register signals in different groups, and the drive clock signal is used to provide a clock signal for each register in each register group.
2. The clock stagger control device according to claim 1, characterized in that, The delay module receives a test clock signal at its input terminal, and its output terminal is connected to the input terminal of the first selection module. The output terminal of the first selection module is connected to the input terminal of the second selection module. The first selection module is also connected to a first enable terminal, which is used to switch the clock signals of different stages of the DFT.
3. The clock stagger control device according to claim 2, characterized in that, The input of the second selection module is also connected to a function clock signal, and the output of the second selection module is connected to the clock terminal of the first register group.
4. The clock stagger control device according to claim 3, characterized in that, The second selection module also includes a second enable terminal, which is used to switch the clock signal in different modes.
5. The clock stagger control device according to claim 1, characterized in that, The relative delay between the test clock signal and the target delay clock signal is less than or equal to half a clock cycle.
6. The clock stagger control device according to claim 4, characterized in that, The output of the second selection module is also connected to the clock terminal of the first latch module via an inverter, and the output of the first latch module is connected to the SI pin of the register in the second register group.
7. A clock stagger control method, characterized in that, The method, applied to the clock misalignment control device as described in any one of claims 1-6, comprises: Obtain the target delay clock signal; When the first enable signal is a first preset value and the second enable signal is a second preset value, a drive clock signal for the register is generated based on the test clock signal and the target delay clock signal. The drive clock signal is used to provide a clock signal for each register in the register group so that the peak power consumption of each register group meets the optimal solution.
8. The method according to claim 7, characterized in that, The method further includes: The target delay clock signal is obtained by adjusting the delay clock signal of the delay module.
9. The method according to claim 7, characterized in that, The method further includes: When the second enable signal is the second preset value, the control chip is in test mode.
10. The method according to claim 7, characterized in that, The method further includes: When the second enable signal is a third preset value, the control chip is in a functional mode, which is used to control the chip to perform a preset function.
11. A chip, characterized in that, It includes one or more sets of clock stagger control devices as described in any one of claims 1-6.
12. The chip according to claim 11, characterized in that, The chip includes: a first control device and a second control device, wherein the first control device includes a first delay module, a first selection module, a second selection module and a first latch module; the second control device includes a second delay module, a third selection module, a fourth selection module and a second latch module; The first selection module is connected to the first register group through the second selection module; the output of the first register group is connected to the input of the first latch module, and the output of the second selection module is connected to the clock terminal of the first latch module through an inverter. The third selection module is connected to the clock terminal of the second register group through the fourth selection module, and the output terminal of the first latch module is connected to the SI terminal of the register in the second register group.