Hierarchical power management system and voltage sag suppression method thereof

Abstract

This invention provides a hierarchical power management system and its voltage sag suppression method, relating to the fields of power management and microarchitecture control technology. It includes at least one application processor core, a system control processor (SCP), and a power management interface. The application processor core integrates a digital voltage sag detector (DDD), power transfer protection (PDP) logic, and an extended activity monitoring unit (AMU); the AMU is configured to monitor the activation state of the PDP logic. The SCP periodically reads the AMU's count data, calculates the PDP intervention rate, and dynamically adjusts the processor core's supply voltage or the DDD trigger threshold based on this intervention rate, forming a closed-loop control. This invention enables cross-level linkage between core internal hardware protection and system-level power management, effectively suppressing performance loss caused by dynamic voltage sags and improving energy efficiency and system reliability.

Description

Technical Field

[0001] This invention relates to the field of power management and microarchitecture control technology, specifically to a hierarchical IR drop protection system based on the coordinated linkage of SCP and Core PDP under the Armv9 architecture, and more particularly to a hierarchical power management system and its voltage drop suppression method. Background Technology

[0002] As semiconductor processes evolve to advanced nodes such as 5nm and 3nm, the transistor density of System-on-Chip (SoC) continues to increase. However, the interconnect metal resistance also increases, leading to a deterioration in the impedance characteristics of the Power Distribution Network (PDN). When the processor performs high computational loads, especially with Scalable Vector Extension (SVE2) or Scalable Matrix Extension (SME) instruction sets based on the Armv9 architecture, the current in the processor core fluctuates drastically (high di / dt) within a very short time, causing a significant dynamic voltage drop (IR Drop) on the PDN. Severe IR Drop can lead to circuit timing violations, resulting in functional errors or system failures.

[0003] To address this issue, existing technologies typically employ a two-layer protection mechanism: integrating hardware-level power delivery protection (PDP) or digital voltage drop detectors (DDD) within the core to immediately implement microarchitectural current limiting measures (such as inserting cavitation cycles or limiting command issuance) upon detecting a voltage drop; and at the system level, the system controller processor (SCP) performs slower power management through dynamic voltage frequency adjustment (DVFS).

[0004] However, existing solutions have significant shortcomings: First, the internal hardware protection is a passive protection that sacrifices instantaneous performance. Its frequent intervention can lead to processor performance significantly lower than the nominal frequency, creating a "performance black hole." Second, the external SCP makes decisions based on millisecond-level average load, and its response speed is severely mismatched with nanosecond-level current bursts. It often fails to prevent IR Drop and may even waste power due to voltage lag. In addition, existing solutions lack specific awareness and optimization for high-power-density vector instructions such as SVE2 / SME, making it difficult to achieve fine-grained energy efficiency control while ensuring the stability of high-performance computing.

[0005] Therefore, existing technologies lack an effective solution that can feed back the nanosecond-level hardware protection status of the core to the system-level power management unit in real time, thereby achieving cross-level, adaptive, and collaborative control. This results in the processor's performance potential not being fully realized under advanced processes, and energy efficiency optimization faces bottlenecks. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention provides a hierarchical power management system and a voltage sag suppression method thereof.

[0007] According to the present invention, a hierarchical power management system and a voltage sag suppression method thereof are provided, the scheme of which is as follows: In a first aspect, a hierarchical power management system is provided, the system comprising: at least one application processor core, the application processor core comprising: A digital voltage drop detector (DDD) is used to detect the power supply voltage inside the application processor core in real time. The power delivery protection (PDP) logic, coupled to the digital voltage drop detector (DDD), is configured to perform a microarchitecture current limiting operation when the DDD detects that the supply voltage is lower than a first trigger threshold. An extended activity monitoring unit (AMU), coupled to the power delivery protection PDP logic, includes at least one first event counter configured to count the activation state of the power delivery protection PDP logic. The system control processor (SCP) is communicatively coupled to the at least one application processor core; The system control processor (SCP) is configured as follows: The count value of the first event counter in the extended activity monitoring unit (AMU) is periodically read; The intervention rate of the power transmission protection PDP logic within a time period is calculated based on the count value. Based on the intervention rate, generate voltage control commands or threshold adjustment commands; A power management interface, coupled between the system control processor (SCP) and an external power management unit, is used to adjust the supply voltage provided to the application processor core according to the voltage control command, or to modify the first trigger threshold of the digital voltage drop detector (DDD) according to the threshold adjustment command, so as to form a closed-loop control.

[0008] Preferably, the application processor core supports the SVE2 instruction set or the SME instruction set; The extended activity monitoring unit (AMU) also includes a second event counter configured to count the number of SVE2 instructions or SME instructions executed by the application processor core. The system control processor SCP is further configured as follows: Read the count value of the second event counter to determine whether the current load of the application processor core is a vector-intensive load; When it is determined that the current load is a vector-intensive load and the intervention rate is on the rise, a predictive voltage control command or threshold adjustment command is generated before the intervention rate exceeds a preset performance loss threshold.

[0009] Preferably, the system control processor SCP is further configured to: Acquire sensor data or chip temperature data that reflect the aging state of the chip; Based on the sensor data or the chip temperature data, determine the compensation amount for the first trigger threshold; The system control processor (SCP) communicates with the application processor core via the System Control and Management Interface (SCMI) protocol. The threshold adjustment command is sent to the application processor core via the power management interface or directly via the system control and management interface to update the first trigger threshold of the digital voltage drop detector (DDD) to the value adjusted by the compensation amount.

[0010] Preferably, the count value of the first event counter is transmitted to the system control processor (SCP) via the system control and management interface (SCMI) protocol, and the threshold adjustment instruction is issued to the application processor core via the system control and management interface (SCMI) protocol.

[0011] Preferably, the microarchitecture current limiting operation performed by the power delivery protection PDP logic includes: inserting cavitation cycles into the pipeline of the application processor core, limiting the instruction issue width, or performing clock gating on some functional units of the application processor core.

[0012] Secondly, a voltage sag suppression method is provided, applied to the hierarchical power management system, the method comprising: The internal power supply voltage is monitored in real time by the digital voltage drop detector (DDD) within the application processor core. When the internal power supply voltage is lower than the first trigger threshold, the power delivery protection (PDP) logic in the application processor core is activated to perform microarchitecture current limiting operation and trigger the first event counter in the extended activity monitoring unit (AMU) to count. The system control processor (SCP) periodically reads the count value of the first event counter from the extended activity monitoring unit (AMU) through the system control and management interface; The system control processor SCP calculates the intervention rate of the power transfer protection PDP logic within the sampling window based on the count value; The system control processor (SCP) determines whether the intervention rate exceeds a preset performance loss threshold. If so, the system control processor SCP generates a voltage boost instruction and sends the voltage boost instruction to an external power management unit through the power management interface to increase the power supply voltage of the application processor core until the intervention rate falls back to an acceptable range.

[0013] Preferably, the method further includes the step of: The number of SVE2 or SME vector instructions executed by the application processor core is counted by the second event counter in the extended activity monitoring unit (AMU). The system control processor (SCP) identifies vector-intensive load scenarios based on the count value of the second event counter; In the vector-intensive load scenario, when the intervention rate begins to rise but does not reach the performance loss threshold, the system control processor SCP performs a predictive voltage boost or a first trigger threshold relaxation operation.

[0014] Preferably, the method further includes the step of: The system control processor SCP acquires chip aging monitoring data or real-time temperature data; The system control processor SCP calculates the dynamic adjustment amount of the first trigger threshold based on the aging monitoring data or the real-time temperature data. The system control processor (SCP) configures the adjusted first trigger threshold to the digital voltage drop detector (DDD) of the application processor core via the system control and management interface (SCMI).

[0015] Preferably, the method further includes the step of: If the intervention rate remains below a preset safety lower limit within multiple consecutive sampling windows, and the proportion of vector instructions in the application processor core is below a preset ratio, the system control processor SCP generates a voltage reduction instruction to gradually reduce the power supply voltage through the power management interface until the intervention rate recovers to an observable level for energy efficiency optimization.

[0016] Thirdly, a computer-readable storage medium is provided that stores a computer program, which, when executed by a processor, implements the steps of the voltage drop suppression method.

[0017] Compared with the prior art, the present invention has the following beneficial effects: 1. This invention extends the activity monitoring unit (AMU) to monitor the intervention strength of the power transmission protection device (PDP) inside the core, enabling the system control processor (SCP) to detect and compensate for the "voltage starvation" state in a timely manner, thereby effectively reducing the performance loss caused by hardware protection and improving the actual computing throughput and performance stability of the processor. 2. By distinguishing the execution load of scalar instructions and vector instructions (such as SVE2 / SME), this invention achieves on-demand voltage management, increases voltage margin only in vector-intensive scenarios, and maintains low voltage operation under normal loads, thereby achieving refined energy efficiency optimization and reducing the overall power consumption of the system. 3. This invention dynamically adjusts the core protection threshold based on chip aging and temperature data through the system control processor SCP, realizing adaptive compensation for process deviations, aging effects and environmental changes, and improving the reliability and performance consistency of the chip throughout its entire life cycle. 4. This invention constructs a cross-level software and hardware closed-loop control system by deeply coordinating the core internal nanosecond-level hardware protection mechanism with the system-level millisecond-level management unit. This enables more precise and timely suppression of dynamic voltage drop (IR Drop), improving the intelligence level and response efficiency of the system power management.

[0018] Other beneficial effects of the present invention will be explained in detail through the introduction of specific technical features and technical solutions in specific embodiments. Those skilled in the art should be able to understand the beneficial technical effects brought about by these technical features and technical solutions through the introduction of these technical features and technical solutions. Attached Figure Description

[0019] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is a schematic diagram of the collaborative system architecture of SCP and Core PDP based on Armv9 architecture; Figure 2 A schematic diagram of the PDP triggering and AMU statistics mechanism inside the Armv9 processor core; Figure 3 The flowchart for SCP's adaptive voltage regulation control based on PDP feedback; Figures 4a-4b A flowchart for predictive protection based on SVE2 instruction awareness. Detailed Implementation

[0020] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0021] This invention provides a hierarchical power management system that utilizes the System Control Processor (SCP) of the Armv9 architecture processor and the core's internal Power Delivery Protection (PDP) mechanism for cross-level linkage to solve the performance jitter and energy efficiency loss problems caused by dynamic voltage drop (IR Drop) in advanced process technologies. (Refer to...) Figure 1 As shown, the system specifically includes: at least one application processor core, the application processor core including: A digital voltage drop detector (DDD) is used to detect the power supply voltage inside the application processor core in real time. Reference Figure 2 and Figure 3 As shown, the power delivery protection (PDP) logic, coupled to the digital voltage drop detector (DDD), is configured to perform microarchitecture current limiting operations when the DDD detects that the supply voltage is lower than a first trigger threshold. The microarchitecture current limiting operations performed by the PDP logic include: inserting cavitation cycles into the pipeline of the application processor core, limiting the instruction issue width, or performing clock gating on some functional units of the application processor core.

[0022] An extended activity monitoring unit (AMU) coupled to power delivery protection (PDP) logic includes at least one first event counter configured to count the activation state of the PDP logic. The system control processor (SCP) is communicatively coupled to at least one application processor core; The system control processor SCP is configured to periodically read the count value of the first event counter in the extended activity monitoring unit (AMU); The intervention rate of the power transmission protection PDP logic within a time period is calculated based on the count value. Based on the intervention rate, generate voltage control commands or threshold adjustment commands; The power management interface, coupled between the system control processor (SCP) and the external power management unit, is used to adjust the supply voltage provided to the application processor core according to voltage control instructions, or to modify the first trigger threshold of the digital voltage drop detector (DDD) according to threshold adjustment instructions, so as to form closed-loop control.

[0023] The application processor core supports the SVE2 instruction set or the SME instruction set. The extended Activity Monitoring Unit (AMU) also includes a second event counter configured to count the number of SVE2 or SME instructions executed by the application processor core. The system control processor (SCP) is further configured to read the count value of the second event counter to determine whether the current load on the application processor core is a vector-intensive load. When it is determined that the current load is a vector-intensive load and the intervention rate is on an upward trend, a predictive voltage control command or threshold adjustment command is generated before the intervention rate exceeds a preset performance loss threshold.

[0024] The system control processor SCP is also configured to acquire sensor data or chip temperature data that reflect the chip's aging state. Based on sensor data or chip temperature data, a compensation amount for the first trigger threshold is determined; wherein, the system control processor (SCP) and the application processor core communicate via the system control and management interface (SCMI) protocol; a threshold adjustment command is sent to the application processor core via the power management interface or directly via the system control and management interface to update the first trigger threshold of the digital voltage drop detector (DDD) to the value adjusted by the compensation amount.

[0025] Furthermore, the count value of the first event counter is transmitted to the system control processor (SCP) via the system control and management interface (SCMI) protocol, and the threshold adjustment instruction is sent to the application processor core via the system control and management interface (SCMI) protocol.

[0026] The present invention also provides a voltage sag suppression method, applied to the aforementioned hierarchical power management system, the method comprising: The internal power supply voltage is monitored in real time by using the digital voltage drop detector (DDD) within the application processor core; When the internal supply voltage is lower than the first trigger threshold, the power delivery protection (PDP) logic in the application processor core is activated to perform microarchitecture current limiting operation and trigger the first event counter in the extended activity monitoring unit (AMU) to count. The system control processor (SCP) periodically reads the count value of the first event counter from the extended activity monitoring unit (AMU) through the system control and management interface; based on the count value, the SCP calculates the intervention rate of the power transfer protection (PDP) logic within the sampling window. The system control processor (SCP) determines whether the intervention rate exceeds a preset performance loss threshold. If so, the SCP generates a voltage boost command and sends it to the external power management unit via the power management interface to increase the power supply voltage of the application processor core until the intervention rate falls back to an acceptable range.

[0027] The voltage drop suppression method also includes the following steps: The number of SVE2 or SME vector instructions executed by the application processor core is counted by the second event counter in the extended activity monitoring unit (AMU). The system control processor SCP identifies vector-intensive load scenarios based on the count value of the second event counter. In vector-intensive load scenarios, when the intervention rate starts to rise but does not reach the performance loss threshold, the system control processor SCP performs a predictive voltage boost or a first trigger threshold relaxation operation.

[0028] Furthermore, the voltage drop suppression method also includes the following steps: The system control processor (SCP) acquires chip aging monitoring data or real-time temperature data. The system control processor SCP calculates the dynamic adjustment amount of the first trigger threshold based on the aging monitoring data or real-time temperature data. The system control processor (SCP) configures the adjusted first trigger threshold to the digital voltage drop detector (DDD) of the application processor core via the system control and management interface (SCMI).

[0029] If the intervention rate remains below the preset safety lower limit for multiple consecutive sampling windows, and the proportion of vector instructions in the application processor core is lower than the preset ratio, the system control processor SCP will generate a voltage reduction instruction to gradually reduce the power supply voltage through the power management interface until the intervention rate rises back to an observable level for energy efficiency optimization.

[0030] The present invention will now be described in more detail.

[0031] Figures 4a-4b As shown, by extending the Activity Monitoring Unit (AMU) to statistically analyze the intervention strength of the PDP within the core, the System Controller Processor (SCP) can detect the core's "voltage starvation" state. Combined with SVE2 / SME instruction ratio analysis, it dynamically adjusts the voltage margin and PDP trigger threshold, ensuring system stability while eliminating unnecessary performance losses. The main components and mechanisms include: 1. Armv9 processor core with PDP feedback mechanism: PDP execution unit: Integrated at the front end of the core pipeline, it monitors the local supply voltage in real time or predicts current demand based on instruction decoding. When an IR drop risk is detected, it performs microarchitecture-level current limiting (Throttling).

[0032] AMU Extension: Utilizes the programmable counter set of Arm AMU (Activity Monitors Unit) to define specific event codes for counting the number of clock cycles in which the PDP mechanism is activated (PDP_ACTIVE_CYCLES) and the number of microoperations canceled due to IRDrop (DROOP_STALL_UOPS).

[0033] 2. Intelligent SCP Controller Based on SCMI Protocol: SCP samples AMU data at high frequencies (e.g., 1ms) via an internal bus (e.g., APB / AXI-Lite).

[0034] Dual feedback loop algorithm: Reactive Loop: Calculates the PDP Rate. If the rate is too high, it indicates that the current voltage cannot support the load fluctuations at the current frequency. The SCP actively requests a voltage boost from the PMIC (AVS Boost) to allow the Core to exit current limiting mode.

[0035] Predictive Loop: This function tracks the percentage of SVE2 / SME vector instructions in the AMU. If a dense vector load is detected, the SCP preemptively issues instructions to modify the sensitivity threshold of the PDP within the Core (via system registers) and increases the voltage margin in advance.

[0036] 3. Dynamic PDP threshold adjustment mechanism: In traditional technologies, the PDP threshold is statically programmed. In this invention, the SCP can dynamically reprogram the PDP trigger voltage threshold inside the core via the SCMI interface based on the chip's aging level and current temperature. For example, in low-temperature environments (where transistor speeds are high), the SCP can reduce PDP sensitivity, allowing for deeper voltage drops and thus extracting more performance.

[0037] In a preferred embodiment, the system includes: 1. Application Processing Unit (AP Cluster) It contains multiple high-performance cores based on the Armv9 architecture (Cortex-X / A700 series). Each core contains: Digital Droop Detector (DDD): A digital sensor distributed around the core critical path, providing nanosecond-level output voltage status.

[0038] Pipeline Throttle Logic: Receives DDD signals and controls the Dispatcher unit to reduce the transmit width (e.g., from 6-wide to 2-wide) or insert cavitation.

[0039] Enhanced AMU: Includes a standard counter (Cycle, Instruction) and auxiliary counters (Aux0: PDP current limiting cycle, Aux1: SVE instruction count).

[0040] 2. System Control Processor (SCP) Based on a Cortex-M or Cortex-R core, it runs real-time firmware. The SCP acts as middleware between the OSPM (OS Power Management) and the hardware, taking over the DVFS policy. The SCP maintains a dynamic voltage-frequency table (DVFSTable), which contains not only frequency-voltage mappings but also the "PDP target budget" (i.e., the maximum percentage of PDP intervention allowed).

[0041] 3. On-chip interconnect and power management interface The SCP communicates with the AP via the MHU (Message Handling Unit) and controls the external PMIC via the I2C / SPMI interface.

[0042] Some specific implementation scenarios: I. Implementation Scenario: IR Drop Suppression Caused by SVE2 Matrix Operations 1. Load mutation: The application starts an AI inference task based on the SVE2 instruction set. The core current jumps instantly from 5A to 15A.

[0043] 2. Core-level protection (<10ns): The core's internal digital voltage drop detector (DDD) detects a local voltage below 0.75V (a preset safety threshold) within two clock cycles.

[0044] PDP logic activation forces the Dispatcher to insert one vacuole every other cycle for the next 50 cycles.

[0045] The AMU's auxiliary counter AMEVCNTR0_AUX (configured to record PDP cycles) increments by 50.

[0046] 3. SCP-level perception (~1ms): The SCP firmware reads AMEVCNTR0_AUX during a timed interrupt. Calculations show that the PDP intervention rate reached 5% in the past 1ms (i.e., 5% of the computing power was used for drop protection).

[0047] At the same time, SCP reads AMEVCNTR1_AUX (configured for SVE instruction counting) to confirm that the current load is vector intensive.

[0048] 4. System-level compensation: SCP determines that the current voltage (0.8V) is insufficient to support such a high di / dt load.

[0049] The SCP sends an I2C command to the PMIC to increase the CPU power supply voltage to 0.85V.

[0050] 5. Closed-loop convergence: As the voltage increases, the voltage dip detected by DDD exceeds 0.75V, and the PDP logic stops triggering.

[0051] The PDP counter in the AMU stops incrementing. The core resumes full-speed pipeline execution, and the SVE2 throughput increases by 20%.

[0052] II. Implementation Scenario: Aging-Based Adaptive Threshold Adjustment 1. Aging Monitoring: During idle periods, SCP runs BIST (built-in self-test) or reads the aging sensor inside the chip and finds that the NMOS speed is slowed down due to the NBTI effect.

[0053] 2. Strategy update: Aging means that the timing margin becomes smaller at the same voltage, making timing violations more likely to occur.

[0054] 3. Threshold Reconfiguration: SCP writes to the Core's system register via the SCMI interface, raising the PDP's trigger voltage threshold from 0.75V to 0.76V. This makes the Core more sensitive to voltage fluctuations, allowing for earlier intervention and protection, preventing calculation errors in aging chips.

[0055] In some embodiments, the present invention can be further extended to heterogeneous SoC systems including NPU (Neural Processing Unit) and GPU, enabling multi-domain linkage: When the NPU performs large-scale convolution operations, causing a drop in the shared power rail voltage, the SCP can utilize the mechanism of the present invention to not only regulate the NPU but also coordinately adjust the PDP threshold on the CPU side to prevent CPU malfunctions caused by cross-domain propagation of power supply noise. AI-assisted decision-making: The SCP can run a lightweight machine learning model internally, using historical data (instruction stream sequence) from the AMU as input to predict the IR Drop probability in the next few microseconds, achieving an evolution of control from "feedback" to "feedforward".

[0056] This invention provides a hierarchical power management system and its voltage drop suppression method. By extending the Active Monitoring Unit (AMU) to statistically analyze the intervention strength of the PDP inside the core, the System Controller Processor (SCP) can sense the "voltage starvation" state of the core. Combined with SVE2 / SME instruction ratio analysis, the voltage margin and PDP trigger threshold are dynamically adjusted to ensure system stability while eliminating unnecessary performance loss.

[0057] Those skilled in the art will understand that, besides implementing the system and its various devices, modules, and units provided by this invention in the form of purely computer-readable program code, the same functions can be achieved entirely through logical programming of the method steps, making the system and its various devices, modules, and units of this invention function in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers. Therefore, the system and its various devices, modules, and units provided by this invention can be considered as a hardware component, and the devices, modules, and units included therein for implementing various functions can also be considered as structures within the hardware component; alternatively, the devices, modules, and units for implementing various functions can be considered as both software modules implementing the method and structures within the hardware component.

[0058] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A hierarchical power management system, characterized in that, include: At least one application processor core, the application processor core comprising: A digital voltage drop detector (DDD) is used to detect the power supply voltage inside the application processor core in real time. The power delivery protection (PDP) logic, coupled to the digital voltage drop detector (DDD), is configured to perform a microarchitecture current limiting operation when the DDD detects that the supply voltage is lower than a first trigger threshold. An extended activity monitoring unit (AMU), coupled to the power delivery protection PDP logic, includes at least one first event counter configured to count the activation state of the power delivery protection PDP logic. The system control processor (SCP) is communicatively coupled to the at least one application processor core; The system control processor (SCP) is configured as follows: The count value of the first event counter in the extended activity monitoring unit (AMU) is periodically read; The intervention rate of the power transmission protection PDP logic within a time period is calculated based on the count value. Based on the intervention rate, generate voltage control commands or threshold adjustment commands; A power management interface, coupled between the system control processor (SCP) and an external power management unit, is used to adjust the supply voltage provided to the application processor core according to the voltage control command, or to modify the first trigger threshold of the digital voltage drop detector (DDD) according to the threshold adjustment command, so as to form a closed-loop control.

2. The hierarchical power management system according to claim 1, characterized in that, The application processor core supports the SVE2 instruction set or the SME instruction set; The extended activity monitoring unit (AMU) also includes a second event counter configured to count the number of SVE2 instructions or SME instructions executed by the application processor core. The system control processor SCP is further configured as follows: Read the count value of the second event counter to determine whether the current load of the application processor core is a vector-intensive load; When it is determined that the current load is a vector-intensive load and the intervention rate is on the rise, a predictive voltage control command or threshold adjustment command is generated before the intervention rate exceeds a preset performance loss threshold.

3. The hierarchical power management system according to claim 1 or 2, characterized in that, The system control processor SCP is also configured to: Acquire sensor data or chip temperature data that reflect the aging state of the chip; Based on the sensor data or the chip temperature data, determine the compensation amount for the first trigger threshold; The system control processor (SCP) communicates with the application processor core via the System Control and Management Interface (SCMI) protocol. The threshold adjustment command is sent to the application processor core via the power management interface or directly via the system control and management interface to update the first trigger threshold of the digital voltage drop detector (DDD) to the value adjusted by the compensation amount.

4. The hierarchical power management system according to claim 3, characterized in that, The count value of the first event counter is transmitted to the system control processor (SCP) via the system control and management interface (SCMI) protocol, and the threshold adjustment instruction is issued to the application processor core via the system control and management interface (SCMI) protocol.

5. The hierarchical power management system according to claim 1, characterized in that, The microarchitecture current limiting operations performed by the power delivery protection (PDP) logic include: inserting cavitation cycles into the pipeline of the application processor core, limiting the instruction issue width, or performing clock gating on some functional units of the application processor core.

6. A voltage sag suppression method, applied to a hierarchical power management system as described in any one of claims 1 to 5, characterized in that, The method includes: The internal power supply voltage is monitored in real time by the digital voltage drop detector (DDD) within the application processor core. When the internal power supply voltage is lower than the first trigger threshold, the power delivery protection (PDP) logic in the application processor core is activated to perform microarchitecture current limiting operation and trigger the first event counter in the extended activity monitoring unit (AMU) to count. The system control processor (SCP) periodically reads the count value of the first event counter from the extended activity monitoring unit (AMU) through the system control and management interface; The system control processor SCP calculates the intervention rate of the power transfer protection PDP logic within the sampling window based on the count value; The system control processor (SCP) determines whether the intervention rate exceeds a preset performance loss threshold. If so, the system control processor SCP generates a voltage boost instruction and sends the voltage boost instruction to an external power management unit through the power management interface to increase the power supply voltage of the application processor core until the intervention rate falls back to an acceptable range.

7. The voltage sag suppression method according to claim 6, characterized in that, It also includes the following steps: The number of SVE2 or SME vector instructions executed by the application processor core is counted by the second event counter in the extended activity monitoring unit (AMU). The system control processor (SCP) identifies vector-intensive load scenarios based on the count value of the second event counter; In the vector-intensive load scenario, when the intervention rate begins to rise but does not reach the performance loss threshold, the system control processor SCP performs a predictive voltage boost or a first trigger threshold relaxation operation.

8. The voltage sag suppression method according to claim 6, characterized in that, It also includes the following steps: The system control processor SCP acquires chip aging monitoring data or real-time temperature data; The system control processor SCP calculates the dynamic adjustment amount of the first trigger threshold based on the aging monitoring data or the real-time temperature data. The system control processor (SCP) configures the adjusted first trigger threshold to the digital voltage drop detector (DDD) of the application processor core via the system control and management interface (SCMI).

9. The voltage sag suppression method according to claim 6, characterized in that, It also includes the following steps: If the intervention rate remains below a preset safety lower limit within multiple consecutive sampling windows, and the proportion of vector instructions in the application processor core is below a preset ratio, the system control processor SCP generates a voltage reduction instruction to gradually reduce the power supply voltage through the power management interface until the intervention rate recovers to an observable level for energy efficiency optimization.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the voltage drop suppression method according to any one of claims 6 to 9.

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