Bicombinary calculation method and system based on double-chain differential coupling principle

Abstract

The application discloses a ternary computing method and system based on a double-chain difference coupling principle. A difference value (XnYn) is directly generated by a forward component Xn and a reverse component Yn in a difference coupling area, forming a three-value logic {‑1, 0, +1}, and a threshold comparison circuit is omitted, and operation follows BH=Σ(XnYn)×3^n. A hierarchical logic system composed of basic operators, minimum complete operators and global operators is constructed, and arbitrary three-value logic operation is realized; a circular waveguide structure is adopted to configure an optical path difference, so that coherent light directly forms three interference states at an output end, and optical three-value logic gates and optical full adders are realized; a double-chain six-bit structure is adopted for symbol coding, a two-dimensional geometric framework is driven to generate a symbol form, and logical and geometric expression unification is realized.

Claims

1. A ternary calculation device for comparison, characterized in that, include: The comparison and difference logic processing unit is configured with physically separated forward processing paths and reverse processing paths. The forward processing paths and reverse processing paths form a symmetrical topological relationship in physical space, so that the signal propagation paths of the two paths are of equal length and the propagation delay is equal. The differential coupling region is located at the intersection of the forward processing path and the reverse processing path, and the differential coupling region includes electrical logic gate circuits or optical interference structures; The ternary bit for comparison consists of a pair of physical storage bits, corresponding to the state Xn of the forward processing path and the state Yn of the reverse processing path, respectively. Xn and Yn are binary states 1 or 0, respectively. The logical value BH of the ternary bit for comparison is determined by the difference relationship (Xn-Yn), and takes the value {-1, 0, +1}. When Xn=1 and Yn=0, (Xn-Yn)=+1, which corresponds to a positive activation state; When Xn=0 and Yn=1, (Xn-Yn)=-1, which corresponds to the reverse activation state; When Xn = Yn, (Xn - Yn) = 0, which corresponds to the neutral state; The ternary number combination follows the combination operation formula: BH=Σ(Xn) Yn)×3 n In this process, forward carry and reverse carry are generated independently in the differential coupling region. When they are generated simultaneously, they cancel each other out in the differential coupling region. When only one of them generates a carry, it is passed to the next level.

2. A method for ternary logical operations, characterized in that, Using a computational architecture with physically separated forward processing paths, reverse processing paths, and differentially coupled regions, the following steps are performed: Decompose the input data into positive and negative components; Determine the format type of the input data: If the input data is in an internally combined ternary format, then the input data will be directly decomposed into positive and negative components. If the input data is in external binary format, then the input data is converted into a binary ternary format and then decomposed into positive and negative components. The forward and reverse components are input to the forward processing path and the reverse processing path, respectively; Binary logic operations are performed on the forward processing path and the reverse processing path respectively to obtain the forward intermediate state Xn and the reverse intermediate state Yn; In the differential coupling region, the state difference between the forward intermediate state Xn and the reverse intermediate state Yn is detected: when Xn=1 and Yn=0, the logic value is +1; when Xn=0 and Yn=1, the logic value is -1; when Xn and Yn are in the same state, the logic value is 0, which is used as the result of the three-valued logic operation. The result of the three-valued logic operation, BH, follows the ratio operation formula BH=Σ(Xn) Yn)×3 n Three-valued logic carry is achieved through differential coupling. The positive carry and the negative carry are generated independently in the differential coupling region. When they are generated at the same time, they cancel each other out in the differential coupling region. When only one is generated, it is passed to the next level.

3. A ternary computer system, characterized in that, include: The processing core includes a ternary comparison calculation device. This device has physically separated forward and reverse processing paths, as well as a difference coupling region. Each ternary comparison bit consists of a forward component Xn and a reverse component Yn. The logic value BH is determined by the difference relationship (Xn...). Yn) is determined, following the ratio calculation formula BH=Σ(Xn) Yn)×3 n ; The dual-bus architecture includes a forward data bus and a reverse data bus, which independently transmit the forward and reverse components of the data. The two buses work in parallel, and the forward bus signal and the reverse bus signal generate a combined ternary logical value in the differential coupling region. The comparison memory includes: a forward memory array for storing forward component data; a reverse memory array for storing reverse component data; and an address mapping unit for mapping the comparison ternary address to the physical address of the forward memory array and the reverse memory array through parity numbers. The format conversion interface converts the read external data format into the Bi-Jun ternary format, and converts the Bi-Jun ternary format data stored in the Bi-Jun memory into the external data format when writing it out. The mode switching unit is used to support switching between traditional binary operation mode and ternary operation mode. The logic value of the ternary bits of the system is determined by the difference relation (Xn). Yn) determined: (Xn=1,Yn=0)→+1, (Xn=0,Yn=1)→ 1, (Xn=Yn)→0.

4. A symbol encoding system based on the principle of dual-chain differential coupling, characterized in that, include: A dual-chain coding structure unit includes a first coding chain (A,B,C) and a second coding chain (a,b,c) to form a six-bit combination code. Each coding bit of the six-bit combination code corresponds to the activation state of a geometric line segment in spatial location, and the coding bit state drives the activation or deactivation of the corresponding line segment. The encoding storage unit stores the six-bit combined encoding and the frame type identifier field; The line segment activation driving circuit drives the physical activation or deactivation of the corresponding geometric line segment according to the state of each bit in the six-bit combined code; The encoded data itself contains complete topological information of the symbol, and changes in the encoding state directly lead to changes in the shape. The first encoding chain and the second encoding chain of the symbol encoding system are independent of each other and support two two-dimensional topological unfolding methods: orthogonal superposition and oblique superposition.

5. A three-valued logic operation element for optical interference, characterized in that, include: The optical input port group includes a first input terminal A for receiving a first coherent optical signal and a second input terminal a for receiving a second coherent optical signal; The optical output port group includes three output terminals (T, R, I), each corresponding to a logic value { 1,0,+1}: The logic value corresponding to the output terminal T 1. Output terminal R corresponds to logic value 0, and output terminal I corresponds to logic value +1; A circular waveguide structure is used so that five ports (A, a, T, R, I) are located on the same circle. The first input port A and the output port T are located at opposite ends of the same diameter of the circle, and the second input port a and the output port I are also located at opposite ends of the same diameter. I. String length and a The length of the T chord is an even multiple of half wavelength λ / 2, and the output terminal R is located on the arc at a position equidistant from the first input terminal A and the second input terminal a. Specifically, when two coherent optical signals are input simultaneously, a constructive interference neutralization state is generated at the R terminal, and destructive interference is generated at both the T and I terminals; when a single A input is received, the optical signal passes through A... The I-string path outputs a bright light at the I terminal, corresponding to a logic value +1; when there is a single input a, the optical signal passes through a... The T-chord path outputs a light at the T-end, corresponding to the logic value. 1; The geometric configuration of the circular waveguide structure satisfies the following condition: the difference between the optical path length from the first input terminal A to the output terminal T and the optical path length from the first input terminal A to the output terminal I is an odd multiple of half the wavelength. The optical interference ternary logic operation element is encapsulated in a sealed housing, and optical crosstalk is isolated between the ports by a transparent insulator.

6. The optical interference ternary logic operation element according to claim 5, characterized in that: The physical dimensions of the circular optical waveguide structure are based on half-wavelength λ / 2 as the basic unit. For any positive integer n, the circumferential diameter is (2n / 2). 2 +2n+1) half-wavelength units; the arc distance between the first input terminal A and the second input terminal a is (2n+1) half-wavelength units; A I. String length and a The length of chord T is (2n) 2 +2n) half-wavelength units, satisfying the Pythagorean triple configuration: (2n+1) 2 +(2n 2 +2n) 2 =(2n 2 +2n+1) 2 The positive integer n is selected based on the working wavelength and manufacturing process.

7. The optical interference ternary logic operation element according to claim 5, characterized in that: The circumferential optical waveguide structure is adjusted to include: Optical input terminals A and a receive coherent light of the same frequency, phase, and direction; Output terminal B is located on the circumference at a single-path propagation position corresponding to the first input terminal A, so that output terminal B has bright light output when only A is input, and B produces dark light when A and a are input at the same time; Output terminal b is located at the single-path propagation position corresponding to the second input terminal a, so that when only a is input, output terminal b has bright light output, and when A and a are input at the same time, they interfere with each other in the output terminal b to produce dark light. Where, the output terminal B = AND(A, NOT(a)) and the output terminal b = AND(a, NOT(A)).

8. The optical interference ternary logic operation element according to claim 5, characterized in that, include: The first input terminal A and the second input terminal a receive interference light of the same frequency, phase and direction; Single output terminal R; The circular optical waveguide structure is equipped with a directional coupler, which directs the optical energy of a single input to the T or I terminal, preventing it from reaching the R terminal. Only when two optical signals are input simultaneously do the two beams undergo constructive interference at R, resulting in effective optical output. The waveguide dimensions satisfy the Pythagorean triple configuration described in claim 6. Specifically, when the first input terminal A and the second input terminal a are input simultaneously, the output logic is 1. When there is only one input at the first input terminal A and the second input terminal a, the R terminal has no valid output and the logic value is 0.

9. The optical interference ternary logic operation element according to claim 5, characterized in that, The circumferential optical waveguide structure is adjusted to include: The first input terminal A and the second input terminal a are connected to a constant reference light signal. The two light signals from the first input terminal A and the second input terminal a originate from the same coherent light source and are split into two paths by a beam splitter. Single output terminal T; The circular waveguide structure satisfies the Pythagorean triple configuration described in claim 6. When the first input terminal A is 0, the constant light directly reaches the output terminal T, and the output logic value is 1. When the first input terminal A is 1, the two light sources generate destructive interference at the output terminal T to form dark light, and the output logic value is 0.

10. The optical interference ternary logic operation element according to claim 5, characterized in that: The optical output port group includes a photoelectric conversion unit that converts the optical ternary logic operation result into dual-channel electrical signals, including: Three independent photodetectors correspond to the output terminals T, R, and I, respectively. The T-terminal photodetector outputs the inverse component Yn, the I-terminal photodetector outputs the forward component Xn, and the R-terminal photodetector outputs the neutral state detection signal. The signal combining circuit combines the outputs of the three photodetectors into a dual-channel electrical signal (Xn, Yn). When there is light at terminal I, it outputs the corresponding logic value +1 (Xn=1, Yn=0), and when there is light at terminal T, it outputs the corresponding logic value (Xn=0, Yn=1).

1. When there is light at terminal R or no light at any of the three terminals, output (Xn=0,Yn=0) the corresponding logic value 0; The dual electrical signals (Xn, Yn) correspond to the positive and negative components, and are input to the differential coupling region of the ternary comparison calculation device as described in claim 1 for ternary logic operation.

11. The cascaded ternary optical path full adder of optical interference ternary logic operation elements according to claim 5, characterized in that, Multiple optical interference ternary logic operation elements are cascaded in the following architecture, which includes: The forward optical path addition path is composed of multiple 2to3 optical conversion elements and the optical path logic gates described in claims 7, 8, and 9, and processes the optical signals of the forward addend, forward addend, and forward carry input; The reverse optical path addition path is composed of multiple 2to3 optical conversion elements and the optical path logic gates described in claims 7, 8, and 9, and processes the optical signals of the reverse addend, the reverse addend, and the reverse carry input. In the optical differential coupling region, the output of the forward optical path and the output of the reverse optical path are combined by a coherent interference mechanism to generate a sum and carry result of a ternary comparison. The carry result is output in a comparison format and directly connected to the corresponding carry input terminal of the high-order ternary comparison full adder. In this system, the forward optical path and the reverse optical path work in parallel. When the forward carry and the reverse carry are generated simultaneously, they cancel each other out through optical difference coupling. When only one of them is generated, it is passed to the next level. The optical path full adder is integrated with the electrical circuit through the photoelectric conversion unit described in claim 10, and the forward optical path addition path and the reverse optical path addition path are respectively arranged in different optical path layers.

12. The system according to claim 3, characterized in that: The system includes a storage interface unit that implements an interleaved storage format based on bit pairs. The positive component of each bit of the bit pair storage structure and its corresponding negative component form a bit pair [Xn,Yn]. They are paired adjacently at the physical storage address to form a bit interleaved storage sequence in the format 0b[Aa][Bb][Cc], with the bit pair as the smallest storage alignment unit. The three physical steady states of the bit pair correspond to three-valued logic: (Xn=1, Yn=0) corresponds to the logic value +1, (Xn=0, Yn=1) corresponds to the logic value...

1. (Xn=0, Yn=0) corresponds to the logical value 0; in the physical storage structure, the forward and reverse components are written to independent storage bits, and the difference relationship (Xn) is... Yn) is naturally calculated by the readout circuit in the differential coupling region.

13. The system according to claim 12, characterized in that: The forward and reverse storage channels are arranged with odd and even addresses interleaved. Forward component data occupies even physical addresses, and reverse component data occupies odd physical addresses, or forward component data occupies odd physical addresses, and reverse component data occupies even physical addresses. In this process, the positive and negative components are read simultaneously within a single address access cycle using the parity address index, forming a complete ternary bit.

14. The system according to claim 3, characterized in that, in, A binary byte consists of N binary bits, where N ≥ 1. Each bit is represented by a pair of binary bits (X, Y). The storage encoding rule is: (X=1, Y=0) corresponds to a logical value +1; (X=0, Y=1) corresponds to a logical value +1. 1; (X=0, Y=0) corresponds to logic value 0; when (X=1, Y=1) occur simultaneously, the physical effect output of the differential coupling region is neutralized, and the storage unit can be configured with decision priority, which includes positive priority, reverse priority or neutral default; The mode switching mechanism switches modes via mode control signals: in decoupled mode, the forward and reverse processing paths work independently, and the system acts as a dual-path parallel binary processor; in coupled mode, the forward and reverse processing paths work together, and the system acts as a ternary processor.

15. The apparatus according to claim 1, characterized in that, The differential coupling region, through a combination of NAND and OR gates at the output terminals (T,R,I) of the 2to3 optical elements, generates eight basic Boolean output modes as shown in Table A below, identified by a 3-bit binary index id∈{0,1,...,7}. This index directly encodes the output value of the operator xy3(xy3ID,x,y) under three valid input conditions: id = xy3(T)<<2 | xy3(R)<<1 | xy3(I), where I is the positive activation input, R is the neutral state input, T is the negative activation input, and x and y values ​​are {0,1}. Table A: Eight basic Boolean output operators for xy3, xy3(xy3ID,x,y) The eight xy3 operators are directly derived from the physical characteristics of the 2to3 element and are generated by directly combining the optical path NOT gate of claim 9 and the optical path AND gate of claim 8.

16. The apparatus according to claim 15, characterized in that, By applying a difference operation to any two of the eight basic Boolean output modes, a univariate ternary difference operator is constructed: Difference operator (gid,x,y) = mode (xid,x,y). Pattern (yid, x, y); 64 candidate combinations of (xid, yid) are deduplicated into 27 different output vectors, covering the entire univariate ternary function space. 3 =27 mappings, forming a minimal complete set; with balanced ternary index gid∈{0t222(= 13),..,0t000(=0),.., 0t111(=+13)} is the identifier, and the output vector is monotonically corresponding to g3 operator table B in lexicographical order with gid: Table B: Complete Comparison Table of 27 g3 Univariate Ternary Difference Operators The difference calculation is achieved by the optical path difference of the aforementioned 2to2 ratio difference optical path element.

17. The apparatus according to claim 16, characterized in that, Arbitrary binary ternary logic operation functions are implemented using a tri-state row selection structure: When input A is in the reverse activation state T, the xy3(4,x,y) operator is selected, and the first row difference operator G3 is applied to B, with the index Tid; when input A is in the neutral state R, the xy3(2,x,y) operator is selected, and the second row difference operator G3 is applied to B, with the index Rid; when input A is in the positive activation state I, the xy3(1,x,y) operator is selected, and the third row difference operator G3 is applied to B, with the index Iid, thus forming the C9 operator; The three difference operators are configured independently, and the combination space is 27. 3 =19683, uniformly configured index T9id is represented in balanced ternary as 0t[Tid(3 bits)_Rid(3 bits)_Iid(3 bits)], with a value range of 0t222_222_222 to 0t111_111_111, uniquely specifying the three-row difference operator configuration, covering all 19683 binary ternary logic mapping operators C9(T9id,A,B), A=(x1-y1), B=(x2-y2), C9(T9id,A,B)=y1*g3(Tid,x2,y2) + x1′y1′ g3(Rid,x2,y2) +x1*g3(Iid,x2,y2).

18. The apparatus according to claim 17, characterized in that, There are 3 commutative subsets that satisfy C9(A,B)=C9(B,A). 6 =729 configurations, with the following configuration constraints: The truth matrix of the three-row difference operator is symmetric about the main diagonal, corresponding to 729 combinations of gid_T=gid_I and gid_R taking all 27 values ​​in T9id, to balance the ternary index T6id∈{0t222_222(= 364),...,0t111_111(=+364)} unique identifier; the free parameters are only the diagonal elements and the upper triangular elements, a total of 6 three-valued parameters, representing the 6-bit code 0t[abc_ef_ _i] of T6id, where b=d, c=g and f=h of T9id are equal, and the corresponding truth table encoding logic mapping operator C6(T6id,A,B) is to fill the 3 equal bits 0t[abc_bef_chi] of T9id and then call the C9(T9id,A,B) operator.

19. The apparatus according to claim 17, characterized in that, include: The Boolean output mode generation unit is addressed by a 3-bit binary index id and outputs one of the eight basic Boolean output modes, which is implemented by the port output of the 2to3 optical element as described in claim 5 and the NOT gate combination as described in claim 9. The differential operator selection unit addresses 27 carefully selected (xid, yid) pairs using balanced ternary index gid, retrieves two outputs from the Boolean output mode generation unit, and performs the difference operation (Xn). Yn); The row selection decomposition structure unit generates a three-state mutually exclusive row selection signal with the input A's encoding (x1, y1): S_T=y1, S_R=AND(NOT(x1),NOT(y1)), and S_I=x1. These signals activate the three row differential operators respectively. The conditional superposition output C9(A,B)=S_T·operator_T+S_R·operator_R+S_I·operator_I. The three optical signals are physically superimposed in the differential coupling region. The T9id configuration interface receives a 9-bit balanced ternary configuration index in the format 0t[gid_T 3 bits][gid_R 3 bits][gid_I 3 bits]. It decodes the index into gid_T, gid_R, and gid_I segments, with values ​​ranging from 0t222_222_222 to 0t111_111_111. This range corresponds to... From +9841 to +9841, dynamic switching between all 19683 configurations is supported; The Boolean output mode generation unit, the difference operator selection unit, and the row selection decomposition structure unit are cascaded in a single physical package, covering all 27 unary ternary functions and all 19,683 binary ternary functions. This achieves a reconfigurable ternary logic operation unit with minimal completeness. The completeness is guaranteed by the algebraic completeness of pairwise differences of the 8 XY3 basic operators, and is implemented through optical elements or electronic logic circuits.

20. The system according to claim 3, characterized in that, The processing core includes the reconfigurable ternary logic operation unit as described in claim 19, which supports a reconfigurable ternary processor basic unit with T9id as the instruction word, and can completely specify a binary ternary logic operation through a single instruction. The instruction space covers all 19,683 binary ternary logical mappings with balanced ternary index T9id, including the following basic logical operations and all 19,683 weight configurations of 3×3 convolution kernels: The AND operation AND(A,B) is performed, T9id=0t102_000_201, the positive result component =Ax·Bx+Ay·By, and the negative result component Y =Ax·By+Ay·Bx; The OR operation OR(A,B) is defined as follows: T9id=0t220_201_011, the positive result component = Ax+Bx, and the negative result component = Ay+By. The addition operation ADD(A,B) is performed, and T9id=0t120_201_012; The difference operation is performed as DIF(A,B), T9id=0t022_102_110, the positive result component = Ax+By, and the negative result component = Ay+Bx; The difference calculation is performed using SUB(A,B), and T9id=0t021_102_210; When the input positive component x and the negative component y are both 1, the input is processed according to the comparison and combination difference logic in the difference coupling region, and according to the comparison, combination and difference same logic in each binary addition path. The two-stage processing rules are uniquely determined by the circuit topology position.

21. The apparatus according to claim 1, characterized in that, Including electrically implemented ternary full adders: The positive binary addition path includes a binary full adder, which performs a binary full addition operation on the positive addend, positive addend and positive carry to generate a positive sum Xs and a positive carry Xc; The reverse binary addition path includes a binary full adder, which performs a binary full addition operation on the reversed addend, reversed sum, and reverse carry to generate a reversed sum Ys and a reversed carry Yc. The two-layer differential coupling unit is implemented by the 2to2 difference logic structure described in claim 7: the first layer is the sum-value differential coupling, the positive local sum BHx=AND(NOT(Ys),Xs), the negative local sum BHy=AND(NOT(Xs),Ys), when Xs=Ys=1, the locals cancel each other and pass on the additional contribution to the carry level; The second layer of carry-differential coupling is as follows: forward carry Cx = AND(NOT(Yc),Xc), reverse carry Cy = AND(NOT(Xc),Yc). When Xc = Yc = 1, the two carrys cancel each other out and the neutral state is passed to the higher bit. The forward and reverse binary addition paths operate in parallel and are not directly cascaded; the carry is connected to the corresponding carry input of the high-order full adder in a dual-path comparison format of forward carry Cx and reverse carry Cy.

22. The apparatus according to claim 1, characterized in that, The same binary bit pair (x, y) supports dual semantic interpretation: symmetric ternary with difference value t=x y is read and retrieved. 1, 0, +1}; Asymmetric ternary is read as a vector sum c = x + y, taking values ​​{0, 1, 2}; The two semantics are switched at the reading and interpretation layer by a prefix identifier, while the underlying bit pair (x, y) remains unchanged; When the signed t is recovered from the known c, the complete relation is t = c 2y, and simultaneously read the inverse component y.

23. The method according to claim 2, characterized in that, The following physical logic processing steps are included: Dual-track comparison coding decomposes a three-valued variable into physically separate positive and negative components, and the two components satisfy the non-coexisting comparison constraint at any time. Instruction truth mapping directly defines the Boolean output of a function in each input state through binary index bit weights; Differential numerical generation involves performing algebraic subtraction on the Boolean outputs of the two paths mentioned above, and naturally constructing a balanced ternary result containing the three states {-1, 0, 1} by utilizing the state differences of the physical paths. Mutual exclusion path selection utilizes the component signals of the first input to construct mutual exclusion control logic, selectively activates a single path from multiple unary operation paths, and combines the state of the second input to synthesize the final operation result; Symbolic symmetric operations construct positive and negative symmetric sign transformation rules in three-valued logic through the algebraic configuration of the sum of the products of components with the same sign and the sum of the products of components with opposite signs. Where A=(Ax,Ay) and B=(Bx,By) are ratios, Ax and Bx are the positive components, and Ay and By are the negative components: The AND operation AND(A,B) = A × B has the following positive result component = Ax·Bx + Ay·By and the negative result component = Ax·By + Ay·Bx, T9id = 0t102_000_201; the truth tables for the AND operation AND(A,B) and the MUL operation MUL(A,B) are defined in Table C below: Table C: Truth Tables for AND(A,B) and MUL(A,B) Operations The truth tables for the OR operation OR(A,B)=A+B and the OR plus ADD(A,B) are shown in Table D below. Table D: Truth table for OR(A,B) and ADD(A,B) operations Comparison and difference operation DIF(A,B)=A The truth table for B and the ratio subtraction operation SUB(A,B) is shown in the following table, subject to E constraints: Table E: Truth table for the comparison difference operation DIF(A,B) and the comparison subtraction operation SUB(A,B) The comparison-combination-NOT operation, the comparison-combination-inverse operation, and the comparison-combination operation correspond to the logical relationships of the I row, O row, and T row of the comparison-combination-difference operation, respectively. The logic and calculation of the basic operation family are implemented by software through an engine and by providing an application processing interface, or by hardware implementation through the optical path element or electronic logic circuit described in claims 7, 8, and 9.

24. The apparatus according to claim 1, characterized in that: The ratio difference logic processing unit includes an optical ratio difference element, including: 2 optical input terminals (A, a), receiving two optical signals representing the ratio composite number, A is the forward component optical signal, and a is the reverse component optical signal; 2 optical output terminals (B, b), outputting two optical signals of the ratio difference result; An optical operation module, the output satisfies: the forward output B = AND(A, NOT(a)), and the reverse output b = AND(a, NOT(A)), which is implemented by the optical path combination of the optical path AND gate described in claim 8 and the optical path NOT gate described in claim 9; Among them, the optical ratio difference element is logically equivalent to the 2to2 ratio difference logic element described in claim 7.

25. The symbol encoding system according to claim 4, wherein: The symbol encoding system uses 8-bit binary byte data to be compatible with modern computer systems, where: the high two bits (Bit7, Bit6) define the frame type, 0b10 is the first type of frame, the field type, 0b11 is the second type of frame, the 龱 type, 0b0x is compatible with the standard ASCII; the last six bits Bit5-0 form a six-bit combined encoding, directly driving the activation states of the six line segments corresponding to the frame type; the encoding spaces of 0b10 and 0b11 are distinguished from the extended ASCII through the system mode register, and the mode switch is determined by the system mode control signal.

26. The symbol encoding system according to claim 4, wherein: The structure of the first type of orthogonal superposition field-type frame is formed by the orthogonal superposition of the three horizontal line segment groups corresponding to the first coding chain (A, B, C) and the three vertical line segment groups corresponding to the second coding chain (a, b, c); Among them, each coding bit directly drives the activation state of the corresponding line segment, and the field-type frame uses the 0b[ABC][abc] ratio group format. Each of the two chains has 8 states, and the orthogonal superposition forms 64 static symbols; Specifically, when acquiring a symbol image of a field-shaped frame rotated 90 degrees, the detected first encoding chain [ABC] and the second encoding chain [abc] are swapped as a whole: 0b[ABC][abc] 0b[abc][ABC]; Conversely, performing a chain-level interchange operation on the encoding will have the same effect as rotating the grid-shaped symbol by 90 degrees.

27. The symbol encoding system according to claim 4, characterized in that, Including: A coding configuration matrix, using an 8-bit word structure, the high two bits Bit7-6 are used as physical frame identification bits, and the low six bits Bit5-0 are used as line segment control bits. The system dynamically switches between ternary coding and standard ASCII through the mode register; An orthogonal chain swapping module, using the 0b[ABC][abc] chain storage format, where [ABC] and [abc] are respectively mapped to the orthogonal horizontal and vertical line segment groups of the display unit. The orthogonal chain swapping module integrates a bus-level chain exchange circuit, and through the overall flipping of the address spaces of the first coding chain and the second coding chain, an equivalent mapping of a 90-degree rotation of the symbol is achieved in O(1) time; A bit pair swapping module, using the 0b[Aa][Bb][Cc] bit pair interleaved storage format, where each pair of bits [Xx] is mapped to a pair of skew-symmetric line segments. The bit pair swapping module integrates a bit pair internal cross logic unit, and through synchronously triggering the bit order swapping of the two components inside each pair of bits, an equivalent mapping of a 90-degree rotation of the symbol is achieved in O(1) time.

28. The device according to claim 1, wherein: The comparison logic processing unit is applied to artificial intelligence reasoning or pattern recognition, and the three-valued logic state { 1, 0, +1} correspond to the inhibition, neutral and activation states of the neural network, respectively. The three-valued activation states are directly generated by the physical effect of the differential coupling region described in claim 1. The forward processing path corresponds to the excitatory weights, and the reverse processing path corresponds to the inhibitory weights. In the multilayer neural network, the combined three-valued activation output of the previous layer is directly used as the input of the forward and reverse components of the next layer. Interlayer propagation is directly supported by the dual-path parallel architecture described in claim 1.

29. The apparatus according to claim 1, characterized in that, The ratio difference logic processing unit is applied to pixel-level image processing and performs the following operations: Pixel ternization maps image pixel values ​​to a ternary representation {T= 1, O=0, I=+1}, stored in the ratio format (Xn, Yn); A 3×3 convolution window, using a 3×3 ternary pixel array, corresponds to the input space of the binary ternary logic function described in claim 20; The convolution kernel and T9id are isomorphically configured, where the nine ternary weights {T,O,I} of the 3×3 convolution kernel are directly isomorphic to the balanced ternary index of T9id. Each T9id uniquely determines a convolution kernel. The convolution kernel is directly configured to the hardware differential coupling circuit through T9id encoding. Among them, 19683 T9ids correspond to 19683 different 3×3 ternary convolution kernels. Feature extraction is performed by parallel computation of pixel-by-pixel operations with convolution kernels within a window using the differential coupling mechanism described in claim 1. The output mapping directly maps the result of the three-value operation to the symbol encoding described in claim 4, or converts it back to the pixel value.

30. The apparatus according to claim 1, characterized in that, The comparison and difference logic processing unit constitutes a hardware accelerator for a ternary convolutional neural network and performs the following processing: Forward path convolution, wherein the forward processing path processes convolution operations with positive weight +1; Reverse path convolution, where the reverse processing path processes negative weights. Convolution operation of 1; Differential coupling synthesis, through the differential coupling mechanism described in claim 1, performs differential synthesis of forward and backward convolution results, and directly outputs the ternary convolution result; The feature maps are stored in a dual-chain format, and the intermediate feature maps are stored using the dual-chain encoding format described in claim 4. The convolution operation is performed layer by layer through reconfigurable ternary logic operations configured by the 9-bit ternary logic state configuration register group T9id. Symbol recognition is directly output, and the output layer directly generates the six-bit code as described in claim 4.

31. The apparatus according to claim 1 or the system according to claim 3, characterized in that... include: A non-volatile memory array with dual bus interfaces stores the positive component BHx of the ternary data in a first physical storage area and the negative component BHy in a second physical storage area. The first physical storage area and the second physical storage area are located on different integrated circuit chips or different physical storage media, and their access permissions are independently controlled. The difference reconstruction unit, only after authentication, simultaneously reads the positive component BHx and the negative component BHy, and performs a difference logic operation BH=BHx. BHy reconstructs the complete ternary data of the ratio; The data protection mechanism is applicable to protecting intermediate computation states in the logical operation domain, protecting neural network weights in the convolutional computation domain, and protecting encoded data in the symbolic representation domain. This involves simultaneously reading BHx and BHy and performing a comparison operation BH=BHx. BHy.

32. A storage interface unit for storing ratio-based ternary data, wherein the ratio-based ternary data uses a pair of binary bits to represent a symmetric ternary bit, the pair of binary bits being the positive component Xn and the negative component Yn of the ratio-based ternary bit, the storage interface unit comprising: In the bit-pair storage structure, the positive component Xn and its corresponding negative component Yn of each compared ternary bit are paired adjacently in physical storage address to form a bit-interleaved storage sequence. The bit pair is the smallest storage alignment unit. The correspondence between the three physical stable states of the bit pair and the ternary logic is as follows: (Xn=1, Yn=0) corresponds to logic value +1; (Xn=0, Yn=1) corresponds to logic value +1; 1; (Xn=0,Yn=0) corresponds to the logic value 0; In the address mapping unit, forward component data occupies even-numbered physical addresses, and reverse component data occupies odd-numbered physical addresses. Both forward and reverse components are addressed simultaneously through the odd-even address index. The format conversion circuit, composed of combinational logic circuits, performs bidirectional lossless conversion between ratio interleaved format and ratio group format by parity bit rearrangement mapping.

33. The ternary calculation device according to claim 1, characterized in that, The ternary multiplication calculation device is implemented using a SoC architecture, with hardware implementation via FPGA or ASIC. In the FPGA implementation, the forward processing path is mapped to a first logic resource region, and the reverse processing path is mapped to a physically isolated second logic resource region. The first and second logic resource regions are interconnected only through differentially coupled logic gates. The ternary logic operations described in claims 19, 20, 21, and 22 are configured using lookup table (LUT) resources. The dual-chain memory structure described in claims 12 and 13 is implemented using block RAM resources. The electrical ternary multiplication full adder described in claim 21 is implemented using a DSP unit. In the SoC implementation, the functional modules of the first logic resource region, the second logic resource region, LUT resources, RAM resources, and the DSP unit are integrated on a single chip via an on-chip interconnect bus. The physical isolation between the forward and reverse processing paths is achieved through independent IP cores or through a custom ASIC chip.

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