Isolation exclusion method, device and equipment for processor core in Linux system

Abstract

This application provides a method, apparatus, and device for isolating and exclusiveizing processor cores in a Linux system. The method includes: receiving a resource isolation configuration request based on a control interface in the proc file system, the resource isolation configuration request including the identification information of the target processor core; performing a resource isolation operation on the target processor core according to the resource isolation configuration request, the resource isolation operation being used to adjust the process scheduling permissions and system resource access permissions of the target processor core; and updating the system scheduling domain configuration based on the resource isolation operation, the system scheduling domain configuration being used to determine the scheduling strategy of tasks on the target processor core. By dynamically adjusting the isolation and exclusive management of multi-core CPU resources through the proc file system, it supports dynamic adjustment of isolation strategies, selective isolation of system resources, and flexible configuration of load balancing modes according to business needs at runtime. This effectively addresses the CPU resource and real-time requirements under different business scenarios, improving system performance and stability.

Description

Technical Field

[0001] This application relates to the field of computers, and in particular to a method, apparatus, and device for isolating and excluding processor cores in a Linux system. Background Technology

[0002] With the rapid development of intelligent vehicle technology, the performance requirements of cockpit chips, as the "brain" of the vehicle cockpit system, are continuously increasing. Modern cockpit chips typically feature a multi-core architecture, simultaneously supporting diverse services such as navigation, entertainment, and intelligent driving assistance. These service scenarios place differentiated demands on the allocation and real-time performance of CPU (Central Processing Unit) resources. However, existing cockpit chip resource management mechanisms are mostly statically configured, unable to dynamically adjust the isolation and allocation of CPU resources according to service requirements, leading to problems such as low resource utilization and delayed response to critical services. Summary of the Invention

[0003] This application provides a method, apparatus, and device for isolating and excluding processor cores in a Linux system, so as to achieve the effect of dynamic isolation and exclusion.

[0004] In a first aspect, embodiments of this application provide a method for isolating and exclusiveizing processor cores in a Linux system, the method comprising:

[0005] Based on the control interface in the proc file system, it receives resource isolation configuration requests, which include the identification information of the target processor core;

[0006] Based on the resource isolation configuration request, a resource isolation operation is performed on the target processor core. The resource isolation operation is used to adjust the process scheduling permissions and system resource access permissions of the target processor core.

[0007] Based on resource isolation operations, update the system scheduling domain configuration, which is used to determine the scheduling policy of tasks on the target processor core.

[0008] In one possible implementation, the control interface includes an isolation control interface, and the resource isolation configuration request includes a first request received based on the isolation control interface; according to the resource isolation configuration request, performing a resource isolation operation on the target processor core includes:

[0009] Identify the isolation configuration type corresponding to the target processor core in the first request;

[0010] When the isolation configuration type indicates that the target processor core needs to be isolated, the isolation information corresponding to the target processor core is set to the isolation state.

[0011] In one possible implementation, identifying the isolation configuration type corresponding to the target processor core in the first request includes:

[0012] Identify the bitmask corresponding to the target processor core in the file of the isolation control interface.

[0013] In one possible implementation, the control interface includes an enhanced type control interface, and the resource isolation configuration request includes a second request received based on the enhanced type control interface; according to the resource isolation configuration request, performing resource isolation operations on the target processor core includes:

[0014] Identify the flag corresponding to the system resource processing request in the second request;

[0015] When the flag for a system resource processing request is active, the system resource processing request is redirected to a processor core other than the target processor core. The system resource processing request includes at least one of an interrupt handling request, a work queue execution request, and a timer trigger request.

[0016] In one possible implementation, the control interface includes an isolation task control interface, and the isolation configuration request includes a third request received based on the isolation task control interface; according to the isolation configuration request, performing resource isolation operations on the target processor core includes:

[0017] Identify the task descriptor of the target task in the third request;

[0018] If a task descriptor is detected, the target task is added to the task list of the target processor core, and then deleted after the target task has been executed.

[0019] In one possible implementation, after updating the system scheduling domain configuration based on resource isolation operations, the following steps are also included:

[0020] Receive scheduling mode configuration requests based on the scheduling mode control interface in the proc file system;

[0021] Based on the scheduling mode configuration request, determine the scheduling mode of the target processor core;

[0022] Based on the scheduling mode of the target processor core, adjust the load balancing strategy of the system scheduling domain. The load balancing strategy includes allowing or disallowing the target processor core to participate in global task scheduling.

[0023] In one possible implementation, the load balancing strategy of the system scheduling domain is adjusted according to the scheduling mode of the target processor core, including:

[0024] When the target processor core's scheduling mode is set to enable load balancing, the load balancing strategy of the system scheduling domain is adjusted according to the load status of the target processor core.

[0025] In one possible implementation, the method further includes:

[0026] Before performing resource isolation operations on the target processor core according to the resource isolation configuration request, the parameters of the target processor core are checked to ensure that the first verification result of the parameters of the target processor core is that the verification passes.

[0027] Secondly, embodiments of this application provide an isolation and exclusivity device for processor cores in a Linux system, the method comprising:

[0028] The information acquisition module is used to receive resource isolation configuration requests based on the control interface in the proc file system. The resource isolation configuration requests include the identification information of the target processor core.

[0029] The isolation processing module is used to perform resource isolation operations on the target processor core according to the resource isolation configuration request. The resource isolation operations are used to adjust the process scheduling permissions and system resource access permissions of the target processor core.

[0030] The update module is used to update the system scheduling domain configuration based on resource isolation operations. The system scheduling domain configuration is used to determine the scheduling policy of tasks on the target processor core.

[0031] Thirdly, embodiments of this application provide a computer device, including: a memory and a processor; the memory stores computer execution instructions; the processor executes the computer execution instructions stored in the memory, causing the processor to perform the first aspect and / or various possible implementations of the first aspect as described above.

[0032] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the first aspect and / or various possible implementations of the first aspect.

[0033] Fifthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the first aspect and / or various possible implementations of the first aspect.

[0034] This application provides a method, apparatus, and device for isolating and exclusiveizing processor cores in a Linux system. The method includes: receiving a resource isolation configuration request based on a control interface in the proc file system, the resource isolation configuration request including the identification information of the target processor core; performing a resource isolation operation on the target processor core according to the resource isolation configuration request, the resource isolation operation being used to adjust the process scheduling permissions and system resource access permissions of the target processor core; and updating the system scheduling domain configuration based on the resource isolation operation, the system scheduling domain configuration being used to determine the scheduling strategy of tasks on the target processor core. By dynamically adjusting the isolation and exclusive management of multi-core CPU resources through the proc file system, it supports dynamic adjustment of isolation strategies, selective isolation of system resources, and flexible configuration of load balancing modes according to business needs at runtime. This effectively addresses the CPU resource and real-time requirements under different business scenarios, improving system performance and stability. Attached Figure Description

[0035] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0036] Figure 1 A flowchart illustrating the method for isolating and exclusiveizing processor cores in a Linux system provided in this application. Figure 1 ;

[0037] Figure 2 A flowchart illustrating the method for isolating and exclusiveizing processor cores in a Linux system provided in this application. Figure 2 ;

[0038] Figure 3 A flowchart illustrating the method for isolating and exclusiveizing processor cores in a Linux system provided in this application. Figure 3 ;

[0039] Figure 4 A flowchart illustrating the method for isolating and exclusiveizing processor cores in a Linux system provided in this application. Figure 4 ;

[0040] Figure 5 A schematic diagram of the structure of the isolation and exclusion device for the processor core in the Linux system provided in this application;

[0041] Figure 6 A schematic diagram of the structure of the computer device provided in this application.

[0042] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0043] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0044] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0045] The cockpit chip, also known as the smart cockpit chip or in-vehicle infotainment system chip, is the "brain" and core computing platform of a car's smart cockpit. Essentially, a cockpit chip is a high-performance, highly integrated system-on-a-chip (SoC) specifically designed to meet the growing demands for intelligence, digitalization, and interaction within modern automotive cockpits.

[0046] To address the complexity and high-performance demands of modern intelligent cockpits, cockpit chips generally employ a multi-core architecture, simultaneously supporting diverse services such as navigation, entertainment, and intelligent driving assistance. Different services typically launch in specific scenarios, creating varying requirements for CPU (Central Processing Unit) resource allocation and real-time performance. For example, in intelligent driving scenarios, processing complex algorithms requires substantial computing power. To meet this need, dedicated CPU cores are isolated for intelligent driving services to ensure stable and efficient operation, unaffected by other services. Similarly, in gaming scenarios, dedicated CPU cores are isolated for games with high computing power requirements. When exiting the game, these CPU cores are returned to other services, achieving rational resource allocation and efficient utilization. In some critical service scenarios, real-time performance is extremely demanding. For instance, in emergency situations, safety alarm systems or critical vehicle control functions can be dynamically and exclusively allocated a dedicated CPU core to ensure timely response and avoid delays or malfunctions caused by resource contention.

[0047] Currently, cockpit chips offer some isolation capabilities. For example, the Linux kernel supports isolation, which can isolate CPU processes, peripheral interrupts, work queues, timer ticks, timers, and load balancing CPU selection. However, this isolation can only be implemented at startup by passing parameters and cannot be modified after startup. This means that once the system starts, the isolation strategy cannot be dynamically adjusted according to actual business needs. Furthermore, isolated CPU cores do not support load balancing, which may result in some CPU cores being idle while others are overloaded, affecting the overall performance and stability of the system.

[0048] Another solution involves the cpuset function within cgroups. While it supports setting up dynamic process isolation and resumption on CPU cores, it doesn't support isolating CPU core peripheral interrupts, work queues, ticks, timers, or selecting load-balancing CPUs. Furthermore, this function is heavily dependent on cgroups; the cgroup mechanism must be enabled to use it. This not only increases system complexity and management costs but also limits its application in certain specific environments.

[0049] To address the aforementioned issues, this application provides a method for isolating and exclusively managing processor cores in a Linux system. This method adds a control interface based on the proc file system, and implements the interface's functionality by operating the control interface, thereby achieving dynamic management of isolated CPU cores. The method for isolating and exclusively managing processor cores in a Linux system provided in this application operates during system runtime. Based on real-time business needs, it dynamically isolates and manages multiple CPU cores. When business needs change, it supports dynamically restoring isolated CPU cores and reintegrating them into the system's resource pool for use by other services. This makes the entire functional mechanism more flexible and better able to adapt to the dynamic changes in cockpit operations.

[0050] In one embodiment, a method for isolating and exclusiveizing processor cores in a Linux system is provided, such as... Figure 1 As shown, the method includes:

[0051] Step 101: Based on the control interface in the proc file system, receive a resource isolation configuration request, which includes the identification information of the target processor core;

[0052] Step 102: Based on the resource isolation configuration request, perform resource isolation operation on the target processor core. The resource isolation operation is used to adjust the process scheduling permissions and system resource access permissions of the target processor core.

[0053] Step 103: Based on resource isolation operations, update the system scheduling domain configuration, which is used to determine the scheduling strategy of tasks on the target processor core.

[0054] A control interface is a mechanism in an operating system that allows users or administrators to query or adjust kernel parameters and control system behavior. The proc filesystem is such a control interface; it provides an interface to kernel runtime information and is presented as a virtual filesystem. In the proc filesystem, the control interface exists as a file. In this embodiment, the control interface is used to receive and process resource isolation configuration requests.

[0055] A resource isolation configuration request is an instruction generated based on a business request to dynamically adjust resource isolation policies. It contains information about the object being adjusted, specifically the identifier of the target processor core, to determine which entity should be isolated. The business request is triggered within a specific business scenario. For the business requirements of that scenario, a dedicated processor core (CPU Core) needs to be allocated to exclusively utilize core resources and avoid interference from other tasks. This dedicated processor core is the target processor core.

[0056] The triggering of a business request indicates entry into a business scenario. For example, in an intelligent driving scenario, a business request can be triggered in various ways to enter the intelligent driving scenario. These methods include manual activation by the user, determination based on vehicle status or environmental perception, and system events such as pre-triggered AEB (Autonomous Emergency Braking) or NOA (Navigate on Autopilot) navigation commands. By monitoring and identifying business requests, it is determined whether dynamic isolation is necessary.

[0057] The target processor core can be one of the system's CPU cores that matches the business request, or it can be one of the dynamically isolated cores reserved during system startup that matches the business request. It's important to note that in a business scenario, not all tasks require the target processor core. Therefore, when determining the target processor core corresponding to a business request, it's necessary to identify the core that needs to be isolated and exclusively processed based on the business type within the request. For example, in an intelligent driving scenario, only the most critical, real-time, and safety-critical computationally intensive tasks require the target processor core; I / O processing and non-critical background tasks can run on other cores.

[0058] Therefore, in this embodiment, in response to a business request, the processor core requiring isolation and exclusive processing is determined as the target processor core. Then, based on the control interface in the proc file system, a resource isolation configuration request for managing the target processor core is received. At different runtimes, the corresponding target processor core determined after the business request is triggered may not be the same. For example, the cores that can be dynamically isolated are reserved at system startup as cores 4-7. In this intelligent driving scenario, based on the real-time scheduling strategy, the target processor core allocated for the business scenario is core 4; however, when entering the intelligent driving scenario again, the allocated target processor core may be core 5.

[0059] For the target processor core, which is the dedicated processor core corresponding to the business request, it needs to be isolated from the system's general scheduling pool. This means that the operating system's default scheduler will typically not allocate ordinary processes or threads to run on these cores. Furthermore, it ensures that only explicitly authorized tasks (processes, threads) can run on the target processor core.

[0060] Furthermore, specific tasks related to business needs require processing by non-isolated processor cores. For example, in intelligent driving scenarios, hardware interrupts related to intelligent driving, such as camera data input, radar data input, critical sensor interrupts, and communication bus interrupts, need to be bound to non-intelligent driving dedicated cores to prevent interruption processing from disrupting critical tasks on dedicated cores.

[0061] Process scheduling permissions refer to the processor core's control over task scheduling, including whether a task is allowed to run on that processor core. For example, process affinity settings can be used to restrict tasks to run only on isolated CPU cores.

[0062] System resource access permissions refer to the processor core's ability to access underlying system resources (such as interrupts, work queues, and timers). For example, migrating interrupt handling tasks from an isolated CPU core to a non-isolated CPU core.

[0063] The system receives resource isolation configuration requests through the control interface and parses the target processor core's identification information and isolation operation type from the request. For example, when a user requests to isolate CPU core 0 through the `exclusive_cpus` interface, the system first verifies the validity of the request, and then isolates CPU core 0, including isolating execution process scheduling permissions and system resource access permissions, such as preventing ordinary tasks from being scheduled to this core, or interrupt redirection. After completing resource isolation, the system updates the scheduling domain configuration to ensure that the task scheduling policy is consistent with the isolation state. For example, after isolating CPU core 0, the scheduling domain configuration will exclude this core from load balancing participation, allowing only specific tasks to run on this core. The entire process is implemented through interaction between the control interface and the kernel resource management module, ensuring that the dynamic isolation policy takes effect in real time.

[0064] It should be noted that the above describes the process of the target processor core entering isolation. When the resource isolation configuration request is to delete isolation or restore some functions of an isolated processor core, the above method can also be used. In this case, the resource isolation configuration request represents the reverse process.

[0065] In the method provided in the above embodiments, after determining the target processor core corresponding to the service request, the target processor core and its corresponding information are managed and configured based on the control interface, thereby ensuring that the target processor core becomes the dedicated processor core for the service request. Specifically, the resource isolation configuration request is received through the control interface, and isolation operations such as process scheduling permissions and system resource access permissions are performed on the target processor core based on the request, solving the problem that the CPU resource isolation strategy cannot be dynamically adjusted. For example, when the system detects the start of the intelligent driving service, the specified CPU core is dynamically isolated through the control interface, and the access permissions of ordinary tasks and system resources (such as interrupts) on that core are restricted, thereby providing exclusive computing resources for the intelligent driving service. By updating the system scheduling domain configuration, it is ensured that the isolated processor core only participates in the scheduling of specific tasks, avoiding resource contention. This technical means, combining the dynamic configuration capability of the control interface and the kernel resource management mechanism, realizes the real-time adjustment of the resource isolation strategy, significantly improving the system's resource utilization and the responsiveness of critical services in multiple scenarios. In addition, through the dual mechanism of isolating process scheduling permissions and system resource access permissions, the interference of non-isolated tasks on critical services is completely eliminated, ensuring the stability of the system and the determinism of task execution.

[0066] In one embodiment, the control interface includes an isolation control interface, and the resource isolation configuration request includes a first request received based on the isolation control interface; according to the resource isolation configuration request, performing a resource isolation operation on the target processor core includes:

[0067] Identify the isolation configuration type corresponding to the target processor core in the first request;

[0068] When the isolation configuration type indicates that the target processor core needs to be isolated, the isolation information corresponding to the target processor core is set to the isolation state.

[0069] The isolation control interface is primarily used to add, delete, and view isolated CPU cores. It provides system administrators and related users with the flexible ability to manage CPU core isolation to meet different performance requirements and resource allocation strategies. Through this interface, users can precisely specify which CPU cores should be isolated, thereby optimizing system performance and stability.

[0070] Isolation configuration type refers to the type of isolation operation performed on CPU cores, including adding, deleting, and viewing isolated CPU cores.

[0071] Specifically, the isolation control interface file supports read and write operations. A read operation outputs the current isolated CPU core information, while a write operation modifies this information. The first request received through the isolation control interface determines whether the isolation configuration type is adding, deleting, or viewing isolated CPU cores. If it's determined to be adding an isolated CPU core, the corresponding process is followed to obtain the added CPU core information. The added CPU core is then process-exclusive, and its isolation status is set to isolated, preventing it from executing other tasks. Simultaneously, the process scheduling permissions and system resource access permissions for the added CPU core are determined. If it's determined to be deleting an isolated CPU core, the corresponding process is followed to obtain the deleted CPU core information. The CPU core to be deleted is then process-exclusive, and it is returned to the entire system. If processes still exist in the isolation group, at least one CPU core must remain in the isolated CPU core group; otherwise, CPU core deletion is not allowed.

[0072] In one embodiment, identifying the isolation configuration type corresponding to the target processor core in the first request includes:

[0073] Identify the bitmask corresponding to the target processor core in the isolation control interface file.

[0074] The isolation control interface file maintains a bitmask, where each bit represents a processor core; for example, bit 0 represents CPU core 0, and bit 1 represents CPU core 1. When a user sets this mask by writing to the isolation interface file, the kernel needs to mark the corresponding CPU core as "isolated." Therefore, the isolation configuration type can be determined by identifying the bitmask corresponding to each processor core.

[0075] In one embodiment, such as Figure 2 As shown, the control interface includes an enhanced type control interface, and the resource isolation configuration request includes a second request received based on the enhanced type control interface; according to the resource isolation configuration request, resource isolation operations are performed on the target processor core, including:

[0076] Step 201: Identify the flag bits corresponding to the system resources in the second request;

[0077] Step 202: When the flag corresponding to the system resource is active, redirect the processing request of the system resource to other processor cores besides the target processor core. The system resources include at least one of interrupts, work queues and timers.

[0078] The enhanced isolation type control interface is used to set parameters for enhanced isolation. Enhanced isolation refers to the isolation of system resource access permissions, other than task scheduling, such as isolation control for interrupts, work queues, ticks, timers, and the selection of load balancer processor cores.

[0079] The flag bit corresponding to the system resource indicates whether it belongs to the enhanced isolation type. If the flag bit is active, the system resource belongs to the enhanced type. The processing request for the system resource needs to be redirected to other processor cores to avoid interfering with the isolation environment of the target processor core.

[0080] It should be noted that each system resource corresponds to a flag bit. When performing resource isolation operations based on the second request, each system resource is traversed, and its corresponding flag bit is used to determine whether it is an enhanced isolation type. If it is an enhanced isolation type, and the exclusivity function is enabled, the processing requests on the CPU core in the current isolation group will be exclusively sent to other CPU cores outside the group.

[0081] In the method provided in the above embodiments, the interference of non-isolated tasks and system resources on the target processor core is eliminated by isolating system resource access permissions. For example, in the intelligent driving business scenario, interrupt handling tasks are migrated to non-isolated CPU cores by isolating system resource access permissions, thereby ensuring that isolated CPU cores are only used for intelligent driving algorithm tasks, thus optimizing resource utilization and system stability.

[0082] In one embodiment, the control interface includes an isolation task control interface, and the isolation configuration request includes a third request received based on the isolation task control interface; according to the isolation configuration request, performing resource isolation operations on the target processor core includes:

[0083] Identify the task descriptor of the target task in the third request;

[0084] If a task descriptor is detected, the target task is added to the task list of the target processor core, and then deleted after the target task has been executed.

[0085] The isolated task control interface is used to add tasks to isolated processor cores. In other words, it manages which task types (processes / threads) are authorized tasks and are restricted to running on isolated processor cores. The isolated task control interface enables process scheduling permission isolation, thereby restricting task scheduling to the target processing core. For example, by setting the CPU affinity parameter of a process, ordinary tasks can be prevented from running on isolated CPU cores.

[0086] Specifically, the isolated task control interface maintains a list or data structure to store the task descriptors of the isolated processor cores. When a user writes the PID (Process ID) or TID (Thread ID) of a target task, if the target task's task descriptor is recognized (e.g., the process PID is preceded by an exclamation mark), it is added to the target processor core's task list. By calling an internal function, the CPU affinity between the target task and the target processor core is forced to be set to include only the isolated processor core. This ensures that the task can only run on the isolated processor core. Furthermore, a callback function can be set to automatically remove the target task from the target processor core's task list when it exits.

[0087] The above embodiments, through the isolated task control interface, ensure that only tasks explicitly added to the task list of the isolated processor core can run on that core. When selecting an isolated processor core to run a task, the scheduler checks if the task is in the list. Tasks not in the task list of the isolated processor core (ordinary tasks) cannot be scheduled to run on the isolated processor core. Furthermore, the automatic removal mechanism upon task exit ensures that isolated processor cores are not wasted due to residual task bindings and maintains the accuracy of the task list.

[0088] In one embodiment, after updating the system scheduling domain configuration based on resource isolation operations, the following is also included:

[0089] Receive scheduling mode configuration requests based on the scheduling mode control interface in the proc file system;

[0090] Based on the scheduling mode configuration request, determine the scheduling mode of the target processor core;

[0091] Based on the scheduling mode of the target processor core, adjust the load balancing strategy of the system scheduling domain. The load balancing strategy includes allowing or disallowing the target processor core to participate in global task scheduling.

[0092] The scheduling mode control interface is used to configure whether load balancing is enabled for isolated processor cores. When enabled, the kernel's load balancer considers isolated processor cores, meaning it will attempt to migrate tasks from busy, non-isolated processor cores to idle, isolated ones. Similarly, the load balancer may also attempt to move tasks from isolated processor cores to other isolated ones to balance the load. When disabled, the load balancer treats isolated processor cores like regular processor cores, but isolation may still be partially effective, depending on other settings. Disabling load balancing for isolated processor cores ensures that tasks on isolated cores are not disturbed and prevents non-dedicated tasks from being mistakenly scheduled to isolated cores.

[0093] Specifically, when the target processor core's scheduling mode is set to enable load balancing, the load balancing strategy of the system scheduling domain is adjusted according to the load status of the target processor core.

[0094] The method provided in the above embodiments optimizes resource allocation by dynamically adjusting the load balancing strategy. For example, in low-load scenarios, isolated processor cores are allowed to participate in global scheduling to avoid resource idleness; in high-load scenarios, their participation in scheduling is prohibited to ensure the exclusive use of resources for critical services. This technical approach significantly improves the utilization rate of system resources while taking into account the performance requirements of critical services.

[0095] In one embodiment, the method further includes:

[0096] Before performing resource isolation operations on the target processor core according to the resource isolation configuration request, the parameters of the target processor core are checked to ensure that the first verification result of the parameters of the target processor core is that the verification passes.

[0097] Parameter checking of the target processor core is used to determine the accuracy of the target processor core information, ensuring that only legitimate processor cores are processed. Parameter checking is required whenever a target processor core is configured for isolation.

[0098] In one specific embodiment, interface files are added to the proc filesystem to implement interface functions through file manipulation. These include the isolation control interface file `exclusive_cpus`, the scheduling mode control interface file `exclusive_sched_mod`, the enhanced type control interface file `exclusive_type`, and the isolation task control interface file `exclusive_tasks`. By extending four control interfaces (`exclusive_cpus`, `exclusive_sched_mod`, `exclusive_type`, and `tasks`) into the Linux kernel's proc filesystem, dynamic management of CPU resources is achieved. Users trigger the kernel module's configuration parsing and resource adjustment logic by manipulating these interface files.

[0099] For example, when a user adds an isolated CPU core via the `exclusive_cpus` interface, the system first verifies the configuration's validity, then implements process exclusivity and enhanced isolation (such as interrupt redirection) on the newly added CPU core, and rebuilds the scheduling domain to update the scheduling policy. Simultaneously, through the enhanced type control interface file `exclusive_type`, users can selectively isolate resources such as interrupts and work queues, further purifying the isolation environment. When business requirements change, users can dynamically reclaim isolated resources through the `exclusive_cpus` or `tasks` interfaces, or adjust the load balancing mode through `exclusive_sched_mod`, thereby achieving optimal resource allocation and high system stability.

[0100] The specific process is as follows: Figure 3 As shown, a specific method of isolation and exclusion includes:

[0101] (1) Isolate CPU control interface:

[0102] S301: The control interface file supports read and write operations. Read operations will output the current isolated CPU information, and write operations will modify the isolated CPU information.

[0103] S302. Perform parameter checks, including determining whether the written CPU information is valid, and whether it is a new or deleted CPU relative to the previous CPU information, and perform different processing based on different judgment results.

[0104] S303. If it is determined that an isolated CPU has been added, the corresponding process is followed to obtain the information of the added CPU.

[0105] S304. Exclusively process the added CPU so that it no longer executes other tasks.

[0106] S305. Exclusivity of enhanced functions for the added CPU, the specific exclusion content depends on the exclusion configuration.

[0107] S306. If it is determined that an isolated CPU has been deleted, the corresponding process is followed to obtain the information of the deleted CPU.

[0108] S307. Exclusively process the CPU to be deleted and return it to the system. If processes still exist in the isolation group, ensure that at least one CPU remains in the isolation CPU group; otherwise, CPU deletion is not permitted.

[0109] S308. Restore the previously enhanced exclusivity function.

[0110] S309. Re-establish the scheduling domain.

[0111] (2) Scheduling mode control:

[0112] S310: The control interface file supports read and write operations. Read operations will output scheduling mode configuration information, and write operations will modify the scheduling mode.

[0113] S311. Perform parameter checks. If the setting mode is the same as the previous mode, ignore and exit.

[0114] S312. If there are isolated CPUs in the current isolation group, the scheduling domain will be re-established according to the setting mode.

[0115] S313, Record the scheduling mode status.

[0116] (3) Add exclusive type control:

[0117] S314. The control interface file supports read and write operations. Read operations will output enhanced exclusive type configuration information, and write operations will modify the enhanced exclusive type.

[0118] S315. Perform parameter checks. If there are no isolated CPUs in the current isolation group, save the configuration values ​​and exit. If there are isolated CPUs, check if the configuration information of a certain enhancement type has changed. If it has changed, perform subsequent exclusion processing; otherwise, ignore the type.

[0119] S316. Perform dynamic exclusion or recovery operations based on changes in configuration type information.

[0120] S317. Record the exclusive type status information.

[0121] (4) Adding isolation tasks:

[0122] S318. The control interface file supports read and write operations. Read operations will output the configured process information, and exited processes will be automatically deleted. During write operations, it will check whether there is an exclamation mark (!) in front of the process PID. If there is, the added process will be deleted; otherwise, a new process will be added.

[0123] S319. For write operations, the CPU affinity of the process is reset based on the addition or removal of the CPU.

[0124] like Figure 4 As shown, the implementation of enhanced isolation includes:

[0125] S401. Traverse all enhanced exclusive types;

[0126] S402. For each enhanced exclusive type, perform a judgment; if the state has not changed, ignore it.

[0127] S403. The procedure to be followed when the interrupt type flag is active;

[0128] S404, Dynamically adjust interrupted housekeeping;

[0129] S405. If the exclusivity function is enabled, interrupts on isolated processor cores in the current isolated processor core set will be exclusively sent to other non-isolated processor cores.

[0130] S406. The process to be followed when the work queue type is active;

[0131] S407, Dynamically adjust work queues in housekeeping;

[0132] S408. Based on the isolation function switch status, determine whether subsequent unbound type wq includes isolated processor cores in the current isolated processor core set when selecting processor cores;

[0133] S409. The procedure followed when the tick type flag is active;

[0134] S410, Dynamic adjustment of tick housekeeping;

[0135] S411. Based on the isolation function switch status, determine whether the timer performs a tick operation or uses wq to simulate a tick;

[0136] S412. The process followed when the timer type flag is active;

[0137] S413, Dynamically adjust timer housekeeping;

[0138] S414. Based on the isolation function switch status, determine whether to enable the detection switch of the isolated processor core in the current isolated processor core set;

[0139] S315. The procedure to be followed when the load balancing CPU selection type takes effect;

[0140] S316. Based on the isolation function switch status, when selecting a load balancing CPU for execution, determine whether to select an isolated processor core from the isolated processor core set.

[0141] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0142] Based on the same inventive concept, this application also provides an isolation and exclusion device for processor cores in a Linux system. The solution provided by this device is similar to the solution described in the above method. Therefore, the specific limitations of one or more embodiments of the isolation and exclusion device for processor cores in a Linux system provided below can be found in the limitations of the isolation and exclusion method for processor cores in a Linux system described above, and will not be repeated here.

[0143] In one embodiment, such as Figure 5 As shown, the isolation and exclusion device for the processor core in the Linux system includes an information acquisition module 501, an isolation processing module 502, and an update module 503, wherein:

[0144] The information acquisition module 501 is used to receive resource isolation configuration requests based on the control interface in the proc file system. The resource isolation configuration requests include the identification information of the target processor core.

[0145] The isolation processing module 502 is used to perform resource isolation operations on the target processor core according to the resource isolation configuration request. The resource isolation operations are used to adjust the process scheduling permissions and system resource access permissions of the target processor core.

[0146] The update module 503 is used to update the system scheduling domain configuration based on resource isolation operations. The system scheduling domain configuration is used to determine the scheduling policy of tasks on the target processor core.

[0147] In one possible implementation, the control interface includes an isolation control interface, and the resource isolation configuration request includes a first request received based on the isolation control interface; the isolation processing module 502 is specifically used for:

[0148] Identify the isolation configuration type corresponding to the target processor core in the first request;

[0149] When the isolation configuration type indicates that the target processor core needs to be isolated, the isolation information corresponding to the target processor core is set to the isolation state.

[0150] In one possible implementation, the isolation processing module 502 is specifically used for:

[0151] Identify the bitmask corresponding to the target processor core in the isolation control interface file.

[0152] In one possible implementation, the control interface includes an enhanced type control interface, and the resource isolation configuration request includes a second request received based on the enhanced type control interface; the isolation processing module 502 is specifically used for:

[0153] Identify the flag bits corresponding to the system resources in the second request;

[0154] When the flag corresponding to the system resource is active, the processing request for the system resource is redirected to a processor core other than the target processor core. The system resource includes at least one of interrupts, work queues, and timers.

[0155] In one possible implementation, the control interface includes an isolation task control interface, and the isolation configuration request includes a third request received based on the isolation task control interface; the isolation processing module 502 is specifically used for:

[0156] Identify the task descriptor of the target task in the third request;

[0157] If a task descriptor is detected, the target task is added to the task list of the target processor core, and then deleted after the target task has been executed.

[0158] In one possible implementation, update module 503 is specifically used for:

[0159] Receive scheduling mode configuration requests based on the scheduling mode control interface in the proc file system;

[0160] Based on the scheduling mode configuration request, determine the scheduling mode of the target processor core;

[0161] Based on the scheduling mode of the target processor core, adjust the load balancing strategy of the system scheduling domain. The load balancing strategy includes allowing or disallowing the target processor core to participate in global task scheduling.

[0162] In one possible implementation, update module 503 is specifically used for:

[0163] When the target processor core's scheduling mode is set to enable load balancing, the load balancing strategy of the system scheduling domain is adjusted according to the load status of the target processor core.

[0164] In one possible implementation, the isolation processing module 502 is also used for:

[0165] Before performing resource isolation operations on the target processor core according to the resource isolation configuration request, the parameters of the target processor core are checked to ensure that the first verification result of the parameters of the target processor core is that the verification passes.

[0166] Each module in the aforementioned isolation and exclusion device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0167] Figure 6 A schematic diagram of the structure of the computer device provided in this application. Figure 6 As shown, the computer device 60 provided in this embodiment includes at least one processor 601 and a memory 602. Optionally, the device 60 further includes a communication component 603. The processor 601, memory 602, and communication component 603 are connected via a bus 604.

[0168] In a specific implementation, at least one processor 601 executes computer execution instructions stored in memory 602, causing at least one processor 601 to perform the above-described method.

[0169] The specific implementation process of processor 601 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0170] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.

[0171] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0172] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0173] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0174] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the above-described method.

[0175] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0176] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.

[0177] The division of units is merely a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0178] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0179] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0180] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0181] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0182] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A method for processor core isolation exclusion in a Linux system, the method comprising: The method includes: Based on the control interface in the proc file system, a resource isolation configuration request is received, which includes the identification information of the target processor core; Based on the resource isolation configuration request, a resource isolation operation is performed on the target processor core, the resource isolation operation being used to adjust the process scheduling permissions and system resource access permissions of the target processor core; Based on the resource isolation operation, the system scheduling domain configuration is updated, which is used to determine the scheduling strategy of tasks on the target processor core.

2. The method of claim 1, wherein, The control interface includes an isolation control interface, and the resource isolation configuration request includes a first request received based on the isolation control interface. The step of performing resource isolation operations on the target processor core according to the resource isolation configuration request includes: Identify the isolation configuration type corresponding to the target processor core mentioned in the first request; When the isolation configuration type indicates that the target processor core needs to be isolated, the isolation information corresponding to the target processor core is set to an isolated state.

3. The method according to claim 2, characterized in that, The step of identifying the isolation configuration type corresponding to the target processor core in the first request includes: Identify the bitmask corresponding to the target processor core in the file of the isolation control interface.

4. The method according to claim 1, characterized in that, The control interface includes an enhanced type control interface, and the resource isolation configuration request includes a second request received based on the enhanced type control interface. The step of performing resource isolation operations on the target processor core according to the resource isolation configuration request includes: Identify the flag bits corresponding to the system resources in the second request; When the flag corresponding to the system resource is active, the processing request for the system resource is redirected to a processor core other than the target processor core. The system resource includes at least one of interrupts, work queues, and timers.

5. The method according to claim 1, characterized in that, The control interface includes an isolation task control interface, and the isolation configuration request includes a third request received based on the isolation task control interface; The step of performing resource isolation operations on the target processor core according to the isolation configuration request includes: Identify the task descriptor of the target task in the third request; Upon recognition of the task descriptor, the target task is added to the task list of the target processor core, and deleted after the target task has been executed.

6. The method according to claim 1, characterized in that, The process of updating the system scheduling domain configuration based on the resource isolation operation also includes: Receive scheduling mode configuration requests based on the scheduling mode control interface in the proc file system; Based on the scheduling mode configuration request, determine the scheduling mode of the target processor core; Based on the scheduling mode of the target processor core, the load balancing strategy of the system scheduling domain is adjusted, and the load balancing strategy includes allowing or disabling the target processor core to participate in global task scheduling.

7. The method according to claim 6, characterized in that, The step of adjusting the load balancing strategy of the system scheduling domain according to the scheduling mode of the target processor core includes: When the target processor core's scheduling mode is set to enable load balancing, the load balancing strategy of the system scheduling domain is adjusted according to the load status of the target processor core.

8. The method according to any one of claims 1-7, characterized in that, The method further includes: Before performing resource isolation operations on the target processor core according to the resource isolation configuration request, the parameters of the target processor core are checked, and the first verification result of the parameters of the target processor core is determined to be a successful verification.

9. An isolation and exclusivity device for processor cores in a Linux system, characterized in that, The method includes: The information acquisition module is used to receive resource isolation configuration requests based on the control interface in the proc file system. The resource isolation configuration requests include the identification information of the target processor core. An isolation processing module is used to perform resource isolation operations on the target processor core according to the resource isolation configuration request. The resource isolation operations are used to adjust the process scheduling permissions and system resource access permissions of the target processor core. An update module is used to update the system scheduling domain configuration based on the resource isolation operation. The system scheduling domain configuration is used to determine the scheduling strategy of tasks on the target processor core.

10. A computer device, characterized in that, include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the method as described in any one of claims 1 to 8.

Images