Load store circuits, processors, and electronic devices

Abstract

The disclosure provides a load store circuit, a processor and an electronic device, and relates to the technical field of computers.The load store circuit comprises an instruction scheduling module, an address generation module, a memory access execution module, a data adjustment module and a buffer module, wherein: the instruction scheduling module is configured to receive a memory access instruction corresponding to a current thread to be executed, and analyze instruction control data corresponding to the memory access instruction; the data adjustment module is configured to determine an access target corresponding to the memory access instruction according to general address data, adjust the instruction control data based on the access target, and obtain control optimization data; the address generation module is configured to generate a target access address corresponding to the memory access instruction by using the control optimization data and the general address data; the memory access execution module is configured to execute a memory access operation on the access target according to the target access address; and the general address buffer in the buffer module is configured to store the general address data.The scheme enables the memory access instruction based on the general address to be completed independently on the hardware side.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and more specifically, to a loading and storage circuit, a processor, and an electronic device. Background Technology

[0002] In multi-threaded parallel processing architectures, Load Store Units (LSUs) are typically used to execute memory access operations for each thread and control access to different memory spaces based on address information. To unify pointer semantics and reduce programming complexity, related technologies have introduced Unified Virtual Addressing (UVA) mechanisms, allowing pointers used in programs to be represented using generic addresses that do not distinguish between memory spaces. However, since generic addresses themselves do not carry memory space information, the memory space to which the generic address belongs still needs to be determined during memory access. Related technologies typically place this determination process on the software side, where the software parses the generic address and generates memory access instructions with explicit access space semantics before handing them over to the LSU for execution, thus increasing software overhead. Summary of the Invention

[0003] The purpose of this disclosure is to provide a loading memory circuit, processor, and electronic device that enables memory access instructions in general address form to be completed on the hardware side without software preprocessing, thereby reducing software overhead and improving memory access efficiency.

[0004] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0005] According to a first aspect of the present disclosure, a load-memory circuit is provided, comprising an instruction scheduling module, an address generation module, and a memory access execution module connected in sequence, and further comprising a data adjustment module connected to the address generation module, wherein: the instruction scheduling module is configured to receive a memory access instruction corresponding to a currently pending thread and parse instruction control data corresponding to the memory access instruction; the data adjustment module is configured to determine the access target corresponding to the memory access instruction based on general address data, and adjust the instruction control data based on the access target to obtain control optimization data; the address generation module is configured to generate a target access address corresponding to the memory access instruction using the control optimization data and the general address data; the memory access execution module is configured to perform a memory access operation on the access target according to the target access address; wherein the load-memory circuit further comprises a buffer module, the buffer module including a general address buffer, for caching the general address data corresponding to the memory access instruction input to the data adjustment module.

[0006] In some example embodiments of this disclosure, based on the foregoing scheme, the data adjustment module is used to: determine the access target corresponding to the memory access instruction according to the preset flag bit in the general address data; wherein, the access target includes either a first type of memory or a second type of memory, and the first type of memory and the second type of memory respectively correspond to different values ​​of the preset flag bit.

[0007] In some example embodiments of this disclosure, based on the foregoing scheme, the currently executed thread includes multiple parallel threads, the memory access instruction is multiple memory access instructions, and the parallel threads correspond one-to-one with the memory access instructions; the first type of memory is global memory, and the second type of memory is private memory; at least one of the multiple memory access instructions is a load instruction; the load instruction includes at least one of a global memory load instruction whose target is the global memory and a private memory load instruction whose target is the private memory; The data adjustment module is configured to perform at least one of the following operations: using the global memory load instruction as a valid instruction to adjust the instruction control data to obtain first load control data; using the private memory load instruction as a valid instruction to adjust the instruction control data to obtain second load control data; wherein the first load control data and the second load control data correspond to different memory access operations.

[0008] In some example embodiments of this disclosure, based on the foregoing scheme, the instruction control data includes operation type data; the data adjustment module is configured to: take the global memory load instruction as a valid instruction, generate a first load activity mask for indicating the execution status of each load instruction; wherein, the identifier bit corresponding to the global memory load instruction in the first load activity mask is a valid identifier; adjust the operation type data corresponding to each global memory load instruction to a global load control field to obtain first load adjustment data, and use the first load adjustment data and the first load activity mask as the first load control data.

[0009] In some example embodiments of this disclosure, based on the foregoing scheme, the instruction control data further includes a task identifier; the data adjustment module is configured to: take the private memory loading instruction as a valid instruction and generate a second loading activity mask for indicating the execution status of each loading instruction; wherein, the identifier bit corresponding to the private memory loading instruction in the second loading activity mask is a valid identifier; adjust the operation type data corresponding to the private memory loading instruction to a private loading control field to obtain second loading adjustment data; use the task identifier to obtain the private memory address corresponding to each private memory loading instruction, and use the second loading adjustment data, the second loading activity mask, and the private memory address as the second loading control data.

[0010] In some example embodiments of this disclosure, based on the foregoing scheme, the private memory address is pre-stored in the private address storage module; the data adjustment module is used to: send the task identifier corresponding to each of the private memory loading instructions to the private address storage module; query the target private memory address corresponding to each of the private memory loading instructions according to the task identifier, and return the target private memory address to the data adjustment module.

[0011] In some example embodiments of this disclosure, based on the foregoing scheme, the address generation module is configured to: generate a global memory load address corresponding to each of the global memory load instructions using the first load control data and the general address data; and generate a private memory load address corresponding to each of the private memory load instructions using the second load control data and the general address data.

[0012] In some example embodiments of this disclosure, based on the foregoing scheme, the loading memory circuit determines the execution status of the loading instruction through a pre-configured barrier counting module; the memory access operation includes a first loading operation and a second loading operation; the memory access execution module is configured to: perform the first loading operation on the global memory according to the global memory loading address and send a count decrement signal to the barrier counting module; perform the second loading operation on the private memory according to the private memory loading address and send the count decrement signal to the barrier counting module; wherein, the preset count value of the barrier counting module is a first value, and when the count value decrements to a preset second value, it is determined that the memory access instructions corresponding to the multiple parallel threads have been executed.

[0013] In some example embodiments of this disclosure, based on the foregoing scheme, the buffer module further includes a write data buffer for caching data written to the target access address; The loading and storing circuit further includes a preprocessing module, one end of which is connected to the write data buffer and the other end of which is connected to the memory access execution module. The preprocessing module is used to obtain the write data required by the memory access execution module during instruction execution from the write data buffer.

[0014] In some example embodiments of this disclosure, based on the foregoing scheme, the memory access instruction is a plurality of memory access instructions, and at least one of the plurality of memory access instructions is a write instruction; the write instruction includes at least one of a global memory write instruction whose target is global memory and a private memory write instruction whose target is private memory. The data adjustment module is configured to: use the global memory write instruction as a valid instruction to perform a first adjustment on the instruction control data to obtain first write control data; use the private memory write instruction as a valid instruction to perform a second adjustment on the instruction control data to obtain second write control data; wherein the first write control data and the second write control data correspond to different memory access operations.

[0015] In some example embodiments of this disclosure, based on the foregoing scheme, the address generation module is configured to: generate a global memory write address corresponding to each of the global memory write instructions using the first write control data and the general address data; and generate a private memory write address corresponding to each of the private memory write instructions using the second write control data and the general address data.

[0016] In some example embodiments of this disclosure, based on the foregoing scheme, the memory access operation includes a first write operation and a second write operation; the memory access execution module is configured to: obtain global memory write data corresponding to each of the global memory write instructions through the preprocessing module, and perform the first write operation on the global memory according to the global memory write address and the global memory write data; obtain private memory write data corresponding to each of the private memory write instructions through the preprocessing module, and perform the second write operation on the private memory according to the private memory write address and the private memory write data.

[0017] In some example embodiments of this disclosure, based on the foregoing scheme, the memory access execution module is configured to: send the first thread number corresponding to each of the global memory write instructions to the preprocessing module; the preprocessing module is configured to: determine the global memory write data corresponding to each of the global memory write instructions according to the first thread number, and return the global memory write data to the memory access execution module.

[0018] According to a second aspect of the present disclosure, an instruction processing method is provided, executed by a loading memory unit. The method includes: an instruction scheduling module receiving a memory access instruction corresponding to a currently pending thread and parsing instruction control data corresponding to the memory access instruction; a data adjustment module determining an access target corresponding to the memory access instruction based on general address data, and adjusting the instruction control data based on the access target to obtain control optimization data; an address generation module generating a target access address corresponding to the memory access instruction using the control optimization data and the general address data; and a memory access execution module performing a memory access operation on the access target based on the target access address; wherein the general address data corresponding to the memory access instruction input to the data adjustment module is cached in the general address buffer of the buffer module.

[0019] According to a third aspect of the present disclosure, a processor is provided, the processor including the load memory circuitry as described in the first aspect.

[0020] According to a fourth aspect of the present disclosure, a chip is provided, the chip including a processor as described in the third aspect.

[0021] According to a fifth aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory storing computer-readable instructions that, when executed by the processor, implement the instruction processing method as described in the second aspect.

[0022] The technical solutions provided in this disclosure may have the following beneficial effects: In the example embodiments of this disclosure, the load-memory circuit, on the one hand, for memory access instructions in the form of general address, determines the access target corresponding to each memory access instruction based on general address data, and adjusts the instruction control data accordingly. This allows the memory access instruction to complete the distinction of the access target before entering the address generation module, thereby avoiding the software-side processing burden caused by relying on the software side to parse the general address and generate a semantically clear access space, as is done in related technologies. On the other hand, the address generation module combines control optimization data and general address data to generate the target access address, ensuring that the generation process of the target access address is based on the completed access target distinction result. Furthermore, the memory access execution module performs a memory access operation on the access target based on the target access address, ensuring that the memory access execution behavior is consistent with the previous access target determination result. Additionally, the general address data is cached through the general address buffer in the buffer module, enabling the data adjustment module and the address generation module to process based on stable address input. This reduces the need for repeated acquisition of general address data in multi-module processing, improving the overall processing flow of the load-memory circuit in multi-threaded parallel memory access scenarios. Therefore, it has the advantages of reducing software overhead and improving memory access processing efficiency.

[0023] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0024] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0025] Figure 1 The schematic diagram illustrates the composition of a load storage circuit according to some embodiments of the present disclosure.

[0026] Figure 2 A schematic diagram illustrating the composition of a load storage circuit according to other embodiments of the present disclosure is shown.

[0027] Figure 3 The schematic diagram illustrates a flowchart of an instruction processing method according to some embodiments of the present disclosure.

[0028] Figure 4 The schematic diagram illustrates the structural schematic of a computer system of an electronic device according to some embodiments of the present disclosure.

[0029] Figure 5A schematic diagram of a computer-readable storage medium according to some embodiments of the present disclosure is shown.

[0030] In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts. Detailed Implementation

[0031] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this specification. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this specification as detailed in the appended claims.

[0032] The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of this specification. The singular forms “a,” “the,” and “the” as used in this specification and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0033] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be more thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art.

[0034] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0035] Furthermore, the accompanying drawings are for illustrative purposes only and are not necessarily drawn to scale. The block diagrams shown in the drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0036] In this example embodiment, a loading and storage circuit is first provided. Figure 1 The diagram illustrates the composition of a load storage circuit according to some embodiments of the present disclosure. The load storage circuit is a circuit implementation of a load storage unit (LSU).

[0037] refer to Figure 1 As shown, the load memory circuit 100 may include an instruction scheduling module 110, an address generation module 120, and a memory access execution module 130 connected in sequence, as well as a buffer module 150 and a data adjustment module 140 connected to the address generation module 120. Specifically, the instruction scheduling module 110 can receive the memory access instruction corresponding to the currently executing thread and parse the instruction control data corresponding to the memory access instruction.

[0038] Specifically, the instruction scheduling module 110 can represent a functional module for receiving memory access instructions corresponding to the currently pending thread and parsing the memory access instructions to obtain corresponding instruction control data. The memory access instruction can represent an instruction type used to trigger a load or write operation on the memory space; it corresponds to a thread and instructs the load memory circuit 100 to perform the corresponding memory access operation on the target memory space. The instruction control data can represent comprehensive control information parsed from the memory access instruction, characterizing the execution attributes and control behavior of the memory access instruction in the load memory circuit 100. This information may include a task identifier to identify the execution task to which the memory access instruction belongs and an operation type field to indicate the access target.

[0039] The data adjustment module 140 can be used to determine the access target corresponding to the memory access instruction based on the general address data, and adjust the instruction control data based on the access target to obtain control optimization data.

[0040] Specifically, the data adjustment module 140 can represent a functional module for processing memory access instructions based on general address data. It determines the access target corresponding to the memory access instruction and adjusts the instruction control data according to the access target to generate control information suitable for subsequent address generation and memory access execution. The data adjustment module 140 can interact with the address generation module 120. General address data can represent address information in a general pointer format, and this address information does not carry a space attribute field for explicitly indicating the memory space type, thus requiring the load memory circuit 100 to determine the corresponding access target based on this address information during execution. The access target can represent the actual memory space type corresponding to the memory access instruction, determined according to the general address data, and is used to indicate the memory space that the memory access instruction should access during subsequent execution. Control optimization data can represent the control information obtained by the data adjustment module 140 after adjusting the instruction control data based on the access target. It is used to indicate the processing method of the memory access instruction in the address generation module 120 and the memory access execution module 130, and serves as the control basis for generating the target access address.

[0041] Address generation module 120 can be used to generate the target access address corresponding to the memory access instruction using control optimization data and general address data.

[0042] Specifically, the address generation module 120 can represent a functional module for performing address calculation processing on memory access instructions based on control optimization data and general address data. It generates a target access address corresponding to the memory access instruction to support the subsequent memory access execution module 130 in performing the memory access operation. The target access address can represent address information calculated by the address generation module 120 based on control optimization data and general address data, indicating the actual access location of the memory access instruction. This address information corresponds to the access target and is used to instruct the memory access execution module 130 to complete the corresponding memory access operation. For example, the target access address can be a 32-bit, 40-bit, 48-bit address or an address with other configured widths; this embodiment does not limit its bit width or format.

[0043] The memory access execution module 130 can be used to perform memory access operations on the access target based on the target access address.

[0044] Specifically, the memory access execution module 130 can represent a functional module for receiving a target access address and performing memory access behavior on the corresponding access target based on the target access address. The memory access operation can represent a storage access behavior performed on the access target based on the target access address, which is used to complete at least one of the data loading or data writing behavior of the storage space corresponding to the memory access instruction during the execution phase.

[0045] Furthermore, the buffer module 150 in the load storage circuit 100 includes a general address buffer 151, which is used to cache the general address data corresponding to the memory access instruction input to the data adjustment module 140.

[0046] Specifically, buffer module 150 can represent a cache function module disposed in the load memory circuit 100, which is used to temporarily store and manage general address data involved in the memory access instruction processing and data related to the memory access operation. General address buffer 151 can represent a storage unit disposed in buffer module 150, which is used to cache general address data corresponding to the memory access instruction and provide general address data to data adjustment module 140 to support access target determination and subsequent address generation processing.

[0047] During the operation of the load memory circuit 100, through the cooperation between the instruction scheduling module 110, address generation module 120, memory access execution module 130, data adjustment module 140 and buffer module 150, the memory access instruction using general address data can complete the determination of the access target, the adjustment of instruction control data and the generation of the target access address within the load memory circuit 100 on the hardware side, and execute the corresponding memory access operation accordingly.

[0048] In the example embodiments of this disclosure, the load-memory circuit, on the one hand, for memory access instructions in the form of general address, determines the access target corresponding to each memory access instruction based on general address data, and adjusts the instruction control data accordingly. This allows the memory access instruction to complete the distinction of the access target before entering the address generation module, thereby avoiding the software-side processing burden caused by relying on the software side to parse the general address and generate a semantically clear access space, as is done in related technologies. On the other hand, the address generation module combines control optimization data and general address data to generate the target access address, ensuring that the generation process of the target access address is based on the completed access target distinction result. Furthermore, the memory access execution module performs a memory access operation on the access target based on the target access address, ensuring that the memory access execution behavior is consistent with the previous access target determination result. Additionally, the general address data is cached through the general address buffer in the buffer module, enabling the data adjustment module and the address generation module to process based on stable address input. This reduces the need for repeated acquisition of general address data in multi-module processing, improving the overall processing flow of the load-memory circuit in multi-threaded parallel memory access scenarios. Therefore, it has the advantages of reducing software overhead and improving memory access processing efficiency.

[0049] The loading and storage circuit in this example embodiment will now be further described.

[0050] In an example embodiment of this disclosure, reference is made to Figure 2 As shown, the instruction scheduling module 110 receives multiple memory access instructions, and the general address data cached in the general address buffer 151 is distributed by the upstream instruction distribution module 210. The upstream instruction distribution module 210 can be used to collect and distribute memory access instructions from the processor front-end or computing unit, and synchronously transmit the general address data corresponding to each memory access instruction to the load memory circuit 100 to support subsequent processing of the memory access instructions. For example, the upstream instruction distribution module can be an MEB (Memory Execution Bridge), etc.

[0051] Furthermore, when performing a memory access operation, the memory access execution module 130 loads or writes data to the target storage unit 220. For example, when the memory access operation is a data loading operation, the memory access execution module 130 can read data corresponding to the target access address from the target storage unit 220; when the memory access operation is a data writing operation, the memory access execution module 130 can store the written data to the corresponding storage location in the target storage unit 220. The target storage unit 220 may include global memory and private memory.

[0052] In addition, in other embodiments of this disclosure, the instruction scheduling module 110 can also be used to receive execution feedback information from the memory access execution module 130, determine the execution progress and completion status of the memory access instruction, and trigger the reception and scheduling of subsequent memory access instructions when it is determined that the memory access instruction has been completed.

[0053] In some embodiments, the specific process by which the data adjustment module 140 determines the access target corresponding to each memory access instruction based on the general address data includes: determining the access target corresponding to the memory access instruction based on the preset flag bit in the general address data; wherein, the access target includes either the first type of memory or the second type of memory, and the first type of memory and the second type of memory correspond to different values ​​of the preset flag bit.

[0054] Specifically, the first type of memory and the second type of memory can be other suitable memory forms such as global memory, private memory, or shared memory. The preset flag bit can represent a specific field set in the general address data, used to distinguish the access target type corresponding to the general address data. Different preset flag bit values ​​are used to indicate global memory or private memory, respectively, to support the data adjustment module 140 in determining the access target of the memory access instruction. For example, for 64-bit general address data, the preset flag bit can be set in the bit[63:62] field. Of course, in other embodiments of this disclosure, the preset flag bit can also be set in other fields of the general address data.

[0055] The aforementioned data adjustment module determines the access target corresponding to each memory access instruction based on the preset flag bit in the general address data. This enables the memory loading circuit to complete the access target determination for memory access instructions using general address data on the hardware side, thereby avoiding reliance on the software side for address parsing and classification. This simplifies the processing flow before the memory access instruction enters the execution stage and reduces software overhead.

[0056] Furthermore, the data adjustment module 140 determines the access target corresponding to each memory access instruction based on the preset flag bits in the general address data, including: when the preset flag bit in the general address data is a first flag value, determining that the access target of the memory access instruction corresponding to the general address data is global memory; when the preset flag bit in the general address data is a second flag value, determining that the access target of the memory access instruction corresponding to the general address data is private memory. The first flag value is different from the second flag value.

[0057] The first identifier value can represent a preset identifier value used to indicate that the access target is global memory; the second identifier value can represent a preset identifier value used to indicate that the access target is private memory. For example, when the preset identifier is set to a length of 2 bits, the first identifier value can be 2'b00 and the second identifier value can be 2'b10; of course, in other embodiments of this disclosure, the first identifier value and the second identifier value can also adopt other combinations of values ​​different from the above examples.

[0058] The following is a detailed description of the instruction execution process in the loading memory circuit when the memory access instruction is a load instruction, in an exemplary embodiment.

[0059] Furthermore, the currently executing threads include multiple parallel threads, the memory access instructions are multiple memory access instructions, and there is a one-to-one correspondence between parallel threads and memory access instructions; the first type of memory is global memory, and the second type of memory is private memory; at least one of the multiple memory access instructions is a load instruction; the load instructions include at least one of a global memory load instruction whose target is global memory and a private memory load instruction whose target is private memory.

[0060] In this context, a parallel thread can represent a basic execution entity in the processor used to execute program instructions. In a multi-threaded parallel execution scenario, each parallel thread has an independent execution context and is associated with a memory access instruction to characterize the memory access operation that the parallel thread needs to perform in the current execution phase. Global memory can represent a storage space in the processor system that can be accessed by multiple parallel threads. It is used to store data shared among multiple parallel threads and serves as a type of access target for memory access instructions for the load-memory circuit 100 to perform memory access operations. Private memory can represent a logical storage space that corresponds one-to-one with a parallel thread and is used to store data that is only visible to the corresponding parallel thread.

[0061] The data adjustment module 140 can be used to: use a global memory load instruction as a valid instruction to adjust the instruction control data to obtain first load control data; and use a private memory load instruction as a valid instruction to adjust the instruction control data to obtain second load control data. The first and second load control data correspond to different memory access operations.

[0062] Here, a load instruction can represent a type of memory access instruction used to retrieve data from a target memory space. A global memory load instruction can represent a load instruction whose target is determined to be global memory among multiple memory access instructions corresponding to multiple parallel threads, used to retrieve data from global memory. A private memory load instruction can represent a load instruction whose target is determined to be private memory among multiple memory access instructions corresponding to multiple parallel threads, used to retrieve data from the private memory corresponding to the parallel thread. A valid instruction can represent a load instruction selected to participate in memory access processing during the current instruction execution process, and its corresponding execution status is marked as executable. A first adjustment can represent a control information adjustment process performed on the instruction control data corresponding to a load instruction whose target is global memory. The first load control data can represent the set of control information obtained from the first adjustment, used to indicate the memory access operation mode for the global memory load instruction. A second adjustment can represent another control information adjustment process performed on the instruction control data corresponding to a load instruction whose target is private memory.

[0063] In this embodiment, by distinguishing loading instructions into global memory loading instructions and private memory loading instructions, and having the data adjustment module perform the first and second adjustments on the corresponding instruction control data as valid instructions respectively, loading instructions for different access targets can form independent loading control data for each other. This allows the memory access operations of loading instructions to be processed differently according to the differences in access targets, which is beneficial to maintaining the orderliness of the memory access processing flow.

[0064] Furthermore, during instruction execution, the instruction control data corresponding to each memory access instruction is parsed and generated by the instruction scheduling module 110. The generated instruction control data is then sent to the address generation module 120 and simultaneously provided to the data adjustment module 140. After receiving the instruction control data, the data adjustment module 140 selectively processes the instruction control data according to the access target corresponding to the load instruction. Specifically, the data adjustment module 140 can prioritize adjusting the instruction control data corresponding to global memory load instructions whose access target is global memory, generating first load control data, and then sending the first load control data to the address generation module 120 after the adjustment, so that the address generation module 120 can generate the access address corresponding to the global memory load instruction based on the first load control data. Then, the instruction control data corresponding to private memory load instructions whose access target is private memory is adjusted again, generating second load control data, and then sending the second load control data to the address generation module 120 after the adjustment, so that the address generation module 120 can generate the access address corresponding to the private memory load instruction based on the second load control data.

[0065] Alternatively, the data adjustment module 140 may first adjust the instruction control data corresponding to the private memory load instruction whose access target is private memory, generate second load control data, and send the second load control data to the address generation module 120 after the adjustment is completed, so that the address generation module 120 generates the access address corresponding to the private memory load instruction based on the second load control data. Then, it may adjust the instruction control data corresponding to the global memory load instruction whose access target is global memory, generate first load control data, and send the first load control data to the address generation module 120 after the adjustment is completed, so that the address generation module 120 generates the access address corresponding to the global memory load instruction based on the first load control data.

[0066] In other words, the data adjustment module generates corresponding load control data for different access targets and sends it to the address generation module after each load control data is generated. This allows the address generation module to generate corresponding access addresses based on different load control data, thus ensuring that different load control data correspond to different memory access operations.

[0067] In this embodiment of the disclosure, the instruction control data includes operation type data. The specific process of adjusting the instruction control data by the data adjustment module 140, taking the global memory load instruction as a valid instruction, to obtain the first load control data includes: taking the global memory load instruction as a valid instruction and generating a first load activity mask to indicate the execution status of each load instruction; wherein, the identifier bit corresponding to the global memory load instruction in the first load activity mask is a valid identifier; adjusting the operation type data corresponding to each global memory load instruction to a global load control field to obtain the first load adjustment data, and using the first load adjustment data and the first load activity mask as the first load control data.

[0068] The Operation Type (OP) data represents control information indicating the execution mode of memory access instructions, characterizing the type of memory access operation to be used during the execution of the corresponding memory access instruction. The execution status represents the executable status of the memory access instruction in the current instruction execution flow, indicating whether the corresponding memory access instruction has been selected to participate in the current memory access process. The first load active mask represents a set of identifier data generated by the data adjustment module 140, indicating which load instructions among multiple load instructions are marked as executable in the current memory access operation. The identifier bit corresponding to the global memory load instruction in the first load active mask is the valid identifier. The valid identifier can represent a value in the first load active mask, indicating that the load instruction at the corresponding position is executable and selected to participate in the memory access operation. For example, the valid identifier can be 1 or other suitable characters.

[0069] For example, when the number of load instructions is 32, the first load activity mask can be set to a width of 32 bits, where each bit corresponds to one load instruction. For load instructions that access global memory, the corresponding bit in the first load activity mask is set to a valid flag, such as a logical value of 1, to indicate that the load instruction is in an executable state in the current memory access operation. For load instructions that access non-global memory, the corresponding bit in the first load activity mask is set to a invalid flag, such as a logical value of 0.

[0070] Furthermore, the global load control field can represent a control field obtained by adjusting the operation type data, which is used to indicate that the memory access operation type of the corresponding load instruction is a load operation targeting global memory. For example, the global load control field can be set to ld.global or other suitable forms. The first load adjustment data can represent the aggregated control information formed after the data adjustment module 140 uniformly adjusts the operation type data corresponding to multiple load instructions. The operation type data corresponding to load instructions whose access target is global memory is adjusted to the global load control field, while the operation type data corresponding to non-global memory load instructions remains unchanged or is set to an invalid status flag. The first load adjustment data is used to characterize the overall result of the operation type data corresponding to each load instruction in this adjustment, and works with the first load activity mask to form the first load control data. In the above process, by generating the first load activity mask and adjusting the operation type data corresponding to the global memory load instructions, the global memory load instructions can be clearly distinguished during memory access execution, thereby supporting the orderly execution of subsequent memory access operations.

[0071] In this embodiment, the instruction control data further includes a task identifier. The specific process of adjusting the instruction control data a second time by the data adjustment module 140, using the private memory loading instruction as a valid instruction, to obtain the second load control data includes: using the private memory loading instruction as a valid instruction to generate a second load activity mask for indicating the execution status of each loading instruction; wherein, the identifier bit corresponding to the private memory loading instruction in the second load activity mask is a valid identifier; adjusting the operation type data corresponding to the private memory loading instruction to a private load control field to obtain the second load adjustment data; using the task identifier to obtain the private memory address corresponding to each private memory loading instruction, and using the second load adjustment data, the second load activity mask, and the private memory address as the second load control data.

[0072] The task ID uniquely identifies the memory access task corresponding to a parallel thread. Each task ID corresponds one-to-one with a parallel thread, indicating the parallel thread to which the load instruction belongs during instruction execution. It also allows the data adjustment module 140 to retrieve the private memory address associated with the corresponding parallel thread based on the task ID. The private memory address represents the target access address corresponding to the private memory load instruction, indicating the data access location of the load instruction within the private memory.

[0073] The second load activity mask can represent another set of identification data generated by the data adjustment module 140, which is used to indicate which load instructions among multiple load instructions are marked as executable in the current memory access operation. In the second load activity mask, the flag bit corresponding to the private memory load instruction is a valid flag.

[0074] For example, when the number of load instructions is 32, the second load activity mask can be set to a width of 32 bits, where each bit corresponds to one load instruction; for a private memory load instruction that accesses private memory, the corresponding bit in the second load activity mask is set to a valid flag, such as a logical value of 1; while for a load instruction that accesses non-private memory, the corresponding bit in the second load activity mask is set to a invalid flag, such as a logical value of 0.

[0075] Furthermore, the private load control field can represent a control field obtained by adjusting the operation type data, which is used to indicate that the memory access operation type of the corresponding load instruction is a load operation targeting private memory; for example, the private load control field can be set to ld.private or other suitable forms. The second load adjustment data can represent the aggregated control information formed by the data adjustment module after uniformly adjusting the operation type data corresponding to multiple load instructions. Among them, the operation type data corresponding to the load instruction whose access target is private memory is adjusted to the private load control field, while the operation type data corresponding to the non-private memory load instruction remains unchanged or is set to an invalid status flag; the second load adjustment data is used to characterize the overall result of the operation type data corresponding to each load instruction in this adjustment, and together with the second load activity mask and the private memory address, constitutes the second load control data. In the above process, by generating the second load activity mask, adjusting the operation type data corresponding to the private memory load instruction and introducing the private memory address associated with the task identifier, the private memory load instruction can be clearly distinguished and obtain the corresponding memory access address during the memory access execution process, thereby supporting the orderly execution of subsequent memory access operations targeting private memory.

[0076] Continue to refer to Figure 2 As shown, the private memory address can be pre-stored in the private address storage module 230; the specific process of obtaining the private memory address corresponding to each private memory loading instruction by the data adjustment module 140 using the task identifier includes: sending the task identifier corresponding to each private memory loading instruction to the private address storage module 230; querying the target private memory address corresponding to each private memory loading instruction according to the task identifier, and returning the target private memory address to the data adjustment module 140.

[0077] The private address storage module 230 can represent a storage module used to store the mapping relationship of private memory addresses corresponding to parallel threads. It interacts with the data adjustment module 140 to support obtaining private memory addresses based on task identifiers. In some embodiments, the private address storage module 230 can be located inside the load storage unit, implemented as part of the load storage circuit 100. In other embodiments, the private address storage module 230 can be set independently of the load storage unit and communicate with the data adjustment module 140 through an interface. The target private memory address can represent the private memory access address obtained by the private address storage module 230 based on the task identifier. It indicates the data access location of the private memory load instruction in the private memory and corresponds one-to-one with the corresponding parallel thread.

[0078] In the above process, by pre-storing the private memory address in the private address storage module, and having the data adjustment module obtain the target private memory address corresponding to the private memory loading instruction based on the task identifier, the private memory loading instruction can obtain the corresponding private memory access address without relying on further parsing of the general address data during execution. This helps to simplify the processing flow of the private memory loading instruction and maintain the orderliness of the memory access execution process.

[0079] In this embodiment of the disclosure, the specific process of generating the target access address corresponding to each memory access instruction by the address generation module using control optimization data and general address data includes: generating the global memory load address corresponding to each global memory load instruction using the first load control data and general address data; and generating the private memory load address corresponding to each private memory load instruction using the second load control data and general address data.

[0080] The global memory load address can represent the target access address generated by the address generation module 120 based on the first load control data and general address data, and is used to indicate the data access location of the global memory load instruction in global memory. The private memory load address can represent the target access address generated by the address generation module 120 based on the second load control data and general address data, and is used to indicate the data access location of the private memory load instruction in private memory.

[0081] The address generation module uses the first and second load control data to generate different load addresses corresponding to global memory load instructions and private memory load instructions, respectively. This allows load instructions for different access targets to be distinguished during the address generation stage, so that subsequent memory access operations can be performed on global memory and private memory based on the corresponding load addresses.

[0082] In the specific implementation process, when parsing the load instructions corresponding to each parallel thread, the instruction scheduling module 110 generates instruction control data corresponding to each load instruction. This instruction control data includes at least operation type data, an activity mask, a task identifier, and base address information. The base address information is used to characterize the address reference used by the load instruction during address generation. Subsequently, the instruction scheduling module 110 sends the instruction control data to the address generation module 120.

[0083] When generating the target access address, the address generation module 120, based on the first and second load control data output by the data adjustment module 140, performs the address generation and memory access triggering process for the load instruction in two steps. Specifically, this includes: a first load operation, targeting the global memory load instruction corresponding to the first load control data. The address generation module 120 determines the global memory load instruction set based on the first load activity mask and extracts the base address information corresponding to this set from the instruction control data; the address generation module 120 further performs address synthesis processing on the base address information and general address data to generate the global memory load address corresponding to each global memory load instruction, and sends the global memory load address to the memory access execution module 130; the memory access execution module 130 executes the first load operation based on the global memory load address, which is a global memory load operation.

[0084] The second loading operation targets the private memory loading instructions corresponding to the second loading control data. After the memory access execution module 130 completes the first loading operation and provides feedback on its completion, the instruction scheduling module 110 allows entry into the next stage of processing. The address generation module 120 determines the set of private memory loading instructions based on the second loading activity mask and extracts the base address information corresponding to this set from the instruction control data. The data adjustment module 140 has obtained the private memory address based on the task identifier and provides it to the address generation module 120 as part of the second loading control data. The address generation module 120 further performs address synthesis processing on the base address information and the private memory address to generate a private memory loading address corresponding to each private memory loading instruction, and sends the private memory loading address to the memory access execution module 130. The memory access execution module 130 executes the second loading operation based on the private memory loading address; this second loading operation is a loading operation targeting private memory. Of course, in other embodiments of this disclosure, the first loading operation can also be a loading operation targeting private memory; the second loading operation can also be a loading operation targeting global memory.

[0085] Continue to refer to Figure 2As shown, in this embodiment of the present disclosure, the load memory circuit 100 determines the execution status of the load instruction through a pre-configured barrier counting module 240. The barrier counting module 240 can represent a counting unit used to record the completion status of multiple memory access operations corresponding to the load instruction. It updates its count by responding to a count decrement signal sent by the memory access execution module 130 to reflect the current execution progress of the load instruction. In some embodiments, the barrier counting module 240 can be located inside the load memory unit, implemented as part of the load memory circuit 100, to achieve local completion determination of the memory access execution process; in other embodiments, the barrier counting module 240 can also be located outside the load memory unit and communicate with the load memory circuit 100 through an interface.

[0086] Furthermore, the memory access operation includes a first load operation and a second load operation; the specific process of the memory access execution module 130 performing the memory access operation on the target access address includes: performing a first load operation on the global memory according to the global memory load address and sending a count decrement signal to the barrier counting module 240; performing a second load operation on the private memory according to the private memory load address and sending a count decrement signal to the barrier counting module 240; wherein, the preset count value of the barrier counting module 240 is a first value, and when the count value decrements to a preset second value, it is determined that the memory access instructions corresponding to multiple parallel threads have been executed.

[0087] The first load operation can represent a load process performed by the memory access execution module 130 on the global memory in the target storage unit 220 based on the global memory load address. This process retrieves data corresponding to the global memory load instruction and serves as a memory access operation during the load instruction execution process. The second load operation can represent another load process performed by the memory access execution module 130 on the private memory in the target storage unit 220 based on the private memory load address. This process retrieves data corresponding to the private memory load instruction and serves as another memory access operation during the load instruction execution process. The count decrease (bc decrease) signal can represent an indication signal sent by the memory access execution module 130 to the barrier counting module 240 after completing a load operation. This signal triggers the barrier counting module 240 to decrease and update the current count value to reflect the execution progress of the load instruction.

[0088] By setting up a barrier counting module and triggering the count decrement upon completion of the first and second loading operations, the completion status of the loading instruction can be accurately determined, thereby improving the determinism of the loading instruction execution process.

[0089] Furthermore, the first value can represent the initial count value preset by the barrier counting module 240 when the loading instruction begins execution, used to indicate the number of loading operations that the loading instruction needs to complete during execution. The second value can represent the target counting threshold used by the barrier counting module 240 to determine the completion of the loading instruction; when the current count value decreases to the second value, it indicates that the multiple loading operations corresponding to the loading instruction have been completed.

[0090] For example, in this embodiment of the disclosure, the first value of the barrier counting module 240 can be set to 2, indicating that the loading instruction needs to complete two loading operations during execution; correspondingly, the second value can be set to 0, serving as a threshold for determining the completion of the loading instruction. When the loading instruction begins execution, the barrier counting module 240 initializes the current count value to the first value; when the memory access execution module 130 completes the first loading operation and sends a count decrement signal, the barrier counting module 240 decrements the current count value to 1; when the memory access execution module 130 further completes the second loading operation and sends a count decrement signal again, the barrier counting module 240 decrements the current count value to the second value, thereby determining that the memory access execution process of the corresponding multiple loading instructions has been completed.

[0091] Furthermore, in some embodiments, the memory access instructions corresponding to each parallel thread can be sent to the load memory circuit 100 via the upstream instruction distribution module 210 under the control of the instruction control module (ICTRL). When the instruction is sent, the instruction control module pre-configures the initial count value of the barrier counting module 240. Specifically, after the memory access instruction is sent, the barrier counting module 240 adds a preset count increment, for example, 2, to the count value associated with the memory access instruction based on the initial count value. Subsequently, the memory access execution module 130 triggers a count decrement update when completing the first and second load operations, respectively. When the count value decreases back to the initial count value, the barrier counting module 240 determines that the corresponding multiple load instructions have been executed.

[0092] It is worth noting that in some embodiments of this disclosure, even if the load instruction corresponding to the general address only triggers one of the first load operation or the second load operation during actual execution, the load memory circuit 100 still performs two count decrement processes on the load instruction according to the pre-configured barrier counting mechanism. Specifically, when the load instruction only contains a global memory load instruction or only contains a private memory load instruction, after the memory access execution module 130 completes the actual load operation, it still sends two count decrement signals to the barrier counting module 240 according to the execution flow corresponding to the two load operations; wherein, one count decrement signal corresponds to the actual load operation, and the other count decrement signal corresponds to the placeholder completion flag of the load operation that did not occur. In this way, the barrier counting module 240 always bases the completion determination of the load instruction on a fixed number of count decrement processes, so that the load memory circuit maintains a consistent execution completion determination rule when handling different general address mapping scenarios, avoiding the introduction of additional determination paths due to differences in the number of load operations.

[0093] Further, refer to Figure 2 As shown in the embodiments of this disclosure, the buffer module 150 in the load memory circuit 100 further includes a write data buffer 152, which is used to cache data written to the target access address. The write data buffer 152 can represent a data storage area in the load memory circuit 100 used to temporarily store data to be written to the target access address, and it is used to cache the write data corresponding to each memory access instruction before the memory access instruction enters the execution phase.

[0094] In addition, the loading memory circuit 100 may also include a preprocessing module 160, one end of which is connected to the write data buffer 152 and the other end is connected to the memory access execution module 130. The preprocessing module 160 is used to obtain the write data required by the memory access execution module 130 during instruction execution from the write data buffer 152.

[0095] The preprocessing module 160 can be represented as a data processing unit located between the write data buffer 152 and the memory access execution module 130. During the instruction execution process of the memory access execution module 130, it reads the write data corresponding to the current memory access instruction from the write data buffer 152, performs necessary data organization, alignment, or selection processing on the write data, and then provides the memory access execution module 130 with write data that meets the requirements of the current memory access operation. The write data can represent the data content corresponding to the memory access instruction and used to write to the target access address.

[0096] By caching the written data and having the preprocessing module retrieve it according to the instruction requirements during the memory access execution phase, the written data corresponding to multiple memory access instructions can be supplied to the memory access execution module in an orderly manner, thereby ensuring data consistency and execution reliability of write-type memory access operations in parallel execution scenarios.

[0097] The following is a detailed description of the instruction execution process in the loading memory circuit when the memory access instruction is a write instruction, in an exemplary embodiment.

[0098] Specifically, at least one of the multiple memory access instructions is a write instruction. When the memory access instruction is a write instruction, the write instruction includes at least one of a global memory write instruction that accesses global memory and a private memory write instruction that accesses private memory.

[0099] A write instruction can represent a type of memory access instruction used to write data to a target memory space. During execution, it updates the target access address with data generated by the corresponding parallel thread. Write instructions can include ordinary write instructions and atomic write instructions. Ordinary write instructions can correspond to store instructions (Store, ST), and atomic write instructions can correspond to atomic operation instructions (Atomic, ATOMIC). A global memory write instruction can represent a write instruction whose access target is determined to be global memory among multiple write instructions corresponding to multiple parallel threads. It is used to store the write data to the target access address in global memory. A private memory write instruction can represent a write instruction whose access target is determined to be private memory among multiple write instructions corresponding to multiple parallel threads. It is used to store the write data to the target access address in the private memory associated with the corresponding parallel thread.

[0100] Furthermore, the specific process of adjusting the instruction control data based on the access target by the data adjustment module 140 to obtain control optimization data includes: taking the global memory write instruction as a valid instruction and adjusting the instruction control data for the first time to obtain the first write control data; taking the private memory write instruction as a valid instruction and adjusting the instruction control data for the second time to obtain the second write control data; wherein the first write control data and the second write control data correspond to different memory access operations.

[0101] The first write control data can represent a set of control information formed by the data adjustment module 140 after adjusting the corresponding instruction control data for a write instruction targeting global memory. This set characterizes the write operation mode and execution state of the global memory write instruction during subsequent memory access execution, and instructs the memory access execution module 130 to perform a write-type memory access operation targeting global memory. The second write control data can represent a set of control information formed by the data adjustment module 140 after adjusting the corresponding instruction control data for a write instruction targeting private memory. This set characterizes the write operation mode and execution state of the private memory write instruction during subsequent memory access execution, and instructs the memory access execution module 130 to perform a write-type memory access operation targeting private memory.

[0102] Furthermore, the first write control data is used to instruct the memory access execution module 130 to perform a first write operation, and the second write control data is used to instruct the memory access execution module 130 to perform a second write operation. The two write operations are independent of each other in execution timing and each corresponds to a complete write process. In this embodiment, by adjusting the instruction control data corresponding to the write instruction to the first write control data and the second write control data respectively, the loading memory circuit can clearly identify the access target of the write instruction on the hardware side, thereby executing the corresponding write operation.

[0103] Specifically, the data adjustment module 140 treats the global memory write instruction as a valid instruction and performs the first adjustment on the instruction control data to obtain the first write control data. The specific process includes: the data adjustment module 140 treats the global memory write instruction as a valid instruction and generates a first write activity mask to indicate the execution status of each write instruction; wherein, the flag bit corresponding to the global memory write instruction in the first write activity mask is a valid flag; the data adjustment module 140 adjusts the operation type data corresponding to each global memory write instruction to a global write control field to obtain the first write adjustment data, and uses the first write adjustment data and the first write activity mask as the first write control data.

[0104] The first write activity mask can represent a set of identifier data generated by the data adjustment module 140 when selecting a global memory write instruction as a valid instruction. This identifier indicates which write instructions among multiple write instructions are marked as valid during the execution phase corresponding to the current first write operation. The first write adjustment data can represent a set of data formed by the data adjustment module 140 after uniformly adjusting the operation type data corresponding to each write instruction in the current instruction set. Operation type data belonging to global memory write instructions are adjusted to a global write control field, while operation type data corresponding to non-global memory write instructions remain unchanged or are set to an invalid status identifier. For example, the global write control field can be ST.global.

[0105] The specific process by which the data adjustment module 140 treats the private memory write instruction as a valid instruction and performs a second adjustment on the instruction control data to obtain the second write control data includes: the data adjustment module 140 treats the private memory write instruction as a valid instruction and generates a second write activity mask to indicate the execution status of each write instruction; wherein, the identifier bit corresponding to the private memory write instruction in the second write activity mask is a valid identifier; the data adjustment module 140 adjusts the operation type data corresponding to the private memory write instruction to a private write control field to obtain the second write adjustment data; the data adjustment module 140 uses the task identifier to obtain the private memory address corresponding to each private memory write instruction, and uses the second write adjustment data, the second write activity mask, and the private memory address as the second write control data.

[0106] The second write activity mask can represent a set of identifier data generated by the data adjustment module 140 when selecting a private memory write instruction as a valid instruction. This identifier indicates which write instructions among multiple write instructions are marked as valid during the execution phase corresponding to the current second write operation. The second write adjustment data can represent a data set formed after the data adjustment module 140 uniformly adjusts the operation type data corresponding to each write instruction in the current instruction set. Operation type data belonging to private memory write instructions is adjusted to a private write control field, while operation type data corresponding to non-private memory write instructions remains unchanged or is set to an invalid status identifier. For example, the private write control field can be ST.private.

[0107] In an exemplary embodiment, the specific process of generating the target access address corresponding to each memory access instruction by the address generation module 120 using control optimization data and general address data includes: generating a global memory write address corresponding to each global memory write instruction using first write control data and general address data; and generating a private memory write address corresponding to each private memory write instruction using second write control data and general address data.

[0108] The global memory write address represents the target access address generated by the address generation module 120 for the global memory write instruction after receiving the first write control data. It corresponds to the write position in global memory and is used to instruct the memory access execution module 130 to perform a write-type memory access operation on global memory. The private memory write address represents the target access address generated by the address generation module 120 for the private memory write instruction after receiving the second write control data. It corresponds to the write position in private memory and is used to instruct the memory access execution module 130 to perform a write-type memory access operation on private memory. Furthermore, the generation process of the global memory write address and the private memory write address is consistent with the generation process of the global memory load address and the private memory load address when the memory access instruction is a load instruction in the aforementioned embodiment, and will not be elaborated further here. In the above steps, the address generation module 120 generates the global memory write address and the private memory write address based on the first write control data and the second write control data respectively, enabling the write instruction to form a target access address matching the access target on the hardware side, ensuring the consistency of subsequent write-type memory access operations.

[0109] In an exemplary embodiment, the memory access operation includes a first write operation and a second write operation. The specific process of the memory access execution module 130 performing the memory access operation on the access target according to the target access address includes: obtaining the global memory write data corresponding to each global memory write instruction through the preprocessing module 160, and performing a first write operation on the global memory according to the global memory write address and the global memory write data; obtaining the private memory write data corresponding to each private memory write instruction through the preprocessing module 160, and performing a second write operation on the private memory according to the private memory write address and the private memory write data.

[0110] The first write operation can represent a write operation performed by the memory access execution module 130 on global memory based on the global memory write address and combined with the global memory write data obtained through the preprocessing module 160, which serves as a memory access operation during the execution of a write instruction. The second write operation can represent another write operation performed by the memory access execution module 130 on private memory based on a private memory write address and combined with the private memory write data obtained through the preprocessing module 160, which serves as another memory access operation during the execution of a write instruction. The global memory write data can represent the data content corresponding to the global memory write instruction, used to write to the global memory write address. During instruction execution, the preprocessing module 160 obtains this data from the write data buffer 152 and provides it to the memory access execution module 130 for the first write operation on global memory. The private memory write data can represent the data content corresponding to the private memory write instruction, used to write to the private memory write address. During instruction execution, the preprocessing module 160 obtains this data from the write data buffer 152 and provides it to the memory access execution module 130 for the second write operation on private memory. Through the above steps, the first write operation is associated with the global memory write instruction, and the second write operation is associated with the private memory write instruction, thereby ensuring that different write instructions trigger the corresponding write operation.

[0111] Furthermore, in other embodiments of this disclosure, the write operation corresponding to the private memory write instruction can be performed first, followed by the write operation corresponding to the global memory write instruction. Additionally, after completing each write operation, the memory access execution module 130 can send a count decrement signal to the barrier counting module 240. Specifically, a count decrement signal is sent once after completing the first write operation and again after completing the second write operation, so that the barrier counting module 240 updates the current count value associated with the write instruction by decrementing it, and determines that the corresponding write instruction has been completed when the count value decreases to a preset value.

[0112] In an exemplary embodiment, the memory access execution module 130 is used to send the first thread number corresponding to each global memory write instruction to the preprocessing module 160; the preprocessing module 160 is used to determine the global memory write data corresponding to each global memory write instruction according to the first thread number, and return the global memory write data to the memory access execution module 130.

[0113] The first thread number can represent a set of numbering information used to identify the identity of a parallel thread. It indicates the location of the write data corresponding to the global memory write instruction in the write data buffer 152. In this embodiment, after the memory access execution module 130 sends the first thread number to the preprocessing module 160, the preprocessing module 160 locates and determines the global memory write data matching the corresponding global memory write instruction in the write data buffer 152 based on the first thread number, and returns the global memory write data to the memory access execution module 130. By having the memory access execution module 130 send the first thread number to the preprocessing module 160, and the preprocessing module 160 determine and return the corresponding global memory write data accordingly, the global memory write instruction can accurately match its write data during the execution phase.

[0114] In an exemplary embodiment, the memory access execution module 130 obtains the private memory write data corresponding to each private memory write instruction through the preprocessing module 160, and performs a second write operation on the private memory based on the private memory write address and the private memory write data. The specific process includes: the memory access execution module 130 sends the second thread number corresponding to each private memory write instruction to the preprocessing module 160; the preprocessing module 160 determines the private memory write data corresponding to each private memory write instruction based on the second thread number, and returns the private memory write data to the memory access execution module 130. The second thread number can be used to indicate the write data position corresponding to the private memory write instruction in the write data buffer 152. In this embodiment, after the memory access execution module 130 sends the second thread number to the preprocessing module 160, the preprocessing module 160 locates and determines the private memory write data matching the corresponding private memory write instruction in the write data buffer 152 based on the second thread number, and returns the private memory write data to the memory access execution module 130.

[0115] Furthermore, in this example embodiment, an instruction processing method is also provided. This instruction processing method can be executed by the load-memory circuit in the above embodiment. Figure 3 This schematically illustrates a flowchart of an instruction processing method according to some embodiments of the present disclosure, with reference to... Figure 3 As shown, the instruction processing method may include: Step S310: The instruction scheduling module receives the memory access instruction corresponding to the currently pending thread and parses the instruction control data corresponding to the memory access instruction. In step S320, the data adjustment module determines the access target corresponding to the memory access instruction based on the general address data, and adjusts the instruction control data based on the access target to obtain control optimization data. In step S330, the address generation module uses control optimization data and general address data to generate the target access address corresponding to the memory access instruction; Step S340: The memory access execution module performs a memory access operation on the access target according to the target access address; The general address data corresponding to the memory access instructions input to the data adjustment module is cached in the general address buffer of the buffer module.

[0116] The specific details of each step in the instruction processing method described above have been described in detail in the corresponding load and store circuits, so they will not be repeated here.

[0117] It should be noted that although the steps of the method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.

[0118] In exemplary embodiments of this disclosure, a processor is also provided, which includes the load-memory circuit described in the above embodiments. Exemplarily, the processor may be a Graphics Processing Unit (GPU) for performing massively parallel computing tasks and processing memory access instructions corresponding to parallel threads through the load-memory circuit. In other embodiments, the processor may also be a Central Processing Unit (CPU) or other programmable processor that supports parallel memory access.

[0119] Furthermore, in an exemplary embodiment of this disclosure, an electronic device capable of implementing the above-described instruction processing method is also provided.

[0120] Those skilled in the art will understand that various aspects of this disclosure can be implemented as a system, method, or program product. Therefore, various aspects of this disclosure can be embodied in the following forms: a completely hardware embodiment, a completely software embodiment (including firmware, microcode, etc.), or an embodiment combining hardware and software aspects, collectively referred to herein as a "circuit," "module," or "system."

[0121] In exemplary embodiments of this disclosure, a chip is also provided, comprising the processor as described in the above embodiments. Exemplarily, the chip may be a graphics processing chip, an artificial intelligence acceleration chip, a general-purpose parallel computing chip, a system-on-a-chip (SoC), or other dedicated processing chip supporting multi-threaded memory access. The processor in the aforementioned chip integrates the aforementioned load-memory circuitry, thereby enabling it to process memory access instructions in general address form.

[0122] The following reference Figure 4 To describe an electronic device 400 according to such an embodiment of the present disclosure. Figure 4 The electronic device 400 shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments disclosed herein.

[0123] like Figure 4 As shown, the electronic device 400 is manifested as a general-purpose computing device. The components of the electronic device 400 may include, but are not limited to: at least one processing unit 410, at least one storage unit 420, a bus 430 connecting different system components (including the storage unit 420 and the processing unit 410), and a display unit 440. Further, the processing unit 410 can be a parallel processing architecture, such as any one or more of a graphics processor, neural network processing unit, programmable logic device, and tensor processing unit. The processing unit 410 includes the loading and storage circuitry described in the above embodiments.

[0124] The storage unit 420 stores program code that can be executed by the processing unit 410, causing the processing unit 410 to perform the steps described in the "Exemplary Methods" section above according to various exemplary embodiments of this disclosure.

[0125] Storage unit 420 may include readable media in the form of volatile storage units, such as random access memory (RAM) 421 and / or cache storage unit 422, and may further include read-only memory (ROM) 423.

[0126] Storage unit 420 may also include a program / utility 424 having a set (at least one) of program modules 425, including but not limited to: an operating system, one or more application programs, other program modules, and program data, each or some combination of these examples may include an implementation of a network environment.

[0127] Bus 430 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0128] Electronic device 400 can also communicate with one or more external devices 470 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with electronic device 400, and / or with any device that enables electronic device 400 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 450. Furthermore, electronic device 400 can also communicate with one or more networks (e.g., Local Area Network (LAN), Wide Area Network (WAN), and / or public networks, such as the Internet) via network adapter 460. As shown, network adapter 460 communicates with other modules of electronic device 400 via bus 430. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 400, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, Redundant Array of Independent Disks (RAID) systems, tape drives, and data backup storage systems.

[0129] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0130] In exemplary embodiments of this disclosure, a computer-readable storage medium is also provided, on which a program product capable of implementing the methods described above is stored. In some possible embodiments, various aspects of this disclosure may also be implemented as a program product including program code that, when the program product is run on a terminal device, causes the terminal device to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of this disclosure.

[0131] refer to Figure 5As shown, a program product 500 for implementing the above-described instruction processing method according to an embodiment of the present disclosure is described. This product may employ a portable compact disc read-only memory (CD-ROM) and include program code, and may run on a terminal device, such as a personal computer. However, the program product of the present disclosure is not limited thereto. In this document, a readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, apparatus, or device.

[0132] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0133] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of sending, propagating, or transmitting programs for use by or in conjunction with an instruction execution system, apparatus, or device.

[0134] The program code contained on the readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0135] Program code for performing the operations of this disclosure can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0136] Furthermore, the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of this disclosure and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0137] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, touch terminal, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0138] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0139] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A loading and storing circuit, characterized in that, The load-memory circuit includes an instruction scheduling module, an address generation module, and a memory access execution module connected in sequence, and also includes a data adjustment module connected to the address generation module, wherein: The instruction scheduling module is used to receive the memory access instruction corresponding to the currently pending thread and parse the instruction control data corresponding to the memory access instruction. The data adjustment module is used to determine the access target corresponding to the memory access instruction based on the general address data, and adjust the instruction control data based on the access target to obtain control optimization data; The address generation module is used to generate the target access address corresponding to the memory access instruction using the control optimization data and the general address data; The memory access execution module is used to perform a memory access operation on the access target according to the target access address; The loading and storage circuit further includes a buffer module, which includes a general address buffer for caching the general address data corresponding to the memory access instruction input to the data adjustment module.

2. The loading and storage circuit according to claim 1, characterized in that, The data adjustment module is used for: The access target corresponding to the memory access instruction is determined based on the preset flag bit in the general address data; The access target includes either a first type of memory or a second type of memory, and the first type of memory and the second type of memory correspond to different values ​​of the preset flag bit.

3. The loading and storage circuit according to claim 2, characterized in that, The currently executing thread includes multiple parallel threads, the memory access instruction is multiple memory access instructions, and the parallel thread corresponds one-to-one with the memory access instruction; The first type of memory is global memory, and the second type of memory is private memory; at least one of the plurality of memory access instructions is a load instruction; the load instruction includes at least one of a global memory load instruction whose target is the global memory and a private memory load instruction whose target is the private memory; The data adjustment module is used to perform at least one of the following operations: The global memory load instruction is used as a valid instruction, and the instruction control data is adjusted to obtain the first load control data; The private memory loading instruction is used as a valid instruction, and the instruction control data is adjusted to obtain the second loading control data; The first load control data and the second load control data correspond to different memory access operations.

4. The loading and storage circuit according to claim 3, characterized in that, The instruction control data includes operation type data; the data adjustment module is used for: The global memory load instruction is used as a valid instruction to generate a first load activity mask to indicate the execution status of each load instruction; wherein, the flag bit corresponding to the global memory load instruction in the first load activity mask is a valid flag; The operation type data corresponding to each of the global memory load instructions is adjusted to a global load control field to obtain the first load adjustment data, and the first load adjustment data and the first load activity mask are used as the first load control data.

5. The loading and storage circuit according to claim 4, characterized in that, The instruction control data also includes a task identifier; the data adjustment module is used for: The private memory loading instruction is used as a valid instruction to generate a second loading activity mask to indicate the execution status of each loading instruction; wherein, the flag bit corresponding to the private memory loading instruction in the second loading activity mask is a valid flag; The operation type data corresponding to the private memory loading instruction is adjusted to the private loading control field to obtain the second loading adjustment data; The private memory address corresponding to each private memory loading instruction is obtained using the task identifier, and the second loading adjustment data, the second loading activity mask, and the private memory address are used as the second loading control data.

6. The loading and storage circuit according to claim 5, characterized in that, The private memory address is pre-stored in the private address storage module; The data adjustment module is used for: Send the task identifier corresponding to each of the private memory loading instructions to the private address storage module; The target private memory address corresponding to each private memory loading instruction is queried based on the task identifier, and the target private memory address is returned to the data adjustment module.

7. The loading and storage circuit according to claim 3, characterized in that, The address generation module is used for: The first loading control data and the general address data are used to generate global memory load addresses corresponding to each of the global memory load instructions; The second load control data and the general address data are used to generate private memory load addresses corresponding to each of the private memory load instructions.

8. The loading and storage circuit according to claim 7, characterized in that, The loading memory circuit determines the execution status of the loading instruction through a pre-configured barrier counting module; the memory access operation includes a first loading operation and a second loading operation; The memory access execution module is used for: The first loading operation is performed on the global memory according to the global memory loading address, and a count decrement signal is sent to the barrier counting module. The second loading operation is performed on the private memory according to the private memory loading address, and the count decrement signal is sent to the barrier counting module. The barrier counting module has a first preset count value, and when the count value decreases to a second preset value, it is determined that the memory access instructions corresponding to the multiple parallel threads have been executed.

9. The loading and storage circuit according to claim 1, characterized in that, The buffer module also includes: Write to the data buffer to cache the data written to the target access address; The loading and storage circuit also includes: The preprocessing module is connected to the write data buffer at one end and to the memory access execution module at the other end. The preprocessing module is used to obtain the write data required by the memory access execution module during instruction execution from the write data buffer.

10. The loading and storage circuit according to claim 9, characterized in that, The memory access instruction is a plurality of memory access instructions, at least one of which is a write instruction; the write instruction includes at least one of a global memory write instruction whose target is global memory and a private memory write instruction whose target is private memory. The data adjustment module is used for: The global memory write instruction is used as a valid instruction, and the instruction control data is adjusted for the first time to obtain the first write control data. The private memory write instruction is taken as a valid instruction, and the instruction control data is adjusted a second time to obtain the second write control data. The first write control data and the second write control data correspond to different memory access operations.

11. The loading and storage circuit according to claim 10, characterized in that, The address generation module is used for: The first write control data and the general address data are used to generate global memory write addresses corresponding to each of the global memory write instructions; The second write control data and the general address data are used to generate private memory write addresses corresponding to each of the private memory write instructions.

12. The loading and storage circuit according to claim 11, characterized in that, The memory access operation includes a first write operation and a second write operation; the memory access execution module is used for: The preprocessing module obtains global memory write data corresponding to each global memory write instruction, and performs the first write operation on the global memory according to the global memory write address and the global memory write data. The preprocessing module obtains the private memory write data corresponding to each private memory write instruction, and performs the second write operation on the private memory according to the private memory write address and the private memory write data.

13. The loading and storage circuit according to claim 12, characterized in that, The memory access execution module is used to: send the first thread number corresponding to each of the global memory write instructions to the preprocessing module; The preprocessing module is configured to: determine the global memory write data corresponding to each of the global memory write instructions based on the first thread number, and return the global memory write data to the memory access execution module.

14. An instruction processing method, characterized in that, Performed by the load-memory circuitry as described in any one of claims 1 to 13, the method comprises: The instruction scheduling module receives the memory access instruction corresponding to the currently pending thread and parses the instruction control data corresponding to the memory access instruction. The data adjustment module determines the access target corresponding to the memory access instruction based on the general address data, and adjusts the instruction control data based on the access target to obtain control optimization data; The address generation module uses the control optimization data and the general address data to generate the target access address corresponding to the memory access instruction; The memory access execution module performs a memory access operation on the access target according to the target access address; The general address data corresponding to the memory access instruction input to the data adjustment module is cached in the general address buffer of the buffer module.

15. A processor, characterized in that, The processor includes a load memory circuit as described in any one of claims 1 to 13.

16. A chip, characterized in that, The chip includes the processor as described in claim 15.

17. An electronic device, characterized in that, include: processor; A memory storing computer-readable instructions that, when executed by the processor, implement the instruction processing method as described in claim 14.

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