Training system, chip and storage medium for parallel bus link

Abstract

The application provides a training system, a chip and a storage medium of a parallel bus link, the system comprising: a data detection module, configured to detect the validity of data signals corresponding to different phase stages in a plurality of preset phase stages of a clock phase, and obtain binary detection results of the data signals corresponding to the different phase stages; a maximum cluster detection module, configured to obtain a plurality of groups of binary sequences based on an initial binary sequence; obtain a target phase adjustment value based on a binary sequence corresponding to a maximum value in a plurality of values corresponding to the plurality of groups of binary sequences; and a clock module, further configured to adjust the clock phase based on the target phase adjustment value, and detect the validity of data signals corresponding to the adjusted clock phase through the data detection module, and when the data signals corresponding to the adjusted clock phase are detected to be valid, training of the parallel bus link is ended. Thus, fine adjustment of the clock phase is realized through the system.

Description

[0001] This application claims priority to Chinese patent application filed on March 3, 2025, with application number 2025102420212, entitled "Parallel Bus Link Training Method, Apparatus, Electronic Device and Storage Medium", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of integrated circuit technology, and more specifically, to a training system, chip, and storage medium for a parallel bus link. Background Technology

[0003] Currently, data transmission protocols between chips and peripherals, such as Serial Peripheral Interface (SPI), Secure Digital Input / Output (SDIO), and Inter-Integrated Circuit (I2C), all exist in serial or low-bit-width form. While simple in design, these protocols are insufficient to meet the performance requirements of high-speed, high-bandwidth, and low-latency chip communication scenarios. Furthermore, in parallel bus solutions with higher bit widths, the large number of data bits, the complexity of cross-time domain signal transmission, and the difficulty in perfectly matching the delays of various signals often necessitate complex link training mechanisms to ensure reliable system operation.

[0004] In related technologies, low-bandwidth serial protocols (such as SPI and SDIO) struggle to meet high bandwidth requirements in high-speed data interconnection between chips and field-programmable gate arrays (FPGAs); while high-bandwidth parallel buses face challenges such as inconsistent signal arrival times, frame header misalignment, and high bit error rates under high-speed operating conditions. Especially when the bus operating frequency reaches 400MHz or higher, due to the significant differences in the signal paths, it is difficult to achieve stable communication using only fixed timing and static phase configuration. Summary of the Invention

[0005] This application provides a training system, chip, and storage medium for a parallel bus link. By configuring the parallel link training system in the chip or FPGA, multi-phase uniform scanning and maximum cluster analysis are performed to determine the location of the stable data transmission interval, thus achieving precise optimization of the timing of the high-speed parallel bus. The technical solution of this application not only significantly increases the stable operating speed of the parallel bus from 25MHz to 400MHz, but also, by finding and locking the center phase point of the widest stability interval, gives the system extremely strong anti-interference capability and robustness.

[0006] Firstly, this application provides a training system for a parallel bus link, the system comprising: The signal receiving module is used to set the parallel bus link status to an active state when a data signal is received. The link training control module is used to send an adjustment signal to the clock module when the parallel bus link is in an active state. The adjustment signal is used to instruct the clock module to adjust to multiple preset phase stages. The clock module is used to adjust the clock phase to multiple preset phase stages after receiving the adjustment signal. The data detection module is used to detect the validity of data signals corresponding to different phase stages among multiple preset phase stages of the clock phase, and obtain the binary detection results of the data signals corresponding to different phase stages. The binary detection results are used to indicate the validity of the data signals. The maximum cluster detection module is used to obtain multiple sets of binary sequences based on the initial binary sequence; and to obtain the target phase adjustment value based on the binary sequence corresponding to the largest value among the multiple values ​​corresponding to the multiple sets of binary sequences. The initial binary sequence is used to represent the data composed of multiple binary detection results corresponding to multiple preset phase stages. The clock module is also used to adjust the clock phase based on the target phase adjustment value, and send a detection signal to the data detection module through the link training control module so that the data detection module can detect the validity of the data signal corresponding to the adjusted clock phase. When the data signal corresponding to the adjusted clock phase is detected to be valid, the parallel bus link training ends.

[0007] The aforementioned technical solution, by configuring a parallel link training system in the chip or FPGA, determines the location of the stable data transmission interval through multi-phase uniform scanning and maximum cluster analysis, thus achieving precise optimization of the timing of the high-speed parallel bus. This application's technical solution not only significantly increases the stable operating speed of the parallel bus from 25MHz to 400MHz, but also, by finding and locking the center phase point of the widest stability interval, gives the system extremely strong anti-interference capability and robustness.

[0008] In this application's technical solution, phase adjustment is performed between the link training control module and the clock module. After each phase adjustment, link detection is conducted on the parallel bus to determine the validity of data transmission within the link. Furthermore, an initial binary sequence is formed based on the detection results corresponding to different phase stages. By sequentially shifting this initial binary sequence, the binary sequence corresponding to the maximum value is determined. Based on the number of shifts to the binary sequence corresponding to the maximum value and the length of the effective window within the binary sequence, a precise target phase adjustment value is determined. This makes the parallel bus more stable after clock phase adjustment based on the target phase adjustment value, achieving efficient data transmission between parallel buses.

[0009] In one possible implementation, the maximum cluster detection module includes a link detection temporary register, a maximum cluster temporary register, and an algorithm control module. The link detection temporary register stores an initial binary sequence. The system includes: The algorithm control module is used to control the initial binary sequence in the link detection temporary register to move sequentially in a preset direction a preset number of times, and after each move, to update the target binary sequence in the maximum cluster temporary register with the moved binary sequence; the multiple sets of binary sequences include the moved binary sequence obtained after each move; the values ​​of the preset number of moves and the preset phase stage are the same as the sequence values ​​of the multiple sets of binary sequences; The algorithm control module is used to obtain the target phase adjustment value based on the target binary sequence in the maximum cluster temporary register.

[0010] The above technical solution, by traversing the initial binary sequence multiple times, can continuously update the target binary sequence in the maximum cluster temporary register through the circular binary sequence, thereby accurately locating the binary sequence corresponding to the maximum value, and using the binary sequence corresponding to the maximum value as the target binary sequence.

[0011] In one possible implementation, the system includes: an algorithm control module, used to control the initial binary sequence in the link detection temporary register to shift by one bit in a preset direction to obtain the shifted binary sequence; and to determine whether the value corresponding to the shifted binary sequence is greater than the value corresponding to the target binary sequence in the maximum cluster temporary register; When the value corresponding to the moved binary sequence is greater than the value corresponding to the target binary sequence in the maximum cluster temporary register, the moved binary sequence is updated to the target binary sequence in the maximum cluster temporary register; and the initial binary sequence is moved again until the number of moves on the initial binary sequence equals the preset number. If the value corresponding to the moved binary sequence is less than or equal to the value corresponding to the target binary sequence in the maximum cluster temporary register, continue moving the initial binary sequence until the number of moves on the initial binary sequence equals the preset number.

[0012] The above technical solution continuously compares the initial binary sequence with the target binary sequence during the sequential movement of the initial binary sequence, ensuring that the binary sequence corresponding to the maximum value is updated to the maximum cluster maximum value temporary register, thus ensuring the accuracy of the positioning of the binary sequence corresponding to the maximum value.

[0013] In one possible implementation, the system includes: the maximum cluster detection module further includes a maximum cluster value temporary register, a maximum value sequence register, and a maximum cluster center value sequence register; the system includes: The maximum cluster maximum value temporary register is used to store the data length of the target binary sequence in the maximum cluster temporary register, starting from the most significant bit, where each bit is a valid detection result. The maximum value sequence number register is used to store the number of moves from the initial binary sequence to the target binary sequence in the maximum cluster temporary register; The maximum cluster center value register is used to store the center position of the data length of the valid detection results. The center position is obtained from the data length of the valid detection results. The algorithm control module is used to determine the difference between the number of moves in the maximum value sequence register and the center position in the maximum cluster center value sequence register, and to determine the target phase adjustment value based on the product of the move difference and the minimum phase adjustment window.

[0014] In one possible implementation, the clock module includes a phase control module and a controllable phase-locked loop; the system includes: The phase control module is used to adjust the clock phase to the target phase phase through a controllable phase-locked loop after receiving the adjustment signal corresponding to the target phase phase. The target phase phase is used to represent any phase phase among multiple preset phase phases. The data detection module is used to detect the validity of data signals whose clock phase is in the target phase stage, and obtain the binary detection result of the data signal corresponding to the target phase stage.

[0015] The above technical solution can ensure the accuracy of the binary detection results for each phase stage by detecting the validity of the data signal corresponding to each phase stage.

[0016] In one possible implementation, the system includes: a data detection module, used to determine whether there is a first consecutive period of data signal as a valid signal within a preset period when the clock phase is in the target phase stage; When the data signal of the first consecutive period within the preset period is a valid signal, the first value is determined as the binary detection result corresponding to the target phase stage, and the first value indicates that the data signal corresponding to the target phase stage is a valid signal; when the data signal of the first consecutive period within the preset period is not a valid signal, the second value is determined as the binary detection result corresponding to the target phase stage, and the second value indicates that the data signal corresponding to the target phase stage is an invalid signal.

[0017] In one possible implementation, the link training control module includes a link training state machine and a link phase control module; the system includes: a link training state machine, used to sequentially traverse multiple preset phase stages when the parallel bus link state is in an active state; The link phase control module is used to determine the first phase adjustment value corresponding to the first phase stage based on the product of the phase index corresponding to the first phase stage and the minimum phase adjustment window when the link training state machine traverses to the first phase stage; and send the adjustment signal corresponding to the first phase stage to the clock module, which includes the first phase adjustment value, so that the clock module adjusts to the first phase stage.

[0018] In one possible implementation, the clock module includes a phase control module and a controllable phase-locked loop; the system includes: a phase control module, used to adjust the clock phase to the target phase adjustment value through the controllable phase-locked loop after receiving the target phase adjustment value sent by the maximum cluster detection module; and to send a detection signal to the data detection module through the link training control module; The data detection module is used to determine, after receiving the detection signal, whether there is a valid data signal of a second consecutive period within a preset period; if there is a valid data signal of a second consecutive period within the preset period, the data signal corresponding to the adjusted clock phase is determined to be valid; if there is no valid data signal of a second consecutive period within the preset period, the data signal corresponding to the adjusted clock phase is determined to be invalid, and the parallel bus link is retrained, with the period value of the second consecutive period being greater than the period value of the first consecutive period.

[0019] The above technical solution, after adjusting the phase clock, performs a validity check on the transmitted data of the parallel bus again to ensure the effectiveness of the clock phase adjustment. Furthermore, since the period value of the second consecutive cycle is greater than that of the first consecutive cycle, the high efficiency of data transmission on the adjusted parallel bus is ensured.

[0020] Secondly, this application provides a chip equipped with a training system for parallel bus links, which is used to execute the training system for parallel bus links in the first aspect or any possible implementation of the first aspect.

[0021] Thirdly, this application provides a chip including a memory and a processor, wherein the memory is used to store executable program code; and the processor is used to call and run the executable program code from the memory, thereby enabling the vehicle to execute the training system of the parallel bus link in the first aspect or any possible implementation of the first aspect.

[0022] Fourthly, this application provides a computer-readable storage medium storing computer program code that, when executed on a computer, causes the computer to perform the training system for the parallel bus link in the first aspect or any possible implementation thereof.

[0023] Fifthly, this application provides a computer program product comprising: computer program code, which, when executed on a computer, causes the computer to execute the training system for the parallel bus link in the first aspect or any possible implementation thereof.

[0024] Based on this, this application achieves nanosecond-level training speed and parallel, efficient resource utilization by configuring the complete link training process as a hardware module controlled by a state machine. It can complete adaptive optimization of the high-speed parallel bus in a short time. Specifically, through multi-phase uniform scanning and maximum cluster analysis, the stable data transmission interval is determined, achieving precise optimization of the high-speed parallel bus timing. This application's technical solution not only significantly increases the stable operating rate of the parallel bus from 25MHz to 400MHz, but also, by finding and locking the center phase point of the widest stability interval, gives the system extremely strong anti-interference capability and robustness. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the structure of a training system with a parallel bus link provided in an embodiment of this application; Figure 2 This is a schematic diagram of a training method for a parallel bus link provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of a training device for a parallel bus link provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of a chip provided in an embodiment of this application. Detailed Implementation

[0026] The technical solutions in this application will be clearly and thoroughly described below with reference to the accompanying drawings. In the description of the embodiments of this application, unless otherwise stated, " / " means "or," for example, A / B can mean A or B. "And / or" in the text is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, in the description of the embodiments of this application, "multiple" refers to two or more than two.

[0027] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as implying or suggesting relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

[0028] With the continuous development of integrated circuit technology and the increasing demand for data throughput, traditional high-speed serial interfaces have been widely used in many applications. Data transmission protocols between chips and peripherals, such as SPI, SDIO, and I2C, exist in serial or low-bit-width forms. Although simple in design, they can no longer meet the system performance requirements in high-speed, high-bandwidth, and low-latency chip communication scenarios. In parallel bus solutions with higher bit widths, due to the large number of data bits, the complexity of cross-time domain signal transmission, and the difficulty in perfectly matching the delays of various signals, complex link training mechanisms are often required to ensure reliable system operation.

[0029] In related technologies, low-bandwidth serial protocols (such as SPI and SDIO) struggle to meet high bandwidth requirements for high-speed data interconnection between chips and FPGAs; while high-bandwidth parallel buses face challenges such as inconsistent signal arrival times, frame header misalignment, and high bit error rates under high-speed operating conditions. Especially when the bus operating frequency reaches 400MHz or higher, the significant differences between signal paths make stable communication difficult to achieve using only fixed timing and static phase configurations. In some systems, the transceiver side may lack complex link training hardware or only provide a simple fixed transmission mode, making it impossible to directly complete adaptive high-speed training.

[0030] To address this issue, traditional solutions often seek phase alignment between data and clock by simply switching between sampling on the rising and falling edges of the clock or adding a fixed phase delay. However, as the target data rate gradually increases to hundreds of megahertz or even higher, slight delay differences between each data line due to factors such as manufacturing processes and circuitry, coupled with the receiver's lack of fine-grained compensation for data delays, lead to significant uncertainty in aligning the clock phase with the data sampling window. This results in a very narrow effective sampling window. If the sampling clock cannot be precisely adjusted to this extremely small window, the system faces the risk of link instability or even connection failure.

[0031] In view of this, this application proposes a training system, chip, and storage medium for a parallel bus link. The training system for the parallel link is configured in a chip or FPGA. By performing multi-phase uniform scanning and maximum cluster analysis, the stable data transmission interval is determined, achieving precise optimization of the timing of the high-speed parallel bus. This application's technical solution not only significantly increases the stable operating speed of the parallel bus from 25MHz to 400MHz, but also, by finding and locking the center phase point of the widest stability interval, gives the system extremely strong anti-interference capability and robustness.

[0032] The following will combine Figure 1 The training process of the parallel bus link training system in this application is described.

[0033] Figure 1This is a schematic diagram of the structure of a training system for a parallel bus link provided in an embodiment of this application.

[0034] For example, Figure 1 The training system with the parallel bus link shown can be configured on a chip or FPGA. For example, Figure 1 The training system shown includes both chip A and chip B (or FPGA) configured with parallel bus links. Chip A and chip B (or FPGA) communicate via the parallel bus and an accompanying clock.

[0035] For example, such as Figure 1 As shown, the training system for the parallel bus link includes a signal receiving module, a data detection module, a clock module, a link training control module, and a maximum cluster detection module.

[0036] The signal receiving module includes a signal detection module and a signal sampling module. The signal sampling module acquires the data signal sent by chip A through the parallel bus, and the signal detection module detects the data signal. When a valid data signal is detected, the valid status signal of the parallel bus link is activated, that is, the parallel bus link status is set to valid, so that the data detection module, clock module, link training control module and maximum cluster detection module can obtain the parallel bus link status.

[0037] When detecting data signals, the signal detection module can determine whether a data signal is valid by checking the consistency of data signals sent in different cycles. For example, chip A and the FPGA transmit data via a 16-bit low-voltage complementary metal-oxide-semiconductor (LVCMOS) parallel bus. If the signal detection module detects 200 consecutive data toggles, it determines the data signal is valid and sets the parallel bus link status to valid. If the signal detection module does not detect 200 consecutive data toggles, it determines the data signal is invalid and continues to detect the data signals sent by chip A until the FPGA powers down or the data signal becomes valid.

[0038] It should be understood that multiple preset phase stages in a parallel bus link training system can be determined by the number of divisions of a unit time interval. For example, if the unit time interval is divided into 64 segments, then there are 64 preset phase stages, and the minimum phase adjustment window is the ratio of the unit time interval to 64. Alternatively, multiple preset phase stages in a parallel bus link training system can be obtained by dividing the unit time interval using a preset phase adjustment window; that is, by using a preset phase adjustment window, multiple non-overlapping clock segments are continuously divided into units of time interval, and the clock segments are accumulated sequentially to obtain multiple preset phase stages; in this case, the preset phase adjustment window is the minimum phase adjustment window.

[0039] It should be noted that traditional solutions achieve 2 / 4 preset phases through delay lines and multiple clocks. This application, however, is adapted to high-speed scenarios, allowing preset phase stages to be set to 32, 64, 128, 256, 512, etc., and thus enabling 10ps granular phase adjustment through MMCM (Mixed-Mode Clock Manager). In other words, this application uses dozens or even hundreds of preset phase stages to achieve fine-grained phase adjustment. For example, with a 200MHz period of 5ns, and a minimum adjustment time of 10ps (i.e., the minimum phase adjustment window), there are 500 preset phase stages. With a 400MHz period of 2.5ns, and a minimum adjustment time of 10ps, there are 250 preset phase stages. Based on this, this application finds an effective time window as small as 10-20ps in the high-speed parallel link, ensuring lossless phase adjustment while improving the system's anti-interference capability and robustness.

[0040] The link training control module includes a link training state machine and a link phase control module. When the link training state machine detects that the parallel bus link is in a valid state, it controls the parallel bus link training system to start training. The specific training process includes a link detection phase, a maximum cluster calculation phase, and a link re-detection phase.

[0041] (a) The link detection phase includes: The link training state machine sequentially traverses multiple preset phase stages. Specifically, the first round of link detection in the link detection stage includes: The link training state machine is adjusted to the first training phase, which corresponds to the first preset phase, with a phase index of 1. The link phase control module sends a first adjustment signal to the phase control module in the clock module. The first adjustment signal includes a first phase adjustment value, which is the product of the phase index corresponding to the first phase and the minimum phase adjustment window. This allows the phase control module to adjust the clock phase to the first preset phase using the first adjustment signal. It should be understood that the adjustment signal includes adjustment signals corresponding to multiple preset phase phases (i.e., the adjustment signals include the first adjustment signal corresponding to the first phase, the second adjustment signal corresponding to the second phase, etc.), and the number of adjustment signals is the same as the number of preset phase phases. For example, eight preset phase phases include eight adjustment signals. The link phase control module sends adjustment signals accordingly as the link training state machine is adjusted, enabling the phase control module to adjust the clock phase using these adjustment signals.

[0042] The clock module includes a controllable phase-locked loop (PLL) and a phase control module. Upon receiving the first adjustment signal, the phase control module controls the PLL to adjust the clock signal to the first phase stage. The signal receiving module collects the data signal corresponding to the first phase stage and sends it to the data detection module. The data detection module performs validity checks on the data signal corresponding to the first phase stage, obtaining a binary detection result. A binary detection result of "1" indicates that the data signal corresponding to the first phase stage is valid, while a binary detection result of "0" indicates that the data signal corresponding to the first phase stage is invalid. That is, the first value is "1", and the second value is "0".

[0043] The data signal may include data frames or code patterns. For example, when the data signal includes data frames, the frame header detection module in the data detection module performs frame header detection on 500 sets of data (preset period, calibrable) in the first phase phase. If a frame header is detected in 400 sets (first continuous period, calibrable) of continuous data, the binary detection result of the data signal corresponding to the first phase phase is set to "1". If no frame header is detected in 400 sets of continuous data, the binary detection result of the data signal corresponding to the first phase phase is set to "0". When the data signal includes code patterns, the data pattern detection module in the data detection module performs code pattern detection on 500 sets of data in the first phase phase. If the correct code pattern is detected in 400 sets of continuous data, the binary detection result of the data signal corresponding to the first phase phase is set to "1". If no correct code pattern is detected in 400 sets of continuous data, the binary detection result of the data signal corresponding to the first phase phase is set to "0". Additionally, if no 500 sets of data signals are received within a preset time period, the binary detection result of the data signal corresponding to the first phase stage is set to "1". Furthermore, the binary detection result of the data signal corresponding to the first phase stage is stored in the link detection temporary register in the maximum cluster detection module.

[0044] The second round of link detection in the link detection phase includes: The link training state machine is adjusted to the second training phase, which corresponds to the second preset phase, with a phase index of 2. The link phase control module sends a second adjustment signal to the phase control module in the clock module. The second adjustment signal includes a second phase adjustment value, which is the product of the phase index corresponding to the second phase and the minimum phase adjustment window, so that the phase control module can adjust the clock phase to the second preset phase using the second adjustment signal.

[0045] After receiving the second adjustment signal, the phase control module controls the controllable phase-locked loop to adjust the clock signal to the second phase stage. The signal receiving module collects the data signal corresponding to the second phase stage and sends it to the data detection module. The data detection module performs validity checks on the data signal corresponding to the second phase stage, obtaining a binary detection result. If the binary detection result is "1", it indicates that the data signal corresponding to the second phase stage is valid; if the binary detection result is "0", it indicates that the data signal corresponding to the second phase stage is invalid. That is, the first value is "1" and the second value is "0". Further, the binary detection result of the data signal corresponding to the second phase stage is stored in the link detection temporary register in the maximum cluster detection module.

[0046] Similarly, the data signals corresponding to the preset phase stages are detected, and the binary detection results of the data signals corresponding to different phase stages are stored in the link detection temporary register. It should be understood that the values ​​corresponding to multiple preset phase stages are the same as the values ​​of the binary detection results stored in the link detection temporary register; for example, 32 preset phase stages correspond to 32 bits of binary data; 128 preset phase stages correspond to 128 bits of binary data.

[0047] (ii) The maximum cluster calculation stage includes: The maximum cluster detection module includes a link detection temporary register, a maximum cluster temporary register, a maximum cluster value temporary register, a maximum value sequence register, a maximum cluster center value sequence register, and an algorithm control module. The algorithm control module controls the data operations in the maximum cluster detection module.

[0048] The link detection temporary register in the maximum cluster detection module stores the binary detection results of data signals corresponding to multiple preset phase stages. These binary detection results are then combined into a circular initial binary sequence (a circular initial binary sequence does not mean the data is circular, but rather that the initial binary sequence is connected end-to-end during movement). This initial binary sequence is stored in the link detection temporary register and the maximum cluster temporary register. The data in the maximum cluster maximum value temporary register, the maximum value sequence register, and the maximum cluster center value sequence register are only updated when the data in the maximum cluster temporary register is updated. The maximum cluster maximum value temporary register records the length of the binary sequence in the maximum value temporary register where the value is a consecutive 1 starting from the most significant bit. The maximum value sequence register records the number of times the value in the maximum value temporary register has been moved relative to the initial binary sequence. The maximum cluster center value sequence register records the number of times the optimal window of the clock phase has been moved to the center position.

[0049] For example, the numerical expression in the maximum cluster center value register can be represented as follows: ; Where y represents the data stored in the maximum cluster center value sequence register; x represents the data recorded in the maximum cluster value temporary register; This means rounding the value up to the nearest integer, i.e., rounding up.

[0050] It should be understood that when the initial binary sequence is 32 bits, shifting the initial binary sequence to the left 32 times or to the right 32 times will result in the same binary sequence as the initial binary sequence.

[0051] To more clearly illustrate the data detection process, let's take an initial binary sequence of 1101 as an example. Since the initial binary sequence consists of 4 bits of data, it needs to be shifted left 4 times to facilitate the processing of the binary sequence.

[0052] First move: The algorithm control module shifts the initial binary sequence 1101 in the control link detection temporary register one bit to the left, obtaining the binary sequence 1011 (i.e., the shifted binary sequence). It then compares 1011 with 1101 in the maximum cluster temporary register. Since 1011 is less than 1101, there is no need to update the data in the maximum cluster temporary register. Therefore, the data in the maximum cluster maximum value temporary register, the maximum value sequence register, and the maximum cluster center value sequence register remain unchanged. The maximum cluster maximum value temporary register, the maximum value sequence register, and the maximum cluster center value sequence register store the initial data.

[0053] Second move: The algorithm control module controls the link to move the binary sequence 1011 in the temporary register to the left by one bit, resulting in the binary sequence 0111. Then, it compares 0111 with 1101 in the maximum cluster temporary register. Since 0111 is less than 1101, there is no need to update the data in the maximum cluster temporary register. Therefore, the data in the maximum cluster maximum value temporary register, the maximum value sequence register, and the maximum cluster center value sequence register are not updated.

[0054] The third move: The algorithm control module shifts the binary sequence 0111 in the control link detection temporary register one bit to the left, obtaining the binary sequence 1110. It then compares 1110 with 1101 in the maximum cluster temporary register. Since 1110 is greater than 1101, 1110 is updated in the maximum cluster temporary register. The data in the maximum cluster temporary register is updated synchronously with the data in the maximum cluster maximum value temporary register, the maximum value sequence register, and the maximum cluster center value sequence register. The maximum cluster maximum value temporary register records 3 data, meaning the length of consecutive 1s from the leftmost position in 1110 is 3. The maximum value sequence register records 3 data, meaning the initial binary sequence 1101 is shifted 3 times to obtain 1110. The maximum cluster center value sequence register records 2 data.

[0055] Fourth move: The algorithm control module controls the link detection temporary register to shift the binary sequence 1110 in the temporary register to the left by one bit, obtaining the binary sequence 1101. Then, it compares 1101 with 1110 in the maximum cluster temporary register. Since 1101 is less than 1110, there is no need to update the data in the maximum cluster temporary register. Therefore, the data in the maximum cluster maximum value temporary register, the maximum value sequence register, and the maximum cluster center value sequence register are not updated.

[0056] Based on the aforementioned sequential movement and traversal of the initial binary sequence, the binary sequence corresponding to the maximum value among multiple sets of binary sequences is determined, namely, the binary sequence 1110 corresponding to the maximum value among 1101, 1011, 0111, and 1110. Further, the data in the maximum value sequence register and the maximum cluster center value sequence register are determined using the binary sequence 1110, and the difference between the maximum value sequence register and the maximum cluster center value sequence register is determined. This difference is then multiplied by the minimum phase adjustment window to determine the target phase adjustment value, which is then sent to the phase control module in the clock module via the algorithm control module.

[0057] (III) The link re-inspection phase includes: After the phase control module adjusts the clock phase to the target phase adjustment value through a controllable phase-locked loop, the signal receiving module acquires the data signal corresponding to the adjusted clock phase and sends it to the data detection module. The data detection module then performs validity checks on the data signal corresponding to the adjusted clock phase.

[0058] For example, when the data signal includes data frames, the frame header detection module in the data detection module will perform frame header detection on 500 sets of data. If a frame header is detected in 420 sets (the second consecutive period, calibrable) of continuous data, the data signal corresponding to the adjusted clock phase is determined to be a valid signal, and the parallel bus link training ends. If no frame header is detected in the 420 sets of continuous data, the data signal corresponding to the adjusted clock phase is determined to be an invalid signal, the clock phase is adjusted to the initial position, and the parallel link training restarts.

[0059] When the data signal includes a code pattern, the data pattern detection module in the data detection module will perform code pattern detection on 500 sets of data. If the correct code pattern is detected in 420 consecutive sets of data, the data signal corresponding to the adjusted clock phase is determined to be a valid signal, and the parallel bus link training ends. If the correct code pattern is not detected in 420 consecutive sets of data, the data signal corresponding to the adjusted clock phase is determined to be an invalid signal, the clock phase is adjusted to the initial position, and the parallel link training restarts.

[0060] Furthermore, assuming the data signal corresponding to the adjusted clock phase is valid, the transmit clock phase is adjusted by the transmit clock module in the parallel bus link training system to enable communication between chip A and chip B. In this way, the parallel bus link can be increased from 25MHz to 400MHz to meet high-speed transmission requirements.

[0061] The aforementioned technical solution, by configuring a parallel link training system in the chip or FPGA, determines the location of the stable data transmission interval through multi-phase uniform scanning and maximum cluster analysis, thus achieving precise optimization of the timing of the high-speed parallel bus. This application's technical solution not only significantly increases the stable operating speed of the parallel bus from 25MHz to 400MHz, but also, by finding and locking the center phase point of the widest stability interval, gives the system extremely strong anti-interference capability and robustness.

[0062] In this application's technical solution, phase adjustment is performed between the link training control module and the clock module. After each phase adjustment, link detection is conducted on the parallel bus to determine the validity of data transmission within the link. Furthermore, an initial binary sequence is formed based on the detection results corresponding to different phase stages. By sequentially shifting this initial binary sequence, the binary sequence corresponding to the maximum value is determined. Based on the number of shifts to the binary sequence corresponding to the maximum value and the length of the effective window within the binary sequence, a precise target phase adjustment value is determined. This makes the parallel bus more stable after clock phase adjustment based on the target phase adjustment value, achieving efficient data transmission between parallel buses.

[0063] For example, a training system for a parallel bus link includes a signal receiving module, a link training control module, a clock module, a data detection module, and a maximum cluster detection module.

[0064] The signal receiving module is used to set the parallel bus link status to an active state when a data signal is received; the link training control module is used to send an adjustment signal to the clock module when the parallel bus link status is active, and the adjustment signal is used to instruct the clock module to adjust to multiple preset phase stages. The clock module is used to adjust the clock phase to multiple preset phase stages after receiving the adjustment signal; the data detection module is used to detect the validity of the data signals corresponding to different phase stages among the multiple preset phase stages, and obtain the binary detection results of the data signals corresponding to different phase stages. The binary detection results are used to indicate the validity of the data signals. The maximum cluster detection module is used to obtain multiple sets of binary sequences based on the initial binary sequence; and to obtain the target phase adjustment value based on the binary sequence corresponding to the largest value among the multiple values ​​corresponding to the multiple sets of binary sequences. The initial binary sequence is used to represent the data composed of multiple binary detection results corresponding to multiple preset phase stages. The clock module is also used to adjust the clock phase based on the target phase adjustment value, and send a detection signal to the data detection module through the link training control module so that the data detection module can detect the validity of the data signal corresponding to the adjusted clock phase. When the data signal corresponding to the adjusted clock phase is detected to be valid, the parallel bus link training ends.

[0065] For example, upon receiving a data signal, setting the parallel bus link state to a valid state includes: the signal sampling module acquiring the data signal sent by chip A, and the signal detection module detecting the validity of the data signal. If the data signal is detected as valid, the data detection module sets the parallel bus link state to a valid state.

[0066] The link training state machine in the link training control module traverses to the first phase stage, and the link phase control module generates a first adjustment signal based on the product of the phase index corresponding to the first phase stage and the minimum phase adjustment window. The phase control module then controls the controllable phase-locked loop to adjust the clock phase to the first phase stage. Further, the data detection module performs validity checks on the data signal corresponding to the first phase stage. If the validity check passes, the binary detection result corresponding to the first phase stage is set to "1"; if the validity check fails, the binary detection result is set to "0". Based on the above method, multiple preset phase stages are traversed to obtain the binary detection results corresponding to multiple preset phase stages, and these results are stored in the link detection temporary register.

[0067] The algorithm control module moves the initial binary sequence to the left (preset direction is left or right). After each move, the resulting binary sequence is compared with the target binary sequence in the maximum cluster temporary register (the initial value of the target binary sequence is the initial binary sequence). If the resulting binary sequence is less than or equal to the target binary sequence, the initial binary sequence is moved again. If the resulting binary sequence is greater than the target binary sequence, the resulting binary sequence is used as the target binary sequence. When the target binary sequence is updated, the length of consecutive 1s from the left in the target binary sequence is stored in the maximum cluster maximum value temporary register; the number of moves from the initial binary sequence to the target binary sequence is stored in the maximum value index register; and the center position is calculated from the data length and stored in the maximum cluster center value index register.

[0068] Based on the above method, the initial binary sequence is moved a preset number of times, and the data stored in the maximum cluster temporary register, the maximum cluster maximum value temporary register, the maximum value sequence register, and the maximum cluster center value sequence register are updated. The algorithm control module determines the difference between the number of moves in the maximum value sequence register and the center position in the maximum cluster center value sequence register, and determines the target phase adjustment value based on the product of the move difference and the minimum phase adjustment window.

[0069] Furthermore, the phase control module adjusts the clock phase to the target phase adjustment value via a controllable phase-locked loop. The data detection module then determines whether a second consecutive period of data signal is valid within the preset period. If a second consecutive period of data signal is valid within the preset period, the data signal corresponding to the adjusted clock phase is determined to be valid, and the parallel bus link training ends. If no second consecutive period of data signal is valid within the preset period, the data signal corresponding to the adjusted clock phase is determined to be invalid, and the parallel bus link training is restarted.

[0070] Understandably, during the training process of a parallel bus link, it is necessary to first determine the unit time interval of the clock phase, and then determine the minimum phase adjustment window based on the unit time interval. It should be understood that the unit time interval is used to represent the unit time (UI). A parallel bus is a parallel bus between the data signal transmitter and the data signal receiver; for example, Figure 1 In this diagram, chip A is the transmitter, chip B / FPGA is the receiver, and the parallel bus refers to the parallel bus between chip A and chip B / FPGA.

[0071] For example, the clock cycle of the parallel bus is obtained, and the corresponding unit time interval is determined based on the clock cycle. The clock cycle is the time required for the parallel bus to complete one data transmission. The clock cycle can be preset in the parallel bus system. The range of clock phase adjustment is determined based on the unit time interval, and the phase of the clock signal is adjusted to ensure that data passing through multiple data lines of the parallel bus is sent and received at the correct time. For example, if the data signal is sampled on both the rising and falling edges, the time elapsed from one rising edge to the next rising edge (or from one falling edge to the next falling edge) is taken as the clock cycle. In this case, the duration of the two unit time intervals is equal to the duration of the clock cycle. If the data signal is sampled only on the rising or falling edge, the duration of the unit time interval is equal to the duration of the clock cycle.

[0072] The minimum phase adjustment window represents the precision of clock phase adjustment. The minimum phase adjustment window can be any one of the following: a unit time interval divided into 32, 64, 128, or 256 segments. Given a defined minimum phase adjustment window, multiple preset phase stages are determined. These preset phase stages typically number in the dozens. Based on these phase stages, clock phase adjustment is performed on the parallel bus to determine the optimal phase, ensuring clock signal alignment, stable data link connection, and normal data transmission.

[0073] For example, based on a preset phase adjustment window size, a phase segment of corresponding size can be continuously divided within a unit time interval, or the unit time interval can be divided equally based on the phase adjustment window size. For instance, if a unit time interval is from 0ns to 3ns and the effective window size is 300ps, the unit time interval can be divided into continuous clock segments, each with a length of 300ps, including: 0 to 300ps, 300 to 600ps, 600 to 900ps, and so on. Then, the clock segments are sequentially accumulated to obtain phase stages: 0 to 300ps, 0 to 600ps, 0 to 900ps, and so on. Thus, when entering the phase adjustment stage for the first time, the phase can be adjusted to 300ps, and when adjusting the phase for the second time, it can be adjusted to 600ps, and so on.

[0074] In the specific implementation process, based on the preset parameter N, one UI is divided into N uniform phase points. For a UI equal to 3ns and N equal to 10, these phase points represent the adjustment status corresponding to 10 phase stages with clock phase offsets of 0ps, 300ps, 600ps, 900ps...2700ps relative to the original clock. Each phase adjustment stage corresponds to one phase point. Phase adjustment is completed based on the corresponding phase point, and then the link is detected.

[0075] In the specific implementation process, the phase adjustment window is obtained by: obtaining the effective window size of the data signal at the parallel bus receiver, determining the size of the phase adjustment window based on the effective window size, and ensuring that the phase adjustment window is less than or equal to the effective window. This ensures that the phase adjustment step size falls within the effective window, improves the accuracy of data acquisition at the signal receiver, and makes the parallel bus link more stable.

[0076] In the specific implementation process, the unit time interval can be divided into n clock segments, each clock segment corresponds to 1 / n unit time interval, the first phase stage is 1 / n, and each time a phase adjustment operation is added, the phase stage increases by the length of one clock segment, that is, the second phase stage is 2 / n. When entering the phase adjustment stage for the mth time, the phase stage is m / n, where m is less than n. In this way, the phase adjustment value is accumulated sequentially to obtain the corresponding phase stage.

[0077] For example, with a unit time interval from 0ns to 10ns and an effective window size of 2ns, the resulting phase stages are 0 to 2ns, 0 to 4ns, 0 to 6ns, 0 to 8ns, and 0 to 10ns. The corresponding phase adjustment values ​​are determined to be 2ns, 4ns, 6ns, 8ns, and 10ns. The phase of the corresponding parallel bus is adjusted sequentially according to the phase adjustment values ​​from smallest to largest. In actual use, the unit time interval and effective window may be smaller. This is only used as an adjustment illustration and does not limit the size and gap of the mixed phase stages of the effective window.

[0078] In the specific implementation process, the training control module of the signal receiver establishes N phase adjustment stages according to the preset parameter settings. In each stage, the phase shifts by 1 / N unit time intervals UI, and the phase shifts N times in total. For the m-th shift, the phase shifts by m / N UI. Since the clock is periodic, the uniform detection of the parameterized phase group is completed through N phase shift stages. For example, for an 800Mbps signal, one UI is 1.25ns. When the phase traversal parameter is set to 64, the value of each phase shift is approximately 19.53ps. Through 64 phase shifts, the detection of 64 phase points at 19.53ps intervals can be completed. In particular, for a 16-bit bus communicating at 800Mbps, the available sampling window length is about 5%UI, that is, a 62.5ps available sampling window. Three phase settings in the traversed sampling phases will fall within this interval. The maximum cluster algorithm will accurately locate the optimal sampling phase, thus achieving a stable link connection.

[0079] Figure 2 This is a schematic diagram of a training method for a parallel bus link provided in an embodiment of this application.

[0080] For example, such as Figure 2 As shown, the signal receiver (such as chip B) detects that the signal transmitter has started sending a signal and begins link training. Link training is used to adjust the clock phase of the parallel bus to optimize the performance of the parallel bus communication link.

[0081] Determine the unit time interval of the parallel bus to be adjusted. Based on the preset phase adjustment window, divide the unit time interval into multiple (i.e., N as shown in the figure) non-overlapping clock segments. Accumulate the clock segments sequentially to obtain multiple phase stages.

[0082] When the link training enters the nth stage, based on each phase stage (i.e., the n stages shown in the figure), the phase adjustment value for the parallel bus to be adjusted is determined. Based on each phase adjustment value, the phase of the parallel bus to be adjusted is adjusted sequentially (i.e., the phase is moved to n / N as shown in the figure). Then, the connection status is checked. Specifically, a preset detection period is obtained, which includes multiple unit time intervals. Based on the detection period, link detection is performed on the phase-adjusted parallel bus, and the connection status corresponding to each unit time interval is obtained, including successful connection. The number of consecutive intervals with a successful connection status is determined. If the proportion of consecutive successful connection intervals to the detection period is greater than or equal to a preset threshold, the detection result is determined to be passed; if the proportion of consecutive successful connection intervals to the detection period is less than the preset threshold, the detection result is determined to be failed (i.e., checking whether the link can be connected as shown in the figure).

[0083] Furthermore, the detection results after each phase adjustment value are recorded until the detection results of all phase adjustment values ​​are obtained (i.e., n=N-1 as shown in the figure). By performing maximum cluster detection on the binary sequences, the binary sequence corresponding to the maximum value among multiple values ​​corresponding to multiple sets of binary sequences is obtained. The center position of the effective window in the binary sequence corresponding to the maximum value is determined, and the target phase adjustment value is determined based on the center position.

[0084] The clock phase of the parallel bus to be adjusted is adjusted based on the target phase adjustment value (i.e., the set optimal phase shown in the figure), and the adjusted parallel bus is subjected to link detection; it is determined whether the link detection passes. If the link detection passes, the phase adjustment of the parallel bus is completed and the link training process is exited; if the link detection fails, the above steps are continued (i.e., if it fails as shown in the figure, the line training is restarted).

[0085] The aforementioned parallel bus link training method divides the unit time interval into smaller segments by using a preset phase adjustment window, thereby obtaining a more refined phase stage for phase adjustment. When the target phase adjustment value obtained in this way is applied to a high-speed parallel bus, it enables the data signal to be correctly sampled even within a very small effective range. For example, on 16-bit or 32-bit high-speed parallel buses, when the available reliable sampling window is less than 5% of the unit time interval, it can maintain a high rate of reliable transmission and effectively improve the signal transmission efficiency of the high-speed parallel bus.

[0086] Furthermore, based on the phase adjustment value determined in the phase stage, the parallel bus is sequentially phase-adjusted. After each phase adjustment, the parallel bus is checked to determine whether the link is properly connected. During the link check, a certain number of unit time intervals can be set, and the connection status is determined for each unit time interval. Based on the number of successful connection cycles in these unit time intervals, the detection result of the corresponding phase adjustment is determined. This allows for the selection of phase adjustment values ​​with smaller fluctuations in the periodic connection status, resulting in more accurate target phase adjustment values ​​and improved stability of the high-speed parallel bus signal transmission process.

[0087] Furthermore, based on the detection results corresponding to different phase adjustment values, the corresponding phase adjustment values ​​are clustered to obtain multiple clusters. The link detection results in each cluster are the same. The cluster center of the cluster is determined, and the corresponding detection result is determined as the candidate cluster center. The target cluster center with the largest value in its cluster is selected, and the phase adjustment value corresponding to the cluster center is taken as the target phase adjustment value. The largest cluster can determine a relatively stable adjustment value range. Within this range, the cluster center is selected to determine the target phase adjustment value, making the parallel bus more stable after adjustment based on the target phase adjustment value. Even if the clock phase deviation occurs due to other reasons during communication, the signal connection can still be maintained stably.

[0088] It should be understood that the above examples are provided to help those skilled in the art understand the embodiments of this application, and are not intended to limit the embodiments of this application to the specific values ​​or scenarios illustrated. Those skilled in the art can obviously make various equivalent modifications or changes based on the above examples, and such modifications or changes also fall within the scope of the embodiments of this application.

[0089] The above text combined Figures 1 to 2 The training system for parallel bus links provided in the embodiments of this application has been described in detail; the following will be combined with Figure 3 and Figure 4 The apparatus embodiments of this application are described in detail below. It should be understood that the apparatus in the embodiments of this application can perform the various methods described in the foregoing embodiments of this application, that is, the specific working processes of the various products described below can be referred to the corresponding processes in the foregoing method embodiments.

[0090] Figure 3 This is a schematic diagram of the structure of a training device for a parallel bus link provided in an embodiment of this application.

[0091] For example, such as Figure 3 As shown, the training device 300 for the parallel bus link includes: Acquisition module 310: used to set the parallel bus link status to an active state when a data signal is received; Processing module 320: Adjusts the clock phase to multiple preset phase stages; performs validity detection on the data signals corresponding to different phase stages among the multiple preset phase stages, and obtains the binary detection results of the data signals corresponding to different phase stages. The binary detection results are used to indicate the validity of the data signals. Processing module 320 is further configured to obtain multiple sets of binary sequences based on the initial binary sequence; obtain a target phase adjustment value based on the binary sequence corresponding to the largest value among the multiple values ​​corresponding to the multiple sets of binary sequences, wherein the initial binary sequence is used to represent the data composed of multiple binary detection results corresponding to multiple preset phase stages; adjust the clock phase based on the target phase adjustment value to detect the validity of the data signal corresponding to the adjusted clock phase; and end the training of the parallel bus link when the data signal corresponding to the adjusted clock phase is detected to be valid.

[0092] It should be noted that the training device 300 for the parallel bus link is embodied in the form of a functional unit. The term "module" here can be implemented in software and / or hardware, without specific limitations.

[0093] For example, a "module" can be a software program, a hardware circuit, or a combination of both that implements the above functions. The hardware circuit may include an application-specific integrated circuit (ASIC), electronic circuitry, a processor (e.g., a shared processor, a proprietary processor, or a group processor) and memory for executing one or more software or firmware programs, integrated logic circuitry, and / or other suitable components that support the described functions.

[0094] Therefore, the units of the various examples described in the embodiments of this application can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0095] Figure 4 This is a schematic diagram of the structure of a chip provided in an embodiment of this application.

[0096] For example, such as Figure 4 As shown, chip 400 includes: memory 410 and processor 420, wherein the memory 410 stores executable program code 430, and the processor 420 is used to call and execute the executable program code 430 to execute a training system for a parallel bus link.

[0097] For example, the memory 410 can be used to store related programs of the parallel bus link training system provided in the embodiments of this application; the processor 420 can call the related programs of the parallel bus link training system stored in the memory 410 to execute the parallel bus link training system of the embodiments of this application; for example, the signal receiving module is used to set the parallel bus link state to an active state when a data signal is received; the link training control module is used to send an adjustment signal to the clock module when the parallel bus link state is active, the adjustment signal being used to instruct the clock module to adjust to multiple preset phase stages; the clock module is used to adjust the clock phase to multiple preset phase stages after receiving the adjustment signal; the data detection module is used to perform validity detection on the data signals corresponding to different phase stages among the multiple preset phase stages, and obtain binary detection results of the data signals corresponding to different phase stages, the binary detection results being used to indicate the validity of the data signals; The maximum cluster detection module is used to obtain multiple sets of binary sequences based on the initial binary sequence; based on the binary sequence corresponding to the largest value among the multiple values ​​corresponding to the multiple sets of binary sequences, the target phase adjustment value is obtained. The initial binary sequence is used to represent the data composed of multiple binary detection results corresponding to multiple preset phase stages. The clock module is also used to adjust the clock phase based on the target phase adjustment value, and send a detection signal to the data detection module through the link training control module so that the data detection module can detect the validity of the data signal corresponding to the adjusted clock phase. When the data signal corresponding to the adjusted clock phase is detected to be valid, the parallel bus link training ends.

[0098] This embodiment can divide the device into functional modules based on the above method example. For example, each module can correspond to a separate function, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware. It should be noted that the module division in this embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods.

[0099] When the functional modules are divided according to their respective functions, the device may also include an acquisition module and a processing module. It should be noted that all relevant content regarding the steps involved in the above method embodiments can be referenced from the functional descriptions of the corresponding functional modules, and will not be repeated here.

[0100] It should be understood that the apparatus provided in this embodiment is used to execute the training system of the above-described parallel bus link, and therefore can achieve the same effect as the above implementation method.

[0101] When using integrated units, the device may include a processing module and a storage module. The processing module may be a processor or a controller that can implement or execute various exemplary logic blocks, modules, and circuits shown in conjunction with the disclosure of this application. The processor may also be a combination of functions that implement computing capabilities, such as a combination of one or more microprocessors, a combination of digital signal processing (DSP) and a microprocessor, etc., and the storage module may be a memory.

[0102] In addition, the device provided in the embodiments of this application may specifically be a chip, component or module. The chip may include a connected processor and a memory. The memory is used to store instructions. When the processor calls and executes the instructions, the chip can execute a training system for a parallel bus link provided in the above embodiments.

[0103] This application also provides a computer-readable storage medium storing computer program code, which, when run on a computer, causes the computer to execute the aforementioned related method steps to implement the parallel bus link training system provided in the above embodiments. The computer-readable storage medium may include, but is not limited to, any type of disk, including floppy disks, optical disks, Digital Video Discs (DVDs), Compact Disc Read-Only Memory (CD-ROMs), microdrives, and magneto-optical disks, read-only memory (ROMs), random access memory (RAMs), erasable programmable read-only memory (EPROMs), electrically erasable programmable read-only memory (EEPROMs), dynamic random access memory (DRAMs), video random access memory (VRAMs), flash memory devices, magnetic cards or optical cards, nanosystems (including molecular memory ICs), or any type of medium or device suitable for storing instructions and / or data.

[0104] This application also provides a computer program product that, when run on a computer, causes the computer to perform the aforementioned related steps to implement the parallel bus link training system provided in the above embodiments.

[0105] The chip, computer-readable storage medium, computer program product or chip provided in this application are all used to execute the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can be referred to the beneficial effects of the corresponding methods provided above, and will not be repeated here.

[0106] Through the above description of the embodiments, those skilled in the art will understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0107] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0108] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A training system using a parallel bus link, characterized in that, The system includes: The signal receiving module is used to set the parallel bus link status to an active state when a data signal is received. The link training control module is used to send an adjustment signal to the clock module when the parallel bus link state is in an active state. The adjustment signal is used to instruct the clock module to adjust to multiple preset phase stages. The clock module is used to adjust the clock phase to the plurality of preset phase stages after receiving the adjustment signal; The data detection module is used to detect the validity of data signals corresponding to different phase stages among the multiple preset phase stages of the clock phase, and obtain binary detection results of data signals corresponding to different phase stages. The binary detection results are used to indicate the validity of the data signals. The maximum cluster detection module is used to obtain multiple sets of binary sequences based on an initial binary sequence; and to obtain a target phase adjustment value based on the binary sequence corresponding to the largest value among the multiple values ​​corresponding to the multiple sets of binary sequences. The initial binary sequence is used to represent the data composed of multiple binary detection results corresponding to the multiple preset phase stages. The clock module is further configured to adjust the clock phase based on the target phase adjustment value, and send a detection signal to the data detection module through the link training control module, so that the data detection module can detect the validity of the data signal corresponding to the adjusted clock phase. When the data signal corresponding to the adjusted clock phase is detected to be valid, the training of the parallel bus link ends.

2. The system according to claim 1, characterized in that, The maximum cluster detection module includes a link detection temporary register, a maximum cluster temporary register, and an algorithm control module. The link detection temporary register stores the initial binary sequence. The system includes: The algorithm control module is used to control the initial binary sequence in the link detection temporary register to move sequentially in a preset direction a preset number of times, and after each move, update the target binary sequence in the maximum cluster temporary register with the moved binary sequence; the multiple sets of binary sequences include the moved binary sequence obtained after each move; the value of the preset number of times, the value of the preset phase stage and the sequence value of the multiple sets of binary sequences are all the same; The algorithm control module is used to obtain the target phase adjustment value based on the target binary sequence in the maximum cluster temporary register.

3. The system according to claim 2, characterized in that, The system includes: The algorithm control module is used to control the initial binary sequence in the link detection temporary register to shift one bit in the preset direction to obtain the shifted binary sequence; and to determine whether the value corresponding to the shifted binary sequence is greater than the value corresponding to the target binary sequence in the maximum cluster temporary register. When the value corresponding to the moved binary sequence is greater than the value corresponding to the target binary sequence in the maximum cluster temporary register, the moved binary sequence is updated to the target binary sequence in the maximum cluster temporary register; and the initial binary sequence is moved again until the number of moves on the initial binary sequence is equal to the preset number; When the value corresponding to the moved binary sequence is less than or equal to the value corresponding to the target binary sequence in the maximum cluster temporary register, the initial binary sequence continues to be moved until the number of moves of the initial binary sequence equals the preset number.

4. The system according to claim 2, characterized in that, The maximum cluster detection module further includes a maximum cluster value temporary storage register, a maximum value sequence register, and a maximum cluster center value sequence register; the system includes: The maximum cluster value temporary register is used to store the data length of the target binary sequence in the maximum cluster temporary register, starting from the most significant bit, where each bit is a valid detection result. The maximum value sequence number register is used to store the number of moves from the initial binary sequence to the target binary sequence in the maximum cluster temporary register; The maximum cluster center value sequence register is used to store the center position of the data length of the valid detection result, and the center position is obtained through the data length of the valid detection result. The algorithm control module is used to determine the movement difference between the number of moves in the maximum value sequence register and the center position in the maximum cluster center value sequence register, and to determine the target phase adjustment value based on the product of the movement difference and the minimum phase adjustment window.

5. The system according to any one of claims 1 to 4, characterized in that, The clock module includes a phase control module and a controllable phase-locked loop; the system includes: The phase control module is used to adjust the clock phase to the target phase phase through the controllable phase-locked loop after receiving the adjustment signal corresponding to the target phase phase. The target phase phase is used to represent any one of the plurality of preset phase phases. The data detection module is used to detect the validity of the data signal whose clock phase is in the target phase stage, and obtain the binary detection result of the data signal corresponding to the target phase stage.

6. The system according to claim 5, characterized in that, The system includes: The data detection module is used to determine whether there is a first continuous period of data signal as a valid signal within a preset period when the clock phase is in the target phase stage; When the data signal of the first continuous period is a valid signal within the preset period, the first value is determined as the binary detection result corresponding to the target phase stage, and the first value indicates that the data signal corresponding to the target phase stage is a valid signal; When no valid data signal of the first continuous period is found within the preset period, the second value is determined as the binary detection result corresponding to the target phase stage, and the second value indicates that the data signal corresponding to the target phase stage is an invalid signal.

7. The system according to any one of claims 1 to 4, characterized in that, The link training control module includes a link training state machine and a link phase control module; the system includes: The link training state machine is used to sequentially traverse the plurality of preset phase stages when the parallel bus link state is in a valid state. The link phase control module is used to determine the first phase adjustment value corresponding to the first phase stage based on the product of the phase index corresponding to the first phase stage and the minimum phase adjustment window when the link training state machine traverses to the first phase stage; and send the adjustment signal corresponding to the first phase stage to the clock module, the adjustment signal corresponding to the first phase stage including the first phase adjustment value, so that the clock module adjusts to the first phase stage.

8. The system according to any one of claims 1 to 4, characterized in that, The clock module includes a phase control module and a controllable phase-locked loop; the system includes: The phase control module is used to adjust the clock phase to the target phase adjustment value through the controllable phase-locked loop after receiving the target phase adjustment value sent by the maximum cluster detection module; and to send the detection signal to the data detection module through the link training control module. The data detection module is used to determine, after receiving the detection signal, whether there is a second consecutive period of data signal within a preset period as a valid signal; If the data signal of the second consecutive period is valid within the preset period, the data signal corresponding to the adjusted clock phase is determined to be valid; if the data signal of the second consecutive period is not valid within the preset period, the data signal corresponding to the adjusted clock phase is determined to be invalid, and the parallel bus link is retrained, wherein the period value of the second consecutive period is greater than the period value of the first consecutive period.

9. A chip, characterized in that, The chip is equipped with a training system for a parallel bus link, and the chip is used to execute the training system for the parallel bus link as described in any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed, implements the training system for the parallel bus link as described in any one of claims 1 to 8.

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